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libata: fix handling of port actions in per-dev action mask
[linux-2.6.git] / drivers / ata / sata_vsc.c
blob0fa1b89f76d588fac3745d4d008712162b6c267d
1 /*
2 * sata_vsc.c - Vitesse VSC7174 4 port DPA SATA
3 *
4 * Maintained by: Jeremy Higdon @ SGI
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004 SGI
9 *
10 * Bits from Jeff Garzik, Copyright RedHat, Inc.
11 *
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2, or (at your option)
16 * any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; see the file COPYING. If not, write to
25 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 *
27 *
28 * libata documentation is available via 'make {ps|pdf}docs',
29 * as Documentation/DocBook/libata.*
30 *
31 * Vitesse hardware documentation presumably available under NDA.
32 * Intel 31244 (same hardware interface) documentation presumably
33 * available from http://developer.intel.com/
34 *
35 */
36
37 #include <linux/kernel.h>
38 #include <linux/module.h>
39 #include <linux/pci.h>
40 #include <linux/init.h>
41 #include <linux/blkdev.h>
42 #include <linux/delay.h>
43 #include <linux/interrupt.h>
44 #include <linux/dma-mapping.h>
45 #include <linux/device.h>
46 #include <scsi/scsi_host.h>
47 #include <linux/libata.h>
48
49 #define DRV_NAME "sata_vsc"
50 #define DRV_VERSION "2.0"
51
52 enum {
53 /* Interrupt register offsets (from chip base address) */
54 VSC_SATA_INT_STAT_OFFSET = 0x00,
55 VSC_SATA_INT_MASK_OFFSET = 0x04,
56
57 /* Taskfile registers offsets */
58 VSC_SATA_TF_CMD_OFFSET = 0x00,
59 VSC_SATA_TF_DATA_OFFSET = 0x00,
60 VSC_SATA_TF_ERROR_OFFSET = 0x04,
61 VSC_SATA_TF_FEATURE_OFFSET = 0x06,
62 VSC_SATA_TF_NSECT_OFFSET = 0x08,
63 VSC_SATA_TF_LBAL_OFFSET = 0x0c,
64 VSC_SATA_TF_LBAM_OFFSET = 0x10,
65 VSC_SATA_TF_LBAH_OFFSET = 0x14,
66 VSC_SATA_TF_DEVICE_OFFSET = 0x18,
67 VSC_SATA_TF_STATUS_OFFSET = 0x1c,
68 VSC_SATA_TF_COMMAND_OFFSET = 0x1d,
69 VSC_SATA_TF_ALTSTATUS_OFFSET = 0x28,
70 VSC_SATA_TF_CTL_OFFSET = 0x29,
71
72 /* DMA base */
73 VSC_SATA_UP_DESCRIPTOR_OFFSET = 0x64,
74 VSC_SATA_UP_DATA_BUFFER_OFFSET = 0x6C,
75 VSC_SATA_DMA_CMD_OFFSET = 0x70,
76
77 /* SCRs base */
78 VSC_SATA_SCR_STATUS_OFFSET = 0x100,
79 VSC_SATA_SCR_ERROR_OFFSET = 0x104,
80 VSC_SATA_SCR_CONTROL_OFFSET = 0x108,
81
82 /* Port stride */
83 VSC_SATA_PORT_OFFSET = 0x200,
84
85 /* Error interrupt status bit offsets */
86 VSC_SATA_INT_ERROR_CRC = 0x40,
87 VSC_SATA_INT_ERROR_T = 0x20,
88 VSC_SATA_INT_ERROR_P = 0x10,
89 VSC_SATA_INT_ERROR_R = 0x8,
90 VSC_SATA_INT_ERROR_E = 0x4,
91 VSC_SATA_INT_ERROR_M = 0x2,
92 VSC_SATA_INT_PHY_CHANGE = 0x1,
93 VSC_SATA_INT_ERROR = (VSC_SATA_INT_ERROR_CRC | VSC_SATA_INT_ERROR_T | \
94 VSC_SATA_INT_ERROR_P | VSC_SATA_INT_ERROR_R | \
95 VSC_SATA_INT_ERROR_E | VSC_SATA_INT_ERROR_M | \
96 VSC_SATA_INT_PHY_CHANGE),
97 };
98
99
100 #define is_vsc_sata_int_err(port_idx, int_status) \
101 (int_status & (VSC_SATA_INT_ERROR << (8 * port_idx)))
102
103
104 static u32 vsc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
105 {
106 if (sc_reg > SCR_CONTROL)
107 return 0xffffffffU;
108 return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
109 }
110
111
112 static void vsc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
113 u32 val)
114 {
115 if (sc_reg > SCR_CONTROL)
116 return;
117 writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
118 }
119
120
121 static void vsc_intr_mask_update(struct ata_port *ap, u8 ctl)
122 {
123 void __iomem *mask_addr;
124 u8 mask;
125
126 mask_addr = ap->host->mmio_base +
127 VSC_SATA_INT_MASK_OFFSET + ap->port_no;
128 mask = readb(mask_addr);
129 if (ctl & ATA_NIEN)
130 mask |= 0x80;
131 else
132 mask &= 0x7F;
133 writeb(mask, mask_addr);
134 }
135
136
137 static void vsc_sata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
138 {
139 struct ata_ioports *ioaddr = &ap->ioaddr;
140 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
141
142 /*
143 * The only thing the ctl register is used for is SRST.
144 * That is not enabled or disabled via tf_load.
145 * However, if ATA_NIEN is changed, then we need to change the interrupt register.
146 */
147 if ((tf->ctl & ATA_NIEN) != (ap->last_ctl & ATA_NIEN)) {
148 ap->last_ctl = tf->ctl;
149 vsc_intr_mask_update(ap, tf->ctl & ATA_NIEN);
150 }
151 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
152 writew(tf->feature | (((u16)tf->hob_feature) << 8),
153 (void __iomem *) ioaddr->feature_addr);
154 writew(tf->nsect | (((u16)tf->hob_nsect) << 8),
155 (void __iomem *) ioaddr->nsect_addr);
156 writew(tf->lbal | (((u16)tf->hob_lbal) << 8),
157 (void __iomem *) ioaddr->lbal_addr);
158 writew(tf->lbam | (((u16)tf->hob_lbam) << 8),
159 (void __iomem *) ioaddr->lbam_addr);
160 writew(tf->lbah | (((u16)tf->hob_lbah) << 8),
161 (void __iomem *) ioaddr->lbah_addr);
162 } else if (is_addr) {
163 writew(tf->feature, (void __iomem *) ioaddr->feature_addr);
164 writew(tf->nsect, (void __iomem *) ioaddr->nsect_addr);
165 writew(tf->lbal, (void __iomem *) ioaddr->lbal_addr);
166 writew(tf->lbam, (void __iomem *) ioaddr->lbam_addr);
167 writew(tf->lbah, (void __iomem *) ioaddr->lbah_addr);
168 }
169
170 if (tf->flags & ATA_TFLAG_DEVICE)
171 writeb(tf->device, (void __iomem *) ioaddr->device_addr);
172
173 ata_wait_idle(ap);
174 }
175
176
177 static void vsc_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
178 {
179 struct ata_ioports *ioaddr = &ap->ioaddr;
180 u16 nsect, lbal, lbam, lbah, feature;
181
182 tf->command = ata_check_status(ap);
183 tf->device = readw((void __iomem *) ioaddr->device_addr);
184 feature = readw((void __iomem *) ioaddr->error_addr);
185 nsect = readw((void __iomem *) ioaddr->nsect_addr);
186 lbal = readw((void __iomem *) ioaddr->lbal_addr);
187 lbam = readw((void __iomem *) ioaddr->lbam_addr);
188 lbah = readw((void __iomem *) ioaddr->lbah_addr);
189
190 tf->feature = feature;
191 tf->nsect = nsect;
192 tf->lbal = lbal;
193 tf->lbam = lbam;
194 tf->lbah = lbah;
195
196 if (tf->flags & ATA_TFLAG_LBA48) {
197 tf->hob_feature = feature >> 8;
198 tf->hob_nsect = nsect >> 8;
199 tf->hob_lbal = lbal >> 8;
200 tf->hob_lbam = lbam >> 8;
201 tf->hob_lbah = lbah >> 8;
202 }
203 }
204
205
206 /*
207 * vsc_sata_interrupt
208 *
209 * Read the interrupt register and process for the devices that have them pending.
210 */
211 static irqreturn_t vsc_sata_interrupt (int irq, void *dev_instance)
212 {
213 struct ata_host *host = dev_instance;
214 unsigned int i;
215 unsigned int handled = 0;
216 u32 int_status;
217
218 spin_lock(&host->lock);
219
220 int_status = readl(host->mmio_base + VSC_SATA_INT_STAT_OFFSET);
221
222 for (i = 0; i < host->n_ports; i++) {
223 if (int_status & ((u32) 0xFF << (8 * i))) {
224 struct ata_port *ap;
225
226 ap = host->ports[i];
227
228 if (is_vsc_sata_int_err(i, int_status)) {
229 u32 err_status;
230 printk(KERN_DEBUG "%s: ignoring interrupt(s)\n", __FUNCTION__);
231 err_status = ap ? vsc_sata_scr_read(ap, SCR_ERROR) : 0;
232 vsc_sata_scr_write(ap, SCR_ERROR, err_status);
233 handled++;
234 }
235
236 if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
237 struct ata_queued_cmd *qc;
238
239 qc = ata_qc_from_tag(ap, ap->active_tag);
240 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
241 handled += ata_host_intr(ap, qc);
242 else if (is_vsc_sata_int_err(i, int_status)) {
243 /*
244 * On some chips (i.e. Intel 31244), an error
245 * interrupt will sneak in at initialization
246 * time (phy state changes). Clearing the SCR
247 * error register is not required, but it prevents
248 * the phy state change interrupts from recurring
249 * later.
250 */
251 u32 err_status;
252 err_status = vsc_sata_scr_read(ap, SCR_ERROR);
253 printk(KERN_DEBUG "%s: clearing interrupt, "
254 "status %x; sata err status %x\n",
255 __FUNCTION__,
256 int_status, err_status);
257 vsc_sata_scr_write(ap, SCR_ERROR, err_status);
258 /* Clear interrupt status */
259 ata_chk_status(ap);
260 handled++;
261 }
262 }
263 }
264 }
265
266 spin_unlock(&host->lock);
267
268 return IRQ_RETVAL(handled);
269 }
270
271
272 static struct scsi_host_template vsc_sata_sht = {
273 .module = THIS_MODULE,
274 .name = DRV_NAME,
275 .ioctl = ata_scsi_ioctl,
276 .queuecommand = ata_scsi_queuecmd,
277 .can_queue = ATA_DEF_QUEUE,
278 .this_id = ATA_SHT_THIS_ID,
279 .sg_tablesize = LIBATA_MAX_PRD,
280 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
281 .emulated = ATA_SHT_EMULATED,
282 .use_clustering = ATA_SHT_USE_CLUSTERING,
283 .proc_name = DRV_NAME,
284 .dma_boundary = ATA_DMA_BOUNDARY,
285 .slave_configure = ata_scsi_slave_config,
286 .slave_destroy = ata_scsi_slave_destroy,
287 .bios_param = ata_std_bios_param,
288 };
289
290
291 static const struct ata_port_operations vsc_sata_ops = {
292 .port_disable = ata_port_disable,
293 .tf_load = vsc_sata_tf_load,
294 .tf_read = vsc_sata_tf_read,
295 .exec_command = ata_exec_command,
296 .check_status = ata_check_status,
297 .dev_select = ata_std_dev_select,
298 .bmdma_setup = ata_bmdma_setup,
299 .bmdma_start = ata_bmdma_start,
300 .bmdma_stop = ata_bmdma_stop,
301 .bmdma_status = ata_bmdma_status,
302 .qc_prep = ata_qc_prep,
303 .qc_issue = ata_qc_issue_prot,
304 .data_xfer = ata_mmio_data_xfer,
305 .freeze = ata_bmdma_freeze,
306 .thaw = ata_bmdma_thaw,
307 .error_handler = ata_bmdma_error_handler,
308 .post_internal_cmd = ata_bmdma_post_internal_cmd,
309 .irq_handler = vsc_sata_interrupt,
310 .irq_clear = ata_bmdma_irq_clear,
311 .scr_read = vsc_sata_scr_read,
312 .scr_write = vsc_sata_scr_write,
313 .port_start = ata_port_start,
314 .port_stop = ata_port_stop,
315 .host_stop = ata_pci_host_stop,
316 };
317
318 static void __devinit vsc_sata_setup_port(struct ata_ioports *port, unsigned long base)
319 {
320 port->cmd_addr = base + VSC_SATA_TF_CMD_OFFSET;
321 port->data_addr = base + VSC_SATA_TF_DATA_OFFSET;
322 port->error_addr = base + VSC_SATA_TF_ERROR_OFFSET;
323 port->feature_addr = base + VSC_SATA_TF_FEATURE_OFFSET;
324 port->nsect_addr = base + VSC_SATA_TF_NSECT_OFFSET;
325 port->lbal_addr = base + VSC_SATA_TF_LBAL_OFFSET;
326 port->lbam_addr = base + VSC_SATA_TF_LBAM_OFFSET;
327 port->lbah_addr = base + VSC_SATA_TF_LBAH_OFFSET;
328 port->device_addr = base + VSC_SATA_TF_DEVICE_OFFSET;
329 port->status_addr = base + VSC_SATA_TF_STATUS_OFFSET;
330 port->command_addr = base + VSC_SATA_TF_COMMAND_OFFSET;
331 port->altstatus_addr = base + VSC_SATA_TF_ALTSTATUS_OFFSET;
332 port->ctl_addr = base + VSC_SATA_TF_CTL_OFFSET;
333 port->bmdma_addr = base + VSC_SATA_DMA_CMD_OFFSET;
334 port->scr_addr = base + VSC_SATA_SCR_STATUS_OFFSET;
335 writel(0, (void __iomem *) base + VSC_SATA_UP_DESCRIPTOR_OFFSET);
336 writel(0, (void __iomem *) base + VSC_SATA_UP_DATA_BUFFER_OFFSET);
337 }
338
339
340 static int __devinit vsc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
341 {
342 static int printed_version;
343 struct ata_probe_ent *probe_ent = NULL;
344 unsigned long base;
345 int pci_dev_busy = 0;
346 void __iomem *mmio_base;
347 int rc;
348
349 if (!printed_version++)
350 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
351
352 rc = pci_enable_device(pdev);
353 if (rc)
354 return rc;
355
356 /*
357 * Check if we have needed resource mapped.
358 */
359 if (pci_resource_len(pdev, 0) == 0) {
360 rc = -ENODEV;
361 goto err_out;
362 }
363
364 rc = pci_request_regions(pdev, DRV_NAME);
365 if (rc) {
366 pci_dev_busy = 1;
367 goto err_out;
368 }
369
370 /*
371 * Use 32 bit DMA mask, because 64 bit address support is poor.
372 */
373 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
374 if (rc)
375 goto err_out_regions;
376 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
377 if (rc)
378 goto err_out_regions;
379
380 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
381 if (probe_ent == NULL) {
382 rc = -ENOMEM;
383 goto err_out_regions;
384 }
385 memset(probe_ent, 0, sizeof(*probe_ent));
386 probe_ent->dev = pci_dev_to_dev(pdev);
387 INIT_LIST_HEAD(&probe_ent->node);
388
389 mmio_base = pci_iomap(pdev, 0, 0);
390 if (mmio_base == NULL) {
391 rc = -ENOMEM;
392 goto err_out_free_ent;
393 }
394 base = (unsigned long) mmio_base;
395
396 /*
397 * Due to a bug in the chip, the default cache line size can't be used
398 */
399 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x80);
400
401 probe_ent->sht = &vsc_sata_sht;
402 probe_ent->port_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
403 ATA_FLAG_MMIO;
404 probe_ent->port_ops = &vsc_sata_ops;
405 probe_ent->n_ports = 4;
406 probe_ent->irq = pdev->irq;
407 probe_ent->irq_flags = IRQF_SHARED;
408 probe_ent->mmio_base = mmio_base;
409
410 /* We don't care much about the PIO/UDMA masks, but the core won't like us
411 * if we don't fill these
412 */
413 probe_ent->pio_mask = 0x1f;
414 probe_ent->mwdma_mask = 0x07;
415 probe_ent->udma_mask = 0x7f;
416
417 /* We have 4 ports per PCI function */
418 vsc_sata_setup_port(&probe_ent->port[0], base + 1 * VSC_SATA_PORT_OFFSET);
419 vsc_sata_setup_port(&probe_ent->port[1], base + 2 * VSC_SATA_PORT_OFFSET);
420 vsc_sata_setup_port(&probe_ent->port[2], base + 3 * VSC_SATA_PORT_OFFSET);
421 vsc_sata_setup_port(&probe_ent->port[3], base + 4 * VSC_SATA_PORT_OFFSET);
422
423 pci_set_master(pdev);
424
425 /*
426 * Config offset 0x98 is "Extended Control and Status Register 0"
427 * Default value is (1 << 28). All bits except bit 28 are reserved in
428 * DPA mode. If bit 28 is set, LED 0 reflects all ports' activity.
429 * If bit 28 is clear, each port has its own LED.
430 */
431 pci_write_config_dword(pdev, 0x98, 0);
432
433 /* FIXME: check ata_device_add return value */
434 ata_device_add(probe_ent);
435 kfree(probe_ent);
436
437 return 0;
438
439 err_out_free_ent:
440 kfree(probe_ent);
441 err_out_regions:
442 pci_release_regions(pdev);
443 err_out:
444 if (!pci_dev_busy)
445 pci_disable_device(pdev);
446 return rc;
447 }
448
449 static const struct pci_device_id vsc_sata_pci_tbl[] = {
450 { PCI_VENDOR_ID_VITESSE, 0x7174,
451 PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 },
452 { PCI_VENDOR_ID_INTEL, 0x3200,
453 PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 },
454
455 { } /* terminate list */
456 };
457
458 static struct pci_driver vsc_sata_pci_driver = {
459 .name = DRV_NAME,
460 .id_table = vsc_sata_pci_tbl,
461 .probe = vsc_sata_init_one,
462 .remove = ata_pci_remove_one,
463 };
464
465 static int __init vsc_sata_init(void)
466 {
467 return pci_register_driver(&vsc_sata_pci_driver);
468 }
469
470 static void __exit vsc_sata_exit(void)
471 {
472 pci_unregister_driver(&vsc_sata_pci_driver);
473 }
474
475 MODULE_AUTHOR("Jeremy Higdon");
476 MODULE_DESCRIPTION("low-level driver for Vitesse VSC7174 SATA controller");
477 MODULE_LICENSE("GPL");
478 MODULE_DEVICE_TABLE(pci, vsc_sata_pci_tbl);
479 MODULE_VERSION(DRV_VERSION);
480
481 module_init(vsc_sata_init);
482 module_exit(vsc_sata_exit);
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