| blob | 91aa565d437490536dfb4d9411b84392b7061df4 |
1 /* Copyright 2008-2012 Broadcom Corporation
2 *
3 * Unless you and Broadcom execute a separate written software license
4 * agreement governing use of this software, this software is licensed to you
5 * under the terms of the GNU General Public License version 2, available
6 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
7 *
8 * Notwithstanding the above, under no circumstances may you combine this
9 * software in any way with any other Broadcom software provided under a
10 * license other than the GPL, without Broadcom's express prior written
11 * consent.
12 *
13 * Written by Yaniv Rosner
14 *
15 */
19 #include <linux/kernel.h>
20 #include <linux/errno.h>
21 #include <linux/pci.h>
22 #include <linux/netdevice.h>
23 #include <linux/delay.h>
24 #include <linux/ethtool.h>
25 #include <linux/mutex.h>
30 /********************************************************/
31 #define ETH_HLEN 14
32 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
33 #define ETH_OVREHEAD (ETH_HLEN + 8 + 8)
34 #define ETH_MIN_PACKET_SIZE 60
35 #define ETH_MAX_PACKET_SIZE 1500
36 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
37 #define MDIO_ACCESS_TIMEOUT 1000
38 #define WC_LANE_MAX 4
39 #define I2C_SWITCH_WIDTH 2
40 #define I2C_BSC0 0
41 #define I2C_BSC1 1
42 #define I2C_WA_RETRY_CNT 3
43 #define MCPR_IMC_COMMAND_READ_OP 1
44 #define MCPR_IMC_COMMAND_WRITE_OP 2
46 /* LED Blink rate that will achieve ~15.9Hz */
47 #define LED_BLINK_RATE_VAL_E3 354
48 #define LED_BLINK_RATE_VAL_E1X_E2 480
49 /***********************************************************/
50 /* Shortcut definitions */
51 /***********************************************************/
53 #define NIG_LATCH_BC_ENABLE_MI_INT 0
55 #define NIG_STATUS_EMAC0_MI_INT \
56 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
57 #define NIG_STATUS_XGXS0_LINK10G \
58 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
59 #define NIG_STATUS_XGXS0_LINK_STATUS \
60 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
61 #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
62 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
63 #define NIG_STATUS_SERDES0_LINK_STATUS \
64 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
65 #define NIG_MASK_MI_INT \
66 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
67 #define NIG_MASK_XGXS0_LINK10G \
68 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
69 #define NIG_MASK_XGXS0_LINK_STATUS \
70 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
71 #define NIG_MASK_SERDES0_LINK_STATUS \
72 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
74 #define MDIO_AN_CL73_OR_37_COMPLETE \
75 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
76 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
78 #define XGXS_RESET_BITS \
79 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \
80 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \
81 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \
82 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
83 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
85 #define SERDES_RESET_BITS \
86 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
87 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \
88 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \
89 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
91 #define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37
92 #define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73
93 #define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM
94 #define AUTONEG_PARALLEL \
95 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
96 #define AUTONEG_SGMII_FIBER_AUTODET \
97 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
98 #define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
100 #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
101 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
102 #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
103 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
104 #define GP_STATUS_SPEED_MASK \
105 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
106 #define GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
107 #define GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
108 #define GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
109 #define GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
110 #define GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
111 #define GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
112 #define GP_STATUS_10G_HIG \
113 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
114 #define GP_STATUS_10G_CX4 \
115 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
116 #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
117 #define GP_STATUS_10G_KX4 \
118 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
119 #define GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR
120 #define GP_STATUS_10G_XFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI
121 #define GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS
122 #define GP_STATUS_10G_SFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI
123 #define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD
124 #define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD
125 #define LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
126 #define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4
127 #define LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
128 #define LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD
129 #define LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
130 #define LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
131 #define LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD
132 #define LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
133 #define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
134 #define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
135 #define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
136 #define LINK_20GTFD LINK_STATUS_SPEED_AND_DUPLEX_20GTFD
137 #define LINK_20GXFD LINK_STATUS_SPEED_AND_DUPLEX_20GXFD
141 #define SFP_EEPROM_CON_TYPE_ADDR 0x2
142 #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7
143 #define SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21
146 #define SFP_EEPROM_COMP_CODE_ADDR 0x3
147 #define SFP_EEPROM_COMP_CODE_SR_MASK (1<<4)
148 #define SFP_EEPROM_COMP_CODE_LR_MASK (1<<5)
149 #define SFP_EEPROM_COMP_CODE_LRM_MASK (1<<6)
151 #define SFP_EEPROM_FC_TX_TECH_ADDR 0x8
152 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
153 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8
155 #define SFP_EEPROM_OPTIONS_ADDR 0x40
156 #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
157 #define SFP_EEPROM_OPTIONS_SIZE 2
159 #define EDC_MODE_LINEAR 0x0022
160 #define EDC_MODE_LIMITING 0x0044
161 #define EDC_MODE_PASSIVE_DAC 0x0055
163 /* BRB default for class 0 E2 */
164 #define DEFAULT0_E2_BRB_MAC_PAUSE_XOFF_THR 170
165 #define DEFAULT0_E2_BRB_MAC_PAUSE_XON_THR 250
166 #define DEFAULT0_E2_BRB_MAC_FULL_XOFF_THR 10
167 #define DEFAULT0_E2_BRB_MAC_FULL_XON_THR 50
169 /* BRB thresholds for E2*/
170 #define PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE 170
171 #define PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
173 #define PFC_E2_BRB_MAC_PAUSE_XON_THR_PAUSE 250
174 #define PFC_E2_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
176 #define PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE 10
177 #define PFC_E2_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 90
179 #define PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE 50
180 #define PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE 250
182 /* BRB default for class 0 E3A0 */
183 #define DEFAULT0_E3A0_BRB_MAC_PAUSE_XOFF_THR 290
184 #define DEFAULT0_E3A0_BRB_MAC_PAUSE_XON_THR 410
185 #define DEFAULT0_E3A0_BRB_MAC_FULL_XOFF_THR 10
186 #define DEFAULT0_E3A0_BRB_MAC_FULL_XON_THR 50
188 /* BRB thresholds for E3A0 */
189 #define PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE 290
190 #define PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
192 #define PFC_E3A0_BRB_MAC_PAUSE_XON_THR_PAUSE 410
193 #define PFC_E3A0_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
195 #define PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE 10
196 #define PFC_E3A0_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 170
198 #define PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE 50
199 #define PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE 410
201 /* BRB default for E3B0 */
202 #define DEFAULT0_E3B0_BRB_MAC_PAUSE_XOFF_THR 330
203 #define DEFAULT0_E3B0_BRB_MAC_PAUSE_XON_THR 490
204 #define DEFAULT0_E3B0_BRB_MAC_FULL_XOFF_THR 15
205 #define DEFAULT0_E3B0_BRB_MAC_FULL_XON_THR 55
207 /* BRB thresholds for E3B0 2 port mode*/
208 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_PAUSE 1025
209 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
211 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_PAUSE 1025
212 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
214 #define PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE 10
215 #define PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 1025
217 #define PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE 50
218 #define PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_NON_PAUSE 1025
220 /* only for E3B0*/
221 #define PFC_E3B0_2P_BRB_FULL_LB_XOFF_THR 1025
222 #define PFC_E3B0_2P_BRB_FULL_LB_XON_THR 1025
224 /* Lossy +Lossless GUARANTIED == GUART */
225 #define PFC_E3B0_2P_MIX_PAUSE_LB_GUART 284
226 /* Lossless +Lossless*/
227 #define PFC_E3B0_2P_PAUSE_LB_GUART 236
228 /* Lossy +Lossy*/
229 #define PFC_E3B0_2P_NON_PAUSE_LB_GUART 342
231 /* Lossy +Lossless*/
232 #define PFC_E3B0_2P_MIX_PAUSE_MAC_0_CLASS_T_GUART 284
233 /* Lossless +Lossless*/
234 #define PFC_E3B0_2P_PAUSE_MAC_0_CLASS_T_GUART 236
235 /* Lossy +Lossy*/
236 #define PFC_E3B0_2P_NON_PAUSE_MAC_0_CLASS_T_GUART 336
237 #define PFC_E3B0_2P_BRB_MAC_0_CLASS_T_GUART_HYST 80
239 #define PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART 0
240 #define PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART_HYST 0
242 /* BRB thresholds for E3B0 4 port mode */
243 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_PAUSE 304
244 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
246 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_PAUSE 384
247 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
249 #define PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE 10
250 #define PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 304
252 #define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE 50
253 #define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE 384
255 /* only for E3B0*/
256 #define PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR 304
257 #define PFC_E3B0_4P_BRB_FULL_LB_XON_THR 384
258 #define PFC_E3B0_4P_LB_GUART 120
260 #define PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART 120
261 #define PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART_HYST 80
263 #define PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART 80
264 #define PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART_HYST 120
266 /* Pause defines*/
267 #define DEFAULT_E3B0_BRB_FULL_LB_XOFF_THR 330
268 #define DEFAULT_E3B0_BRB_FULL_LB_XON_THR 490
269 #define DEFAULT_E3B0_LB_GUART 40
271 #define DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART 40
272 #define DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART_HYST 0
274 #define DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART 40
275 #define DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART_HYST 0
277 /* ETS defines*/
278 #define DCBX_INVALID_COS (0xFF)
280 #define ETS_BW_LIMIT_CREDIT_UPPER_BOUND (0x5000)
281 #define ETS_BW_LIMIT_CREDIT_WEIGHT (0x5000)
282 #define ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS (1360)
283 #define ETS_E3B0_NIG_MIN_W_VAL_20GBPS (2720)
284 #define ETS_E3B0_PBF_MIN_W_VAL (10000)
286 #define MAX_PACKET_SIZE (9700)
287 #define WC_UC_TIMEOUT 100
288 #define MAX_KR_LINK_RETRY 4
290 /**********************************************************/
291 /* INTERFACE */
292 /**********************************************************/
294 #define CL22_WR_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
295 bnx2x_cl45_write(_bp, _phy, \
296 (_phy)->def_md_devad, \
297 (_bank + (_addr & 0xf)), \
298 _val)
300 #define CL22_RD_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
301 bnx2x_cl45_read(_bp, _phy, \
302 (_phy)->def_md_devad, \
303 (_bank + (_addr & 0xf)), \
304 _val)
307 {
313 }
316 {
322 }
324 /******************************************************************/
325 /* EPIO/GPIO section */
326 /******************************************************************/
328 {
331 /* Sanity check */
335 }
338 /* Set this EPIO to output */
343 }
345 {
348 /* Sanity check */
352 }
355 /* Set this EPIO to output */
359 else
364 /* Set the value for this EPIO */
367 }
370 {
379 }
380 }
383 {
392 }
395 }
396 /******************************************************************/
397 /* ETS section */
398 /******************************************************************/
400 {
401 /* ETS disabled configuration*/
406 /* mapping between entry priority to client number (0,1,2 -debug and
407 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
408 * 3bits client num.
409 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
410 * cos1-100 cos0-011 dbg1-010 dbg0-001 MCP-000
411 */
414 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
415 * as strict. Bits 0,1,2 - debug and management entries, 3 -
416 * COS0 entry, 4 - COS1 entry.
417 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
418 * bit4 bit3 bit2 bit1 bit0
419 * MCP and debug are strict
420 */
423 /* defines which entries (clients) are subjected to WFQ arbitration */
425 /* For strict priority entries defines the number of consecutive
426 * slots for the highest priority.
427 */
429 /* mapping between the CREDIT_WEIGHT registers and actual client
430 * numbers
431 */
439 /* ETS mode disable */
441 /* If ETS mode is enabled (there is no strict priority) defines a WFQ
442 * weight for COS0/COS1.
443 */
446 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */
449 /* Defines the number of consecutive slots for the strict priority */
451 }
452 /******************************************************************************
453 * Description:
454 * Getting min_w_val will be set according to line speed .
455 *.
456 ******************************************************************************/
458 {
460 /* Calculate min_w_val.*/
464 else
468 /* If the link isn't up (static configuration for example ) The
469 * link will be according to 20GBPS.
470 */
472 }
473 /******************************************************************************
474 * Description:
475 * Getting credit upper bound form min_w_val.
476 *.
477 ******************************************************************************/
479 {
481 MAX_PACKET_SIZE);
483 }
484 /******************************************************************************
485 * Description:
486 * Set credit upper bound for NIG.
487 *.
488 ******************************************************************************/
492 {
513 credit_upper_bound);
515 credit_upper_bound);
517 credit_upper_bound);
518 }
519 }
520 /******************************************************************************
521 * Description:
522 * Will return the NIG ETS registers to init values.Except
523 * credit_upper_bound.
524 * That isn't used in this configuration (No WFQ is enabled) and will be
525 * configured acording to spec
526 *.
527 ******************************************************************************/
530 {
534 /* Mapping between entry priority to client number (0,1,2 -debug and
535 * management clients, 3 - COS0 client, 4 - COS1, ... 8 -
536 * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by
537 * reset value or init tool
538 */
545 }
546 /* For strict priority entries defines the number of consecutive
547 * slots for the highest priority.
548 */
551 /* Mapping between the CREDIT_WEIGHT registers and actual client
552 * numbers
553 */
555 /*Port 1 has 6 COS*/
559 /*Port 0 has 9 COS*/
563 }
565 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
566 * as strict. Bits 0,1,2 - debug and management entries, 3 -
567 * COS0 entry, 4 - COS1 entry.
568 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
569 * bit4 bit3 bit2 bit1 bit0
570 * MCP and debug are strict
571 */
574 else
576 /* defines which entries (clients) are subjected to WFQ arbitration */
580 /* Please notice the register address are note continuous and a
581 * for here is note appropriate.In 2 port mode port0 only COS0-5
582 * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4
583 * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT
584 * are never used for WFQ
585 */
602 }
605 }
606 /******************************************************************************
607 * Description:
608 * Set credit upper bound for PBF.
609 *.
610 ******************************************************************************/
614 {
622 /* In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4
623 * port mode port1 has COS0-2 that can be used for WFQ.
624 */
631 }
635 }
637 /******************************************************************************
638 * Description:
639 * Will return the PBF ETS registers to init values.Except
640 * credit_upper_bound.
641 * That isn't used in this configuration (No WFQ is enabled) and will be
642 * configured acording to spec
643 *.
644 ******************************************************************************/
646 {
654 /* Mapping between entry priority to client number 0 - COS0
655 * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num.
656 * TODO_ETS - Should be done by reset value or init tool
657 */
659 /* 0x688 (|011|0 10|00 1|000) */
661 else
662 /* (10 1|100 |011|0 10|00 1|000) */
665 /* TODO_ETS - Should be done by reset value or init tool */
667 /* 0x688 (|011|0 10|00 1|000)*/
669 else
670 /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */
682 /* In 2 port mode port0 has COS0-5 that can be used for WFQ.
683 * In 4 port mode port1 has COS0-2 that can be used for WFQ.
684 */
691 }
697 }
698 /******************************************************************************
699 * Description:
700 * E3B0 disable will return basicly the values to init values.
701 *.
702 ******************************************************************************/
705 {
712 }
719 }
721 /******************************************************************************
722 * Description:
723 * Disable will return basicly the values to init values.
724 *
725 ******************************************************************************/
728 {
739 }
742 }
744 /******************************************************************************
745 * Description
746 * Set the COS mappimg to SP and BW until this point all the COS are not
747 * set as SP or BW.
748 ******************************************************************************/
753 {
768 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ,
769 nig_cli_subject2wfq_bitmap);
772 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0,
773 pbf_cli_subject2wfq_bitmap);
776 }
778 /******************************************************************************
779 * Description:
780 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are
781 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
782 ******************************************************************************/
790 {
793 /* Calculate and set BW for this COS - use 1 instead of 0 for BW */
799 nig_reg_adress_crd_weight =
801 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0;
807 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
808 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1;
814 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
815 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2;
823 nig_reg_adress_crd_weight =
824 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3;
825 pbf_reg_adress_crd_weight =
826 PBF_REG_COS3_WEIGHT_P0;
831 nig_reg_adress_crd_weight =
832 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4;
838 nig_reg_adress_crd_weight =
839 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5;
842 }
849 }
850 /******************************************************************************
851 * Description:
852 * Calculate the total BW.A value of 0 isn't legal.
853 *
854 ******************************************************************************/
859 {
865 /* Calculate total BW requested */
872 /* This is to prevent a state when ramrods
873 * can't be sent
874 */
877 }
880 }
881 }
883 /* Check total BW is valid */
889 }
892 /* We can handle a case whre the BW isn't 100 this can happen
893 * if the TC are joined.
894 */
895 }
897 }
899 /******************************************************************************
900 * Description:
901 * Invalidate all the sp_pri_to_cos.
902 *
903 ******************************************************************************/
905 {
909 }
910 /******************************************************************************
911 * Description:
912 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
913 * according to sp_pri_to_cos.
914 *
915 ******************************************************************************/
919 {
923 DCBX_E3B0_MAX_NUM_COS_PORT0;
929 }
933 "parameter There can't be two COS's with "
936 }
941 }
943 /******************************************************************************
944 * Description:
945 * Returns the correct value according to COS and priority in
946 * the sp_pri_cli register.
947 *
948 ******************************************************************************/
953 {
959 }
960 /******************************************************************************
961 * Description:
962 * Returns the correct value according to COS and priority in the
963 * sp_pri_cli register for NIG.
964 *
965 ******************************************************************************/
967 {
968 /* MCP Dbg0 and dbg1 are always with higher strict pri*/
975 }
976 /******************************************************************************
977 * Description:
978 * Returns the correct value according to COS and priority in the
979 * sp_pri_cli register for PBF.
980 *
981 ******************************************************************************/
983 {
990 }
992 /******************************************************************************
993 * Description:
994 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
995 * according to sp_pri_to_cos.(which COS has higher priority)
996 *
997 ******************************************************************************/
1000 {
1004 /* MCP Dbg0 and dbg1 are always with higher strict pri*/
1010 DCBX_E3B0_MAX_NUM_COS_PORT0;
1014 /* Set all the strict priority first */
1019 "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1022 }
1030 /* COS is used remove it from bitmap.*/
1033 "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1034 "invalid There can't be two COS's with"
1037 }
1039 pri_set++;
1040 }
1041 }
1043 /* Set all the Non strict priority i= COS*/
1046 /* Check if COS was already used for SP */
1048 /* COS wasn't used for SP */
1054 /* COS is used remove it from bitmap.*/
1056 pri_set++;
1057 }
1058 }
1064 }
1067 /* Only 6 usable clients*/
1073 /* Only 9 usable clients*/
1078 pri_cli_nig_lsb);
1080 pri_cli_nig_msb);
1083 }
1085 }
1087 /******************************************************************************
1088 * Description:
1089 * Configure the COS to ETS according to BW and SP settings.
1090 ******************************************************************************/
1094 {
1105 DCBX_E3B0_MAX_NUM_COS_PORT0;
1112 }
1118 }
1120 /* Prepare sp strict priority parameters*/
1123 /* Prepare BW parameters*/
1130 }
1132 /* Upper bound is set according to current link speed (min_w_val
1133 * should be the same for upper bound and COS credit val).
1134 */
1142 /* The function also sets the BW in HW(not the mappin
1143 * yet)
1144 */
1147 total_bw,
1149 port);
1155 params,
1156 sp_pri_to_cos,
1158 cos_entry);
1164 }
1169 }
1170 }
1172 /* Set SP register (which COS has higher priority) */
1174 sp_pri_to_cos);
1180 }
1182 /* Set client mapping of BW and strict */
1184 cos_sp_bitmap,
1185 cos_bw_bitmap);
1190 }
1192 }
1194 {
1195 /* ETS disabled configuration */
1198 /* Defines which entries (clients) are subjected to WFQ arbitration
1199 * COS0 0x8
1200 * COS1 0x10
1201 */
1203 /* Mapping between the ARB_CREDIT_WEIGHT registers and actual
1204 * client numbers (WEIGHT_0 does not actually have to represent
1205 * client 0)
1206 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
1207 * cos1-001 cos0-000 dbg1-100 dbg0-011 MCP-010
1208 */
1212 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1214 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1216 /* ETS mode enabled*/
1219 /* Defines the number of consecutive slots for the strict priority */
1221 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
1222 * as strict. Bits 0,1,2 - debug and management entries, 3 - COS0
1223 * entry, 4 - COS1 entry.
1224 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1225 * bit4 bit3 bit2 bit1 bit0
1226 * MCP and debug are strict
1227 */
1230 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/
1232 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1234 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1235 }
1239 {
1240 /* ETS disabled configuration*/
1253 }
1256 total_bw;
1258 total_bw;
1267 }
1270 {
1271 /* ETS disabled configuration*/
1276 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
1277 * as strict. Bits 0,1,2 - debug and management entries,
1278 * 3 - COS0 entry, 4 - COS1 entry.
1279 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1280 * bit4 bit3 bit2 bit1 bit0
1281 * MCP and debug are strict
1282 */
1284 /* For strict priority entries defines the number of consecutive slots
1285 * for the highest priority.
1286 */
1288 /* ETS mode disable */
1290 /* Defines the number of consecutive slots for the strict priority */
1293 /* Defines the number of consecutive slots for the strict priority */
1296 /* Mapping between entry priority to client number (0,1,2 -debug and
1297 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
1298 * 3bits client num.
1299 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
1300 * dbg0-010 dbg1-001 cos1-100 cos0-011 MCP-000
1301 * dbg0-010 dbg1-001 cos0-011 cos1-100 MCP-000
1302 */
1307 }
1309 /******************************************************************/
1310 /* EEE section */
1311 /******************************************************************/
1313 {
1321 }
1324 {
1338 }
1341 }
1344 {
1358 }
1361 }
1364 {
1370 /* time value in eee_mode --> used directly*/
1373 /* hsi value in eee_mode --> time */
1375 EEE_MODE_NVRAM_MASK,
1378 }
1380 /* hsi values in nvram --> time*/
1384 eee_power_mode)) &
1385 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
1386 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
1390 }
1393 }
1396 /******************************************************************/
1397 /* PFC section */
1398 /******************************************************************/
1401 u8 is_lb)
1402 {
1404 u32 xmac_base;
1407 /* XMAC base adrr */
1410 /* Initialize pause and pfc registers */
1415 /* No PFC support */
1417 FEATURE_CONFIG_PFC_ENABLED)) {
1419 /* RX flow control - Process pause frame in receive direction
1420 */
1424 /* TX flow control - Send pause packet when buffer is full */
1429 XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN |
1430 XMAC_PFC_CTRL_HI_REG_RX_PFC_EN |
1431 XMAC_PFC_CTRL_HI_REG_TX_PFC_EN |
1432 XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
1433 /* Write pause and PFC registers */
1439 }
1441 /* Write pause and PFC registers */
1447 /* Set MAC address for source TX Pause/PFC frames */
1458 }
1464 {
1465 /* Read pfc statistic */
1473 /* PFC received frames */
1475 EMAC_REG_RX_PFC_STATS_XOFF_RCVD);
1482 /* PFC received sent */
1484 EMAC_REG_RX_PFC_STATS_XOFF_SENT);
1490 }
1492 /* Read pfc statistic*/
1496 {
1497 /* Read pfc statistic */
1508 pfc_frames_received);
1509 }
1510 }
1511 /******************************************************************/
1512 /* MAC/PBF section */
1513 /******************************************************************/
1515 {
1517 /* Set clause 45 mode, slow down the MDIO clock to 2.5MHz
1518 * (a value of 49==0x31) and make sure that the AUTO poll is off
1519 */
1523 else
1527 EMAC_MDIO_MODE_CLOCK_CNT);
1530 else
1537 }
1539 {
1540 u32 port4mode_ovwr_val;
1541 /* Check 4-port override enabled */
1544 /* Return 4-port mode override value */
1546 }
1547 /* Return 4-port mode from input pin */
1549 }
1553 {
1554 /* reset and unreset the emac core */
1558 u32 val;
1559 u16 timeout;
1567 /* init emac - use read-modify-write */
1568 /* self clear reset */
1579 }
1580 timeout--;
1583 /* Set mac address */
1593 }
1596 u16 tx_pause_en,
1597 u8 enable)
1598 {
1602 enable);
1604 enable);
1607 }
1610 {
1617 /* Disable RX and TX */
1619 }
1623 {
1624 u32 val;
1627 /* Reset UMAC */
1637 /* This register opens the gate for the UMAC despite its name */
1641 UMAC_COMMAND_CONFIG_REG_PAD_EN |
1642 UMAC_COMMAND_CONFIG_REG_SW_RESET |
1643 UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK;
1661 }
1674 /* Set MAC address for source TX Pause/PFC frames (under SW reset) */
1684 /* Enable RX and TX */
1687 UMAC_COMMAND_CONFIG_REG_RX_ENA;
1691 /* Remove SW Reset */
1694 /* Check loopback mode */
1699 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
1700 * length used by the MAC receive logic to check frames.
1701 */
1707 }
1709 /* Define the XMAC mode */
1711 {
1715 /* In 4-port mode, need to set the mode only once, so if XMAC is
1716 * already out of reset, it means the mode has already been set,
1717 * and it must not* reset the XMAC again, since it controls both
1718 * ports of the path
1719 */
1723 MISC_REGISTERS_RESET_REG_2_XMAC)) {
1727 }
1729 /* Hard reset */
1731 MISC_REGISTERS_RESET_REG_2_XMAC);
1735 MISC_REGISTERS_RESET_REG_2_XMAC);
1739 /* Set the number of ports on the system side to up to 2 */
1742 /* Set the number of ports on the Warp Core to 10G */
1745 /* Set the number of ports on the system side to 1 */
1750 /* Set the number of ports on the Warp Core to 10G */
1755 /* Set the number of ports on the Warp Core to 20G */
1757 }
1758 }
1759 /* Soft reset */
1761 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1765 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1767 }
1770 {
1776 MISC_REGISTERS_RESET_REG_2_XMAC) {
1777 /* Send an indication to change the state in the NIG back to XON
1778 * Clearing this bit enables the next set of this bit to get
1779 * rising edge
1780 */
1788 }
1789 }
1793 {
1802 /* This register determines on which events the MAC will assert
1803 * error on the i/f to the NIG along w/ EOP.
1804 */
1806 /* This register tells the NIG whether to send traffic to UMAC
1807 * or XMAC
1808 */
1811 /* Set Max packet size */
1814 /* CRC append for Tx packets */
1817 /* update PFC */
1826 }
1828 /* Enable TX and RX */
1831 /* Check loopback mode */
1841 }
1845 {
1849 u32 val;
1853 /* Disable BMAC */
1857 /* enable emac and not bmac */
1860 /* ASIC */
1863 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1864 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1867 /* select the master lanes (out of 0-3) */
1869 /* select XGXS */
1874 /* select SerDes */
1876 }
1879 EMAC_RX_MODE_RESET);
1881 EMAC_TX_MODE_RESET);
1884 /* config GMII mode */
1888 /* pause enable/disable */
1890 EMAC_RX_MODE_FLOW_EN);
1894 EMAC_TX_MODE_FLOW_EN));
1896 FEATURE_CONFIG_PFC_ENABLED)) {
1899 EMAC_REG_EMAC_RX_MODE,
1900 EMAC_RX_MODE_FLOW_EN);
1904 EMAC_REG_EMAC_TX_MODE,
1906 EMAC_TX_MODE_FLOW_EN));
1909 EMAC_TX_MODE_FLOW_EN);
1910 }
1912 /* KEEP_VLAN_TAG, promiscuous */
1916 /* Setting this bit causes MAC control frames (except for pause
1917 * frames) to be passed on for processing. This setting has no
1918 * affect on the operation of the pause frames. This bit effects
1919 * all packets regardless of RX Parser packet sorting logic.
1920 * Turn the PFC off to make sure we are in Xon state before
1921 * enabling it.
1922 */
1926 /* Enable PFC again */
1928 EMAC_REG_RX_PFC_MODE_RX_EN |
1929 EMAC_REG_RX_PFC_MODE_TX_EN |
1930 EMAC_REG_RX_PFC_MODE_PRIORITIES);
1934 EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
1936 EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
1938 }
1941 /* Set Loopback */
1945 else
1949 /* enable emac */
1952 /* enable emac for jumbo packets */
1957 /* strip CRC */
1960 /* disable the NIG in/out to the bmac */
1965 /* enable the NIG in/out to the emac */
1969 FEATURE_CONFIG_PFC_ENABLED) ||
1980 }
1984 {
1988 NIG_REG_INGRESS_BMAC0_MEM;
1992 FEATURE_CONFIG_PFC_ENABLED)) &&
1994 /* Enable BigMAC to react on received Pause packets */
2000 /* tx control */
2003 FEATURE_CONFIG_PFC_ENABLED) &&
2009 }
2013 u8 is_lb)
2014 {
2015 /* Set rx control: Strip CRC and enable BigMAC to relay
2016 * control packets to the system as well
2017 */
2021 NIG_REG_INGRESS_BMAC0_MEM;
2025 FEATURE_CONFIG_PFC_ENABLED)) &&
2027 /* Enable BigMAC to react on received Pause packets */
2034 /* Tx control */
2037 FEATURE_CONFIG_PFC_ENABLED) &&
2046 /* Enable PFC RX & TX & STATS and set 8 COS */
2056 /* Clear the force Xon */
2060 /* disable PFC RX & TX & STATS and set 8 COS */
2063 }
2067 /* Set Time (based unit is 512 bit time) between automatic
2068 * re-sending of PP packets amd enable automatic re-send of
2069 * Per-Priroity Packet as long as pp_gen is asserted and
2070 * pp_disable is low.
2071 */
2081 /* mac control */
2086 }
2087 /* When PFC enabled, Pass pause frames towards the NIG. */
2094 }
2096 /* PFC BRB internal port configuration params */
2098 u32 pause_xoff;
2099 u32 pause_xon;
2100 u32 full_xoff;
2101 u32 full_xon;
2102 };
2105 u32 per_class_guaranty_mode;
2106 u32 lb_guarantied_hyst;
2107 u32 full_lb_xoff_th;
2108 u32 full_lb_xon_threshold;
2109 u32 lb_guarantied;
2110 u32 mac_0_class_t_guarantied;
2111 u32 mac_0_class_t_guarantied_hyst;
2112 u32 mac_1_class_t_guarantied;
2113 u32 mac_1_class_t_guarantied_hyst;
2114 };
2122 };
2126 {
2136 /* Class0 defaults */
2138 DEFAULT0_E2_BRB_MAC_PAUSE_XOFF_THR;
2140 DEFAULT0_E2_BRB_MAC_PAUSE_XON_THR;
2142 DEFAULT0_E2_BRB_MAC_FULL_XOFF_THR;
2144 DEFAULT0_E2_BRB_MAC_FULL_XON_THR;
2145 /* Pause able*/
2147 PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2149 PFC_E2_BRB_MAC_PAUSE_XON_THR_PAUSE;
2151 PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE;
2153 PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE;
2154 /* non pause able*/
2156 PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2158 PFC_E2_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2160 PFC_E2_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2162 PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2164 /* Class0 defaults */
2166 DEFAULT0_E3A0_BRB_MAC_PAUSE_XOFF_THR;
2168 DEFAULT0_E3A0_BRB_MAC_PAUSE_XON_THR;
2170 DEFAULT0_E3A0_BRB_MAC_FULL_XOFF_THR;
2172 DEFAULT0_E3A0_BRB_MAC_FULL_XON_THR;
2173 /* Pause able */
2175 PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2177 PFC_E3A0_BRB_MAC_PAUSE_XON_THR_PAUSE;
2179 PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE;
2181 PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE;
2182 /* non pause able*/
2184 PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2186 PFC_E3A0_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2188 PFC_E3A0_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2190 PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2192 /* Class0 defaults */
2194 DEFAULT0_E3B0_BRB_MAC_PAUSE_XOFF_THR;
2196 DEFAULT0_E3B0_BRB_MAC_PAUSE_XON_THR;
2198 DEFAULT0_E3B0_BRB_MAC_FULL_XOFF_THR;
2200 DEFAULT0_E3B0_BRB_MAC_FULL_XON_THR;
2203 FLAGS_4_PORT_MODE) {
2205 PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2207 PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_PAUSE;
2209 PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE;
2211 PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE;
2212 /* non pause able*/
2214 PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2216 PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2218 PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2220 PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2223 PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2225 PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_PAUSE;
2227 PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE;
2229 PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE;
2230 /* non pause able*/
2232 PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2234 PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2236 PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2238 PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2239 }
2244 }
2248 struct bnx2x_pfc_brb_e3b0_val
2252 {
2258 FLAGS_4_PORT_MODE) {
2260 PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR;
2262 PFC_E3B0_4P_BRB_FULL_LB_XON_THR;
2264 PFC_E3B0_4P_LB_GUART;
2266 PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART;
2268 PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART_HYST;
2270 PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART;
2272 PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART_HYST;
2275 PFC_E3B0_2P_BRB_FULL_LB_XOFF_THR;
2277 PFC_E3B0_2P_BRB_FULL_LB_XON_THR;
2279 PFC_E3B0_2P_BRB_MAC_0_CLASS_T_GUART_HYST;
2281 PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART;
2283 PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART_HYST;
2287 /* nonpauseable= Lossy + pauseable = Lossless*/
2289 PFC_E3B0_2P_MIX_PAUSE_LB_GUART;
2291 PFC_E3B0_2P_MIX_PAUSE_MAC_0_CLASS_T_GUART;
2293 /* Lossless +Lossless*/
2295 PFC_E3B0_2P_PAUSE_LB_GUART;
2297 PFC_E3B0_2P_PAUSE_MAC_0_CLASS_T_GUART;
2299 /* Lossy +Lossy*/
2301 PFC_E3B0_2P_NON_PAUSE_LB_GUART;
2303 PFC_E3B0_2P_NON_PAUSE_MAC_0_CLASS_T_GUART;
2304 }
2305 }
2310 DEFAULT_E3B0_BRB_FULL_LB_XOFF_THR;
2312 DEFAULT_E3B0_BRB_FULL_LB_XON_THR;
2314 DEFAULT_E3B0_LB_GUART;
2316 DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART;
2318 DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART_HYST;
2320 DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART;
2322 DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART_HYST;
2323 }
2324 }
2327 struct bnx2x_nig_brb_pfc_port_params
2329 {
2336 FEATURE_CONFIG_PFC_ENABLED;
2341 /* default - pause configuration */
2348 /* First COS */
2351 else
2355 /* The number of free blocks below which the pause signal to class 0
2356 * of MAC #n is asserted. n=0,1
2357 */
2359 BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 ,
2361 /* The number of free blocks above which the pause signal to class 0
2362 * of MAC #n is de-asserted. n=0,1
2363 */
2366 /* The number of free blocks below which the full signal to class 0
2367 * of MAC #n is asserted. n=0,1
2368 */
2371 /* The number of free blocks above which the full signal to class 0
2372 * of MAC #n is de-asserted. n=0,1
2373 */
2378 /* Second COS */
2381 else
2385 /* The number of free blocks below which the pause signal to
2386 * class 1 of MAC #n is asserted. n=0,1
2387 */
2389 BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0,
2392 /* The number of free blocks above which the pause signal to
2393 * class 1 of MAC #n is de-asserted. n=0,1
2394 */
2396 BRB1_REG_PAUSE_1_XON_THRESHOLD_0,
2398 /* The number of free blocks below which the full signal to
2399 * class 1 of MAC #n is asserted. n=0,1
2400 */
2402 BRB1_REG_FULL_1_XOFF_THRESHOLD_0,
2404 /* The number of free blocks above which the full signal to
2405 * class 1 of MAC #n is de-asserted. n=0,1
2406 */
2408 BRB1_REG_FULL_1_XON_THRESHOLD_0,
2413 params,
2415 pfc_params,
2416 pfc_enabled);
2421 /* The hysteresis on the guarantied buffer space for the Lb
2422 * port before signaling XON.
2423 */
2427 /* The number of free blocks below which the full signal to the
2428 * LB port is asserted.
2429 */
2432 /* The number of free blocks above which the full signal to the
2433 * LB port is de-asserted.
2434 */
2437 /* The number of blocks guarantied for the MAC #n port. n=0,1
2438 */
2440 /* The number of blocks guarantied for the LB port. */
2444 /* The number of blocks guarantied for the MAC #n port. */
2449 /* The number of blocks guarantied for class #t in MAC0. t=0,1
2450 */
2455 /* The hysteresis on the guarantied buffer space for class in
2456 * MAC0. t=0,1
2457 */
2463 /* The number of blocks guarantied for class #t in MAC1.t=0,1
2464 */
2469 /* The hysteresis on the guarantied buffer space for class #t
2470 * in MAC1. t=0,1
2471 */
2476 }
2479 }
2481 /******************************************************************************
2482 * Description:
2483 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are
2484 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
2485 ******************************************************************************/
2487 u8 cos_entry,
2489 {
2495 NIG_REG_P1_RX_COS0_PRIORITY_MASK :
2496 NIG_REG_P0_RX_COS0_PRIORITY_MASK;
2500 NIG_REG_P1_RX_COS1_PRIORITY_MASK :
2501 NIG_REG_P0_RX_COS1_PRIORITY_MASK;
2505 NIG_REG_P1_RX_COS2_PRIORITY_MASK :
2506 NIG_REG_P0_RX_COS2_PRIORITY_MASK;
2523 }
2528 }
2530 {
2536 }
2539 {
2546 }
2551 {
2559 FEATURE_CONFIG_PFC_ENABLED;
2562 /* When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
2563 * MAC control frames (that are not pause packets)
2564 * will be forwarded to the XCM.
2565 */
2567 NIG_REG_LLH0_XCM_MASK);
2568 /* NIG params will override non PFC params, since it's possible to
2569 * do transition from PFC to SAFC
2570 */
2577 else
2580 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2592 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2594 }
2615 /* output enable for RX_XCM # IF */
2619 /* HW PFC TX enable */
2632 NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,
2636 NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0,
2638 }
2640 NIG_REG_P0_PKT_PRIORITY_TO_COS,
2641 pkt_priority_to_cos);
2642 }
2647 {
2648 /* The PFC and pause are orthogonal to one another, meaning when
2649 * PFC is enabled, the pause are disabled, and when PFC is
2650 * disabled, pause are set according to the pause result.
2651 */
2652 u32 val;
2659 else
2664 /* update NIG params */
2667 /* update BRB params */
2686 }
2689 else
2694 FEATURE_CONFIG_PFC_ENABLED) ||
2698 }
2700 }
2705 u8 is_lb)
2706 {
2710 NIG_REG_INGRESS_BMAC0_MEM;
2712 u32 val;
2716 /* XGXS control */
2722 /* tx MAC SA */
2731 /* mac control */
2736 }
2741 /* set rx mtu */
2748 /* set tx mtu */
2753 /* set cnt max size */
2758 /* configure safc */
2765 }
2769 u8 is_lb)
2770 {
2774 NIG_REG_INGRESS_BMAC0_MEM;
2784 /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
2792 /* tx MAC SA */
2804 /* Configure SAFC */
2811 /* set rx mtu */
2817 /* set tx mtu */
2822 /* set cnt max size */
2830 }
2834 u8 is_lb)
2835 {
2839 u32 val;
2840 /* reset and unreset the BigMac */
2848 /* enable access for bmac registers */
2851 /* Enable BMAC according to BMAC type*/
2854 else
2861 FEATURE_CONFIG_PFC_ENABLED) ||
2873 }
2876 {
2878 NIG_REG_INGRESS_BMAC0_MEM;
2882 /* Only if the bmac is out of reset */
2885 nig_bmac_enable) {
2888 /* Clear Rx Enable bit in BMAC_CONTROL register */
2890 BIGMAC2_REGISTER_BMAC_CONTROL,
2894 BIGMAC2_REGISTER_BMAC_CONTROL,
2897 /* Clear Rx Enable bit in BMAC_CONTROL register */
2899 BIGMAC_REGISTER_BMAC_CONTROL,
2903 BIGMAC_REGISTER_BMAC_CONTROL,
2905 }
2907 }
2908 }
2911 u32 line_speed)
2912 {
2918 /* disable port */
2921 /* wait for init credit */
2930 count--;
2931 }
2937 }
2945 /* update threshold */
2947 /* update init credit */
2954 /* update threshold */
2956 /* update init credit */
2963 line_speed);
2965 }
2966 }
2971 /* probe the credit changes */
2976 /* enable port */
2979 }
2981 /**
2982 * bnx2x_get_emac_base - retrive emac base address
2983 *
2984 * @bp: driver handle
2985 * @mdc_mdio_access: access type
2986 * @port: port id
2987 *
2988 * This function selects the MDC/MDIO access (through emac0 or
2989 * emac1) depend on the mdc_mdio_access, port, port swapped. Each
2990 * phy has a default access mode, which could also be overridden
2991 * by nvram configuration. This parameter, whether this is the
2992 * default phy configuration, or the nvram overrun
2993 * configuration, is passed here as mdc_mdio_access and selects
2994 * the emac_base for the CL45 read/writes operations
2995 */
2998 {
3006 else
3012 else
3023 }
3026 }
3028 /******************************************************************/
3029 /* CL22 access functions */
3030 /******************************************************************/
3034 {
3036 u8 i;
3038 /* Switch to CL22 */
3043 /* address */
3045 EMAC_MDIO_COMM_COMMAND_WRITE_22 |
3046 EMAC_MDIO_COMM_START_BUSY);
3056 }
3057 }
3061 }
3064 }
3069 {
3071 u16 i;
3074 /* Switch to CL22 */
3079 /* address */
3081 EMAC_MDIO_COMM_COMMAND_READ_22 |
3082 EMAC_MDIO_COMM_START_BUSY);
3093 }
3094 }
3100 }
3103 }
3105 /******************************************************************/
3106 /* CL45 access functions */
3107 /******************************************************************/
3110 {
3111 u32 val;
3112 u16 i;
3116 EMAC_MDIO_STATUS_10MB);
3117 /* address */
3119 EMAC_MDIO_COMM_COMMAND_ADDRESS |
3120 EMAC_MDIO_COMM_START_BUSY);
3130 }
3131 }
3138 /* data */
3140 EMAC_MDIO_COMM_COMMAND_READ_45 |
3141 EMAC_MDIO_COMM_START_BUSY);
3148 EMAC_REG_EMAC_MDIO_COMM);
3152 }
3153 }
3159 }
3160 }
3161 /* Work around for E3 A0 */
3165 u16 temp_val;
3167 }
3168 }
3172 EMAC_MDIO_STATUS_10MB);
3174 }
3178 {
3179 u32 tmp;
3180 u8 i;
3184 EMAC_MDIO_STATUS_10MB);
3186 /* address */
3188 EMAC_MDIO_COMM_COMMAND_ADDRESS |
3189 EMAC_MDIO_COMM_START_BUSY);
3199 }
3200 }
3206 /* data */
3208 EMAC_MDIO_COMM_COMMAND_WRITE_45 |
3209 EMAC_MDIO_COMM_START_BUSY);
3216 EMAC_REG_EMAC_MDIO_COMM);
3220 }
3221 }
3226 }
3227 }
3228 /* Work around for E3 A0 */
3232 u16 temp_val;
3234 }
3235 }
3238 EMAC_MDIO_STATUS_10MB);
3240 }
3241 /******************************************************************/
3242 /* BSC access functions from E3 */
3243 /******************************************************************/
3245 {
3251 /* Read I2C output PINs */
3257 SHARED_HW_CFG_E3_I2C_MUX1_SHIFT;
3259 /* Read I2C output value */
3268 }
3272 u8 sl_devid,
3273 u16 sl_addr,
3274 u8 lc_addr,
3275 u8 xfer_cnt,
3277 {
3285 }
3289 xfer_cnt);
3291 }
3296 /* enable the engine */
3301 /* program slave device ID */
3305 /* start xfer with 0 byte to update the address pointer ???*/
3308 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3312 /* poll for completion */
3320 i);
3323 }
3324 }
3328 /* start xfer with read op */
3331 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3336 /* poll for completion */
3346 }
3347 }
3353 #ifdef __BIG_ENDIAN
3358 #endif
3359 }
3361 }
3365 {
3366 u16 val;
3369 }
3373 {
3374 u8 phy_index;
3375 /* Probe for the phy according to the given phy_addr, and execute
3376 * the read request on it
3377 */
3383 }
3384 }
3386 }
3390 {
3391 u8 phy_index;
3392 /* Probe for the phy according to the given phy_addr, and execute
3393 * the write request on it
3394 */
3400 }
3401 }
3403 }
3406 {
3418 /* Figure out path swap value */
3422 else
3428 /* Figure out port swap value */
3432 else
3441 /* Figure out path swap value */
3442 path_swap_ovr =
3447 path_swap =
3449 }
3454 }
3456 }
3460 {
3461 u32 ser_lane;
3465 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
3466 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
3473 /* In Dual-lane mode, two lanes are joined together,
3474 * so in order to configure them, the AER broadcast method is
3475 * used here.
3476 * 0x200 is the broadcast address for lanes 0,1
3477 * 0x201 is the broadcast address for lanes 2,3
3478 */
3483 else
3489 }
3491 /******************************************************************/
3492 /* Internal phy section */
3493 /******************************************************************/
3496 {
3499 /* Set Clause 22 */
3505 /* Set Clause 45 */
3507 }
3510 {
3511 u32 val;
3517 /* reset and unreset the SerDes/XGXS */
3525 DEFAULT_PHY_DEV_ADDR);
3526 }
3529 {
3531 u8 port;
3532 u32 val;
3538 /* reset and unreset the SerDes/XGXS */
3546 }
3550 {
3553 /* Resolve pause mode and advertisement Please refer to Table
3554 * 28B-3 of the 802.3ab-1999 spec
3555 */
3561 else
3563 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3579 }
3581 }
3585 {
3589 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
3591 phy_index++) {
3599 }
3613 SPEED_AUTO_NEG)
3621 }
3622 }
3627 {
3628 u16 val;
3630 /* read modify write pause advertizing */
3635 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3638 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3639 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3641 }
3643 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3644 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3646 }
3649 }
3671 }
3677 }
3682 {
3685 u16 pause_result;
3698 MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP) <<
3699 lane;
3711 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
3714 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
3716 }
3719 MDIO_AN_DEVAD,
3722 MDIO_AN_DEVAD,
3724 }
3732 }
3737 {
3741 /* Update the advertised flow-controled of LD/LP in AN */
3744 /* But set the flow-control result as the requested one */
3751 }
3753 }
3754 /******************************************************************/
3755 /* Warpcore section */
3756 /******************************************************************/
3757 /* The init_internal_warpcore should mirror the xgxs,
3758 * i.e. reset the lane (if needed), set aer for the
3759 * init configuration, and set/clear SGMII flag. Internal
3760 * phy init is done purely in phy_init stage.
3761 */
3768 /* Set to default registers that may be overriden by 10G force */
3785 /* Disable Autoneg: re-enable it after adv is done. */
3789 /* Check adding advertisement for 1G KX */
3793 u16 sd_digital;
3796 /* Enable CL37 1G Parallel Detect */
3800 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3804 }
3808 /* Check adding advertisement for 10G KR */
3810 /* Enable 10G Parallel Detect */
3815 }
3817 /* Set Transmit PMD settings */
3825 MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL,
3828 MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL,
3831 /* Advertised speeds */
3835 /* Advertised and set FEC (Forward Error Correction) */
3837 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2,
3839 MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ));
3841 /* Enable CL37 BAM */
3845 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
3851 }
3853 /* Advertise pause */
3855 /* Set KR Autoneg Work-Around flag for Warpcore version older than D108
3856 */
3862 }
3869 /* Over 1G - AN local device user page 1 */
3873 /* Enable Autoneg */
3877 }
3882 {
3884 u16 val;
3886 /* Disable Autoneg */
3908 /* Disable CL36 PCS Tx */
3912 /* Double Wide Single Data Rate @ pll rate */
3916 /* Leave cl72 training enable, needed for KR */
3918 MDIO_WC_REG_PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150,
3921 /* Leave CL72 enabled */
3923 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3926 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3929 /* Set speed via PMA/PMD register */
3936 /* Enable encoded forced speed */
3940 /* Turn TX scramble payload only the 64/66 scrambler */
3944 /* Turn RX scramble payload only the 64/66 scrambler */
3948 /* set and clear loopback to cause a reset to 64/66 decoder */
3954 }
3958 u8 is_xfi)
3959 {
3962 /* Hold rxSeqStart */
3968 /* Hold tx_fifo_reset */
3974 /* Disable CL73 AN */
3977 /* Disable 100FX Enable and Auto-Detect */
3983 /* Disable 100FX Idle detect */
3989 /* Set Block address to Remote PHY & Clear forced_speed[5] */
3995 /* Turn off auto-detect & fiber mode */
3999 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4002 /* Set filter_force_link, disable_false_link and parallel_detect */
4006 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4009 /* Set XFI / SFI */
4020 tx_driver_val =
4030 tx_driver_val =
4034 }
4038 /* Set Transmit PMD settings */
4041 MDIO_WC_REG_TX_FIR_TAP,
4045 tx_driver_val);
4047 /* Enable fiber mode, enable and invert sig_det */
4053 /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */
4059 /* Enable LPI pass through */
4062 MDIO_WC_REG_EEE_COMBO_CONTROL0,
4067 /* 10G XFI Full Duplex */
4071 /* Release tx_fifo_reset */
4077 /* Release rxSeqStart */
4082 }
4086 {
4088 }
4092 u16 lane)
4093 {
4094 /* Rx0 anaRxControl1G */
4098 /* Rx2 anaRxControl1G */
4126 /* Serdes Digital Misc1 */
4130 /* Serdes Digital4 Misc3 */
4134 /* Set Transmit PMD settings */
4136 MDIO_WC_REG_TX_FIR_TAP,
4140 MDIO_WC_REG_TX_FIR_TAP_ENABLE));
4146 }
4150 u8 fiber_mode,
4151 u8 always_autoneg)
4152 {
4156 /* Clear XFI clock comp in non-10G single lane mode. */
4163 /* SGMII Autoneg */
4167 MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
4187 }
4200 }
4202 /* SGMII Slave mode and disable signal detect */
4207 else
4211 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4212 digctrl_kx1);
4214 /* Turn off parallel detect */
4218 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4221 /* Re-enable parallel detect */
4223 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4226 /* Enable autodet */
4228 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4230 }
4234 u8 reset)
4235 {
4236 u16 val;
4237 /* Take lane out of reset after configuration is finished */
4242 else
4248 }
4249 /* Clear SFI/XFI link settings registers */
4252 u16 lane)
4253 {
4255 u16 val16;
4257 /* Set XFI clock comp as default. */
4289 }
4292 u32 chip_id,
4295 {
4296 u32 cfg_pin;
4303 PORT_HW_CFG_E3_MOD_ABS_MASK) >>
4304 PORT_HW_CFG_E3_MOD_ABS_SHIFT;
4306 /* Should not happen. This function called upon interrupt
4307 * triggered by GPIO ( since EPIO can only generate interrupts
4308 * to MCP).
4309 * So if this function was called and none of the GPIOs was set,
4310 * it means the shit hit the fan.
4311 */
4316 cfg_pin);
4318 }
4325 }
4328 }
4332 {
4335 u32 gpio_val;
4342 /* Call the handling function in case module is detected */
4345 else
4347 }
4350 {
4360 }
4365 {
4367 u32 serdes_net_if;
4376 /* return if there is no link partner */
4380 }
4386 PORT_HW_CFG_NET_SERDES_IF_MASK);
4390 /* Do we get link yet? */
4394 /*10G KR*/
4406 /* Reset the lane to see if link comes up.*/
4410 /* restart Autoneg */
4417 }
4422 }
4426 }
4430 {
4432 u32 serdes_net_if;
4433 u8 fiber_mode;
4438 PORT_HW_CFG_NET_SERDES_IF_MASK);
4456 /* Enable KR Auto Neg */
4462 }
4477 }
4479 params,
4480 fiber_mode,
4482 }
4496 }
4497 /* Issue Module detection */
4506 }
4509 /* Issue Module detection */
4518 }
4526 serdes_net_if);
4528 }
4529 }
4531 /* Take lane out of reset after configuration is finished */
4534 }
4538 u8 tx_en)
4539 {
4541 u32 cfg_pin;
4547 PORT_HW_CFG_TX_LASER_MASK;
4548 /* Set the !tx_en since this pin is DISABLE_TX_LASER */
4550 /* For 20G, the expected pin to be used is 3 pins after the current */
4555 }
4559 {
4561 u16 val16;
4565 /* Global register */
4568 /* Clear loopback settings (if any) */
4569 /* 10G & 20G */
4581 /* Update those 1-copy registers */
4584 /* Enable 1G MDIO (1-copy) */
4586 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4589 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4595 MDIO_WC_REG_XGXSBLK1_LANECTRL2,
4598 }
4602 {
4604 u16 val16;
4605 u32 lane;
4610 /* 10/100/1000 */
4612 /* Update those 1-copy registers */
4615 /* Enable 1G MDIO (1-copy) */
4617 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4620 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4622 /* Set 1G loopback based on lane (1-copy) */
4627 MDIO_WC_REG_XGXSBLK1_LANECTRL2,
4630 /* Switch back to 4-copy registers */
4633 /* 10G & 20G */
4644 }
4645 }
4650 {
4652 u8 link_10g_plus;
4662 LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
4665 /* Fall thru */
4672 /* Fall thru */
4680 /* Fall thru */
4687 /* Fall thru */
4700 }
4717 }
4722 /* anything 10 and over uses the bmac */
4728 else
4733 else
4735 }
4745 /* indicate no mac active */
4749 }
4750 }
4754 {
4758 /* Update PHY configuration */
4767 /* Sync media type */
4775 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT;
4778 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT;
4781 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT;
4784 /* Sync AEU offset */
4791 /* Sync PFC status */
4794 FEATURE_CONFIG_PFC_ENABLED;
4795 else
4803 }
4807 {
4811 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
4812 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
4814 /* set the master_ln for AN */
4816 MDIO_REG_BANK_XGXS_BLOCK2,
4817 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4821 MDIO_REG_BANK_XGXS_BLOCK2 ,
4822 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4824 }
4828 u8 set_serdes)
4829 {
4831 u16 mii_control;
4832 u16 i;
4834 MDIO_REG_BANK_COMBO_IEEE0,
4837 /* reset the unicore */
4839 MDIO_REG_BANK_COMBO_IEEE0,
4840 MDIO_COMBO_IEEE0_MII_CONTROL,
4842 MDIO_COMBO_IEEO_MII_CONTROL_RESET));
4846 /* wait for the reset to self clear */
4850 /* the reset erased the previous bank value */
4852 MDIO_REG_BANK_COMBO_IEEE0,
4853 MDIO_COMBO_IEEE0_MII_CONTROL,
4859 }
4860 }
4868 }
4872 {
4874 /* Each two bits represents a lane number:
4875 * No swap is 0123 => 0x1b no need to enable the swap
4876 */
4880 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
4881 PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
4883 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
4884 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
4888 MDIO_REG_BANK_XGXS_BLOCK2,
4889 MDIO_XGXS_BLOCK2_RX_LN_SWAP,
4891 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
4892 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
4895 MDIO_REG_BANK_XGXS_BLOCK2,
4897 }
4901 MDIO_REG_BANK_XGXS_BLOCK2,
4902 MDIO_XGXS_BLOCK2_TX_LN_SWAP,
4904 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
4907 MDIO_REG_BANK_XGXS_BLOCK2,
4909 }
4910 }
4914 {
4916 u16 control2;
4918 MDIO_REG_BANK_SERDES_DIGITAL,
4919 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4923 else
4928 MDIO_REG_BANK_SERDES_DIGITAL,
4929 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4930 control2);
4934 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
4938 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4939 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
4940 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
4943 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4944 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4948 control2 |=
4949 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
4952 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4953 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4954 control2);
4956 /* Disable parallel detection of HiG */
4958 MDIO_REG_BANK_XGXS_BLOCK2,
4959 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
4960 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
4961 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
4962 }
4963 }
4968 u8 enable_cl73)
4969 {
4971 u16 reg_val;
4973 /* CL37 Autoneg */
4975 MDIO_REG_BANK_COMBO_IEEE0,
4978 /* CL37 Autoneg Enabled */
4983 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
4986 MDIO_REG_BANK_COMBO_IEEE0,
4989 /* Enable/Disable Autodetection */
4992 MDIO_REG_BANK_SERDES_DIGITAL,
4995 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
4999 else
5003 MDIO_REG_BANK_SERDES_DIGITAL,
5006 /* Enable TetonII and BAM autoneg */
5008 MDIO_REG_BANK_BAM_NEXT_PAGE,
5009 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
5012 /* Enable BAM aneg Mode and TetonII aneg Mode */
5014 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
5016 /* TetonII and BAM Autoneg Disabled */
5018 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
5019 }
5021 MDIO_REG_BANK_BAM_NEXT_PAGE,
5022 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
5023 reg_val);
5026 /* Enable Cl73 FSM status bits */
5028 MDIO_REG_BANK_CL73_USERB0,
5029 MDIO_CL73_USERB0_CL73_UCTRL,
5032 /* Enable BAM Station Manager*/
5034 MDIO_REG_BANK_CL73_USERB0,
5035 MDIO_CL73_USERB0_CL73_BAM_CTRL1,
5036 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
5037 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
5038 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
5040 /* Advertise CL73 link speeds */
5042 MDIO_REG_BANK_CL73_IEEEB1,
5043 MDIO_CL73_IEEEB1_AN_ADV2,
5046 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
5049 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
5053 MDIO_REG_BANK_CL73_IEEEB1,
5054 MDIO_CL73_IEEEB1_AN_ADV2,
5055 reg_val);
5057 /* CL73 Autoneg Enabled */
5064 MDIO_REG_BANK_CL73_IEEEB0,
5066 }
5068 /* program SerDes, forced speed */
5072 {
5074 u16 reg_val;
5076 /* program duplex, disable autoneg and sgmii*/
5078 MDIO_REG_BANK_COMBO_IEEE0,
5081 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5082 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
5086 MDIO_REG_BANK_COMBO_IEEE0,
5089 /* Program speed
5090 * - needed only if the speed is greater than 1G (2.5G or 10G)
5091 */
5093 MDIO_REG_BANK_SERDES_DIGITAL,
5095 /* clearing the speed value before setting the right speed */
5099 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
5106 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
5108 reg_val |=
5109 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
5110 }
5113 MDIO_REG_BANK_SERDES_DIGITAL,
5116 }
5120 {
5124 /* set extended capabilities */
5130 MDIO_REG_BANK_OVER_1G,
5134 MDIO_REG_BANK_OVER_1G,
5136 }
5140 u16 ieee_fc)
5141 {
5143 u16 val;
5144 /* for AN, we are always publishing full duplex */
5147 MDIO_REG_BANK_COMBO_IEEE0,
5150 MDIO_REG_BANK_CL73_IEEEB1,
5155 MDIO_REG_BANK_CL73_IEEEB1,
5157 }
5161 u8 enable_cl73)
5162 {
5164 u16 mii_control;
5167 /* Enable and restart BAM/CL37 aneg */
5171 MDIO_REG_BANK_CL73_IEEEB0,
5172 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5176 MDIO_REG_BANK_CL73_IEEEB0,
5177 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5179 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
5180 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
5184 MDIO_REG_BANK_COMBO_IEEE0,
5185 MDIO_COMBO_IEEE0_MII_CONTROL,
5189 mii_control);
5191 MDIO_REG_BANK_COMBO_IEEE0,
5192 MDIO_COMBO_IEEE0_MII_CONTROL,
5194 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5195 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
5196 }
5197 }
5202 {
5204 u16 control1;
5206 /* in SGMII mode, the unicore is always slave */
5209 MDIO_REG_BANK_SERDES_DIGITAL,
5210 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
5213 /* set sgmii mode (and not fiber) */
5215 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
5216 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
5218 MDIO_REG_BANK_SERDES_DIGITAL,
5219 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
5220 control1);
5222 /* if forced speed */
5224 /* set speed, disable autoneg */
5225 u16 mii_control;
5228 MDIO_REG_BANK_COMBO_IEEE0,
5229 MDIO_COMBO_IEEE0_MII_CONTROL,
5232 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
5233 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
5237 mii_control |=
5238 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
5241 mii_control |=
5242 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
5245 /* there is nothing to set for 10M */
5248 /* invalid speed for SGMII */
5252 }
5254 /* setting the full duplex */
5256 mii_control |=
5257 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
5259 MDIO_REG_BANK_COMBO_IEEE0,
5260 MDIO_COMBO_IEEE0_MII_CONTROL,
5261 mii_control);
5264 /* enable and restart AN */
5266 }
5267 }
5269 /* Link management
5270 */
5273 {
5279 MDIO_REG_BANK_SERDES_DIGITAL,
5280 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
5283 MDIO_REG_BANK_SERDES_DIGITAL,
5284 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
5290 }
5293 MDIO_REG_BANK_10G_PARALLEL_DETECT,
5294 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
5301 }
5303 }
5308 u32 gp_status)
5309 {
5312 u16 pause_result;
5316 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
5318 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
5321 MDIO_REG_BANK_CL73_IEEEB1,
5322 MDIO_CL73_IEEEB1_AN_ADV1,
5325 MDIO_REG_BANK_CL73_IEEEB1,
5326 MDIO_CL73_IEEEB1_AN_LP_ADV1,
5335 MDIO_REG_BANK_COMBO_IEEE0,
5336 MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
5339 MDIO_REG_BANK_COMBO_IEEE0,
5340 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
5347 }
5350 }
5355 u32 gp_status)
5356 {
5360 /* resolve from gp_status in case of AN complete and not sgmii */
5362 /* Update the advertised flow-controled of LD/LP in AN */
5365 /* But set the flow-control result as the requested one */
5374 }
5376 }
5378 }
5382 {
5386 /* Step 1: Make sure signal is detected */
5388 MDIO_REG_BANK_RX0,
5389 MDIO_RX0_RX_STATUS,
5396 MDIO_REG_BANK_CL73_IEEEB0,
5397 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5398 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
5400 }
5401 /* Step 2: Check CL73 state machine */
5403 MDIO_REG_BANK_CL73_USERB0,
5404 MDIO_CL73_USERB0_CL73_USTAT1,
5408 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
5410 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
5414 }
5415 /* Step 3: Check CL37 Message Pages received to indicate LP
5416 * supports only CL37
5417 */
5419 MDIO_REG_BANK_REMOTE_PHY,
5420 MDIO_REMOTE_PHY_MISC_RX_STATUS,
5424 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
5426 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
5429 cl37_fsm_received);
5431 }
5432 /* The combined cl37/cl73 fsm state information indicating that
5433 * we are connected to a device which does not support cl73, but
5434 * does support cl37 BAM. In this case we disable cl73 and
5435 * restart cl37 auto-neg
5436 */
5438 /* Disable CL73 */
5440 MDIO_REG_BANK_CL73_IEEEB0,
5441 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5443 /* Restart CL37 autoneg */
5446 }
5451 u32 gp_status)
5452 {
5455 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5459 LINK_STATUS_PARALLEL_DETECTION_USED;
5460 }
5464 u16 is_link_up,
5465 u16 speed_mask,
5466 u16 is_duplex)
5467 {
5482 else
5490 else
5499 else
5507 else
5515 speed_mask);
5534 speed_mask);
5536 }
5545 }
5549 }
5554 {
5560 /* Read gp_status */
5562 MDIO_REG_BANK_GP_STATUS,
5563 MDIO_GP_STATUS_TOP_AN_STATUS1,
5573 duplex);
5582 gp_status);
5583 }
5587 /* Check signal is detected */
5589 }
5590 }
5592 /* Read LP advertised speeds*/
5595 u16 val;
5602 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
5604 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
5606 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5613 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
5616 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5617 }
5622 }
5627 {
5629 u8 lane;
5633 /* Read gp_status */
5635 u16 temp_link_up;
5649 /* Check for either KR or generic link up. */
5656 /* Check Autoneg complete */
5658 MDIO_WC_REG_GP2_STATUS_GP_2_4,
5662 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5664 /* Check parallel detect used */
5666 MDIO_WC_REG_PAR_DET_10G_STATUS,
5670 LINK_STATUS_PARALLEL_DETECTION_USED;
5671 }
5673 }
5674 }
5678 u16 val;
5685 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
5687 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
5689 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5696 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
5699 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5701 }
5710 }
5719 duplex);
5724 }
5726 {
5729 u16 lp_up2;
5730 u16 tx_driver;
5731 u16 bank;
5733 /* read precomp */
5735 MDIO_REG_BANK_OVER_1G,
5738 /* bits [10:7] at lp_up2, positioned at [15:12] */
5740 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
5741 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
5749 bank,
5752 /* replace tx_driver bits [15:12] */
5758 bank,
5760 }
5761 }
5762 }
5766 {
5773 EMAC_REG_EMAC_MODE,
5775 EMAC_MODE_PORT_MII_10M |
5776 EMAC_MODE_HALF_DUPLEX));
5795 /* 10G not valid for EMAC */
5799 }
5805 mode);
5809 }
5813 {
5821 bank,
5822 MDIO_RX0_RX_EQ_BOOST,
5824 }
5829 bank,
5830 MDIO_TX0_TX_DRIVER,
5832 }
5833 }
5838 {
5845 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
5848 /* forced speed requested? */
5854 /* disable autoneg */
5857 /* program speed and duplex */
5863 /* AN enabled */
5866 /* program duplex & pause advertisement (for aneg) */
5870 /* enable autoneg */
5873 /* enable and restart AN */
5875 }
5881 }
5882 }
5887 {
5895 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
5897 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
5900 else
5909 /* reset the SerDes and wait for reset bit return low */
5914 /* setting the masterLn_def again after the reset */
5918 }
5921 }
5926 {
5928 /* Wait for soft reset to get cleared up to 1 sec */
5933 else
5935 MDIO_PMA_DEVAD,
5940 }
5948 }
5951 {
5953 u32 mask;
5956 /* Setting the status to report on link up for either XGXS or SerDes */
5963 NIG_MASK_XGXS0_LINK_STATUS);
5967 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
5970 }
5977 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
5980 }
5981 }
5984 mask);
5996 }
5999 u8 exp_mi_int)
6000 {
6003 /* Disable the MI INT ( external phy int ) by writing 1 to the
6004 * status register. Link down indication is high-active-signal,
6005 * so in this case we need to write the status to clear the XOR
6006 */
6007 /* Read Latched signals */
6011 /* Handle only those with latched-signal=up.*/
6014 NIG_REG_STATUS_INTERRUPT_PORT0
6016 NIG_STATUS_EMAC0_MI_INT);
6017 else
6019 NIG_REG_STATUS_INTERRUPT_PORT0
6021 NIG_STATUS_EMAC0_MI_INT);
6025 /* For all latched-signal=up : Re-Arm Latch signals */
6028 }
6029 /* For all latched-signal=up,Write original_signal to status */
6030 }
6034 {
6037 u32 mask;
6038 /* First reset all status we assume only one line will be
6039 * change at a time
6040 */
6043 NIG_STATUS_XGXS0_LINK_STATUS |
6044 NIG_STATUS_SERDES0_LINK_STATUS));
6052 /* Disable the link interrupt by writing 1 to
6053 * the relevant lane in the status register
6054 */
6055 u32 ser_lane =
6057 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
6058 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
6060 NIG_STATUS_XGXS0_LINK_STATUS_SIZE);
6063 }
6065 mask);
6068 mask);
6069 }
6070 }
6073 {
6077 u8 digit;
6080 /* Need more than 10chars for this format */
6084 }
6094 else
6097 str_ptr++;
6102 str_ptr++;
6105 }
6106 }
6108 }
6112 {
6116 }
6119 u16 len)
6120 {
6130 /* Extract first external phy*/
6136 ver_p,
6139 }
6145 ver_p++;
6146 remain_len--;
6148 spirom_ver,
6149 ver_p,
6152 }
6153 }
6156 }
6160 {
6170 /* change the uni_phy_addr in the nig */
6176 }
6190 /* set aer mmd back */
6194 /* and md_devad */
6196 md_devad);
6197 }
6199 u16 mii_ctrl;
6208 mii_ctrl |
6209 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
6210 }
6211 }
6215 {
6219 u8 phy_idx;
6220 u32 tmp;
6226 /* In case */
6231 }
6232 }
6239 SHARED_HW_CFG_LED_MAC1);
6243 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
6245 EMAC_LED_100MB_OVERRIDE |
6246 EMAC_LED_10MB_OVERRIDE);
6247 else
6254 /* For all other phys, OPER mode is same as ON, so in case
6255 * link is down, do nothing
6256 */
6261 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) ||
6263 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) &&
6265 /* This is a work-around for E2+8727 Configurations */
6274 /* Return here without enabling traffic
6275 * LED blink and setting rate in ON mode.
6276 * In oper mode, enabling LED blink
6277 * and setting rate is needed.
6278 */
6281 }
6283 /* This is a work-around for HW issue found when link
6284 * is up in CL73
6285 */
6295 else
6297 hw_led_mode);
6299 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) &&
6305 /* Break here; otherwise, it'll disable the
6306 * intended override.
6307 */
6311 hw_led_mode);
6314 /* Set blinking rate to ~15.9Hz */
6317 LED_BLINK_RATE_VAL_E3);
6318 else
6320 LED_BLINK_RATE_VAL_E1X_E2);
6332 /* For speeds less than 10G LED scheme is different */
6339 }
6345 mode);
6347 }
6350 }
6352 /* This function comes to reflect the actual link state read DIRECTLY from the
6353 * HW
6354 */
6356 u8 is_serdes)
6357 {
6365 u16 link_up;
6368 /* Check 20G link */
6375 /* Check 10G link and below*/
6378 MDIO_WC_REG_GP2_STATUS_GP_2_1,
6383 }
6388 MDIO_REG_BANK_GP_STATUS,
6389 MDIO_GP_STATUS_TOP_AN_STATUS1,
6391 /* link is up only if both local phy and external phy are up */
6394 }
6395 /* In XGXS loopback mode, do not check external PHY */
6401 /* No external PHY */
6410 phy_index++) {
6412 ETH_PHY_SFP_FIBER) ||
6414 ETH_PHY_XFP_FIBER) ||
6416 ETH_PHY_DA_TWINAX));
6421 ext_phy_link_up |=
6425 }
6426 }
6428 }
6432 }
6436 {
6440 /* In case of external phy existence, the line speed would be the
6441 * line speed linked up by the external phy. In case it is direct
6442 * only, then the line_speed during initialization will be
6443 * equal to the req_line_speed
6444 */
6447 /* Initialize the internal phy in case this is a direct board
6448 * (no external phys), or this board has external phy which requires
6449 * to first.
6450 */
6453 /* init ext phy and enable link state int */
6467 params,
6468 vars);
6469 }
6471 /* Init external phy*/
6474 SUPPORTED_FIBRE)
6478 phy_index++) {
6479 /* No need to initialize second phy in case of first
6480 * phy only selection. In case of second phy, we do
6481 * need to initialize the first phy, since they are
6482 * connected.
6483 */
6485 SUPPORTED_FIBRE)
6490 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
6494 }
6498 }
6499 }
6500 /* Reset the interrupt indication after phy was initialized */
6504 NIG_STATUS_XGXS0_LINK_STATUS |
6505 NIG_STATUS_SERDES0_LINK_STATUS |
6506 NIG_MASK_MI_INT));
6508 }
6512 {
6513 /* reset the SerDes/XGXS */
6516 }
6520 {
6522 u8 gpio_port;
6523 /* HW reset */
6526 else
6529 MISC_REGISTERS_GPIO_OUTPUT_LOW,
6530 gpio_port);
6532 MISC_REGISTERS_GPIO_OUTPUT_LOW,
6533 gpio_port);
6535 }
6539 {
6546 /* indicate no mac active */
6549 /* update shared memory */
6551 LINK_STATUS_LINK_UP |
6552 LINK_STATUS_PHYSICAL_LINK_FLAG |
6553 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE |
6554 LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK |
6555 LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK |
6556 LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK |
6557 LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE |
6558 LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE);
6562 /* activate nig drain */
6565 /* disable emac */
6570 /* reset BigMac/Xmac */
6575 MISC_REGISTERS_RESET_REG_2_CLEAR,
6577 }
6585 SHMEM_EEE_ACTIVE_BIT);
6590 }
6593 }
6597 u8 link_10g)
6598 {
6604 LINK_STATUS_PHYSICAL_LINK_FLAG);
6609 LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
6613 LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
6622 }
6636 }
6637 }
6647 }
6655 /* AN complete? */
6657 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
6661 }
6662 }
6664 /* PBF - link up */
6669 /* disable drain */
6672 /* update shared memory */
6675 /* Check remote fault */
6680 }
6681 }
6684 }
6685 /* The bnx2x_link_update function should be called upon link
6686 * interrupt.
6687 * Link is considered up as follows:
6688 * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
6689 * to be up
6690 * - SINGLE_MEDIA - The link between the 577xx and the external
6691 * phy (XGXS) need to up as well as the external link of the
6692 * phy (PHY_EXT1)
6693 * - DUAL_MEDIA - The link between the 577xx and the first
6694 * external phy needs to be up, and at least one of the 2
6695 * external phy link must be up.
6696 */
6698 {
6710 phy_index++) {
6718 /* different consideration, since vars holds inner state */
6720 }
6733 is_mi_int,
6740 /* disable emac */
6744 /* Step 1:
6745 * Check external link change only for external phys, and apply
6746 * priority selection between them in case the link on both phys
6747 * is up. Note that instead of the common vars, a temporary
6748 * vars argument is used since each phy may have different link/
6749 * speed/duplex result
6750 */
6752 phy_index++) {
6756 /* Read link status and params of this ext phy */
6761 phy_index);
6764 phy_index);
6766 }
6775 /* In this option, the first PHY makes sure to pass the
6776 * traffic through itself only.
6777 * Its not clear how to reset the link on the second phy
6778 */
6782 /* In this option, the first PHY makes sure to pass the
6783 * traffic through the second PHY.
6784 */
6788 /* Link indication on both PHYs with the following cases
6789 * is invalid:
6790 * - FIRST_PHY means that second phy wasn't initialized,
6791 * hence its link is expected to be down
6792 * - SECOND_PHY means that first phy should not be able
6793 * to link up by itself (using configuration)
6794 * - DEFAULT should be overriden during initialiazation
6795 */
6801 }
6802 }
6803 }
6805 /* Step 2:
6806 * Read the status of the internal phy. In case of
6807 * DIRECT_SINGLE_MEDIA board, this link is the external link,
6808 * otherwise this is the link between the 577xx and the first
6809 * external phy
6810 */
6815 /* The INT_PHY flow control reside in the vars. This include the
6816 * case where the speed or flow control are not set to AUTO.
6817 * Otherwise, the active external phy flow control result is set
6818 * to the vars. The ext_phy_line_speed is needed to check if the
6819 * speed is different between the internal phy and external phy.
6820 * This case may be result of intermediate link speed change.
6821 */
6824 /* Link speed is taken from the XGXS. AN and FC result from
6825 * the external phy.
6826 */
6829 /* if active_external_phy is first PHY and link is up - disable
6830 * disable TX on second external PHY
6831 */
6839 }
6840 }
6845 SUPPORTED_FIBRE)
6847 else
6853 active_external_phy);
6854 }
6857 phy_index++) {
6859 FLAGS_REARM_LATCH_SIGNAL) {
6861 phy_index ==
6862 active_external_phy);
6864 }
6865 }
6869 /* Upon link speed change set the NIG into drain mode. Comes to
6870 * deals with possible FIFO glitch due to clk change when speed
6871 * is decreased without link down indicator
6872 */
6878 " different than the external"
6880 ext_phy_line_speed);
6886 }
6887 }
6889 /* anything 10 and over uses the bmac */
6894 /* In case external phy link is up, and internal link is down
6895 * (not initialized yet probably after link initialization, it
6896 * needs to be initialized.
6897 * Note that after link down-up as result of cable plug, the xgxs
6898 * link would probably become up again without the need
6899 * initialize it
6900 */
6906 FLAGS_INIT_XGXS_FIRST);
6908 FLAGS_INIT_XGXS_FIRST)
6913 else
6919 vars);
6920 }
6921 }
6922 /* Link is up only if both local phy and external phy (in case of
6923 * non-direct board) are up and no fault detected on active PHY.
6924 */
6930 /* Update the PFC configuration in case it was changed */
6933 else
6938 else
6941 /* Update MCP link status was changed */
6946 }
6948 /*****************************************************************************/
6949 /* External Phy section */
6950 /*****************************************************************************/
6952 {
6958 }
6962 {
6968 }
6972 u8 port)
6973 {
6982 }
6987 {
6988 u16 val;
6990 MDIO_AN_DEVAD,
6993 MDIO_AN_DEVAD,
6999 }
7001 /******************************************************************/
7002 /* common BCM8073/BCM8727 PHY SECTION */
7003 /******************************************************************/
7007 {
7013 }
7017 u16 pause_result;
7021 MDIO_AN_DEVAD,
7025 MDIO_AN_DEVAD,
7034 pause_result);
7035 }
7036 }
7039 u8 port)
7040 {
7045 /* Boot port from external ROM */
7046 /* EDC grst */
7048 MDIO_PMA_DEVAD,
7049 MDIO_PMA_REG_GEN_CTRL,
7052 /* ucode reboot and rst */
7054 MDIO_PMA_DEVAD,
7055 MDIO_PMA_REG_GEN_CTRL,
7059 MDIO_PMA_DEVAD,
7062 /* Reset internal microprocessor */
7064 MDIO_PMA_DEVAD,
7065 MDIO_PMA_REG_GEN_CTRL,
7066 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
7068 /* Release srst bit */
7070 MDIO_PMA_DEVAD,
7071 MDIO_PMA_REG_GEN_CTRL,
7072 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
7074 /* Delay 100ms per the PHY specifications */
7077 /* 8073 sometimes taking longer to download */
7079 count++;
7082 "bnx2x_8073_8727_external_rom_boot port %x:"
7087 }
7090 MDIO_PMA_DEVAD,
7093 MDIO_PMA_DEVAD,
7099 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)));
7101 /* Clear ser_boot_ctl bit */
7103 MDIO_PMA_DEVAD,
7108 "bnx2x_8073_8727_external_rom_boot port %x:"
7113 }
7115 /******************************************************************/
7116 /* BCM8073 PHY SECTION */
7117 /******************************************************************/
7119 {
7120 /* This is only required for 8073A1, version 102 only */
7121 u16 val;
7123 /* Read 8073 HW revision*/
7125 MDIO_PMA_DEVAD,
7129 /* No need to workaround in 8073 A1 */
7131 }
7134 MDIO_PMA_DEVAD,
7137 /* SNR should be applied only for version 0x102 */
7142 }
7145 {
7149 MDIO_PMA_DEVAD,
7153 /* No need to workaround in 8073 A1 */
7155 }
7156 /* XAUI workaround in 8073 A0: */
7158 /* After loading the boot ROM and restarting Autoneg, poll
7159 * Dev1, Reg $C820:
7160 */
7164 MDIO_PMA_DEVAD,
7165 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7167 /* If bit [14] = 0 or bit [13] = 0, continue on with
7168 * system initialization (XAUI work-around not required, as
7169 * these bits indicate 2.5G or 1G link up).
7170 */
7176 /* If bit 15 is 0, then poll Dev1, Reg $C841 until it's
7177 * MSB (bit15) goes to 1 (indicating that the XAUI
7178 * workaround has completed), then continue on with
7179 * system initialization.
7180 */
7183 MDIO_PMA_DEVAD,
7189 }
7191 }
7193 }
7195 }
7198 }
7201 {
7202 /* Force KR or KX */
7211 }
7216 {
7217 u16 cl37_val;
7223 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
7226 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
7227 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
7229 }
7231 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
7232 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
7234 }
7236 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
7237 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
7239 }
7246 }
7251 {
7254 u8 gpio_port;
7259 else
7261 /* Restore normal power mode*/
7268 /* enable LASI */
7284 /* Swap polarity if required - Must be done only in non-1G mode */
7286 /* Configure the 8073 to swap _P and _N of the KR lines */
7288 /* 10G Rx/Tx and 1G Tx signal polarity swap */
7290 MDIO_PMA_DEVAD,
7293 MDIO_PMA_DEVAD,
7294 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL,
7296 }
7299 /* Enable CL37 BAM */
7303 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
7306 MDIO_AN_DEVAD,
7309 MDIO_AN_DEVAD,
7312 }
7320 }
7326 /* Note that 2.5G works only when used with 1G
7327 * advertisement
7328 */
7334 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
7337 /* Note that 2.5G works only when used with 1G advertisement */
7340 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
7343 }
7351 u16 phy_ver;
7352 /* Allow 2.5G for A1 and above */
7359 else
7364 }
7367 /* Add support for CL37 (passive mode) II */
7374 /* Add support for CL37 (passive mode) III */
7377 /* The SNR will improve about 2db by changing BW and FEE main
7378 * tap. Rest commands are executed after link is up
7379 * Change FFE main cursor to 5 in EDC register
7380 */
7386 /* Enable FEC (Forware Error Correction) Request in the AN */
7393 /* Restart autoneg */
7399 }
7404 {
7416 /* clear the interrupt LASI status register */
7422 /* Clear MSG-OUT */
7426 /* Check the LASI */
7432 /* Check the link status */
7448 }
7454 /* Check the link status on 1.1.2 */
7464 /* The SNR will improve about 2dbby changing the BW and FEE main
7465 * tap. The 1st write to change FFE main tap is set before
7466 * restart AN. Change PLL Bandwidth in EDC register
7467 */
7472 /* Change CDR Bandwidth in EDC register */
7476 }
7481 /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
7501 }
7504 /* Swap polarity if required */
7506 PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7507 /* Configure the 8073 to swap P and N of the KR lines */
7509 MDIO_XS_DEVAD,
7511 /* Set bit 3 to invert Rx in 1G mode and clear this bit
7512 * when it`s in 10G mode.
7513 */
7522 MDIO_XS_DEVAD,
7523 MDIO_XS_REG_8073_RX_CTRL_PCIE,
7524 val1);
7525 }
7529 }
7537 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
7540 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
7541 }
7544 }
7548 {
7550 u8 gpio_port;
7553 else
7556 gpio_port);
7558 MISC_REGISTERS_GPIO_OUTPUT_LOW,
7559 gpio_port);
7560 }
7562 /******************************************************************/
7563 /* BCM8705 PHY SECTION */
7564 /******************************************************************/
7568 {
7571 /* Restore normal power mode*/
7574 /* HW reset */
7587 /* BCM8705 doesn't have microcode, hence the 0 */
7590 }
7595 {
7621 }
7623 }
7625 /******************************************************************/
7626 /* SFP+ module Section */
7627 /******************************************************************/
7630 u8 pmd_dis)
7631 {
7633 /* Disable transmitter only for bootcodes which can enable it afterwards
7634 * (for D3 link)
7635 */
7638 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED)
7643 }
7647 MDIO_PMA_DEVAD,
7649 }
7652 {
7653 u8 gpio_port;
7658 else
7663 }
7667 u8 tx_en)
7668 {
7669 u16 val;
7672 u32 tx_en_mode;
7674 /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
7678 PORT_HW_CFG_TX_LASER_MASK;
7685 MDIO_PMA_DEVAD,
7686 MDIO_PMA_REG_PHY_IDENTIFIER,
7691 else
7695 MDIO_PMA_DEVAD,
7696 MDIO_PMA_REG_PHY_IDENTIFIER,
7697 val);
7703 {
7704 u16 gpio_pin;
7708 else
7715 }
7719 }
7720 }
7724 u8 tx_en)
7725 {
7730 else
7732 }
7737 {
7740 u16 i;
7745 }
7746 /* Set the read command byte count */
7751 /* Set the read command address */
7754 addr);
7756 /* Activate read command */
7761 /* Wait up to 500us for command complete status */
7764 MDIO_PMA_DEVAD,
7767 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7770 }
7773 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7778 }
7780 /* Read the buffer */
7783 MDIO_PMA_DEVAD,
7786 }
7790 MDIO_PMA_DEVAD,
7793 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7796 }
7798 }
7804 {
7808 u16 addr32;
7814 }
7816 /* 4 byte aligned address */
7820 data_array);
7826 j++;
7827 }
7828 }
7831 }
7836 {
7844 }
7846 /* Need to read from 1.8000 to clear it */
7848 MDIO_PMA_DEVAD,
7849 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7852 /* Set the read command byte count */
7854 MDIO_PMA_DEVAD,
7855 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7858 /* Set the read command address */
7860 MDIO_PMA_DEVAD,
7861 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7862 addr);
7863 /* Set the destination address */
7865 MDIO_PMA_DEVAD,
7867 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
7869 /* Activate read command */
7871 MDIO_PMA_DEVAD,
7872 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7874 /* Wait appropriate time for two-wire command to finish before
7875 * polling the status register
7876 */
7879 /* Wait up to 500us for command complete status */
7882 MDIO_PMA_DEVAD,
7885 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7888 }
7891 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7896 }
7898 /* Read the buffer */
7901 MDIO_PMA_DEVAD,
7904 }
7908 MDIO_PMA_DEVAD,
7911 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7914 }
7917 }
7922 {
7938 }
7940 }
7945 {
7952 /* First check for copper cable */
7954 params,
7955 SFP_EEPROM_CON_TYPE_ADDR,
7960 }
7964 {
7965 u8 copper_module_type;
7967 /* Check if its active cable (includes SFP+ module)
7968 * of passive cable
7969 */
7971 params,
7972 SFP_EEPROM_FC_TX_TECH_ADDR,
7976 "Failed to read copper-cable-type"
7979 }
7982 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
7986 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
7990 EDC_MODE_PASSIVE_DAC;
7994 copper_module_type);
7996 }
7998 }
8006 val);
8008 }
8013 /* Update media type for non-PMF sync */
8019 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
8022 }
8023 }
8028 params,
8029 SFP_EEPROM_OPTIONS_ADDR,
8030 SFP_EEPROM_OPTIONS_SIZE,
8035 }
8038 else
8040 }
8043 }
8044 /* This function read the relevant field from the module (SFP+), and verify it
8045 * is compliant with this board
8046 */
8049 {
8060 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
8063 }
8066 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) {
8067 /* Use specific phy request */
8070 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
8071 /* Use first phy request only in case of non-dual media*/
8076 }
8079 /* No support in OPT MDL detection */
8083 }
8090 }
8092 /* format the warning message */
8094 params,
8095 SFP_EEPROM_VENDOR_NAME_ADDR,
8096 SFP_EEPROM_VENDOR_NAME_SIZE,
8099 else
8102 params,
8103 SFP_EEPROM_PART_NO_ADDR,
8104 SFP_EEPROM_PART_NO_SIZE,
8107 else
8114 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG)
8117 }
8122 {
8123 u8 val;
8125 u16 timeout;
8126 /* Initialization time after hot-plug may take up to 300ms for
8127 * some phys type ( e.g. JDSU )
8128 */
8137 }
8139 }
8141 }
8145 u8 is_power_up) {
8146 /* Make sure GPIOs are not using for LED mode */
8147 u16 val;
8148 /* In the GPIO register, bit 4 is use to determine if the GPIOs are
8149 * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
8150 * output
8151 * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0
8152 * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1
8153 * where the 1st bit is the over-current(only input), and 2nd bit is
8154 * for power( only output )
8155 *
8156 * In case of NOC feature is disabled and power is up, set GPIO control
8157 * as input to enable listening of over-current indication
8158 */
8163 else
8164 /* Set GPIO control to OUTPUT, and set the power bit
8165 * to according to the is_power_up
8166 */
8170 MDIO_PMA_DEVAD,
8171 MDIO_PMA_REG_8727_GPIO_CTRL,
8172 val);
8173 }
8177 u16 edc_mode)
8178 {
8179 u16 cur_limiting_mode;
8182 MDIO_PMA_DEVAD,
8183 MDIO_PMA_REG_ROM_VER2,
8186 cur_limiting_mode);
8191 MDIO_PMA_DEVAD,
8192 MDIO_PMA_REG_ROM_VER2,
8193 EDC_MODE_LIMITING);
8198 /* Changing to LRM mode takes quite few seconds. So do it only
8199 * if current mode is limiting (default is LRM)
8200 */
8205 MDIO_PMA_DEVAD,
8206 MDIO_PMA_REG_LRM_MODE,
8209 MDIO_PMA_DEVAD,
8210 MDIO_PMA_REG_ROM_VER2,
8213 MDIO_PMA_DEVAD,
8214 MDIO_PMA_REG_MISC_CTRL0,
8217 MDIO_PMA_DEVAD,
8218 MDIO_PMA_REG_LRM_MODE,
8220 }
8222 }
8226 u16 edc_mode)
8227 {
8228 u16 phy_identifier;
8229 u16 rom_ver2_val;
8231 MDIO_PMA_DEVAD,
8232 MDIO_PMA_REG_PHY_IDENTIFIER,
8236 MDIO_PMA_DEVAD,
8237 MDIO_PMA_REG_PHY_IDENTIFIER,
8241 MDIO_PMA_DEVAD,
8242 MDIO_PMA_REG_ROM_VER2,
8244 /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
8246 MDIO_PMA_DEVAD,
8247 MDIO_PMA_REG_ROM_VER2,
8251 MDIO_PMA_DEVAD,
8252 MDIO_PMA_REG_PHY_IDENTIFIER,
8256 }
8260 u32 action)
8261 {
8274 action);
8276 }
8277 }
8280 u8 gpio_mode)
8281 {
8287 PORT_HW_CFG_FAULT_MODULE_LED_MASK;
8295 {
8298 PORT_HW_CFG_FAULT_MODULE_LED_GPIO0;
8303 }
8307 fault_led_gpio);
8308 }
8309 }
8312 u8 gpio_mode)
8313 {
8314 u32 pin_cfg;
8320 PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >>
8321 PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT;
8325 }
8328 u8 gpio_mode)
8329 {
8333 /* Low ==> if SFP+ module is supported otherwise
8334 * High ==> if SFP+ module is not on the approved vendor list
8335 */
8339 }
8343 u8 power)
8344 {
8345 u32 pin_cfg;
8351 PORT_HW_CFG_E3_PWR_DIS_MASK) >>
8352 PORT_HW_CFG_E3_PWR_DIS_SHIFT;
8358 /* Low ==> corresponding SFP+ module is powered
8359 * high ==> the SFP+ module is powered down
8360 */
8362 }
8366 {
8369 /* Put Warpcore in low power mode */
8372 /* Put LCPLL in low power mode */
8376 }
8380 u8 power)
8381 {
8395 }
8396 }
8399 u16 edc_mode)
8400 {
8406 /* This is a global register which controls all lanes */
8421 }
8426 /* A must read */
8430 /* Restart microcode to re-read the new mode */
8434 }
8438 u16 edc_mode)
8439 {
8451 }
8452 }
8456 {
8458 u16 edc_mode;
8467 /* Power up module */
8473 /* check SFP+ module compatibility */
8476 /* Turn on fault module-detected led */
8478 MISC_REGISTERS_GPIO_HIGH);
8480 /* Check if need to power down the SFP+ module */
8482 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) {
8486 }
8488 /* Turn off fault module-detected led */
8490 }
8492 /* Check and set limiting mode / LRM mode on 8726. On 8727 it
8493 * is done automatically
8494 */
8497 /* Enable transmit for this module if the module is approved, or
8498 * if unapproved modules should also enable the Tx laser
8499 */
8502 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
8504 else
8508 }
8511 {
8514 u32 gpio_val;
8518 else
8526 }
8528 /* Set valid module led off */
8531 /* Get current gpio val reflecting module plugged in / out*/
8534 /* Call the handling function in case module is detected */
8538 MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
8539 gpio_port);
8542 else
8548 config));
8550 MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
8551 gpio_port);
8552 /* Module was plugged out.
8553 * Disable transmit for this module
8554 */
8557 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER) ||
8560 }
8561 }
8563 /******************************************************************/
8564 /* Used by 8706 and 8727 */
8565 /******************************************************************/
8568 u16 alarm_status_offset,
8569 u16 alarm_ctrl_offset)
8570 {
8578 /* Mask or enable the fault event. */
8582 else
8585 }
8586 /******************************************************************/
8587 /* common BCM8706/BCM8726 PHY SECTION */
8588 /******************************************************************/
8592 {
8597 /* Clear RX Alarm*/
8602 MDIO_PMA_LASI_TXCTRL);
8604 /* clear LASI indication*/
8622 /* Link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
8623 * are set, or if the autoneg bit 1 is set
8624 */
8629 else
8633 }
8635 /* Capture 10G link fault. Read twice to clear stale value. */
8643 }
8646 }
8648 /******************************************************************/
8649 /* BCM8706 PHY SECTION */
8650 /******************************************************************/
8654 {
8655 u32 tx_en_mode;
8661 /* HW reset */
8666 /* Wait until fw is loaded */
8673 }
8676 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8677 u8 i;
8678 u16 reg;
8682 MDIO_XS_8706_REG_BANK_RX0);
8684 /* Clear first 3 bits of the control */
8686 /* Set control bits according to configuration */
8691 }
8692 }
8693 /* Force speed */
8698 MDIO_PMA_DEVAD,
8703 /* Arm LASI for link and Tx fault. */
8707 /* Force 1Gbps using autoneg with 1G advertisement */
8709 /* Allow CL37 through CL73 */
8714 /* Enable Full-Duplex advertisement on CL37 */
8717 /* Enable CL37 AN */
8720 /* 1G support */
8724 /* Enable clause 73 AN */
8733 }
8736 /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
8737 * power mode, if TX Laser is disabled
8738 */
8752 }
8755 }
8760 {
8762 }
8764 /******************************************************************/
8765 /* BCM8726 PHY SECTION */
8766 /******************************************************************/
8769 {
8773 }
8777 {
8779 /* Need to wait 100ms after reset */
8782 /* Micro controller re-boot */
8786 /* Set soft reset */
8788 MDIO_PMA_DEVAD,
8789 MDIO_PMA_REG_GEN_CTRL,
8790 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
8793 MDIO_PMA_DEVAD,
8797 MDIO_PMA_DEVAD,
8798 MDIO_PMA_REG_GEN_CTRL,
8799 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
8801 /* wait for 150ms for microcode load */
8804 /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
8806 MDIO_PMA_DEVAD,
8811 }
8816 {
8818 u16 val1;
8828 }
8829 }
8831 }
8837 {
8846 /* Need to call module detected on initialization since the module
8847 * detection triggered by actual module insertion might occur before
8848 * driver is loaded, and when driver is loaded, it reset all
8849 * registers, including the transmitter
8850 */
8866 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
8868 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
8869 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8871 /* Set Flow control */
8883 /* Enable RX-ALARM control to receive interrupt for 1G speed
8884 * change
8885 */
8895 }
8897 /* Set TX PreEmphasis if needed */
8899 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8905 MDIO_PMA_DEVAD,
8906 MDIO_PMA_REG_8726_TX_CTRL1,
8910 MDIO_PMA_DEVAD,
8911 MDIO_PMA_REG_8726_TX_CTRL2,
8913 }
8917 }
8921 {
8924 /* Set serial boot control for external load */
8926 MDIO_PMA_DEVAD,
8928 }
8930 /******************************************************************/
8931 /* BCM8727 PHY SECTION */
8932 /******************************************************************/
8936 {
8940 u16 val;
8941 /* Only NOC flavor requires to set the LED specifically */
8958 }
8960 MDIO_PMA_DEVAD,
8961 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8966 MDIO_PMA_DEVAD,
8967 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8968 val);
8970 MDIO_PMA_DEVAD,
8971 MDIO_PMA_REG_8727_GPIO_CTRL,
8976 MDIO_PMA_DEVAD,
8977 MDIO_PMA_REG_8727_GPIO_CTRL,
8978 val);
8979 }
8983 u8 port;
8984 /* The PHY reset is controlled by GPIO 1. Fake the port number
8985 * to cancel the swap done in set_gpio()
8986 */
8993 }
8998 {
8999 u32 tx_en_mode;
9001 u16 rx_alarm_ctrl_val;
9002 u16 lasi_ctrl_val;
9004 /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
9008 /* Should be 0x6 to enable XS on Tx side. */
9012 /* enable LASI */
9015 rx_alarm_ctrl_val);
9022 /* Initially configure MOD_ABS to interrupt when module is
9023 * presence( bit 8)
9024 */
9027 /* Set EDC off by setting OPTXLOS signal input to low (bit 9).
9028 * When the EDC is off it locks onto a reference clock and avoids
9029 * becoming 'lost'
9030 */
9038 /* Enable/Disable PHY transmitter output */
9041 /* Make MOD_ABS give interrupt on change */
9048 /* Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
9049 * status which reflect SFP+ module over-current
9050 */
9064 /* Set option 1G speed */
9074 /* Power down the XAUI until link is up in case of dual-media
9075 * and 1G
9076 */
9079 MDIO_PMA_DEVAD,
9083 MDIO_PMA_DEVAD,
9085 }
9088 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
9090 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
9091 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
9099 /* Since the 8727 has only single reset pin, need to set the 10G
9100 * registers although it is default
9101 */
9112 }
9114 /* Set 2-wire transfer rate of SFP+ module EEPROM
9115 * to 100Khz since some DACs(direct attached cables) do
9116 * not work at 400Khz.
9117 */
9122 /* Set TX PreEmphasis if needed */
9124 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
9135 }
9137 /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
9138 * power mode, if TX Laser is disabled
9139 */
9160 }
9163 }
9167 {
9173 config));
9175 MDIO_PMA_DEVAD,
9179 /* Module is absent */
9183 /* 1. Set mod_abs to detect next module
9184 * presence event
9185 * 2. Set EDC off by setting OPTXLOS signal input to low
9186 * (bit 9).
9187 * When the EDC is off it locks onto a reference clock and
9188 * avoids becoming 'lost'.
9189 */
9194 MDIO_PMA_DEVAD,
9197 /* Clear RX alarm since it stays up as long as
9198 * the mod_abs wasn't changed
9199 */
9201 MDIO_PMA_DEVAD,
9205 /* Module is present */
9208 /* First disable transmitter, and if the module is ok, the
9209 * module_detection will enable it
9210 * 1. Set mod_abs to detect next module absent event ( bit 8)
9211 * 2. Restore the default polarity of the OPRXLOS signal and
9212 * this signal will then correctly indicate the presence or
9213 * absence of the Rx signal. (bit 9)
9214 */
9219 MDIO_PMA_DEVAD,
9222 /* Clear RX alarm since it stays up as long as the mod_abs
9223 * wasn't changed. This is need to be done before calling the
9224 * module detection, otherwise it will clear* the link update
9225 * alarm
9226 */
9228 MDIO_PMA_DEVAD,
9233 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
9238 else
9240 }
9243 rx_alarm_status);
9244 /* No need to check link status in case of module plugged in/out */
9245 }
9251 {
9257 /* If PHY is not initialized, do not check link status */
9264 /* Check the LASI on Rx */
9272 MDIO_PMA_LASI_TXCTRL);
9279 /* Clear MSG-OUT */
9283 /* If a module is present and there is need to check
9284 * for over current
9285 */
9287 /* Check over-current using 8727 GPIO0 input*/
9297 oc_port);
9299 "been detected and the power to "
9300 "that SFP+ module has been removed "
9301 "to prevent failure of the card. "
9302 "Please remove the SFP+ module and "
9303 "restart the system to clear this "
9305 oc_port);
9306 /* Disable all RX_ALARMs except for mod_abs */
9308 MDIO_PMA_DEVAD,
9312 MDIO_PMA_DEVAD,
9314 /* Wait for module_absent_event */
9317 MDIO_PMA_DEVAD,
9319 /* Clear RX alarm */
9321 MDIO_PMA_DEVAD,
9324 }
9327 /* When module absent bit is set, check module */
9330 /* Enable all mod_abs and link detection bits */
9334 }
9342 }
9345 MDIO_PMA_DEVAD,
9348 /* Bits 0..2 --> speed detected,
9349 * Bits 13..15--> link is down
9350 */
9365 }
9367 /* Capture 10G link fault. */
9377 }
9378 }
9384 }
9389 MDIO_PMA_DEVAD,
9391 /* In case of dual-media board and 1G, power up the XAUI side,
9392 * otherwise power it down. For 10G it is done automatically
9393 */
9396 else
9399 MDIO_PMA_DEVAD,
9401 }
9403 }
9407 {
9410 /* Enable/Disable PHY transmitter output */
9413 /* Disable Transmitter */
9415 /* Clear LASI */
9418 }
9420 /******************************************************************/
9421 /* BCM8481/BCM84823/BCM84833 PHY SECTION */
9422 /******************************************************************/
9425 u8 port)
9426 {
9434 /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */
9435 /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
9447 }
9454 }
9457 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
9466 }
9473 }
9475 /* lower 16 bits of the register SPI_FW_STATUS */
9477 /* upper 16 bits of register SPI_FW_STATUS */
9482 }
9484 }
9487 {
9490 /* PHYC_CTL_LED_CTL */
9492 MDIO_PMA_DEVAD,
9498 MDIO_PMA_DEVAD,
9502 MDIO_PMA_DEVAD,
9503 MDIO_PMA_REG_8481_LED1_MASK,
9507 MDIO_PMA_DEVAD,
9508 MDIO_PMA_REG_8481_LED2_MASK,
9511 /* Select activity source by Tx and Rx, as suggested by PHY AE */
9513 MDIO_PMA_DEVAD,
9514 MDIO_PMA_REG_8481_LED3_MASK,
9517 /* Select the closest activity blink rate to that in 10/100/1000 */
9519 MDIO_PMA_DEVAD,
9520 MDIO_PMA_REG_8481_LED3_BLINK,
9523 /* Configure the blink rate to ~15.9 Hz */
9525 MDIO_PMA_DEVAD,
9526 MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH,
9527 MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ);
9531 else
9540 /* 'Interrupt Mask' */
9542 MDIO_AN_DEVAD,
9544 }
9549 {
9554 /* Save spirom version */
9556 }
9557 /* This phy uses the NIG latch mechanism since link indication
9558 * arrives through its LED4 and not via its LASI signal, so we
9559 * get steady signal instead of clear on read
9560 */
9569 /* set 1000 speed advertisement */
9576 MDIO_AN_DEVAD,
9577 MDIO_AN_REG_8481_LEGACY_AN_ADV,
9582 /* Disable forced speed */
9588 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
9600 an_1000_val);
9602 /* set 100 speed advertisement */
9606 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))) {
9608 /* Enable autoneg and restart autoneg for legacy speeds */
9614 }
9615 /* set 10 speed advertisement */
9619 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) &&
9622 SUPPORTED_10baseT_Full)))) {
9628 }
9630 /* Only 10/100 are allowed to work in FORCE mode */
9634 SUPPORTED_100baseT_Full))) {
9636 /* Enabled AUTO-MDIX when autoneg is disabled */
9640 /* The PHY needs this set even for forced link. */
9643 }
9647 SUPPORTED_10baseT_Full))) {
9648 /* Enabled AUTO-MDIX when autoneg is disabled */
9653 }
9657 an_10_100_val);
9662 /* Always write this if this is not 84833.
9663 * For 84833, write it only when it's a forced speed.
9664 */
9668 MDIO_AN_DEVAD,
9673 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
9676 /* Restart autoneg for 10G*/
9679 MDIO_AN_DEVAD,
9680 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9683 MDIO_AN_DEVAD,
9684 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9691 MDIO_AN_DEVAD,
9692 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9696 }
9701 {
9703 /* Restore normal power mode*/
9707 /* HW reset */
9713 }
9715 #define PHY84833_CMDHDLR_WAIT 300
9716 #define PHY84833_CMDHDLR_MAX_ARGS 5
9719 u16 fw_cmd,
9721 {
9723 u16 val;
9725 /* Write CMD_OPEN_OVERRIDE to STATUS reg */
9727 MDIO_84833_CMD_HDLR_STATUS,
9728 PHY84833_STATUS_CMD_OPEN_OVERRIDE);
9735 }
9739 }
9741 /* Prepare argument(s) and issue command */
9746 }
9756 }
9761 }
9762 /* Gather returning data */
9767 }
9769 MDIO_84833_CMD_HDLR_STATUS,
9770 PHY84833_STATUS_CMD_CLEAR_COMPLETE);
9772 }
9778 {
9779 u32 pair_swap;
9784 /* Check for configuration. */
9788 PORT_HW_CFG_RJ45_PAIR_SWAP_MASK;
9793 /* Only the second argument is used for this command */
9802 }
9805 u32 shmem_base_path[],
9806 u32 chip_id)
9807 {
9809 u32 idx;
9810 u8 reset_gpios;
9812 /* Assume that these will be GPIOs, not EPIOs. */
9814 /* Map config param to register bit. */
9819 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
9820 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
9823 }
9826 /* E2, look from diff place of shmem. */
9835 }
9837 }
9840 }
9844 {
9846 u8 reset_gpios;
9849 other_shmem_base_addr));
9853 /* Work around for 84833 LED failure inside RESET status */
9855 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
9856 MDIO_AN_REG_8481_MII_CTRL_FORCE_1G);
9858 MDIO_AN_REG_8481_1G_100T_EXT_CTRL,
9859 MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF);
9870 reset_gpios);
9873 }
9877 {
9885 eee_idle);
9891 }
9895 /* eee_idle in 1u --> eee_status in 16u */
9898 SHMEM_EEE_TIME_OUTPUT_BIT;
9903 }
9906 }
9911 {
9918 /* Make Certain LPI is disabled */
9922 /* Prevent Phy from working in EEE and advertising it */
9928 }
9934 }
9939 {
9951 }
9955 /* Mask events preventing LPI generation */
9962 }
9964 #define PHY84833_CONSTANT_LATENCY 1193
9968 {
9971 u16 val;
9980 else
9985 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
9986 port);
9988 /* MDIO reset */
9990 MDIO_PMA_DEVAD,
9992 }
9996 /* Wait for GPHY to come out of reset */
9999 /* BCM84823 requires that XGXS links up first @ 10G for normal
10000 * behavior.
10001 */
10002 u16 temp;
10008 }
10013 MDIO_CTL_REG_84823_MEDIA_LINE_MASK |
10014 MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN |
10015 MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK |
10016 MDIO_CTL_REG_84823_MEDIA_FIBER_1G);
10020 MDIO_CTL_REG_84823_MEDIA_LINE_MASK);
10023 MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L);
10024 }
10030 /* Do nothing. Essentially this is like the priority copper */
10039 /* Do nothing here. The first PHY won't be initialized at all */
10045 }
10057 /* Keep AutogrEEEn disabled. */
10064 PHY84833_CMDHDLR_MAX_ARGS);
10067 }
10070 else
10072 /* 84833 PHY has a better feature and doesn't need to support this. */
10077 PORT_HW_CFG_ENABLE_CMS_MASK;
10083 else
10087 }
10092 /* Configure EEE support */
10096 SHMEM_EEE_SUPPORTED_SHIFT;
10097 /* Propogate params' bits --> vars (for migration exposure) */
10100 else
10105 else
10113 }
10120 else
10125 }
10129 }
10132 /* Bring PHY out of super isolate mode as the final step. */
10134 MDIO_CTL_DEVAD,
10138 MDIO_CTL_DEVAD,
10140 }
10142 }
10147 {
10153 /* Check 10G-BaseT link status */
10154 /* Check PMD signal ok */
10162 /* Check link 10G */
10171 /* Enable expansion register 0x42 (Operation mode status) */
10173 MDIO_AN_DEVAD,
10176 /* Get legacy speed operation status */
10178 MDIO_AN_DEVAD,
10179 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
10183 legacy_status);
10198 else
10205 /* Check legacy speed AN resolution */
10207 MDIO_AN_DEVAD,
10208 MDIO_AN_REG_8481_LEGACY_MII_STATUS,
10212 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
10214 MDIO_AN_DEVAD,
10215 MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
10219 LINK_STATUS_PARALLEL_DETECTION_USED;
10220 }
10221 }
10227 /* Read LP advertised speeds */
10232 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
10235 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
10238 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
10241 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
10244 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
10251 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
10254 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
10261 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
10263 /* Determine if EEE was negotiated */
10274 }
10285 SHMEM_EEE_LP_ADV_STATUS_SHIFT);
10286 }
10287 }
10290 }
10294 {
10296 u32 spirom_ver;
10300 }
10304 {
10309 }
10313 {
10318 }
10322 {
10324 u8 port;
10325 u16 val16;
10329 else
10334 MISC_REGISTERS_GPIO_OUTPUT_LOW,
10335 port);
10338 MDIO_CTL_DEVAD,
10342 MDIO_CTL_DEVAD,
10344 }
10345 }
10349 {
10351 u16 val;
10352 u8 port;
10356 else
10365 SHARED_HW_CFG_LED_EXTPHY1) {
10367 /* Set LED masks */
10369 MDIO_PMA_DEVAD,
10370 MDIO_PMA_REG_8481_LED1_MASK,
10374 MDIO_PMA_DEVAD,
10375 MDIO_PMA_REG_8481_LED2_MASK,
10379 MDIO_PMA_DEVAD,
10380 MDIO_PMA_REG_8481_LED3_MASK,
10384 MDIO_PMA_DEVAD,
10385 MDIO_PMA_REG_8481_LED5_MASK,
10390 MDIO_PMA_DEVAD,
10391 MDIO_PMA_REG_8481_LED1_MASK,
10393 }
10398 port);
10401 SHARED_HW_CFG_LED_EXTPHY1) {
10403 /* Set LED masks */
10405 MDIO_PMA_DEVAD,
10406 MDIO_PMA_REG_8481_LED1_MASK,
10410 MDIO_PMA_DEVAD,
10411 MDIO_PMA_REG_8481_LED2_MASK,
10415 MDIO_PMA_DEVAD,
10416 MDIO_PMA_REG_8481_LED3_MASK,
10420 MDIO_PMA_DEVAD,
10421 MDIO_PMA_REG_8481_LED5_MASK,
10426 MDIO_PMA_DEVAD,
10427 MDIO_PMA_REG_8481_LED1_MASK,
10429 }
10436 SHARED_HW_CFG_LED_EXTPHY1) {
10437 /* Set control reg */
10439 MDIO_PMA_DEVAD,
10440 MDIO_PMA_REG_8481_LINK_SIGNAL,
10446 MDIO_PMA_DEVAD,
10447 MDIO_PMA_REG_8481_LINK_SIGNAL,
10448 val);
10450 /* Set LED masks */
10452 MDIO_PMA_DEVAD,
10453 MDIO_PMA_REG_8481_LED1_MASK,
10457 MDIO_PMA_DEVAD,
10458 MDIO_PMA_REG_8481_LED2_MASK,
10462 MDIO_PMA_DEVAD,
10463 MDIO_PMA_REG_8481_LED3_MASK,
10467 MDIO_PMA_DEVAD,
10468 MDIO_PMA_REG_8481_LED5_MASK,
10472 MDIO_PMA_DEVAD,
10473 MDIO_PMA_REG_8481_LED1_MASK,
10475 }
10483 SHARED_HW_CFG_LED_EXTPHY1) {
10485 /* Set control reg */
10487 MDIO_PMA_DEVAD,
10488 MDIO_PMA_REG_8481_LINK_SIGNAL,
10492 MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
10496 MDIO_PMA_DEVAD,
10497 MDIO_PMA_REG_8481_LINK_SIGNAL,
10499 }
10501 /* Set LED masks */
10503 MDIO_PMA_DEVAD,
10504 MDIO_PMA_REG_8481_LED1_MASK,
10508 MDIO_PMA_DEVAD,
10509 MDIO_PMA_REG_8481_LED2_MASK,
10513 MDIO_PMA_DEVAD,
10514 MDIO_PMA_REG_8481_LED3_MASK,
10518 MDIO_PMA_DEVAD,
10519 MDIO_PMA_REG_8481_LED5_MASK,
10524 MDIO_PMA_DEVAD,
10525 MDIO_PMA_REG_8481_LED1_MASK,
10528 /* Tell LED3 to blink on source */
10530 MDIO_PMA_DEVAD,
10531 MDIO_PMA_REG_8481_LINK_SIGNAL,
10536 MDIO_PMA_DEVAD,
10537 MDIO_PMA_REG_8481_LINK_SIGNAL,
10538 val);
10539 }
10541 }
10543 /* This is a workaround for E3+84833 until autoneg
10544 * restart is fixed in f/w
10545 */
10549 }
10550 }
10552 /******************************************************************/
10553 /* 54618SE PHY SECTION */
10554 /******************************************************************/
10558 {
10560 u8 port;
10562 u32 cfg_pin;
10567 /* This works with E3 only, no need to check the chip
10568 * before determining the port.
10569 */
10575 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10576 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10578 /* Drive pin high to bring the GPHY out of reset. */
10581 /* wait for GPHY to reset */
10584 /* reset phy */
10589 /* Wait for GPHY to reset */
10592 /* Configure LED4: set to INTR (0x6). */
10593 /* Accessing shadow register 0xe. */
10595 MDIO_REG_GPHY_SHADOW,
10596 MDIO_REG_GPHY_SHADOW_LED_SEL2);
10598 MDIO_REG_GPHY_SHADOW,
10603 MDIO_REG_GPHY_SHADOW,
10605 /* Configure INTR based on link status change. */
10607 MDIO_REG_INTR_MASK,
10610 /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */
10612 MDIO_REG_GPHY_SHADOW,
10613 MDIO_REG_GPHY_SHADOW_AUTO_DET_MED);
10615 MDIO_REG_GPHY_SHADOW,
10619 MDIO_REG_GPHY_SHADOW,
10622 /* Set up fc */
10623 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
10627 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC)
10631 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
10634 /* read all advertisement */
10644 MDIO_PMA_REG_CTRL,
10647 /* Disable forced speed */
10654 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
10666 an_1000_val);
10671 /* set 100 speed advertisement */
10675 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)))) {
10677 /* Enable autoneg and restart autoneg for legacy speeds */
10683 }
10685 /* set 10 speed advertisement */
10689 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)))) {
10695 }
10697 /* Only 10/100 are allowed to work in FORCE mode */
10700 /* Enabled AUTO-MDIX when autoneg is disabled */
10705 }
10707 /* Enabled AUTO-MDIX when autoneg is disabled */
10712 }
10714 /* Check if we should turn on Auto-GrEEEn */
10718 FEATURE_CONFIG_AUTOGREEEN_ENABLED) {
10724 }
10728 MDIO_REG_GPHY_CL45_DATA_REG,
10729 MDIO_REG_GPHY_EEE_ADV);
10731 MDIO_REG_GPHY_CL45_ADDR_REG,
10734 MDIO_REG_GPHY_CL45_DATA_REG,
10735 temp);
10736 }
10749 }
10754 {
10756 u16 temp;
10759 MDIO_REG_GPHY_SHADOW,
10760 MDIO_REG_GPHY_SHADOW_LED_SEL1);
10762 MDIO_REG_GPHY_SHADOW,
10780 }
10782 MDIO_REG_GPHY_SHADOW,
10785 }
10790 {
10792 u32 cfg_pin;
10793 u8 port;
10795 /* In case of no EPIO routed to reset the GPHY, put it
10796 * in low power mode.
10797 */
10799 /* This works with E3 only, no need to check the chip
10800 * before determining the port.
10801 */
10806 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10807 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10809 /* Drive pin low to put GPHY in reset. */
10811 }
10816 {
10818 u16 val;
10822 /* Get speed operation status */
10828 /* Read status to clear the PHY interrupt. */
10830 MDIO_REG_INTR_STATUS,
10846 }
10847 /* Omitting 100Base-T4 for now */
10865 /* Check legacy speed AN resolution */
10871 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
10877 LINK_STATUS_PARALLEL_DETECTION_USED;
10882 /* Report whether EEE is resolved. */
10886 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
10890 MDIO_REG_GPHY_CL45_ADDR_REG,
10891 MDIO_AN_DEVAD);
10893 MDIO_REG_GPHY_CL45_DATA_REG,
10894 MDIO_REG_GPHY_EEE_RESOLVED);
10896 MDIO_REG_GPHY_CL45_ADDR_REG,
10899 MDIO_REG_GPHY_CL45_DATA_REG,
10901 }
10903 }
10908 /* Report LP advertised speeds */
10913 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
10916 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
10919 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
10922 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
10925 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
10930 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
10933 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
10934 }
10935 }
10937 }
10941 {
10943 u16 val;
10948 /* Enable master/slave manual mmode and set to master */
10949 /* mii write 9 [bits set 11 12] */
10952 /* forced 1G and disable autoneg */
10953 /* set val [mii read 0] */
10954 /* set val [expr $val & [bits clear 6 12 13]] */
10955 /* set val [expr $val | [bits set 6 8]] */
10956 /* mii write 0 $val */
10962 /* Set external loopback and Tx using 6dB coding */
10963 /* mii write 0x18 7 */
10964 /* set val [mii read 0x18] */
10965 /* mii write 0x18 [expr $val | [bits set 10 15]] */
10970 /* This register opens the gate for the UMAC despite its name */
10973 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
10974 * length used by the MAC receive logic to check frames.
10975 */
10977 }
10979 /******************************************************************/
10980 /* SFX7101 PHY SECTION */
10981 /******************************************************************/
10984 {
10986 /* SFX7101_XGXS_TEST1 */
10989 }
10994 {
10999 /* Restore normal power mode*/
11002 /* HW reset */
11013 /* Restart autoneg */
11020 /* Save spirom version */
11029 }
11034 {
11036 u8 link_up;
11051 /* if link is up print the AN outcome of the SFX7101 PHY */
11063 /* read LP advertised speeds */
11066 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
11067 }
11069 }
11072 {
11082 }
11085 {
11089 MDIO_PMA_DEVAD,
11094 /* Writes a self-clearing reset */
11096 MDIO_PMA_DEVAD,
11097 MDIO_PMA_REG_7101_RESET,
11099 /* Wait for clear */
11101 MDIO_PMA_DEVAD,
11106 }
11107 }
11111 /* Low power mode is controlled by GPIO 2 */
11114 /* The PHY reset is controlled by GPIO 1 */
11117 }
11121 {
11135 }
11137 MDIO_PMA_DEVAD,
11138 MDIO_PMA_REG_7107_LINK_LED_CNTL,
11139 val);
11140 }
11142 /******************************************************************/
11143 /* STATIC PHY DECLARATION */
11144 /******************************************************************/
11170 };
11181 SUPPORTED_10baseT_Full |
11182 SUPPORTED_100baseT_Half |
11183 SUPPORTED_100baseT_Full |
11184 SUPPORTED_1000baseT_Full |
11185 SUPPORTED_2500baseX_Full |
11186 SUPPORTED_TP |
11187 SUPPORTED_Autoneg |
11188 SUPPORTED_Pause |
11189 SUPPORTED_Asym_Pause),
11205 };
11216 SUPPORTED_10baseT_Full |
11217 SUPPORTED_100baseT_Half |
11218 SUPPORTED_100baseT_Full |
11219 SUPPORTED_1000baseT_Full |
11220 SUPPORTED_2500baseX_Full |
11221 SUPPORTED_10000baseT_Full |
11222 SUPPORTED_FIBRE |
11223 SUPPORTED_Autoneg |
11224 SUPPORTED_Pause |
11225 SUPPORTED_Asym_Pause),
11241 };
11247 FLAGS_TX_ERROR_CHECK),
11252 SUPPORTED_10baseT_Full |
11253 SUPPORTED_100baseT_Half |
11254 SUPPORTED_100baseT_Full |
11255 SUPPORTED_1000baseT_Full |
11256 SUPPORTED_10000baseT_Full |
11257 SUPPORTED_20000baseKR2_Full |
11258 SUPPORTED_20000baseMLD2_Full |
11259 SUPPORTED_FIBRE |
11260 SUPPORTED_Autoneg |
11261 SUPPORTED_Pause |
11262 SUPPORTED_Asym_Pause),
11278 };
11290 SUPPORTED_TP |
11291 SUPPORTED_Autoneg |
11292 SUPPORTED_Pause |
11293 SUPPORTED_Asym_Pause),
11309 };
11319 SUPPORTED_2500baseX_Full |
11320 SUPPORTED_1000baseT_Full |
11321 SUPPORTED_FIBRE |
11322 SUPPORTED_Autoneg |
11323 SUPPORTED_Pause |
11324 SUPPORTED_Asym_Pause),
11340 };
11350 SUPPORTED_FIBRE |
11351 SUPPORTED_Pause |
11352 SUPPORTED_Asym_Pause),
11368 };
11378 SUPPORTED_1000baseT_Full |
11379 SUPPORTED_FIBRE |
11380 SUPPORTED_Pause |
11381 SUPPORTED_Asym_Pause),
11397 };
11404 FLAGS_INIT_XGXS_FIRST |
11405 FLAGS_TX_ERROR_CHECK),
11410 SUPPORTED_1000baseT_Full |
11411 SUPPORTED_Autoneg |
11412 SUPPORTED_FIBRE |
11413 SUPPORTED_Pause |
11414 SUPPORTED_Asym_Pause),
11430 };
11437 FLAGS_TX_ERROR_CHECK),
11442 SUPPORTED_1000baseT_Full |
11443 SUPPORTED_FIBRE |
11444 SUPPORTED_Pause |
11445 SUPPORTED_Asym_Pause),
11461 };
11467 FLAGS_REARM_LATCH_SIGNAL,
11472 SUPPORTED_10baseT_Full |
11473 SUPPORTED_100baseT_Half |
11474 SUPPORTED_100baseT_Full |
11475 SUPPORTED_1000baseT_Full |
11476 SUPPORTED_10000baseT_Full |
11477 SUPPORTED_TP |
11478 SUPPORTED_Autoneg |
11479 SUPPORTED_Pause |
11480 SUPPORTED_Asym_Pause),
11496 };
11503 FLAGS_REARM_LATCH_SIGNAL |
11504 FLAGS_TX_ERROR_CHECK),
11509 SUPPORTED_10baseT_Full |
11510 SUPPORTED_100baseT_Half |
11511 SUPPORTED_100baseT_Full |
11512 SUPPORTED_1000baseT_Full |
11513 SUPPORTED_10000baseT_Full |
11514 SUPPORTED_TP |
11515 SUPPORTED_Autoneg |
11516 SUPPORTED_Pause |
11517 SUPPORTED_Asym_Pause),
11533 };
11540 FLAGS_REARM_LATCH_SIGNAL |
11541 FLAGS_TX_ERROR_CHECK |
11542 FLAGS_EEE_10GBT),
11547 SUPPORTED_100baseT_Full |
11548 SUPPORTED_1000baseT_Full |
11549 SUPPORTED_10000baseT_Full |
11550 SUPPORTED_TP |
11551 SUPPORTED_Autoneg |
11552 SUPPORTED_Pause |
11553 SUPPORTED_Asym_Pause),
11569 };
11580 SUPPORTED_10baseT_Full |
11581 SUPPORTED_100baseT_Half |
11582 SUPPORTED_100baseT_Full |
11583 SUPPORTED_1000baseT_Full |
11584 SUPPORTED_TP |
11585 SUPPORTED_Autoneg |
11586 SUPPORTED_Pause |
11587 SUPPORTED_Asym_Pause),
11603 };
11604 /*****************************************************************/
11605 /* */
11606 /* Populate the phy according. Main function: bnx2x_populate_phy */
11607 /* */
11608 /*****************************************************************/
11612 u8 phy_index)
11613 {
11614 /* Get the 4 lanes xgxs config rx and tx */
11617 /* INT_PHY and EXT_PHY1 share the same value location in
11618 * the shmem. When num_phys is greater than 1, than this value
11619 * applies only to EXT_PHY1
11620 */
11637 }
11644 }
11645 }
11649 {
11665 }
11668 }
11671 {
11672 u32 phy_addr;
11673 u32 chip_id;
11677 PORT_FEATURE_CONNECTED_SWITCH_MASK);
11683 u32 serdes_net_if;
11685 MISC_REG_WC0_CTRL_PHY_ADDR);
11689 else
11691 /* Check Dual mode */
11695 PORT_HW_CFG_NET_SERDES_IF_MASK);
11696 /* Set the appropriate supported and flags indications per
11697 * interface type of the chip
11698 */
11702 SUPPORTED_10baseT_Full |
11703 SUPPORTED_100baseT_Half |
11704 SUPPORTED_100baseT_Full |
11705 SUPPORTED_1000baseT_Full |
11706 SUPPORTED_FIBRE |
11707 SUPPORTED_Autoneg |
11708 SUPPORTED_Pause |
11709 SUPPORTED_Asym_Pause);
11717 SUPPORTED_10000baseT_Full |
11718 SUPPORTED_FIBRE |
11719 SUPPORTED_Pause |
11720 SUPPORTED_Asym_Pause);
11726 SUPPORTED_10000baseT_Full |
11727 SUPPORTED_FIBRE |
11728 SUPPORTED_Autoneg |
11729 SUPPORTED_Pause |
11730 SUPPORTED_Asym_Pause);
11736 SUPPORTED_FIBRE |
11737 SUPPORTED_Pause |
11738 SUPPORTED_Asym_Pause);
11744 SUPPORTED_FIBRE |
11745 SUPPORTED_Pause |
11746 SUPPORTED_Asym_Pause);
11750 serdes_net_if);
11752 }
11754 /* Enable MDC/MDIO work-around for E3 A0 since free running MDC
11755 * was not set as expected. For B0, ECO will be enabled so there
11756 * won't be an issue there
11757 */
11760 else
11766 NIG_REG_SERDES0_CTRL_PHY_ADDR +
11772 NIG_REG_XGXS0_CTRL_PHY_ADDR +
11779 }
11780 }
11783 SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
11784 port);
11787 else
11795 }
11798 u8 phy_index,
11799 u32 shmem_base,
11800 u32 shmem2_base,
11801 u8 port,
11803 {
11809 /* Select the phy type */
11826 /* BCM8727_NOC => BCM8727 no over current */
11857 /* In case external PHY wasn't found */
11862 }
11867 /* The shmem address of the phy version is located on different
11868 * structures. In case this structure is too old, do not set
11869 * the address
11870 */
11877 /* Check specific mdc mdio settings */
11880 SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
11889 }
11890 /* Check specific mdc mdio settings */
11893 SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >>
11895 SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
11896 }
11901 /* Remove 100Mb link supported for BCM84833 when phy fw
11902 * version lower than or equal to 1.39
11903 */
11908 SUPPORTED_100baseT_Full);
11909 }
11911 /* In case mdc/mdio_access of the external phy is different than the
11912 * mdc/mdio access of the XGXS, a HW lock must be taken in each access
11913 * to prevent one port interfere with another port's CL45 operations.
11914 */
11922 }
11926 {
11934 }
11938 u8 phy_index)
11939 {
11941 u32 link_config;
11942 /* Populate the default phy configuration for MF mode */
11949 dev_info.
11957 dev_info.
11959 }
11988 }
12006 }
12007 }
12010 {
12015 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
12018 PORT_HW_CFG_PHY_SELECTION_MASK;
12034 }
12039 }
12043 {
12051 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
12054 phy_index++) {
12061 }
12071 phy_index);
12074 phy_index++)
12077 }
12082 FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET)
12090 /* Update media type for non-PMF sync only for the first time
12091 * In case the media type changes afterwards, it will be updated
12092 * using the update_status function
12093 */
12098 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
12100 actual_phy_idx));
12101 }
12106 }
12110 }
12114 {
12126 /* set bmac loopback */
12130 }
12134 {
12145 /* set bmac loopback */
12149 }
12153 {
12158 else
12164 /* Set WC to loopback mode since link is required to provide clock
12165 * to the XMAC in 20G mode
12166 */
12171 params);
12175 }
12179 {
12190 }
12194 {
12201 else
12214 }
12218 else
12220 }
12223 /* set 10G XGXS loopback */
12226 params);
12229 /* set external phy loopback */
12230 u8 phy_index;
12236 params);
12237 }
12238 }
12242 }
12245 {
12261 /* disable attentions */
12264 NIG_MASK_XGXS0_LINK10G |
12265 NIG_MASK_SERDES0_LINK_STATUS |
12266 NIG_MASK_MI_INT));
12276 }
12301 else
12303 }
12308 }
12313 }
12316 u8 reset_ext_phy)
12317 {
12321 /* disable attentions */
12325 SHMEM_EEE_ACTIVE_BIT);
12329 NIG_MASK_XGXS0_LINK10G |
12330 NIG_MASK_SERDES0_LINK_STATUS |
12331 NIG_MASK_MI_INT));
12333 /* activate nig drain */
12336 /* disable nig egress interface */
12340 }
12342 /* Stop BigMac rx */
12348 }
12349 /* disable emac */
12354 /* The PHY reset is controlled by GPIO 1
12355 * Hold it as vars low
12356 */
12357 /* clear link led */
12363 phy_index++) {
12369 params);
12370 }
12372 FLAGS_REARM_LATCH_SIGNAL)
12374 }
12375 }
12378 /* Clear latching indication */
12382 }
12387 /* disable nig ingress interface */
12389 /* reset BigMac */
12398 MISC_REGISTERS_RESET_REG_2_XMAC)
12400 XMAC_CTRL_REG_SOFT_RESET);
12401 }
12405 }
12407 /****************************************************************************/
12408 /* Common function */
12409 /****************************************************************************/
12411 u32 shmem_base_path[],
12413 u32 chip_id)
12414 {
12417 u16 val;
12425 /* PART1 - Reset both phys */
12428 /* In E2, same phy is using for port0 of the two paths */
12437 }
12439 /* Extract the ext phy address for the port */
12445 }
12446 /* disable attentions */
12450 NIG_MASK_XGXS0_LINK10G |
12451 NIG_MASK_SERDES0_LINK_STATUS |
12452 NIG_MASK_MI_INT));
12454 /* Need to take the phy out of low power mode in order
12455 * to write to access its registers
12456 */
12458 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
12459 port);
12461 /* Reset the phy */
12463 MDIO_PMA_DEVAD,
12464 MDIO_PMA_REG_CTRL,
12466 }
12468 /* Add delay of 150ms after reset */
12477 }
12479 /* PART2 - Download firmware to both phys */
12483 else
12489 port_of_path))
12492 /* Only set bit 10 = 1 (Tx power down) */
12494 MDIO_PMA_DEVAD,
12497 /* Phase1 of TX_POWER_DOWN reset */
12499 MDIO_PMA_DEVAD,
12500 MDIO_PMA_REG_TX_POWER_DOWN,
12502 }
12504 /* Toggle Transmitter: Power down and then up with 600ms delay
12505 * between
12506 */
12509 /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
12511 /* Phase2 of POWER_DOWN_RESET */
12512 /* Release bit 10 (Release Tx power down) */
12514 MDIO_PMA_DEVAD,
12518 MDIO_PMA_DEVAD,
12522 /* Read modify write the SPI-ROM version select register */
12524 MDIO_PMA_DEVAD,
12527 MDIO_PMA_DEVAD,
12530 /* set GPIO2 back to LOW */
12533 }
12535 }
12537 u32 shmem_base_path[],
12539 u32 chip_id)
12540 {
12541 u32 val;
12542 s8 port;
12544 /* Use port1 because of the static port-swap */
12545 /* Enable the module detection interrupt */
12556 /* In E2, same phy is using for port0 of the two paths */
12563 }
12564 /* Extract the ext phy address for the port */
12570 }
12572 /* Reset phy*/
12577 /* Set fault module detected LED on */
12579 MISC_REGISTERS_GPIO_HIGH,
12580 port);
12581 }
12584 }
12587 {
12626 /* Don't override the io_gpio and io_port */
12628 }
12629 }
12632 u32 shmem_base_path[],
12634 u32 chip_id)
12635 {
12640 s8 port_of_path;
12647 /* Retrieve the reset gpio/port which control the reset.
12648 * Default is GPIO1, PORT1
12649 */
12653 /* Calculate the port based on port swap */
12656 /* Initiate PHY reset*/
12658 port);
12661 port);
12665 /* PART1 - Reset both phys */
12669 /* In E2, same phy is using for port0 of the two paths */
12678 }
12680 /* Extract the ext phy address for the port */
12686 }
12687 /* disable attentions */
12691 NIG_MASK_XGXS0_LINK10G |
12692 NIG_MASK_SERDES0_LINK_STATUS |
12693 NIG_MASK_MI_INT));
12696 /* Reset the phy */
12699 }
12701 /* Add delay of 150ms after reset */
12709 }
12710 /* PART2 - Download firmware to both phys */
12714 else
12719 port_of_path))
12721 /* Disable PHY transmitter output */
12723 MDIO_PMA_DEVAD,
12726 }
12728 }
12731 u32 shmem_base_path[],
12732 u32 shmem2_base_path[],
12733 u8 phy_index,
12734 u32 chip_id)
12735 {
12736 u8 reset_gpios;
12742 reset_gpios);
12744 }
12748 {
12750 /* Wait for FW completing its initialization. */
12753 MDIO_PMA_DEVAD,
12758 }
12762 }
12764 /* Put the port in super isolate mode. */
12766 MDIO_CTL_DEVAD,
12770 MDIO_CTL_DEVAD,
12773 /* Save spirom version */
12776 }
12779 u32 shmem_base,
12780 u32 shmem2_base,
12781 u32 chip_id)
12782 {
12790 }
12797 }
12799 }
12804 {
12810 shmem2_base_path,
12817 shmem2_base_path,
12822 /* GPIO1 affects both ports, so there's need to pull
12823 * it for single port alone
12824 */
12826 shmem2_base_path,
12830 /* GPIO3's are linked, and so both need to be toggled
12831 * to obtain required 2us pulse.
12832 */
12834 shmem2_base_path,
12843 ext_phy_type);
12845 }
12852 }
12856 {
12865 /* Enable EPIO */
12868 }
12869 /* Check if common init was already done */
12875 phy_ver);
12877 }
12879 /* Read the ext_phy_type for arbitrary port(0) */
12881 phy_index++) {
12887 shmem2_base_path,
12889 chip_id);
12890 }
12892 }
12896 {
12898 u32 cfg_pin;
12900 u32 pin_val;
12905 PORT_HW_CFG_E3_OVER_CURRENT_MASK) >>
12906 PORT_HW_CFG_E3_OVER_CURRENT_SHIFT;
12908 /* Ignore check if no external input PIN available */
12915 " been detected and the power to "
12916 "that SFP+ module has been removed"
12917 " to prevent failure of the card."
12918 " Please remove the SFP+ module and"
12919 " restart the system to clear this"
12923 }
12926 }
12930 u8 notify)
12931 {
12933 /* Compare new value with previous value */
12934 u8 led_mode;
12940 /* If values differ */
12944 /* a. Update shmem->link_status accordingly
12945 * b. Update link_vars->link_up
12946 */
12953 /* activate nig drain */
12955 /* Set LED mode to off since the PHY doesn't know about these
12956 * errors
12957 */
12966 /* Clear nig drain */
12968 }
12970 /* Update the LED according to the link state */
12973 /* Update link status in the shared memory */
12976 /* C. Trigger General Attention */
12980 }
12982 /******************************************************************************
12983 * Description:
12984 * This function checks for half opened connection change indication.
12985 * When such change occurs, it calls the bnx2x_analyze_link_error
12986 * to check if Remote Fault is set or cleared. Reception of remote fault
12987 * status message in the MAC indicates that the peer's MAC has detected
12988 * a fault, for example, due to break in the TX side of fiber.
12989 *
12990 ******************************************************************************/
12993 u8 notify)
12994 {
12997 u32 mac_base;
12998 /* In case link status is physically up @ 10G do */
13006 /* Check E3 XMAC */
13007 /* Note that link speed cannot be queried here, since it may be
13008 * zero while link is down. In case UMAC is active, LSS will
13009 * simply not be set
13010 */
13013 /* Clear stick bits (Requires rising edge) */
13016 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
13017 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
13024 /* Check E1X / E2 BMAC */
13025 u32 lss_status_reg;
13028 NIG_REG_INGRESS_BMAC0_MEM;
13029 /* Read BIGMAC_REGISTER_RX_LSS_STATUS */
13032 else
13039 }
13041 }
13044 {
13045 u16 phy_idx;
13054 }
13055 }
13062 }
13064 }
13067 {
13068 u8 phy_index;
13071 phy_index++) {
13076 }
13080 }
13082 }
13085 u32 shmem_base,
13086 u32 shmem2_base,
13087 u8 port)
13088 {
13092 phy_index++) {
13098 }
13100 FLAGS_FAN_FAILURE_DET_REQ);
13101 }
13103 }
13106 {
13107 u8 phy_index;
13112 NIG_MASK_XGXS0_LINK10G |
13113 NIG_MASK_SERDES0_LINK_STATUS |
13114 NIG_MASK_MI_INT));
13117 phy_index++) {
13121 params);
13123 }
13124 }
13125 }
13129 u8 port)
13130 {
13132 u32 val;
13136 shmem_base,
13137 port,
13144 phy_index++) {
13150 }
13155 }
13156 }
13157 }
13162 /* Set GPIO3 to trigger SFP+ module insertion/removal */
13182 else
13185 /* Open appropriate AEU for interrupts */
13190 /* Enable the GPIO to trigger interrupt */
13194 }