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drm/i915: add power monitoring support
[linux-2.6.git] / drivers / gpu / drm / i915 / i915_irq.c
blobb5dba4795f6f5441a3ac68aff606de49481f8279
1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
2 */
3 /*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #include <linux/sysrq.h>
30 #include <linux/slab.h>
31 #include "drmP.h"
32 #include "drm.h"
33 #include "i915_drm.h"
34 #include "i915_drv.h"
35 #include "i915_trace.h"
36 #include "intel_drv.h"
37
38 #define MAX_NOPID ((u32)~0)
39
40 /**
41 * Interrupts that are always left unmasked.
42 *
43 * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
44 * we leave them always unmasked in IMR and then control enabling them through
45 * PIPESTAT alone.
46 */
47 #define I915_INTERRUPT_ENABLE_FIX \
48 (I915_ASLE_INTERRUPT | \
49 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \
50 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \
51 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | \
52 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | \
53 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
54
55 /** Interrupts that we mask and unmask at runtime. */
56 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT)
57
58 #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
59 PIPE_VBLANK_INTERRUPT_STATUS)
60
61 #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
62 PIPE_VBLANK_INTERRUPT_ENABLE)
63
64 #define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \
65 DRM_I915_VBLANK_PIPE_B)
66
67 void
68 ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
69 {
70 if ((dev_priv->gt_irq_mask_reg & mask) != 0) {
71 dev_priv->gt_irq_mask_reg &= ~mask;
72 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
73 (void) I915_READ(GTIMR);
74 }
75 }
76
77 void
78 ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
79 {
80 if ((dev_priv->gt_irq_mask_reg & mask) != mask) {
81 dev_priv->gt_irq_mask_reg |= mask;
82 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
83 (void) I915_READ(GTIMR);
84 }
85 }
86
87 /* For display hotplug interrupt */
88 void
89 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
90 {
91 if ((dev_priv->irq_mask_reg & mask) != 0) {
92 dev_priv->irq_mask_reg &= ~mask;
93 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
94 (void) I915_READ(DEIMR);
95 }
96 }
97
98 static inline void
99 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
100 {
101 if ((dev_priv->irq_mask_reg & mask) != mask) {
102 dev_priv->irq_mask_reg |= mask;
103 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
104 (void) I915_READ(DEIMR);
105 }
106 }
107
108 void
109 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
110 {
111 if ((dev_priv->irq_mask_reg & mask) != 0) {
112 dev_priv->irq_mask_reg &= ~mask;
113 I915_WRITE(IMR, dev_priv->irq_mask_reg);
114 (void) I915_READ(IMR);
115 }
116 }
117
118 void
119 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
120 {
121 if ((dev_priv->irq_mask_reg & mask) != mask) {
122 dev_priv->irq_mask_reg |= mask;
123 I915_WRITE(IMR, dev_priv->irq_mask_reg);
124 (void) I915_READ(IMR);
125 }
126 }
127
128 static inline u32
129 i915_pipestat(int pipe)
130 {
131 if (pipe == 0)
132 return PIPEASTAT;
133 if (pipe == 1)
134 return PIPEBSTAT;
135 BUG();
136 }
137
138 void
139 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
140 {
141 if ((dev_priv->pipestat[pipe] & mask) != mask) {
142 u32 reg = i915_pipestat(pipe);
143
144 dev_priv->pipestat[pipe] |= mask;
145 /* Enable the interrupt, clear any pending status */
146 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
147 (void) I915_READ(reg);
148 }
149 }
150
151 void
152 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
153 {
154 if ((dev_priv->pipestat[pipe] & mask) != 0) {
155 u32 reg = i915_pipestat(pipe);
156
157 dev_priv->pipestat[pipe] &= ~mask;
158 I915_WRITE(reg, dev_priv->pipestat[pipe]);
159 (void) I915_READ(reg);
160 }
161 }
162
163 /**
164 * intel_enable_asle - enable ASLE interrupt for OpRegion
165 */
166 void intel_enable_asle (struct drm_device *dev)
167 {
168 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
169
170 if (HAS_PCH_SPLIT(dev))
171 ironlake_enable_display_irq(dev_priv, DE_GSE);
172 else {
173 i915_enable_pipestat(dev_priv, 1,
174 I915_LEGACY_BLC_EVENT_ENABLE);
175 if (IS_I965G(dev))
176 i915_enable_pipestat(dev_priv, 0,
177 I915_LEGACY_BLC_EVENT_ENABLE);
178 }
179 }
180
181 /**
182 * i915_pipe_enabled - check if a pipe is enabled
183 * @dev: DRM device
184 * @pipe: pipe to check
185 *
186 * Reading certain registers when the pipe is disabled can hang the chip.
187 * Use this routine to make sure the PLL is running and the pipe is active
188 * before reading such registers if unsure.
189 */
190 static int
191 i915_pipe_enabled(struct drm_device *dev, int pipe)
192 {
193 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
194 unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF;
195
196 if (I915_READ(pipeconf) & PIPEACONF_ENABLE)
197 return 1;
198
199 return 0;
200 }
201
202 /* Called from drm generic code, passed a 'crtc', which
203 * we use as a pipe index
204 */
205 u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
206 {
207 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
208 unsigned long high_frame;
209 unsigned long low_frame;
210 u32 high1, high2, low, count;
211
212 high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
213 low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
214
215 if (!i915_pipe_enabled(dev, pipe)) {
216 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
217 "pipe %d\n", pipe);
218 return 0;
219 }
220
221 /*
222 * High & low register fields aren't synchronized, so make sure
223 * we get a low value that's stable across two reads of the high
224 * register.
225 */
226 do {
227 high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
228 PIPE_FRAME_HIGH_SHIFT);
229 low = ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
230 PIPE_FRAME_LOW_SHIFT);
231 high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
232 PIPE_FRAME_HIGH_SHIFT);
233 } while (high1 != high2);
234
235 count = (high1 << 8) | low;
236
237 return count;
238 }
239
240 u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
241 {
242 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
243 int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45;
244
245 if (!i915_pipe_enabled(dev, pipe)) {
246 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
247 "pipe %d\n", pipe);
248 return 0;
249 }
250
251 return I915_READ(reg);
252 }
253
254 /*
255 * Handle hotplug events outside the interrupt handler proper.
256 */
257 static void i915_hotplug_work_func(struct work_struct *work)
258 {
259 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
260 hotplug_work);
261 struct drm_device *dev = dev_priv->dev;
262 struct drm_mode_config *mode_config = &dev->mode_config;
263 struct drm_encoder *encoder;
264
265 if (mode_config->num_encoder) {
266 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
267 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
268
269 if (intel_encoder->hot_plug)
270 (*intel_encoder->hot_plug) (intel_encoder);
271 }
272 }
273 /* Just fire off a uevent and let userspace tell us what to do */
274 drm_helper_hpd_irq_event(dev);
275 }
276
277 static void i915_handle_rps_change(struct drm_device *dev)
278 {
279 drm_i915_private_t *dev_priv = dev->dev_private;
280 u32 busy_up, busy_down, max_avg, min_avg;
281 u8 new_delay = dev_priv->cur_delay;
282
283 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
284 busy_up = I915_READ(RCPREVBSYTUPAVG);
285 busy_down = I915_READ(RCPREVBSYTDNAVG);
286 max_avg = I915_READ(RCBMAXAVG);
287 min_avg = I915_READ(RCBMINAVG);
288
289 /* Handle RCS change request from hw */
290 if (busy_up > max_avg) {
291 if (dev_priv->cur_delay != dev_priv->max_delay)
292 new_delay = dev_priv->cur_delay - 1;
293 if (new_delay < dev_priv->max_delay)
294 new_delay = dev_priv->max_delay;
295 } else if (busy_down < min_avg) {
296 if (dev_priv->cur_delay != dev_priv->min_delay)
297 new_delay = dev_priv->cur_delay + 1;
298 if (new_delay > dev_priv->min_delay)
299 new_delay = dev_priv->min_delay;
300 }
301
302 if (ironlake_set_drps(dev, new_delay))
303 dev_priv->cur_delay = new_delay;
304
305 return;
306 }
307
308 irqreturn_t ironlake_irq_handler(struct drm_device *dev)
309 {
310 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
311 int ret = IRQ_NONE;
312 u32 de_iir, gt_iir, de_ier, pch_iir;
313 struct drm_i915_master_private *master_priv;
314 struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
315
316 /* disable master interrupt before clearing iir */
317 de_ier = I915_READ(DEIER);
318 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
319 (void)I915_READ(DEIER);
320
321 de_iir = I915_READ(DEIIR);
322 gt_iir = I915_READ(GTIIR);
323 pch_iir = I915_READ(SDEIIR);
324
325 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0)
326 goto done;
327
328 ret = IRQ_HANDLED;
329
330 if (dev->primary->master) {
331 master_priv = dev->primary->master->driver_priv;
332 if (master_priv->sarea_priv)
333 master_priv->sarea_priv->last_dispatch =
334 READ_BREADCRUMB(dev_priv);
335 }
336
337 if (gt_iir & GT_PIPE_NOTIFY) {
338 u32 seqno = render_ring->get_gem_seqno(dev, render_ring);
339 render_ring->irq_gem_seqno = seqno;
340 trace_i915_gem_request_complete(dev, seqno);
341 DRM_WAKEUP(&dev_priv->render_ring.irq_queue);
342 dev_priv->hangcheck_count = 0;
343 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
344 }
345 if (gt_iir & GT_BSD_USER_INTERRUPT)
346 DRM_WAKEUP(&dev_priv->bsd_ring.irq_queue);
347
348
349 if (de_iir & DE_GSE)
350 ironlake_opregion_gse_intr(dev);
351
352 if (de_iir & DE_PLANEA_FLIP_DONE) {
353 intel_prepare_page_flip(dev, 0);
354 intel_finish_page_flip(dev, 0);
355 }
356
357 if (de_iir & DE_PLANEB_FLIP_DONE) {
358 intel_prepare_page_flip(dev, 1);
359 intel_finish_page_flip(dev, 1);
360 }
361
362 if (de_iir & DE_PIPEA_VBLANK)
363 drm_handle_vblank(dev, 0);
364
365 if (de_iir & DE_PIPEB_VBLANK)
366 drm_handle_vblank(dev, 1);
367
368 /* check event from PCH */
369 if ((de_iir & DE_PCH_EVENT) &&
370 (pch_iir & SDE_HOTPLUG_MASK)) {
371 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
372 }
373
374 if (de_iir & DE_PCU_EVENT) {
375 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
376 i915_handle_rps_change(dev);
377 }
378
379 /* should clear PCH hotplug event before clear CPU irq */
380 I915_WRITE(SDEIIR, pch_iir);
381 I915_WRITE(GTIIR, gt_iir);
382 I915_WRITE(DEIIR, de_iir);
383
384 done:
385 I915_WRITE(DEIER, de_ier);
386 (void)I915_READ(DEIER);
387
388 return ret;
389 }
390
391 /**
392 * i915_error_work_func - do process context error handling work
393 * @work: work struct
394 *
395 * Fire an error uevent so userspace can see that a hang or error
396 * was detected.
397 */
398 static void i915_error_work_func(struct work_struct *work)
399 {
400 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
401 error_work);
402 struct drm_device *dev = dev_priv->dev;
403 char *error_event[] = { "ERROR=1", NULL };
404 char *reset_event[] = { "RESET=1", NULL };
405 char *reset_done_event[] = { "ERROR=0", NULL };
406
407 DRM_DEBUG_DRIVER("generating error event\n");
408 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
409
410 if (atomic_read(&dev_priv->mm.wedged)) {
411 if (IS_I965G(dev)) {
412 DRM_DEBUG_DRIVER("resetting chip\n");
413 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
414 if (!i965_reset(dev, GDRST_RENDER)) {
415 atomic_set(&dev_priv->mm.wedged, 0);
416 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
417 }
418 } else {
419 DRM_DEBUG_DRIVER("reboot required\n");
420 }
421 }
422 }
423
424 static struct drm_i915_error_object *
425 i915_error_object_create(struct drm_device *dev,
426 struct drm_gem_object *src)
427 {
428 struct drm_i915_error_object *dst;
429 struct drm_i915_gem_object *src_priv;
430 int page, page_count;
431
432 if (src == NULL)
433 return NULL;
434
435 src_priv = to_intel_bo(src);
436 if (src_priv->pages == NULL)
437 return NULL;
438
439 page_count = src->size / PAGE_SIZE;
440
441 dst = kmalloc(sizeof(*dst) + page_count * sizeof (u32 *), GFP_ATOMIC);
442 if (dst == NULL)
443 return NULL;
444
445 for (page = 0; page < page_count; page++) {
446 void *s, *d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
447 unsigned long flags;
448
449 if (d == NULL)
450 goto unwind;
451 local_irq_save(flags);
452 s = kmap_atomic(src_priv->pages[page], KM_IRQ0);
453 memcpy(d, s, PAGE_SIZE);
454 kunmap_atomic(s, KM_IRQ0);
455 local_irq_restore(flags);
456 dst->pages[page] = d;
457 }
458 dst->page_count = page_count;
459 dst->gtt_offset = src_priv->gtt_offset;
460
461 return dst;
462
463 unwind:
464 while (page--)
465 kfree(dst->pages[page]);
466 kfree(dst);
467 return NULL;
468 }
469
470 static void
471 i915_error_object_free(struct drm_i915_error_object *obj)
472 {
473 int page;
474
475 if (obj == NULL)
476 return;
477
478 for (page = 0; page < obj->page_count; page++)
479 kfree(obj->pages[page]);
480
481 kfree(obj);
482 }
483
484 static void
485 i915_error_state_free(struct drm_device *dev,
486 struct drm_i915_error_state *error)
487 {
488 i915_error_object_free(error->batchbuffer[0]);
489 i915_error_object_free(error->batchbuffer[1]);
490 i915_error_object_free(error->ringbuffer);
491 kfree(error->active_bo);
492 kfree(error);
493 }
494
495 static u32
496 i915_get_bbaddr(struct drm_device *dev, u32 *ring)
497 {
498 u32 cmd;
499
500 if (IS_I830(dev) || IS_845G(dev))
501 cmd = MI_BATCH_BUFFER;
502 else if (IS_I965G(dev))
503 cmd = (MI_BATCH_BUFFER_START | (2 << 6) |
504 MI_BATCH_NON_SECURE_I965);
505 else
506 cmd = (MI_BATCH_BUFFER_START | (2 << 6));
507
508 return ring[0] == cmd ? ring[1] : 0;
509 }
510
511 static u32
512 i915_ringbuffer_last_batch(struct drm_device *dev)
513 {
514 struct drm_i915_private *dev_priv = dev->dev_private;
515 u32 head, bbaddr;
516 u32 *ring;
517
518 /* Locate the current position in the ringbuffer and walk back
519 * to find the most recently dispatched batch buffer.
520 */
521 bbaddr = 0;
522 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
523 ring = (u32 *)(dev_priv->render_ring.virtual_start + head);
524
525 while (--ring >= (u32 *)dev_priv->render_ring.virtual_start) {
526 bbaddr = i915_get_bbaddr(dev, ring);
527 if (bbaddr)
528 break;
529 }
530
531 if (bbaddr == 0) {
532 ring = (u32 *)(dev_priv->render_ring.virtual_start
533 + dev_priv->render_ring.size);
534 while (--ring >= (u32 *)dev_priv->render_ring.virtual_start) {
535 bbaddr = i915_get_bbaddr(dev, ring);
536 if (bbaddr)
537 break;
538 }
539 }
540
541 return bbaddr;
542 }
543
544 /**
545 * i915_capture_error_state - capture an error record for later analysis
546 * @dev: drm device
547 *
548 * Should be called when an error is detected (either a hang or an error
549 * interrupt) to capture error state from the time of the error. Fills
550 * out a structure which becomes available in debugfs for user level tools
551 * to pick up.
552 */
553 static void i915_capture_error_state(struct drm_device *dev)
554 {
555 struct drm_i915_private *dev_priv = dev->dev_private;
556 struct drm_i915_gem_object *obj_priv;
557 struct drm_i915_error_state *error;
558 struct drm_gem_object *batchbuffer[2];
559 unsigned long flags;
560 u32 bbaddr;
561 int count;
562
563 spin_lock_irqsave(&dev_priv->error_lock, flags);
564 error = dev_priv->first_error;
565 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
566 if (error)
567 return;
568
569 error = kmalloc(sizeof(*error), GFP_ATOMIC);
570 if (!error) {
571 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
572 return;
573 }
574
575 error->seqno = i915_get_gem_seqno(dev, &dev_priv->render_ring);
576 error->eir = I915_READ(EIR);
577 error->pgtbl_er = I915_READ(PGTBL_ER);
578 error->pipeastat = I915_READ(PIPEASTAT);
579 error->pipebstat = I915_READ(PIPEBSTAT);
580 error->instpm = I915_READ(INSTPM);
581 if (!IS_I965G(dev)) {
582 error->ipeir = I915_READ(IPEIR);
583 error->ipehr = I915_READ(IPEHR);
584 error->instdone = I915_READ(INSTDONE);
585 error->acthd = I915_READ(ACTHD);
586 error->bbaddr = 0;
587 } else {
588 error->ipeir = I915_READ(IPEIR_I965);
589 error->ipehr = I915_READ(IPEHR_I965);
590 error->instdone = I915_READ(INSTDONE_I965);
591 error->instps = I915_READ(INSTPS);
592 error->instdone1 = I915_READ(INSTDONE1);
593 error->acthd = I915_READ(ACTHD_I965);
594 error->bbaddr = I915_READ64(BB_ADDR);
595 }
596
597 bbaddr = i915_ringbuffer_last_batch(dev);
598
599 /* Grab the current batchbuffer, most likely to have crashed. */
600 batchbuffer[0] = NULL;
601 batchbuffer[1] = NULL;
602 count = 0;
603 list_for_each_entry(obj_priv,
604 &dev_priv->render_ring.active_list, list) {
605
606 struct drm_gem_object *obj = &obj_priv->base;
607
608 if (batchbuffer[0] == NULL &&
609 bbaddr >= obj_priv->gtt_offset &&
610 bbaddr < obj_priv->gtt_offset + obj->size)
611 batchbuffer[0] = obj;
612
613 if (batchbuffer[1] == NULL &&
614 error->acthd >= obj_priv->gtt_offset &&
615 error->acthd < obj_priv->gtt_offset + obj->size &&
616 batchbuffer[0] != obj)
617 batchbuffer[1] = obj;
618
619 count++;
620 }
621
622 /* We need to copy these to an anonymous buffer as the simplest
623 * method to avoid being overwritten by userpace.
624 */
625 error->batchbuffer[0] = i915_error_object_create(dev, batchbuffer[0]);
626 error->batchbuffer[1] = i915_error_object_create(dev, batchbuffer[1]);
627
628 /* Record the ringbuffer */
629 error->ringbuffer = i915_error_object_create(dev,
630 dev_priv->render_ring.gem_object);
631
632 /* Record buffers on the active list. */
633 error->active_bo = NULL;
634 error->active_bo_count = 0;
635
636 if (count)
637 error->active_bo = kmalloc(sizeof(*error->active_bo)*count,
638 GFP_ATOMIC);
639
640 if (error->active_bo) {
641 int i = 0;
642 list_for_each_entry(obj_priv,
643 &dev_priv->render_ring.active_list, list) {
644 struct drm_gem_object *obj = &obj_priv->base;
645
646 error->active_bo[i].size = obj->size;
647 error->active_bo[i].name = obj->name;
648 error->active_bo[i].seqno = obj_priv->last_rendering_seqno;
649 error->active_bo[i].gtt_offset = obj_priv->gtt_offset;
650 error->active_bo[i].read_domains = obj->read_domains;
651 error->active_bo[i].write_domain = obj->write_domain;
652 error->active_bo[i].fence_reg = obj_priv->fence_reg;
653 error->active_bo[i].pinned = 0;
654 if (obj_priv->pin_count > 0)
655 error->active_bo[i].pinned = 1;
656 if (obj_priv->user_pin_count > 0)
657 error->active_bo[i].pinned = -1;
658 error->active_bo[i].tiling = obj_priv->tiling_mode;
659 error->active_bo[i].dirty = obj_priv->dirty;
660 error->active_bo[i].purgeable = obj_priv->madv != I915_MADV_WILLNEED;
661
662 if (++i == count)
663 break;
664 }
665 error->active_bo_count = i;
666 }
667
668 do_gettimeofday(&error->time);
669
670 spin_lock_irqsave(&dev_priv->error_lock, flags);
671 if (dev_priv->first_error == NULL) {
672 dev_priv->first_error = error;
673 error = NULL;
674 }
675 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
676
677 if (error)
678 i915_error_state_free(dev, error);
679 }
680
681 void i915_destroy_error_state(struct drm_device *dev)
682 {
683 struct drm_i915_private *dev_priv = dev->dev_private;
684 struct drm_i915_error_state *error;
685
686 spin_lock(&dev_priv->error_lock);
687 error = dev_priv->first_error;
688 dev_priv->first_error = NULL;
689 spin_unlock(&dev_priv->error_lock);
690
691 if (error)
692 i915_error_state_free(dev, error);
693 }
694
695 /**
696 * i915_handle_error - handle an error interrupt
697 * @dev: drm device
698 *
699 * Do some basic checking of regsiter state at error interrupt time and
700 * dump it to the syslog. Also call i915_capture_error_state() to make
701 * sure we get a record and make it available in debugfs. Fire a uevent
702 * so userspace knows something bad happened (should trigger collection
703 * of a ring dump etc.).
704 */
705 static void i915_handle_error(struct drm_device *dev, bool wedged)
706 {
707 struct drm_i915_private *dev_priv = dev->dev_private;
708 u32 eir = I915_READ(EIR);
709 u32 pipea_stats = I915_READ(PIPEASTAT);
710 u32 pipeb_stats = I915_READ(PIPEBSTAT);
711
712 i915_capture_error_state(dev);
713
714 printk(KERN_ERR "render error detected, EIR: 0x%08x\n",
715 eir);
716
717 if (IS_G4X(dev)) {
718 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
719 u32 ipeir = I915_READ(IPEIR_I965);
720
721 printk(KERN_ERR " IPEIR: 0x%08x\n",
722 I915_READ(IPEIR_I965));
723 printk(KERN_ERR " IPEHR: 0x%08x\n",
724 I915_READ(IPEHR_I965));
725 printk(KERN_ERR " INSTDONE: 0x%08x\n",
726 I915_READ(INSTDONE_I965));
727 printk(KERN_ERR " INSTPS: 0x%08x\n",
728 I915_READ(INSTPS));
729 printk(KERN_ERR " INSTDONE1: 0x%08x\n",
730 I915_READ(INSTDONE1));
731 printk(KERN_ERR " ACTHD: 0x%08x\n",
732 I915_READ(ACTHD_I965));
733 I915_WRITE(IPEIR_I965, ipeir);
734 (void)I915_READ(IPEIR_I965);
735 }
736 if (eir & GM45_ERROR_PAGE_TABLE) {
737 u32 pgtbl_err = I915_READ(PGTBL_ER);
738 printk(KERN_ERR "page table error\n");
739 printk(KERN_ERR " PGTBL_ER: 0x%08x\n",
740 pgtbl_err);
741 I915_WRITE(PGTBL_ER, pgtbl_err);
742 (void)I915_READ(PGTBL_ER);
743 }
744 }
745
746 if (IS_I9XX(dev)) {
747 if (eir & I915_ERROR_PAGE_TABLE) {
748 u32 pgtbl_err = I915_READ(PGTBL_ER);
749 printk(KERN_ERR "page table error\n");
750 printk(KERN_ERR " PGTBL_ER: 0x%08x\n",
751 pgtbl_err);
752 I915_WRITE(PGTBL_ER, pgtbl_err);
753 (void)I915_READ(PGTBL_ER);
754 }
755 }
756
757 if (eir & I915_ERROR_MEMORY_REFRESH) {
758 printk(KERN_ERR "memory refresh error\n");
759 printk(KERN_ERR "PIPEASTAT: 0x%08x\n",
760 pipea_stats);
761 printk(KERN_ERR "PIPEBSTAT: 0x%08x\n",
762 pipeb_stats);
763 /* pipestat has already been acked */
764 }
765 if (eir & I915_ERROR_INSTRUCTION) {
766 printk(KERN_ERR "instruction error\n");
767 printk(KERN_ERR " INSTPM: 0x%08x\n",
768 I915_READ(INSTPM));
769 if (!IS_I965G(dev)) {
770 u32 ipeir = I915_READ(IPEIR);
771
772 printk(KERN_ERR " IPEIR: 0x%08x\n",
773 I915_READ(IPEIR));
774 printk(KERN_ERR " IPEHR: 0x%08x\n",
775 I915_READ(IPEHR));
776 printk(KERN_ERR " INSTDONE: 0x%08x\n",
777 I915_READ(INSTDONE));
778 printk(KERN_ERR " ACTHD: 0x%08x\n",
779 I915_READ(ACTHD));
780 I915_WRITE(IPEIR, ipeir);
781 (void)I915_READ(IPEIR);
782 } else {
783 u32 ipeir = I915_READ(IPEIR_I965);
784
785 printk(KERN_ERR " IPEIR: 0x%08x\n",
786 I915_READ(IPEIR_I965));
787 printk(KERN_ERR " IPEHR: 0x%08x\n",
788 I915_READ(IPEHR_I965));
789 printk(KERN_ERR " INSTDONE: 0x%08x\n",
790 I915_READ(INSTDONE_I965));
791 printk(KERN_ERR " INSTPS: 0x%08x\n",
792 I915_READ(INSTPS));
793 printk(KERN_ERR " INSTDONE1: 0x%08x\n",
794 I915_READ(INSTDONE1));
795 printk(KERN_ERR " ACTHD: 0x%08x\n",
796 I915_READ(ACTHD_I965));
797 I915_WRITE(IPEIR_I965, ipeir);
798 (void)I915_READ(IPEIR_I965);
799 }
800 }
801
802 I915_WRITE(EIR, eir);
803 (void)I915_READ(EIR);
804 eir = I915_READ(EIR);
805 if (eir) {
806 /*
807 * some errors might have become stuck,
808 * mask them.
809 */
810 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
811 I915_WRITE(EMR, I915_READ(EMR) | eir);
812 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
813 }
814
815 if (wedged) {
816 atomic_set(&dev_priv->mm.wedged, 1);
817
818 /*
819 * Wakeup waiting processes so they don't hang
820 */
821 DRM_WAKEUP(&dev_priv->render_ring.irq_queue);
822 }
823
824 queue_work(dev_priv->wq, &dev_priv->error_work);
825 }
826
827 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
828 {
829 struct drm_device *dev = (struct drm_device *) arg;
830 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
831 struct drm_i915_master_private *master_priv;
832 u32 iir, new_iir;
833 u32 pipea_stats, pipeb_stats;
834 u32 vblank_status;
835 u32 vblank_enable;
836 int vblank = 0;
837 unsigned long irqflags;
838 int irq_received;
839 int ret = IRQ_NONE;
840 struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
841
842 atomic_inc(&dev_priv->irq_received);
843
844 if (HAS_PCH_SPLIT(dev))
845 return ironlake_irq_handler(dev);
846
847 iir = I915_READ(IIR);
848
849 if (IS_I965G(dev)) {
850 vblank_status = I915_START_VBLANK_INTERRUPT_STATUS;
851 vblank_enable = PIPE_START_VBLANK_INTERRUPT_ENABLE;
852 } else {
853 vblank_status = I915_VBLANK_INTERRUPT_STATUS;
854 vblank_enable = I915_VBLANK_INTERRUPT_ENABLE;
855 }
856
857 for (;;) {
858 irq_received = iir != 0;
859
860 /* Can't rely on pipestat interrupt bit in iir as it might
861 * have been cleared after the pipestat interrupt was received.
862 * It doesn't set the bit in iir again, but it still produces
863 * interrupts (for non-MSI).
864 */
865 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
866 pipea_stats = I915_READ(PIPEASTAT);
867 pipeb_stats = I915_READ(PIPEBSTAT);
868
869 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
870 i915_handle_error(dev, false);
871
872 /*
873 * Clear the PIPE(A|B)STAT regs before the IIR
874 */
875 if (pipea_stats & 0x8000ffff) {
876 if (pipea_stats & PIPE_FIFO_UNDERRUN_STATUS)
877 DRM_DEBUG_DRIVER("pipe a underrun\n");
878 I915_WRITE(PIPEASTAT, pipea_stats);
879 irq_received = 1;
880 }
881
882 if (pipeb_stats & 0x8000ffff) {
883 if (pipeb_stats & PIPE_FIFO_UNDERRUN_STATUS)
884 DRM_DEBUG_DRIVER("pipe b underrun\n");
885 I915_WRITE(PIPEBSTAT, pipeb_stats);
886 irq_received = 1;
887 }
888 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
889
890 if (!irq_received)
891 break;
892
893 ret = IRQ_HANDLED;
894
895 /* Consume port. Then clear IIR or we'll miss events */
896 if ((I915_HAS_HOTPLUG(dev)) &&
897 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
898 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
899
900 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
901 hotplug_status);
902 if (hotplug_status & dev_priv->hotplug_supported_mask)
903 queue_work(dev_priv->wq,
904 &dev_priv->hotplug_work);
905
906 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
907 I915_READ(PORT_HOTPLUG_STAT);
908 }
909
910 I915_WRITE(IIR, iir);
911 new_iir = I915_READ(IIR); /* Flush posted writes */
912
913 if (dev->primary->master) {
914 master_priv = dev->primary->master->driver_priv;
915 if (master_priv->sarea_priv)
916 master_priv->sarea_priv->last_dispatch =
917 READ_BREADCRUMB(dev_priv);
918 }
919
920 if (iir & I915_USER_INTERRUPT) {
921 u32 seqno =
922 render_ring->get_gem_seqno(dev, render_ring);
923 render_ring->irq_gem_seqno = seqno;
924 trace_i915_gem_request_complete(dev, seqno);
925 DRM_WAKEUP(&dev_priv->render_ring.irq_queue);
926 dev_priv->hangcheck_count = 0;
927 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
928 }
929
930 if (HAS_BSD(dev) && (iir & I915_BSD_USER_INTERRUPT))
931 DRM_WAKEUP(&dev_priv->bsd_ring.irq_queue);
932
933 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
934 intel_prepare_page_flip(dev, 0);
935
936 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
937 intel_prepare_page_flip(dev, 1);
938
939 if (pipea_stats & vblank_status) {
940 vblank++;
941 drm_handle_vblank(dev, 0);
942 intel_finish_page_flip(dev, 0);
943 }
944
945 if (pipeb_stats & vblank_status) {
946 vblank++;
947 drm_handle_vblank(dev, 1);
948 intel_finish_page_flip(dev, 1);
949 }
950
951 if ((pipea_stats & I915_LEGACY_BLC_EVENT_STATUS) ||
952 (pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS) ||
953 (iir & I915_ASLE_INTERRUPT))
954 opregion_asle_intr(dev);
955
956 /* With MSI, interrupts are only generated when iir
957 * transitions from zero to nonzero. If another bit got
958 * set while we were handling the existing iir bits, then
959 * we would never get another interrupt.
960 *
961 * This is fine on non-MSI as well, as if we hit this path
962 * we avoid exiting the interrupt handler only to generate
963 * another one.
964 *
965 * Note that for MSI this could cause a stray interrupt report
966 * if an interrupt landed in the time between writing IIR and
967 * the posting read. This should be rare enough to never
968 * trigger the 99% of 100,000 interrupts test for disabling
969 * stray interrupts.
970 */
971 iir = new_iir;
972 }
973
974 return ret;
975 }
976
977 static int i915_emit_irq(struct drm_device * dev)
978 {
979 drm_i915_private_t *dev_priv = dev->dev_private;
980 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
981
982 i915_kernel_lost_context(dev);
983
984 DRM_DEBUG_DRIVER("\n");
985
986 dev_priv->counter++;
987 if (dev_priv->counter > 0x7FFFFFFFUL)
988 dev_priv->counter = 1;
989 if (master_priv->sarea_priv)
990 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
991
992 BEGIN_LP_RING(4);
993 OUT_RING(MI_STORE_DWORD_INDEX);
994 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
995 OUT_RING(dev_priv->counter);
996 OUT_RING(MI_USER_INTERRUPT);
997 ADVANCE_LP_RING();
998
999 return dev_priv->counter;
1000 }
1001
1002 void i915_trace_irq_get(struct drm_device *dev, u32 seqno)
1003 {
1004 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1005 struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
1006
1007 if (dev_priv->trace_irq_seqno == 0)
1008 render_ring->user_irq_get(dev, render_ring);
1009
1010 dev_priv->trace_irq_seqno = seqno;
1011 }
1012
1013 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
1014 {
1015 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1016 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1017 int ret = 0;
1018 struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
1019
1020 DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
1021 READ_BREADCRUMB(dev_priv));
1022
1023 if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
1024 if (master_priv->sarea_priv)
1025 master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
1026 return 0;
1027 }
1028
1029 if (master_priv->sarea_priv)
1030 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1031
1032 render_ring->user_irq_get(dev, render_ring);
1033 DRM_WAIT_ON(ret, dev_priv->render_ring.irq_queue, 3 * DRM_HZ,
1034 READ_BREADCRUMB(dev_priv) >= irq_nr);
1035 render_ring->user_irq_put(dev, render_ring);
1036
1037 if (ret == -EBUSY) {
1038 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
1039 READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
1040 }
1041
1042 return ret;
1043 }
1044
1045 /* Needs the lock as it touches the ring.
1046 */
1047 int i915_irq_emit(struct drm_device *dev, void *data,
1048 struct drm_file *file_priv)
1049 {
1050 drm_i915_private_t *dev_priv = dev->dev_private;
1051 drm_i915_irq_emit_t *emit = data;
1052 int result;
1053
1054 if (!dev_priv || !dev_priv->render_ring.virtual_start) {
1055 DRM_ERROR("called with no initialization\n");
1056 return -EINVAL;
1057 }
1058
1059 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1060
1061 mutex_lock(&dev->struct_mutex);
1062 result = i915_emit_irq(dev);
1063 mutex_unlock(&dev->struct_mutex);
1064
1065 if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
1066 DRM_ERROR("copy_to_user\n");
1067 return -EFAULT;
1068 }
1069
1070 return 0;
1071 }
1072
1073 /* Doesn't need the hardware lock.
1074 */
1075 int i915_irq_wait(struct drm_device *dev, void *data,
1076 struct drm_file *file_priv)
1077 {
1078 drm_i915_private_t *dev_priv = dev->dev_private;
1079 drm_i915_irq_wait_t *irqwait = data;
1080
1081 if (!dev_priv) {
1082 DRM_ERROR("called with no initialization\n");
1083 return -EINVAL;
1084 }
1085
1086 return i915_wait_irq(dev, irqwait->irq_seq);
1087 }
1088
1089 /* Called from drm generic code, passed 'crtc' which
1090 * we use as a pipe index
1091 */
1092 int i915_enable_vblank(struct drm_device *dev, int pipe)
1093 {
1094 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1095 unsigned long irqflags;
1096 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1097 u32 pipeconf;
1098
1099 pipeconf = I915_READ(pipeconf_reg);
1100 if (!(pipeconf & PIPEACONF_ENABLE))
1101 return -EINVAL;
1102
1103 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
1104 if (HAS_PCH_SPLIT(dev))
1105 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1106 DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1107 else if (IS_I965G(dev))
1108 i915_enable_pipestat(dev_priv, pipe,
1109 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1110 else
1111 i915_enable_pipestat(dev_priv, pipe,
1112 PIPE_VBLANK_INTERRUPT_ENABLE);
1113 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
1114 return 0;
1115 }
1116
1117 /* Called from drm generic code, passed 'crtc' which
1118 * we use as a pipe index
1119 */
1120 void i915_disable_vblank(struct drm_device *dev, int pipe)
1121 {
1122 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1123 unsigned long irqflags;
1124
1125 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
1126 if (HAS_PCH_SPLIT(dev))
1127 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1128 DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1129 else
1130 i915_disable_pipestat(dev_priv, pipe,
1131 PIPE_VBLANK_INTERRUPT_ENABLE |
1132 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1133 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
1134 }
1135
1136 void i915_enable_interrupt (struct drm_device *dev)
1137 {
1138 struct drm_i915_private *dev_priv = dev->dev_private;
1139
1140 if (!HAS_PCH_SPLIT(dev))
1141 opregion_enable_asle(dev);
1142 dev_priv->irq_enabled = 1;
1143 }
1144
1145
1146 /* Set the vblank monitor pipe
1147 */
1148 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1149 struct drm_file *file_priv)
1150 {
1151 drm_i915_private_t *dev_priv = dev->dev_private;
1152
1153 if (!dev_priv) {
1154 DRM_ERROR("called with no initialization\n");
1155 return -EINVAL;
1156 }
1157
1158 return 0;
1159 }
1160
1161 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1162 struct drm_file *file_priv)
1163 {
1164 drm_i915_private_t *dev_priv = dev->dev_private;
1165 drm_i915_vblank_pipe_t *pipe = data;
1166
1167 if (!dev_priv) {
1168 DRM_ERROR("called with no initialization\n");
1169 return -EINVAL;
1170 }
1171
1172 pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1173
1174 return 0;
1175 }
1176
1177 /**
1178 * Schedule buffer swap at given vertical blank.
1179 */
1180 int i915_vblank_swap(struct drm_device *dev, void *data,
1181 struct drm_file *file_priv)
1182 {
1183 /* The delayed swap mechanism was fundamentally racy, and has been
1184 * removed. The model was that the client requested a delayed flip/swap
1185 * from the kernel, then waited for vblank before continuing to perform
1186 * rendering. The problem was that the kernel might wake the client
1187 * up before it dispatched the vblank swap (since the lock has to be
1188 * held while touching the ringbuffer), in which case the client would
1189 * clear and start the next frame before the swap occurred, and
1190 * flicker would occur in addition to likely missing the vblank.
1191 *
1192 * In the absence of this ioctl, userland falls back to a correct path
1193 * of waiting for a vblank, then dispatching the swap on its own.
1194 * Context switching to userland and back is plenty fast enough for
1195 * meeting the requirements of vblank swapping.
1196 */
1197 return -EINVAL;
1198 }
1199
1200 struct drm_i915_gem_request *
1201 i915_get_tail_request(struct drm_device *dev)
1202 {
1203 drm_i915_private_t *dev_priv = dev->dev_private;
1204 return list_entry(dev_priv->render_ring.request_list.prev,
1205 struct drm_i915_gem_request, list);
1206 }
1207
1208 /**
1209 * This is called when the chip hasn't reported back with completed
1210 * batchbuffers in a long time. The first time this is called we simply record
1211 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1212 * again, we assume the chip is wedged and try to fix it.
1213 */
1214 void i915_hangcheck_elapsed(unsigned long data)
1215 {
1216 struct drm_device *dev = (struct drm_device *)data;
1217 drm_i915_private_t *dev_priv = dev->dev_private;
1218 uint32_t acthd;
1219
1220 /* No reset support on this chip yet. */
1221 if (IS_GEN6(dev))
1222 return;
1223
1224 if (!IS_I965G(dev))
1225 acthd = I915_READ(ACTHD);
1226 else
1227 acthd = I915_READ(ACTHD_I965);
1228
1229 /* If all work is done then ACTHD clearly hasn't advanced. */
1230 if (list_empty(&dev_priv->render_ring.request_list) ||
1231 i915_seqno_passed(i915_get_gem_seqno(dev,
1232 &dev_priv->render_ring),
1233 i915_get_tail_request(dev)->seqno)) {
1234 dev_priv->hangcheck_count = 0;
1235 return;
1236 }
1237
1238 if (dev_priv->last_acthd == acthd && dev_priv->hangcheck_count > 0) {
1239 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1240 i915_handle_error(dev, true);
1241 return;
1242 }
1243
1244 /* Reset timer case chip hangs without another request being added */
1245 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1246
1247 if (acthd != dev_priv->last_acthd)
1248 dev_priv->hangcheck_count = 0;
1249 else
1250 dev_priv->hangcheck_count++;
1251
1252 dev_priv->last_acthd = acthd;
1253 }
1254
1255 /* drm_dma.h hooks
1256 */
1257 static void ironlake_irq_preinstall(struct drm_device *dev)
1258 {
1259 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1260
1261 I915_WRITE(HWSTAM, 0xeffe);
1262
1263 /* XXX hotplug from PCH */
1264
1265 I915_WRITE(DEIMR, 0xffffffff);
1266 I915_WRITE(DEIER, 0x0);
1267 (void) I915_READ(DEIER);
1268
1269 /* and GT */
1270 I915_WRITE(GTIMR, 0xffffffff);
1271 I915_WRITE(GTIER, 0x0);
1272 (void) I915_READ(GTIER);
1273
1274 /* south display irq */
1275 I915_WRITE(SDEIMR, 0xffffffff);
1276 I915_WRITE(SDEIER, 0x0);
1277 (void) I915_READ(SDEIER);
1278 }
1279
1280 static int ironlake_irq_postinstall(struct drm_device *dev)
1281 {
1282 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1283 /* enable kind of interrupts always enabled */
1284 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1285 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1286 u32 render_mask = GT_PIPE_NOTIFY | GT_BSD_USER_INTERRUPT;
1287 u32 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG |
1288 SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG;
1289
1290 dev_priv->irq_mask_reg = ~display_mask;
1291 dev_priv->de_irq_enable_reg = display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK;
1292
1293 /* should always can generate irq */
1294 I915_WRITE(DEIIR, I915_READ(DEIIR));
1295 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
1296 I915_WRITE(DEIER, dev_priv->de_irq_enable_reg);
1297 (void) I915_READ(DEIER);
1298
1299 /* user interrupt should be enabled, but masked initial */
1300 dev_priv->gt_irq_mask_reg = ~render_mask;
1301 dev_priv->gt_irq_enable_reg = render_mask;
1302
1303 I915_WRITE(GTIIR, I915_READ(GTIIR));
1304 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
1305 I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg);
1306 (void) I915_READ(GTIER);
1307
1308 dev_priv->pch_irq_mask_reg = ~hotplug_mask;
1309 dev_priv->pch_irq_enable_reg = hotplug_mask;
1310
1311 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1312 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask_reg);
1313 I915_WRITE(SDEIER, dev_priv->pch_irq_enable_reg);
1314 (void) I915_READ(SDEIER);
1315
1316 if (IS_IRONLAKE_M(dev)) {
1317 /* Clear & enable PCU event interrupts */
1318 I915_WRITE(DEIIR, DE_PCU_EVENT);
1319 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1320 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1321 }
1322
1323 return 0;
1324 }
1325
1326 void i915_driver_irq_preinstall(struct drm_device * dev)
1327 {
1328 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1329
1330 atomic_set(&dev_priv->irq_received, 0);
1331
1332 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
1333 INIT_WORK(&dev_priv->error_work, i915_error_work_func);
1334
1335 if (HAS_PCH_SPLIT(dev)) {
1336 ironlake_irq_preinstall(dev);
1337 return;
1338 }
1339
1340 if (I915_HAS_HOTPLUG(dev)) {
1341 I915_WRITE(PORT_HOTPLUG_EN, 0);
1342 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1343 }
1344
1345 I915_WRITE(HWSTAM, 0xeffe);
1346 I915_WRITE(PIPEASTAT, 0);
1347 I915_WRITE(PIPEBSTAT, 0);
1348 I915_WRITE(IMR, 0xffffffff);
1349 I915_WRITE(IER, 0x0);
1350 (void) I915_READ(IER);
1351 }
1352
1353 /*
1354 * Must be called after intel_modeset_init or hotplug interrupts won't be
1355 * enabled correctly.
1356 */
1357 int i915_driver_irq_postinstall(struct drm_device *dev)
1358 {
1359 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1360 u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
1361 u32 error_mask;
1362
1363 DRM_INIT_WAITQUEUE(&dev_priv->render_ring.irq_queue);
1364
1365 if (HAS_BSD(dev))
1366 DRM_INIT_WAITQUEUE(&dev_priv->bsd_ring.irq_queue);
1367
1368 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1369
1370 if (HAS_PCH_SPLIT(dev))
1371 return ironlake_irq_postinstall(dev);
1372
1373 /* Unmask the interrupts that we always want on. */
1374 dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX;
1375
1376 dev_priv->pipestat[0] = 0;
1377 dev_priv->pipestat[1] = 0;
1378
1379 if (I915_HAS_HOTPLUG(dev)) {
1380 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1381
1382 /* Note HDMI and DP share bits */
1383 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
1384 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
1385 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1386 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
1387 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1388 hotplug_en |= HDMID_HOTPLUG_INT_EN;
1389 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
1390 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
1391 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
1392 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
1393 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS)
1394 hotplug_en |= CRT_HOTPLUG_INT_EN;
1395 /* Ignore TV since it's buggy */
1396
1397 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
1398
1399 /* Enable in IER... */
1400 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
1401 /* and unmask in IMR */
1402 i915_enable_irq(dev_priv, I915_DISPLAY_PORT_INTERRUPT);
1403 }
1404
1405 /*
1406 * Enable some error detection, note the instruction error mask
1407 * bit is reserved, so we leave it masked.
1408 */
1409 if (IS_G4X(dev)) {
1410 error_mask = ~(GM45_ERROR_PAGE_TABLE |
1411 GM45_ERROR_MEM_PRIV |
1412 GM45_ERROR_CP_PRIV |
1413 I915_ERROR_MEMORY_REFRESH);
1414 } else {
1415 error_mask = ~(I915_ERROR_PAGE_TABLE |
1416 I915_ERROR_MEMORY_REFRESH);
1417 }
1418 I915_WRITE(EMR, error_mask);
1419
1420 /* Disable pipe interrupt enables, clear pending pipe status */
1421 I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1422 I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1423 /* Clear pending interrupt status */
1424 I915_WRITE(IIR, I915_READ(IIR));
1425
1426 I915_WRITE(IER, enable_mask);
1427 I915_WRITE(IMR, dev_priv->irq_mask_reg);
1428 (void) I915_READ(IER);
1429
1430 opregion_enable_asle(dev);
1431
1432 return 0;
1433 }
1434
1435 static void ironlake_irq_uninstall(struct drm_device *dev)
1436 {
1437 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1438 I915_WRITE(HWSTAM, 0xffffffff);
1439
1440 I915_WRITE(DEIMR, 0xffffffff);
1441 I915_WRITE(DEIER, 0x0);
1442 I915_WRITE(DEIIR, I915_READ(DEIIR));
1443
1444 I915_WRITE(GTIMR, 0xffffffff);
1445 I915_WRITE(GTIER, 0x0);
1446 I915_WRITE(GTIIR, I915_READ(GTIIR));
1447 }
1448
1449 void i915_driver_irq_uninstall(struct drm_device * dev)
1450 {
1451 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1452
1453 if (!dev_priv)
1454 return;
1455
1456 dev_priv->vblank_pipe = 0;
1457
1458 if (HAS_PCH_SPLIT(dev)) {
1459 ironlake_irq_uninstall(dev);
1460 return;
1461 }
1462
1463 if (I915_HAS_HOTPLUG(dev)) {
1464 I915_WRITE(PORT_HOTPLUG_EN, 0);
1465 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1466 }
1467
1468 I915_WRITE(HWSTAM, 0xffffffff);
1469 I915_WRITE(PIPEASTAT, 0);
1470 I915_WRITE(PIPEBSTAT, 0);
1471 I915_WRITE(IMR, 0xffffffff);
1472 I915_WRITE(IER, 0x0);
1473
1474 I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1475 I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1476 I915_WRITE(IIR, I915_READ(IIR));
1477 }
Linus' kernel tree