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[ALSA] Add HDSP MADI driver
[linux-2.6.git] / sound / pci / rme9652 / rme9652.c
blobf3037402d58fd199bb05c78f7669b84d4ecb4bf2
1 /*
2 * ALSA driver for RME Digi9652 audio interfaces
3 *
4 * Copyright (c) 1999 IEM - Winfried Ritsch
5 * Copyright (c) 1999-2001 Paul Davis
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 *
21 */
22
23 #include <sound/driver.h>
24 #include <linux/delay.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
27 #include <linux/pci.h>
28 #include <linux/slab.h>
29 #include <linux/moduleparam.h>
30
31 #include <sound/core.h>
32 #include <sound/control.h>
33 #include <sound/pcm.h>
34 #include <sound/info.h>
35 #include <sound/asoundef.h>
36 #include <sound/initval.h>
37
38 #include <asm/current.h>
39 #include <asm/io.h>
40
41 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
42 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
43 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
44 static int precise_ptr[SNDRV_CARDS] = { [0 ... (SNDRV_CARDS-1)] = 0 }; /* Enable precise pointer */
45
46 module_param_array(index, int, NULL, 0444);
47 MODULE_PARM_DESC(index, "Index value for RME Digi9652 (Hammerfall) soundcard.");
48 module_param_array(id, charp, NULL, 0444);
49 MODULE_PARM_DESC(id, "ID string for RME Digi9652 (Hammerfall) soundcard.");
50 module_param_array(enable, bool, NULL, 0444);
51 MODULE_PARM_DESC(enable, "Enable/disable specific RME96{52,36} soundcards.");
52 module_param_array(precise_ptr, bool, NULL, 0444);
53 MODULE_PARM_DESC(precise_ptr, "Enable precise pointer (doesn't work reliably).");
54 MODULE_AUTHOR("Paul Davis <pbd@op.net>, Winfried Ritsch");
55 MODULE_DESCRIPTION("RME Digi9652/Digi9636");
56 MODULE_LICENSE("GPL");
57 MODULE_SUPPORTED_DEVICE("{{RME,Hammerfall},"
58 "{RME,Hammerfall-Light}}");
59
60 /* The Hammerfall has two sets of 24 ADAT + 2 S/PDIF channels, one for
61 capture, one for playback. Both the ADAT and S/PDIF channels appear
62 to the host CPU in the same block of memory. There is no functional
63 difference between them in terms of access.
64
65 The Hammerfall Light is identical to the Hammerfall, except that it
66 has 2 sets 18 channels (16 ADAT + 2 S/PDIF) for capture and playback.
67 */
68
69 #define RME9652_NCHANNELS 26
70 #define RME9636_NCHANNELS 18
71
72 /* Preferred sync source choices - used by "sync_pref" control switch */
73
74 #define RME9652_SYNC_FROM_SPDIF 0
75 #define RME9652_SYNC_FROM_ADAT1 1
76 #define RME9652_SYNC_FROM_ADAT2 2
77 #define RME9652_SYNC_FROM_ADAT3 3
78
79 /* Possible sources of S/PDIF input */
80
81 #define RME9652_SPDIFIN_OPTICAL 0 /* optical (ADAT1) */
82 #define RME9652_SPDIFIN_COAXIAL 1 /* coaxial (RCA) */
83 #define RME9652_SPDIFIN_INTERN 2 /* internal (CDROM) */
84
85 /* ------------- Status-Register bits --------------------- */
86
87 #define RME9652_IRQ (1<<0) /* IRQ is High if not reset by irq_clear */
88 #define RME9652_lock_2 (1<<1) /* ADAT 3-PLL: 1=locked, 0=unlocked */
89 #define RME9652_lock_1 (1<<2) /* ADAT 2-PLL: 1=locked, 0=unlocked */
90 #define RME9652_lock_0 (1<<3) /* ADAT 1-PLL: 1=locked, 0=unlocked */
91 #define RME9652_fs48 (1<<4) /* sample rate is 0=44.1/88.2,1=48/96 Khz */
92 #define RME9652_wsel_rd (1<<5) /* if Word-Clock is used and valid then 1 */
93 /* bits 6-15 encode h/w buffer pointer position */
94 #define RME9652_sync_2 (1<<16) /* if ADAT-IN 3 in sync to system clock */
95 #define RME9652_sync_1 (1<<17) /* if ADAT-IN 2 in sync to system clock */
96 #define RME9652_sync_0 (1<<18) /* if ADAT-IN 1 in sync to system clock */
97 #define RME9652_DS_rd (1<<19) /* 1=Double Speed Mode, 0=Normal Speed */
98 #define RME9652_tc_busy (1<<20) /* 1=time-code copy in progress (960ms) */
99 #define RME9652_tc_out (1<<21) /* time-code out bit */
100 #define RME9652_F_0 (1<<22) /* 000=64kHz, 100=88.2kHz, 011=96kHz */
101 #define RME9652_F_1 (1<<23) /* 111=32kHz, 110=44.1kHz, 101=48kHz, */
102 #define RME9652_F_2 (1<<24) /* external Crystal Chip if ERF=1 */
103 #define RME9652_ERF (1<<25) /* Error-Flag of SDPIF Receiver (1=No Lock) */
104 #define RME9652_buffer_id (1<<26) /* toggles by each interrupt on rec/play */
105 #define RME9652_tc_valid (1<<27) /* 1 = a signal is detected on time-code input */
106 #define RME9652_SPDIF_READ (1<<28) /* byte available from Rev 1.5+ S/PDIF interface */
107
108 #define RME9652_sync (RME9652_sync_0|RME9652_sync_1|RME9652_sync_2)
109 #define RME9652_lock (RME9652_lock_0|RME9652_lock_1|RME9652_lock_2)
110 #define RME9652_F (RME9652_F_0|RME9652_F_1|RME9652_F_2)
111 #define rme9652_decode_spdif_rate(x) ((x)>>22)
112
113 /* Bit 6..15 : h/w buffer pointer */
114
115 #define RME9652_buf_pos 0x000FFC0
116
117 /* Bits 31,30,29 are bits 5,4,3 of h/w pointer position on later
118 Rev G EEPROMS and Rev 1.5 cards or later.
119 */
120
121 #define RME9652_REV15_buf_pos(x) ((((x)&0xE0000000)>>26)|((x)&RME9652_buf_pos))
122
123 #ifndef PCI_VENDOR_ID_XILINX
124 #define PCI_VENDOR_ID_XILINX 0x10ee
125 #endif
126 #ifndef PCI_DEVICE_ID_XILINX_HAMMERFALL
127 #define PCI_DEVICE_ID_XILINX_HAMMERFALL 0x3fc4
128 #endif
129
130 /* amount of io space we remap for register access. i'm not sure we
131 even need this much, but 1K is nice round number :)
132 */
133
134 #define RME9652_IO_EXTENT 1024
135
136 #define RME9652_init_buffer 0
137 #define RME9652_play_buffer 32 /* holds ptr to 26x64kBit host RAM */
138 #define RME9652_rec_buffer 36 /* holds ptr to 26x64kBit host RAM */
139 #define RME9652_control_register 64
140 #define RME9652_irq_clear 96
141 #define RME9652_time_code 100 /* useful if used with alesis adat */
142 #define RME9652_thru_base 128 /* 132...228 Thru for 26 channels */
143
144 /* Read-only registers */
145
146 /* Writing to any of the register locations writes to the status
147 register. We'll use the first location as our point of access.
148 */
149
150 #define RME9652_status_register 0
151
152 /* --------- Control-Register Bits ---------------- */
153
154
155 #define RME9652_start_bit (1<<0) /* start record/play */
156 /* bits 1-3 encode buffersize/latency */
157 #define RME9652_Master (1<<4) /* Clock Mode Master=1,Slave/Auto=0 */
158 #define RME9652_IE (1<<5) /* Interupt Enable */
159 #define RME9652_freq (1<<6) /* samplerate 0=44.1/88.2, 1=48/96 kHz */
160 #define RME9652_freq1 (1<<7) /* if 0, 32kHz, else always 1 */
161 #define RME9652_DS (1<<8) /* Doule Speed 0=44.1/48, 1=88.2/96 Khz */
162 #define RME9652_PRO (1<<9) /* S/PDIF out: 0=consumer, 1=professional */
163 #define RME9652_EMP (1<<10) /* Emphasis 0=None, 1=ON */
164 #define RME9652_Dolby (1<<11) /* Non-audio bit 1=set, 0=unset */
165 #define RME9652_opt_out (1<<12) /* Use 1st optical OUT as SPDIF: 1=yes,0=no */
166 #define RME9652_wsel (1<<13) /* use Wordclock as sync (overwrites master) */
167 #define RME9652_inp_0 (1<<14) /* SPDIF-IN: 00=optical (ADAT1), */
168 #define RME9652_inp_1 (1<<15) /* 01=koaxial (Cinch), 10=Internal CDROM */
169 #define RME9652_SyncPref_ADAT2 (1<<16)
170 #define RME9652_SyncPref_ADAT3 (1<<17)
171 #define RME9652_SPDIF_RESET (1<<18) /* Rev 1.5+: h/w S/PDIF receiver */
172 #define RME9652_SPDIF_SELECT (1<<19)
173 #define RME9652_SPDIF_CLOCK (1<<20)
174 #define RME9652_SPDIF_WRITE (1<<21)
175 #define RME9652_ADAT1_INTERNAL (1<<22) /* Rev 1.5+: if set, internal CD connector carries ADAT */
176
177 /* buffersize = 512Bytes * 2^n, where n is made from Bit2 ... Bit0 */
178
179 #define RME9652_latency 0x0e
180 #define rme9652_encode_latency(x) (((x)&0x7)<<1)
181 #define rme9652_decode_latency(x) (((x)>>1)&0x7)
182 #define rme9652_running_double_speed(s) ((s)->control_register & RME9652_DS)
183 #define RME9652_inp (RME9652_inp_0|RME9652_inp_1)
184 #define rme9652_encode_spdif_in(x) (((x)&0x3)<<14)
185 #define rme9652_decode_spdif_in(x) (((x)>>14)&0x3)
186
187 #define RME9652_SyncPref_Mask (RME9652_SyncPref_ADAT2|RME9652_SyncPref_ADAT3)
188 #define RME9652_SyncPref_ADAT1 0
189 #define RME9652_SyncPref_SPDIF (RME9652_SyncPref_ADAT2|RME9652_SyncPref_ADAT3)
190
191 /* the size of a substream (1 mono data stream) */
192
193 #define RME9652_CHANNEL_BUFFER_SAMPLES (16*1024)
194 #define RME9652_CHANNEL_BUFFER_BYTES (4*RME9652_CHANNEL_BUFFER_SAMPLES)
195
196 /* the size of the area we need to allocate for DMA transfers. the
197 size is the same regardless of the number of channels - the
198 9636 still uses the same memory area.
199
200 Note that we allocate 1 more channel than is apparently needed
201 because the h/w seems to write 1 byte beyond the end of the last
202 page. Sigh.
203 */
204
205 #define RME9652_DMA_AREA_BYTES ((RME9652_NCHANNELS+1) * RME9652_CHANNEL_BUFFER_BYTES)
206 #define RME9652_DMA_AREA_KILOBYTES (RME9652_DMA_AREA_BYTES/1024)
207
208 typedef struct snd_rme9652 {
209 int dev;
210
211 spinlock_t lock;
212 int irq;
213 unsigned long port;
214 void __iomem *iobase;
215
216 int precise_ptr;
217
218 u32 control_register; /* cached value */
219 u32 thru_bits; /* thru 1=on, 0=off channel 1=Bit1... channel 26= Bit26 */
220
221 u32 creg_spdif;
222 u32 creg_spdif_stream;
223
224 char *card_name; /* hammerfall or hammerfall light names */
225
226 size_t hw_offsetmask; /* &-with status register to get real hw_offset */
227 size_t prev_hw_offset; /* previous hw offset */
228 size_t max_jitter; /* maximum jitter in frames for
229 hw pointer */
230 size_t period_bytes; /* guess what this is */
231
232 unsigned char ds_channels;
233 unsigned char ss_channels; /* different for hammerfall/hammerfall-light */
234
235 struct snd_dma_buffer playback_dma_buf;
236 struct snd_dma_buffer capture_dma_buf;
237
238 unsigned char *capture_buffer; /* suitably aligned address */
239 unsigned char *playback_buffer; /* suitably aligned address */
240
241 pid_t capture_pid;
242 pid_t playback_pid;
243
244 snd_pcm_substream_t *capture_substream;
245 snd_pcm_substream_t *playback_substream;
246 int running;
247
248 int passthru; /* non-zero if doing pass-thru */
249 int hw_rev; /* h/w rev * 10 (i.e. 1.5 has hw_rev = 15) */
250
251 int last_spdif_sample_rate; /* so that we can catch externally ... */
252 int last_adat_sample_rate; /* ... induced rate changes */
253
254 char *channel_map;
255
256 snd_card_t *card;
257 snd_pcm_t *pcm;
258 struct pci_dev *pci;
259 snd_kcontrol_t *spdif_ctl;
260
261 } rme9652_t;
262
263 /* These tables map the ALSA channels 1..N to the channels that we
264 need to use in order to find the relevant channel buffer. RME
265 refer to this kind of mapping as between "the ADAT channel and
266 the DMA channel." We index it using the logical audio channel,
267 and the value is the DMA channel (i.e. channel buffer number)
268 where the data for that channel can be read/written from/to.
269 */
270
271 static char channel_map_9652_ss[26] = {
272 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
273 18, 19, 20, 21, 22, 23, 24, 25
274 };
275
276 static char channel_map_9636_ss[26] = {
277 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
278 /* channels 16 and 17 are S/PDIF */
279 24, 25,
280 /* channels 18-25 don't exist */
281 -1, -1, -1, -1, -1, -1, -1, -1
282 };
283
284 static char channel_map_9652_ds[26] = {
285 /* ADAT channels are remapped */
286 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23,
287 /* channels 12 and 13 are S/PDIF */
288 24, 25,
289 /* others don't exist */
290 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
291 };
292
293 static char channel_map_9636_ds[26] = {
294 /* ADAT channels are remapped */
295 1, 3, 5, 7, 9, 11, 13, 15,
296 /* channels 8 and 9 are S/PDIF */
297 24, 25
298 /* others don't exist */
299 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
300 };
301
302 static int snd_hammerfall_get_buffer(struct pci_dev *pci, struct snd_dma_buffer *dmab, size_t size)
303 {
304 dmab->dev.type = SNDRV_DMA_TYPE_DEV;
305 dmab->dev.dev = snd_dma_pci_data(pci);
306 if (snd_dma_get_reserved_buf(dmab, snd_dma_pci_buf_id(pci))) {
307 if (dmab->bytes >= size)
308 return 0;
309 }
310 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
311 size, dmab) < 0)
312 return -ENOMEM;
313 return 0;
314 }
315
316 static void snd_hammerfall_free_buffer(struct snd_dma_buffer *dmab, struct pci_dev *pci)
317 {
318 if (dmab->area) {
319 dmab->dev.dev = NULL; /* make it anonymous */
320 snd_dma_reserve_buf(dmab, snd_dma_pci_buf_id(pci));
321 }
322 }
323
324
325 static struct pci_device_id snd_rme9652_ids[] = {
326 {
327 .vendor = 0x10ee,
328 .device = 0x3fc4,
329 .subvendor = PCI_ANY_ID,
330 .subdevice = PCI_ANY_ID,
331 }, /* RME Digi9652 */
332 { 0, },
333 };
334
335 MODULE_DEVICE_TABLE(pci, snd_rme9652_ids);
336
337 static inline void rme9652_write(rme9652_t *rme9652, int reg, int val)
338 {
339 writel(val, rme9652->iobase + reg);
340 }
341
342 static inline unsigned int rme9652_read(rme9652_t *rme9652, int reg)
343 {
344 return readl(rme9652->iobase + reg);
345 }
346
347 static inline int snd_rme9652_use_is_exclusive(rme9652_t *rme9652)
348 {
349 unsigned long flags;
350 int ret = 1;
351
352 spin_lock_irqsave(&rme9652->lock, flags);
353 if ((rme9652->playback_pid != rme9652->capture_pid) &&
354 (rme9652->playback_pid >= 0) && (rme9652->capture_pid >= 0)) {
355 ret = 0;
356 }
357 spin_unlock_irqrestore(&rme9652->lock, flags);
358 return ret;
359 }
360
361 static inline int rme9652_adat_sample_rate(rme9652_t *rme9652)
362 {
363 if (rme9652_running_double_speed(rme9652)) {
364 return (rme9652_read(rme9652, RME9652_status_register) &
365 RME9652_fs48) ? 96000 : 88200;
366 } else {
367 return (rme9652_read(rme9652, RME9652_status_register) &
368 RME9652_fs48) ? 48000 : 44100;
369 }
370 }
371
372 static inline void rme9652_compute_period_size(rme9652_t *rme9652)
373 {
374 unsigned int i;
375
376 i = rme9652->control_register & RME9652_latency;
377 rme9652->period_bytes = 1 << ((rme9652_decode_latency(i) + 8));
378 rme9652->hw_offsetmask =
379 (rme9652->period_bytes * 2 - 1) & RME9652_buf_pos;
380 rme9652->max_jitter = 80;
381 }
382
383 static snd_pcm_uframes_t rme9652_hw_pointer(rme9652_t *rme9652)
384 {
385 int status;
386 unsigned int offset, frag;
387 snd_pcm_uframes_t period_size = rme9652->period_bytes / 4;
388 snd_pcm_sframes_t delta;
389
390 status = rme9652_read(rme9652, RME9652_status_register);
391 if (!rme9652->precise_ptr)
392 return (status & RME9652_buffer_id) ? period_size : 0;
393 offset = status & RME9652_buf_pos;
394
395 /* The hardware may give a backward movement for up to 80 frames
396 Martin Kirst <martin.kirst@freenet.de> knows the details.
397 */
398
399 delta = rme9652->prev_hw_offset - offset;
400 delta &= 0xffff;
401 if (delta <= (snd_pcm_sframes_t)rme9652->max_jitter * 4)
402 offset = rme9652->prev_hw_offset;
403 else
404 rme9652->prev_hw_offset = offset;
405 offset &= rme9652->hw_offsetmask;
406 offset /= 4;
407 frag = status & RME9652_buffer_id;
408
409 if (offset < period_size) {
410 if (offset > rme9652->max_jitter) {
411 if (frag)
412 printk(KERN_ERR "Unexpected hw_pointer position (bufid == 0): status: %x offset: %d\n", status, offset);
413 } else if (!frag)
414 return 0;
415 offset -= rme9652->max_jitter;
416 if (offset < 0)
417 offset += period_size * 2;
418 } else {
419 if (offset > period_size + rme9652->max_jitter) {
420 if (!frag)
421 printk(KERN_ERR "Unexpected hw_pointer position (bufid == 1): status: %x offset: %d\n", status, offset);
422 } else if (frag)
423 return period_size;
424 offset -= rme9652->max_jitter;
425 }
426
427 return offset;
428 }
429
430 static inline void rme9652_reset_hw_pointer(rme9652_t *rme9652)
431 {
432 int i;
433
434 /* reset the FIFO pointer to zero. We do this by writing to 8
435 registers, each of which is a 32bit wide register, and set
436 them all to zero. Note that s->iobase is a pointer to
437 int32, not pointer to char.
438 */
439
440 for (i = 0; i < 8; i++) {
441 rme9652_write(rme9652, i * 4, 0);
442 udelay(10);
443 }
444 rme9652->prev_hw_offset = 0;
445 }
446
447 static inline void rme9652_start(rme9652_t *s)
448 {
449 s->control_register |= (RME9652_IE | RME9652_start_bit);
450 rme9652_write(s, RME9652_control_register, s->control_register);
451 }
452
453 static inline void rme9652_stop(rme9652_t *s)
454 {
455 s->control_register &= ~(RME9652_start_bit | RME9652_IE);
456 rme9652_write(s, RME9652_control_register, s->control_register);
457 }
458
459 static int rme9652_set_interrupt_interval(rme9652_t *s,
460 unsigned int frames)
461 {
462 int restart = 0;
463 int n;
464
465 spin_lock_irq(&s->lock);
466
467 if ((restart = s->running)) {
468 rme9652_stop(s);
469 }
470
471 frames >>= 7;
472 n = 0;
473 while (frames) {
474 n++;
475 frames >>= 1;
476 }
477
478 s->control_register &= ~RME9652_latency;
479 s->control_register |= rme9652_encode_latency(n);
480
481 rme9652_write(s, RME9652_control_register, s->control_register);
482
483 rme9652_compute_period_size(s);
484
485 if (restart)
486 rme9652_start(s);
487
488 spin_unlock_irq(&s->lock);
489
490 return 0;
491 }
492
493 static int rme9652_set_rate(rme9652_t *rme9652, int rate)
494 {
495 int restart;
496 int reject_if_open = 0;
497 int xrate;
498
499 if (!snd_rme9652_use_is_exclusive (rme9652)) {
500 return -EBUSY;
501 }
502
503 /* Changing from a "single speed" to a "double speed" rate is
504 not allowed if any substreams are open. This is because
505 such a change causes a shift in the location of
506 the DMA buffers and a reduction in the number of available
507 buffers.
508
509 Note that a similar but essentially insoluble problem
510 exists for externally-driven rate changes. All we can do
511 is to flag rate changes in the read/write routines.
512 */
513
514 spin_lock_irq(&rme9652->lock);
515 xrate = rme9652_adat_sample_rate(rme9652);
516
517 switch (rate) {
518 case 44100:
519 if (xrate > 48000) {
520 reject_if_open = 1;
521 }
522 rate = 0;
523 break;
524 case 48000:
525 if (xrate > 48000) {
526 reject_if_open = 1;
527 }
528 rate = RME9652_freq;
529 break;
530 case 88200:
531 if (xrate < 48000) {
532 reject_if_open = 1;
533 }
534 rate = RME9652_DS;
535 break;
536 case 96000:
537 if (xrate < 48000) {
538 reject_if_open = 1;
539 }
540 rate = RME9652_DS | RME9652_freq;
541 break;
542 default:
543 spin_unlock_irq(&rme9652->lock);
544 return -EINVAL;
545 }
546
547 if (reject_if_open && (rme9652->capture_pid >= 0 || rme9652->playback_pid >= 0)) {
548 spin_unlock_irq(&rme9652->lock);
549 return -EBUSY;
550 }
551
552 if ((restart = rme9652->running)) {
553 rme9652_stop(rme9652);
554 }
555 rme9652->control_register &= ~(RME9652_freq | RME9652_DS);
556 rme9652->control_register |= rate;
557 rme9652_write(rme9652, RME9652_control_register, rme9652->control_register);
558
559 if (restart) {
560 rme9652_start(rme9652);
561 }
562
563 if (rate & RME9652_DS) {
564 if (rme9652->ss_channels == RME9652_NCHANNELS) {
565 rme9652->channel_map = channel_map_9652_ds;
566 } else {
567 rme9652->channel_map = channel_map_9636_ds;
568 }
569 } else {
570 if (rme9652->ss_channels == RME9652_NCHANNELS) {
571 rme9652->channel_map = channel_map_9652_ss;
572 } else {
573 rme9652->channel_map = channel_map_9636_ss;
574 }
575 }
576
577 spin_unlock_irq(&rme9652->lock);
578 return 0;
579 }
580
581 static void rme9652_set_thru(rme9652_t *rme9652, int channel, int enable)
582 {
583 int i;
584
585 rme9652->passthru = 0;
586
587 if (channel < 0) {
588
589 /* set thru for all channels */
590
591 if (enable) {
592 for (i = 0; i < RME9652_NCHANNELS; i++) {
593 rme9652->thru_bits |= (1 << i);
594 rme9652_write(rme9652, RME9652_thru_base + i * 4, 1);
595 }
596 } else {
597 for (i = 0; i < RME9652_NCHANNELS; i++) {
598 rme9652->thru_bits &= ~(1 << i);
599 rme9652_write(rme9652, RME9652_thru_base + i * 4, 0);
600 }
601 }
602
603 } else {
604 int mapped_channel;
605
606 snd_assert(channel == RME9652_NCHANNELS, return);
607
608 mapped_channel = rme9652->channel_map[channel];
609
610 if (enable) {
611 rme9652->thru_bits |= (1 << mapped_channel);
612 } else {
613 rme9652->thru_bits &= ~(1 << mapped_channel);
614 }
615
616 rme9652_write(rme9652,
617 RME9652_thru_base + mapped_channel * 4,
618 enable ? 1 : 0);
619 }
620 }
621
622 static int rme9652_set_passthru(rme9652_t *rme9652, int onoff)
623 {
624 if (onoff) {
625 rme9652_set_thru(rme9652, -1, 1);
626
627 /* we don't want interrupts, so do a
628 custom version of rme9652_start().
629 */
630
631 rme9652->control_register =
632 RME9652_inp_0 |
633 rme9652_encode_latency(7) |
634 RME9652_start_bit;
635
636 rme9652_reset_hw_pointer(rme9652);
637
638 rme9652_write(rme9652, RME9652_control_register,
639 rme9652->control_register);
640 rme9652->passthru = 1;
641 } else {
642 rme9652_set_thru(rme9652, -1, 0);
643 rme9652_stop(rme9652);
644 rme9652->passthru = 0;
645 }
646
647 return 0;
648 }
649
650 static void rme9652_spdif_set_bit (rme9652_t *rme9652, int mask, int onoff)
651 {
652 if (onoff)
653 rme9652->control_register |= mask;
654 else
655 rme9652->control_register &= ~mask;
656
657 rme9652_write(rme9652, RME9652_control_register, rme9652->control_register);
658 }
659
660 static void rme9652_spdif_write_byte (rme9652_t *rme9652, const int val)
661 {
662 long mask;
663 long i;
664
665 for (i = 0, mask = 0x80; i < 8; i++, mask >>= 1) {
666 if (val & mask)
667 rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_WRITE, 1);
668 else
669 rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_WRITE, 0);
670
671 rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_CLOCK, 1);
672 rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_CLOCK, 0);
673 }
674 }
675
676 static int rme9652_spdif_read_byte (rme9652_t *rme9652)
677 {
678 long mask;
679 long val;
680 long i;
681
682 val = 0;
683
684 for (i = 0, mask = 0x80; i < 8; i++, mask >>= 1) {
685 rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_CLOCK, 1);
686 if (rme9652_read (rme9652, RME9652_status_register) & RME9652_SPDIF_READ)
687 val |= mask;
688 rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_CLOCK, 0);
689 }
690
691 return val;
692 }
693
694 static void rme9652_write_spdif_codec (rme9652_t *rme9652, const int address, const int data)
695 {
696 rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_SELECT, 1);
697 rme9652_spdif_write_byte (rme9652, 0x20);
698 rme9652_spdif_write_byte (rme9652, address);
699 rme9652_spdif_write_byte (rme9652, data);
700 rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_SELECT, 0);
701 }
702
703
704 static int rme9652_spdif_read_codec (rme9652_t *rme9652, const int address)
705 {
706 int ret;
707
708 rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_SELECT, 1);
709 rme9652_spdif_write_byte (rme9652, 0x20);
710 rme9652_spdif_write_byte (rme9652, address);
711 rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_SELECT, 0);
712 rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_SELECT, 1);
713
714 rme9652_spdif_write_byte (rme9652, 0x21);
715 ret = rme9652_spdif_read_byte (rme9652);
716 rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_SELECT, 0);
717
718 return ret;
719 }
720
721 static void rme9652_initialize_spdif_receiver (rme9652_t *rme9652)
722 {
723 /* XXX what unsets this ? */
724
725 rme9652->control_register |= RME9652_SPDIF_RESET;
726
727 rme9652_write_spdif_codec (rme9652, 4, 0x40);
728 rme9652_write_spdif_codec (rme9652, 17, 0x13);
729 rme9652_write_spdif_codec (rme9652, 6, 0x02);
730 }
731
732 static inline int rme9652_spdif_sample_rate(rme9652_t *s)
733 {
734 unsigned int rate_bits;
735
736 if (rme9652_read(s, RME9652_status_register) & RME9652_ERF) {
737 return -1; /* error condition */
738 }
739
740 if (s->hw_rev == 15) {
741
742 int x, y, ret;
743
744 x = rme9652_spdif_read_codec (s, 30);
745
746 if (x != 0)
747 y = 48000 * 64 / x;
748 else
749 y = 0;
750
751 if (y > 30400 && y < 33600) ret = 32000;
752 else if (y > 41900 && y < 46000) ret = 44100;
753 else if (y > 46000 && y < 50400) ret = 48000;
754 else if (y > 60800 && y < 67200) ret = 64000;
755 else if (y > 83700 && y < 92000) ret = 88200;
756 else if (y > 92000 && y < 100000) ret = 96000;
757 else ret = 0;
758 return ret;
759 }
760
761 rate_bits = rme9652_read(s, RME9652_status_register) & RME9652_F;
762
763 switch (rme9652_decode_spdif_rate(rate_bits)) {
764 case 0x7:
765 return 32000;
766 break;
767
768 case 0x6:
769 return 44100;
770 break;
771
772 case 0x5:
773 return 48000;
774 break;
775
776 case 0x4:
777 return 88200;
778 break;
779
780 case 0x3:
781 return 96000;
782 break;
783
784 case 0x0:
785 return 64000;
786 break;
787
788 default:
789 snd_printk("%s: unknown S/PDIF input rate (bits = 0x%x)\n",
790 s->card_name, rate_bits);
791 return 0;
792 break;
793 }
794 }
795
796 /*-----------------------------------------------------------------------------
797 Control Interface
798 ----------------------------------------------------------------------------*/
799
800 static u32 snd_rme9652_convert_from_aes(snd_aes_iec958_t *aes)
801 {
802 u32 val = 0;
803 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME9652_PRO : 0;
804 val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? RME9652_Dolby : 0;
805 if (val & RME9652_PRO)
806 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME9652_EMP : 0;
807 else
808 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME9652_EMP : 0;
809 return val;
810 }
811
812 static void snd_rme9652_convert_to_aes(snd_aes_iec958_t *aes, u32 val)
813 {
814 aes->status[0] = ((val & RME9652_PRO) ? IEC958_AES0_PROFESSIONAL : 0) |
815 ((val & RME9652_Dolby) ? IEC958_AES0_NONAUDIO : 0);
816 if (val & RME9652_PRO)
817 aes->status[0] |= (val & RME9652_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
818 else
819 aes->status[0] |= (val & RME9652_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
820 }
821
822 static int snd_rme9652_control_spdif_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
823 {
824 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
825 uinfo->count = 1;
826 return 0;
827 }
828
829 static int snd_rme9652_control_spdif_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
830 {
831 rme9652_t *rme9652 = snd_kcontrol_chip(kcontrol);
832
833 snd_rme9652_convert_to_aes(&ucontrol->value.iec958, rme9652->creg_spdif);
834 return 0;
835 }
836
837 static int snd_rme9652_control_spdif_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
838 {
839 rme9652_t *rme9652 = snd_kcontrol_chip(kcontrol);
840 int change;
841 u32 val;
842
843 val = snd_rme9652_convert_from_aes(&ucontrol->value.iec958);
844 spin_lock_irq(&rme9652->lock);
845 change = val != rme9652->creg_spdif;
846 rme9652->creg_spdif = val;
847 spin_unlock_irq(&rme9652->lock);
848 return change;
849 }
850
851 static int snd_rme9652_control_spdif_stream_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
852 {
853 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
854 uinfo->count = 1;
855 return 0;
856 }
857
858 static int snd_rme9652_control_spdif_stream_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
859 {
860 rme9652_t *rme9652 = snd_kcontrol_chip(kcontrol);
861
862 snd_rme9652_convert_to_aes(&ucontrol->value.iec958, rme9652->creg_spdif_stream);
863 return 0;
864 }
865
866 static int snd_rme9652_control_spdif_stream_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
867 {
868 rme9652_t *rme9652 = snd_kcontrol_chip(kcontrol);
869 int change;
870 u32 val;
871
872 val = snd_rme9652_convert_from_aes(&ucontrol->value.iec958);
873 spin_lock_irq(&rme9652->lock);
874 change = val != rme9652->creg_spdif_stream;
875 rme9652->creg_spdif_stream = val;
876 rme9652->control_register &= ~(RME9652_PRO | RME9652_Dolby | RME9652_EMP);
877 rme9652_write(rme9652, RME9652_control_register, rme9652->control_register |= val);
878 spin_unlock_irq(&rme9652->lock);
879 return change;
880 }
881
882 static int snd_rme9652_control_spdif_mask_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
883 {
884 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
885 uinfo->count = 1;
886 return 0;
887 }
888
889 static int snd_rme9652_control_spdif_mask_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
890 {
891 ucontrol->value.iec958.status[0] = kcontrol->private_value;
892 return 0;
893 }
894
895 #define RME9652_ADAT1_IN(xname, xindex) \
896 { .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = xname, .index = xindex, \
897 .info = snd_rme9652_info_adat1_in, \
898 .get = snd_rme9652_get_adat1_in, \
899 .put = snd_rme9652_put_adat1_in }
900
901 static unsigned int rme9652_adat1_in(rme9652_t *rme9652)
902 {
903 if (rme9652->control_register & RME9652_ADAT1_INTERNAL)
904 return 1;
905 return 0;
906 }
907
908 static int rme9652_set_adat1_input(rme9652_t *rme9652, int internal)
909 {
910 int restart = 0;
911
912 if (internal) {
913 rme9652->control_register |= RME9652_ADAT1_INTERNAL;
914 } else {
915 rme9652->control_register &= ~RME9652_ADAT1_INTERNAL;
916 }
917
918 /* XXX do we actually need to stop the card when we do this ? */
919
920 if ((restart = rme9652->running)) {
921 rme9652_stop(rme9652);
922 }
923
924 rme9652_write(rme9652, RME9652_control_register, rme9652->control_register);
925
926 if (restart) {
927 rme9652_start(rme9652);
928 }
929
930 return 0;
931 }
932
933 static int snd_rme9652_info_adat1_in(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
934 {
935 static char *texts[2] = {"ADAT1", "Internal"};
936
937 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
938 uinfo->count = 1;
939 uinfo->value.enumerated.items = 2;
940 if (uinfo->value.enumerated.item > 1)
941 uinfo->value.enumerated.item = 1;
942 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
943 return 0;
944 }
945
946 static int snd_rme9652_get_adat1_in(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
947 {
948 rme9652_t *rme9652 = snd_kcontrol_chip(kcontrol);
949
950 spin_lock_irq(&rme9652->lock);
951 ucontrol->value.enumerated.item[0] = rme9652_adat1_in(rme9652);
952 spin_unlock_irq(&rme9652->lock);
953 return 0;
954 }
955
956 static int snd_rme9652_put_adat1_in(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
957 {
958 rme9652_t *rme9652 = snd_kcontrol_chip(kcontrol);
959 int change;
960 unsigned int val;
961
962 if (!snd_rme9652_use_is_exclusive(rme9652))
963 return -EBUSY;
964 val = ucontrol->value.enumerated.item[0] % 2;
965 spin_lock_irq(&rme9652->lock);
966 change = val != rme9652_adat1_in(rme9652);
967 if (change)
968 rme9652_set_adat1_input(rme9652, val);
969 spin_unlock_irq(&rme9652->lock);
970 return change;
971 }
972
973 #define RME9652_SPDIF_IN(xname, xindex) \
974 { .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = xname, .index = xindex, \
975 .info = snd_rme9652_info_spdif_in, \
976 .get = snd_rme9652_get_spdif_in, .put = snd_rme9652_put_spdif_in }
977
978 static unsigned int rme9652_spdif_in(rme9652_t *rme9652)
979 {
980 return rme9652_decode_spdif_in(rme9652->control_register &
981 RME9652_inp);
982 }
983
984 static int rme9652_set_spdif_input(rme9652_t *rme9652, int in)
985 {
986 int restart = 0;
987
988 rme9652->control_register &= ~RME9652_inp;
989 rme9652->control_register |= rme9652_encode_spdif_in(in);
990
991 if ((restart = rme9652->running)) {
992 rme9652_stop(rme9652);
993 }
994
995 rme9652_write(rme9652, RME9652_control_register, rme9652->control_register);
996
997 if (restart) {
998 rme9652_start(rme9652);
999 }
1000
1001 return 0;
1002 }
1003
1004 static int snd_rme9652_info_spdif_in(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1005 {
1006 static char *texts[3] = {"ADAT1", "Coaxial", "Internal"};
1007
1008 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1009 uinfo->count = 1;
1010 uinfo->value.enumerated.items = 3;
1011 if (uinfo->value.enumerated.item > 2)
1012 uinfo->value.enumerated.item = 2;
1013 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1014 return 0;
1015 }
1016
1017 static int snd_rme9652_get_spdif_in(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1018 {
1019 rme9652_t *rme9652 = snd_kcontrol_chip(kcontrol);
1020
1021 spin_lock_irq(&rme9652->lock);
1022 ucontrol->value.enumerated.item[0] = rme9652_spdif_in(rme9652);
1023 spin_unlock_irq(&rme9652->lock);
1024 return 0;
1025 }
1026
1027 static int snd_rme9652_put_spdif_in(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1028 {
1029 rme9652_t *rme9652 = snd_kcontrol_chip(kcontrol);
1030 int change;
1031 unsigned int val;
1032
1033 if (!snd_rme9652_use_is_exclusive(rme9652))
1034 return -EBUSY;
1035 val = ucontrol->value.enumerated.item[0] % 3;
1036 spin_lock_irq(&rme9652->lock);
1037 change = val != rme9652_spdif_in(rme9652);
1038 if (change)
1039 rme9652_set_spdif_input(rme9652, val);
1040 spin_unlock_irq(&rme9652->lock);
1041 return change;
1042 }
1043
1044 #define RME9652_SPDIF_OUT(xname, xindex) \
1045 { .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = xname, .index = xindex, \
1046 .info = snd_rme9652_info_spdif_out, \
1047 .get = snd_rme9652_get_spdif_out, .put = snd_rme9652_put_spdif_out }
1048
1049 static int rme9652_spdif_out(rme9652_t *rme9652)
1050 {
1051 return (rme9652->control_register & RME9652_opt_out) ? 1 : 0;
1052 }
1053
1054 static int rme9652_set_spdif_output(rme9652_t *rme9652, int out)
1055 {
1056 int restart = 0;
1057
1058 if (out) {
1059 rme9652->control_register |= RME9652_opt_out;
1060 } else {
1061 rme9652->control_register &= ~RME9652_opt_out;
1062 }
1063
1064 if ((restart = rme9652->running)) {
1065 rme9652_stop(rme9652);
1066 }
1067
1068 rme9652_write(rme9652, RME9652_control_register, rme9652->control_register);
1069
1070 if (restart) {
1071 rme9652_start(rme9652);
1072 }
1073
1074 return 0;
1075 }
1076
1077 static int snd_rme9652_info_spdif_out(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1078 {
1079 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1080 uinfo->count = 1;
1081 uinfo->value.integer.min = 0;
1082 uinfo->value.integer.max = 1;
1083 return 0;
1084 }
1085
1086 static int snd_rme9652_get_spdif_out(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1087 {
1088 rme9652_t *rme9652 = snd_kcontrol_chip(kcontrol);
1089
1090 spin_lock_irq(&rme9652->lock);
1091 ucontrol->value.integer.value[0] = rme9652_spdif_out(rme9652);
1092 spin_unlock_irq(&rme9652->lock);
1093 return 0;
1094 }
1095
1096 static int snd_rme9652_put_spdif_out(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1097 {
1098 rme9652_t *rme9652 = snd_kcontrol_chip(kcontrol);
1099 int change;
1100 unsigned int val;
1101
1102 if (!snd_rme9652_use_is_exclusive(rme9652))
1103 return -EBUSY;
1104 val = ucontrol->value.integer.value[0] & 1;
1105 spin_lock_irq(&rme9652->lock);
1106 change = (int)val != rme9652_spdif_out(rme9652);
1107 rme9652_set_spdif_output(rme9652, val);
1108 spin_unlock_irq(&rme9652->lock);
1109 return change;
1110 }
1111
1112 #define RME9652_SYNC_MODE(xname, xindex) \
1113 { .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = xname, .index = xindex, \
1114 .info = snd_rme9652_info_sync_mode, \
1115 .get = snd_rme9652_get_sync_mode, .put = snd_rme9652_put_sync_mode }
1116
1117 static int rme9652_sync_mode(rme9652_t *rme9652)
1118 {
1119 if (rme9652->control_register & RME9652_wsel) {
1120 return 2;
1121 } else if (rme9652->control_register & RME9652_Master) {
1122 return 1;
1123 } else {
1124 return 0;
1125 }
1126 }
1127
1128 static int rme9652_set_sync_mode(rme9652_t *rme9652, int mode)
1129 {
1130 int restart = 0;
1131
1132 switch (mode) {
1133 case 0:
1134 rme9652->control_register &=
1135 ~(RME9652_Master | RME9652_wsel);
1136 break;
1137 case 1:
1138 rme9652->control_register =
1139 (rme9652->control_register & ~RME9652_wsel) | RME9652_Master;
1140 break;
1141 case 2:
1142 rme9652->control_register |=
1143 (RME9652_Master | RME9652_wsel);
1144 break;
1145 }
1146
1147 if ((restart = rme9652->running)) {
1148 rme9652_stop(rme9652);
1149 }
1150
1151 rme9652_write(rme9652, RME9652_control_register, rme9652->control_register);
1152
1153 if (restart) {
1154 rme9652_start(rme9652);
1155 }
1156
1157 return 0;
1158 }
1159
1160 static int snd_rme9652_info_sync_mode(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1161 {
1162 static char *texts[3] = {"AutoSync", "Master", "Word Clock"};
1163
1164 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1165 uinfo->count = 1;
1166 uinfo->value.enumerated.items = 3;
1167 if (uinfo->value.enumerated.item > 2)
1168 uinfo->value.enumerated.item = 2;
1169 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1170 return 0;
1171 }
1172
1173 static int snd_rme9652_get_sync_mode(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1174 {
1175 rme9652_t *rme9652 = snd_kcontrol_chip(kcontrol);
1176
1177 spin_lock_irq(&rme9652->lock);
1178 ucontrol->value.enumerated.item[0] = rme9652_sync_mode(rme9652);
1179 spin_unlock_irq(&rme9652->lock);
1180 return 0;
1181 }
1182
1183 static int snd_rme9652_put_sync_mode(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1184 {
1185 rme9652_t *rme9652 = snd_kcontrol_chip(kcontrol);
1186 int change;
1187 unsigned int val;
1188
1189 val = ucontrol->value.enumerated.item[0] % 3;
1190 spin_lock_irq(&rme9652->lock);
1191 change = (int)val != rme9652_sync_mode(rme9652);
1192 rme9652_set_sync_mode(rme9652, val);
1193 spin_unlock_irq(&rme9652->lock);
1194 return change;
1195 }
1196
1197 #define RME9652_SYNC_PREF(xname, xindex) \
1198 { .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = xname, .index = xindex, \
1199 .info = snd_rme9652_info_sync_pref, \
1200 .get = snd_rme9652_get_sync_pref, .put = snd_rme9652_put_sync_pref }
1201
1202 static int rme9652_sync_pref(rme9652_t *rme9652)
1203 {
1204 switch (rme9652->control_register & RME9652_SyncPref_Mask) {
1205 case RME9652_SyncPref_ADAT1:
1206 return RME9652_SYNC_FROM_ADAT1;
1207 case RME9652_SyncPref_ADAT2:
1208 return RME9652_SYNC_FROM_ADAT2;
1209 case RME9652_SyncPref_ADAT3:
1210 return RME9652_SYNC_FROM_ADAT3;
1211 case RME9652_SyncPref_SPDIF:
1212 return RME9652_SYNC_FROM_SPDIF;
1213 }
1214 /* Not reachable */
1215 return 0;
1216 }
1217
1218 static int rme9652_set_sync_pref(rme9652_t *rme9652, int pref)
1219 {
1220 int restart;
1221
1222 rme9652->control_register &= ~RME9652_SyncPref_Mask;
1223 switch (pref) {
1224 case RME9652_SYNC_FROM_ADAT1:
1225 rme9652->control_register |= RME9652_SyncPref_ADAT1;
1226 break;
1227 case RME9652_SYNC_FROM_ADAT2:
1228 rme9652->control_register |= RME9652_SyncPref_ADAT2;
1229 break;
1230 case RME9652_SYNC_FROM_ADAT3:
1231 rme9652->control_register |= RME9652_SyncPref_ADAT3;
1232 break;
1233 case RME9652_SYNC_FROM_SPDIF:
1234 rme9652->control_register |= RME9652_SyncPref_SPDIF;
1235 break;
1236 }
1237
1238 if ((restart = rme9652->running)) {
1239 rme9652_stop(rme9652);
1240 }
1241
1242 rme9652_write(rme9652, RME9652_control_register, rme9652->control_register);
1243
1244 if (restart) {
1245 rme9652_start(rme9652);
1246 }
1247
1248 return 0;
1249 }
1250
1251 static int snd_rme9652_info_sync_pref(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1252 {
1253 static char *texts[4] = {"IEC958 In", "ADAT1 In", "ADAT2 In", "ADAT3 In"};
1254 rme9652_t *rme9652 = snd_kcontrol_chip(kcontrol);
1255
1256 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1257 uinfo->count = 1;
1258 uinfo->value.enumerated.items = rme9652->ss_channels == RME9652_NCHANNELS ? 4 : 3;
1259 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1260 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1261 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1262 return 0;
1263 }
1264
1265 static int snd_rme9652_get_sync_pref(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1266 {
1267 rme9652_t *rme9652 = snd_kcontrol_chip(kcontrol);
1268
1269 spin_lock_irq(&rme9652->lock);
1270 ucontrol->value.enumerated.item[0] = rme9652_sync_pref(rme9652);
1271 spin_unlock_irq(&rme9652->lock);
1272 return 0;
1273 }
1274
1275 static int snd_rme9652_put_sync_pref(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1276 {
1277 rme9652_t *rme9652 = snd_kcontrol_chip(kcontrol);
1278 int change, max;
1279 unsigned int val;
1280
1281 if (!snd_rme9652_use_is_exclusive(rme9652))
1282 return -EBUSY;
1283 max = rme9652->ss_channels == RME9652_NCHANNELS ? 4 : 3;
1284 val = ucontrol->value.enumerated.item[0] % max;
1285 spin_lock_irq(&rme9652->lock);
1286 change = (int)val != rme9652_sync_pref(rme9652);
1287 rme9652_set_sync_pref(rme9652, val);
1288 spin_unlock_irq(&rme9652->lock);
1289 return change;
1290 }
1291
1292 static int snd_rme9652_info_thru(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1293 {
1294 rme9652_t *rme9652 = snd_kcontrol_chip(kcontrol);
1295 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1296 uinfo->count = rme9652->ss_channels;
1297 uinfo->value.integer.min = 0;
1298 uinfo->value.integer.max = 1;
1299 return 0;
1300 }
1301
1302 static int snd_rme9652_get_thru(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1303 {
1304 rme9652_t *rme9652 = snd_kcontrol_chip(kcontrol);
1305 unsigned int k;
1306 u32 thru_bits = rme9652->thru_bits;
1307
1308 for (k = 0; k < rme9652->ss_channels; ++k) {
1309 ucontrol->value.integer.value[k] = !!(thru_bits & (1 << k));
1310 }
1311 return 0;
1312 }
1313
1314 static int snd_rme9652_put_thru(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1315 {
1316 rme9652_t *rme9652 = snd_kcontrol_chip(kcontrol);
1317 int change;
1318 unsigned int chn;
1319 u32 thru_bits = 0;
1320
1321 if (!snd_rme9652_use_is_exclusive(rme9652))
1322 return -EBUSY;
1323
1324 for (chn = 0; chn < rme9652->ss_channels; ++chn) {
1325 if (ucontrol->value.integer.value[chn])
1326 thru_bits |= 1 << chn;
1327 }
1328
1329 spin_lock_irq(&rme9652->lock);
1330 change = thru_bits ^ rme9652->thru_bits;
1331 if (change) {
1332 for (chn = 0; chn < rme9652->ss_channels; ++chn) {
1333 if (!(change & (1 << chn)))
1334 continue;
1335 rme9652_set_thru(rme9652,chn,thru_bits&(1<<chn));
1336 }
1337 }
1338 spin_unlock_irq(&rme9652->lock);
1339 return !!change;
1340 }
1341
1342 #define RME9652_PASSTHRU(xname, xindex) \
1343 { .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = xname, .index = xindex, \
1344 .info = snd_rme9652_info_passthru, \
1345 .put = snd_rme9652_put_passthru, \
1346 .get = snd_rme9652_get_passthru }
1347
1348 static int snd_rme9652_info_passthru(snd_kcontrol_t * kcontrol, snd_ctl_elem_info_t * uinfo)
1349 {
1350 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1351 uinfo->count = 1;
1352 uinfo->value.integer.min = 0;
1353 uinfo->value.integer.max = 1;
1354 return 0;
1355 }
1356
1357 static int snd_rme9652_get_passthru(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1358 {
1359 rme9652_t *rme9652 = snd_kcontrol_chip(kcontrol);
1360
1361 spin_lock_irq(&rme9652->lock);
1362 ucontrol->value.integer.value[0] = rme9652->passthru;
1363 spin_unlock_irq(&rme9652->lock);
1364 return 0;
1365 }
1366
1367 static int snd_rme9652_put_passthru(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1368 {
1369 rme9652_t *rme9652 = snd_kcontrol_chip(kcontrol);
1370 int change;
1371 unsigned int val;
1372 int err = 0;
1373
1374 if (!snd_rme9652_use_is_exclusive(rme9652))
1375 return -EBUSY;
1376
1377 val = ucontrol->value.integer.value[0] & 1;
1378 spin_lock_irq(&rme9652->lock);
1379 change = (ucontrol->value.integer.value[0] != rme9652->passthru);
1380 if (change)
1381 err = rme9652_set_passthru(rme9652, val);
1382 spin_unlock_irq(&rme9652->lock);
1383 return err ? err : change;
1384 }
1385
1386 /* Read-only switches */
1387
1388 #define RME9652_SPDIF_RATE(xname, xindex) \
1389 { .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = xname, .index = xindex, \
1390 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
1391 .info = snd_rme9652_info_spdif_rate, \
1392 .get = snd_rme9652_get_spdif_rate }
1393
1394 static int snd_rme9652_info_spdif_rate(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1395 {
1396 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1397 uinfo->count = 1;
1398 uinfo->value.integer.min = 0;
1399 uinfo->value.integer.max = 96000;
1400 return 0;
1401 }
1402
1403 static int snd_rme9652_get_spdif_rate(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1404 {
1405 rme9652_t *rme9652 = snd_kcontrol_chip(kcontrol);
1406
1407 spin_lock_irq(&rme9652->lock);
1408 ucontrol->value.integer.value[0] = rme9652_spdif_sample_rate(rme9652);
1409 spin_unlock_irq(&rme9652->lock);
1410 return 0;
1411 }
1412
1413 #define RME9652_ADAT_SYNC(xname, xindex, xidx) \
1414 { .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = xname, .index = xindex, \
1415 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
1416 .info = snd_rme9652_info_adat_sync, \
1417 .get = snd_rme9652_get_adat_sync, .private_value = xidx }
1418
1419 static int snd_rme9652_info_adat_sync(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1420 {
1421 static char *texts[4] = {"No Lock", "Lock", "No Lock Sync", "Lock Sync"};
1422
1423 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1424 uinfo->count = 1;
1425 uinfo->value.enumerated.items = 4;
1426 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1427 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1428 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1429 return 0;
1430 }
1431
1432 static int snd_rme9652_get_adat_sync(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1433 {
1434 rme9652_t *rme9652 = snd_kcontrol_chip(kcontrol);
1435 unsigned int mask1, mask2, val;
1436
1437 switch (kcontrol->private_value) {
1438 case 0: mask1 = RME9652_lock_0; mask2 = RME9652_sync_0; break;
1439 case 1: mask1 = RME9652_lock_1; mask2 = RME9652_sync_1; break;
1440 case 2: mask1 = RME9652_lock_2; mask2 = RME9652_sync_2; break;
1441 default: return -EINVAL;
1442 }
1443 val = rme9652_read(rme9652, RME9652_status_register);
1444 ucontrol->value.enumerated.item[0] = (val & mask1) ? 1 : 0;
1445 ucontrol->value.enumerated.item[0] |= (val & mask2) ? 2 : 0;
1446 return 0;
1447 }
1448
1449 #define RME9652_TC_VALID(xname, xindex) \
1450 { .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = xname, .index = xindex, \
1451 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
1452 .info = snd_rme9652_info_tc_valid, \
1453 .get = snd_rme9652_get_tc_valid }
1454
1455 static int snd_rme9652_info_tc_valid(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1456 {
1457 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1458 uinfo->count = 1;
1459 uinfo->value.integer.min = 0;
1460 uinfo->value.integer.max = 1;
1461 return 0;
1462 }
1463
1464 static int snd_rme9652_get_tc_valid(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1465 {
1466 rme9652_t *rme9652 = snd_kcontrol_chip(kcontrol);
1467
1468 ucontrol->value.integer.value[0] =
1469 (rme9652_read(rme9652, RME9652_status_register) & RME9652_tc_valid) ? 1 : 0;
1470 return 0;
1471 }
1472
1473 #if ALSA_HAS_STANDARD_WAY_OF_RETURNING_TIMECODE
1474
1475 /* FIXME: this routine needs a port to the new control API --jk */
1476
1477 static int snd_rme9652_get_tc_value(void *private_data,
1478 snd_kswitch_t *kswitch,
1479 snd_switch_t *uswitch)
1480 {
1481 rme9652_t *s = (rme9652_t *) private_data;
1482 u32 value;
1483 int i;
1484
1485 uswitch->type = SNDRV_SW_TYPE_DWORD;
1486
1487 if ((rme9652_read(s, RME9652_status_register) &
1488 RME9652_tc_valid) == 0) {
1489 uswitch->value.data32[0] = 0;
1490 return 0;
1491 }
1492
1493 /* timecode request */
1494
1495 rme9652_write(s, RME9652_time_code, 0);
1496
1497 /* XXX bug alert: loop-based timing !!!! */
1498
1499 for (i = 0; i < 50; i++) {
1500 if (!(rme9652_read(s, i * 4) & RME9652_tc_busy))
1501 break;
1502 }
1503
1504 if (!(rme9652_read(s, i * 4) & RME9652_tc_busy)) {
1505 return -EIO;
1506 }
1507
1508 value = 0;
1509
1510 for (i = 0; i < 32; i++) {
1511 value >>= 1;
1512
1513 if (rme9652_read(s, i * 4) & RME9652_tc_out)
1514 value |= 0x80000000;
1515 }
1516
1517 if (value > 2 * 60 * 48000) {
1518 value -= 2 * 60 * 48000;
1519 } else {
1520 value = 0;
1521 }
1522
1523 uswitch->value.data32[0] = value;
1524
1525 return 0;
1526 }
1527
1528 #endif /* ALSA_HAS_STANDARD_WAY_OF_RETURNING_TIMECODE */
1529
1530 static snd_kcontrol_new_t snd_rme9652_controls[] = {
1531 {
1532 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1533 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
1534 .info = snd_rme9652_control_spdif_info,
1535 .get = snd_rme9652_control_spdif_get,
1536 .put = snd_rme9652_control_spdif_put,
1537 },
1538 {
1539 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
1540 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1541 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1542 .info = snd_rme9652_control_spdif_stream_info,
1543 .get = snd_rme9652_control_spdif_stream_get,
1544 .put = snd_rme9652_control_spdif_stream_put,
1545 },
1546 {
1547 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1548 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1549 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
1550 .info = snd_rme9652_control_spdif_mask_info,
1551 .get = snd_rme9652_control_spdif_mask_get,
1552 .private_value = IEC958_AES0_NONAUDIO |
1553 IEC958_AES0_PROFESSIONAL |
1554 IEC958_AES0_CON_EMPHASIS,
1555 },
1556 {
1557 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1558 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1559 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
1560 .info = snd_rme9652_control_spdif_mask_info,
1561 .get = snd_rme9652_control_spdif_mask_get,
1562 .private_value = IEC958_AES0_NONAUDIO |
1563 IEC958_AES0_PROFESSIONAL |
1564 IEC958_AES0_PRO_EMPHASIS,
1565 },
1566 RME9652_SPDIF_IN("IEC958 Input Connector", 0),
1567 RME9652_SPDIF_OUT("IEC958 Output also on ADAT1", 0),
1568 RME9652_SYNC_MODE("Sync Mode", 0),
1569 RME9652_SYNC_PREF("Preferred Sync Source", 0),
1570 {
1571 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1572 .name = "Channels Thru",
1573 .index = 0,
1574 .info = snd_rme9652_info_thru,
1575 .get = snd_rme9652_get_thru,
1576 .put = snd_rme9652_put_thru,
1577 },
1578 RME9652_SPDIF_RATE("IEC958 Sample Rate", 0),
1579 RME9652_ADAT_SYNC("ADAT1 Sync Check", 0, 0),
1580 RME9652_ADAT_SYNC("ADAT2 Sync Check", 0, 1),
1581 RME9652_TC_VALID("Timecode Valid", 0),
1582 RME9652_PASSTHRU("Passthru", 0)
1583 };
1584
1585 static snd_kcontrol_new_t snd_rme9652_adat3_check =
1586 RME9652_ADAT_SYNC("ADAT3 Sync Check", 0, 2);
1587
1588 static snd_kcontrol_new_t snd_rme9652_adat1_input =
1589 RME9652_ADAT1_IN("ADAT1 Input Source", 0);
1590
1591 static int snd_rme9652_create_controls(snd_card_t *card, rme9652_t *rme9652)
1592 {
1593 unsigned int idx;
1594 int err;
1595 snd_kcontrol_t *kctl;
1596
1597 for (idx = 0; idx < ARRAY_SIZE(snd_rme9652_controls); idx++) {
1598 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_rme9652_controls[idx], rme9652))) < 0)
1599 return err;
1600 if (idx == 1) /* IEC958 (S/PDIF) Stream */
1601 rme9652->spdif_ctl = kctl;
1602 }
1603
1604 if (rme9652->ss_channels == RME9652_NCHANNELS)
1605 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_rme9652_adat3_check, rme9652))) < 0)
1606 return err;
1607
1608 if (rme9652->hw_rev >= 15)
1609 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_rme9652_adat1_input, rme9652))) < 0)
1610 return err;
1611
1612 return 0;
1613 }
1614
1615 /*------------------------------------------------------------
1616 /proc interface
1617 ------------------------------------------------------------*/
1618
1619 static void
1620 snd_rme9652_proc_read(snd_info_entry_t *entry, snd_info_buffer_t *buffer)
1621 {
1622 rme9652_t *rme9652 = (rme9652_t *) entry->private_data;
1623 u32 thru_bits = rme9652->thru_bits;
1624 int show_auto_sync_source = 0;
1625 int i;
1626 unsigned int status;
1627 int x;
1628
1629 status = rme9652_read(rme9652, RME9652_status_register);
1630
1631 snd_iprintf(buffer, "%s (Card #%d)\n", rme9652->card_name, rme9652->card->number + 1);
1632 snd_iprintf(buffer, "Buffers: capture %p playback %p\n",
1633 rme9652->capture_buffer, rme9652->playback_buffer);
1634 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
1635 rme9652->irq, rme9652->port, (unsigned long)rme9652->iobase);
1636 snd_iprintf(buffer, "Control register: %x\n", rme9652->control_register);
1637
1638 snd_iprintf(buffer, "\n");
1639
1640 x = 1 << (6 + rme9652_decode_latency(rme9652->control_register &
1641 RME9652_latency));
1642
1643 snd_iprintf(buffer, "Latency: %d samples (2 periods of %lu bytes)\n",
1644 x, (unsigned long) rme9652->period_bytes);
1645 snd_iprintf(buffer, "Hardware pointer (frames): %ld\n",
1646 rme9652_hw_pointer(rme9652));
1647 snd_iprintf(buffer, "Passthru: %s\n",
1648 rme9652->passthru ? "yes" : "no");
1649
1650 if ((rme9652->control_register & (RME9652_Master | RME9652_wsel)) == 0) {
1651 snd_iprintf(buffer, "Clock mode: autosync\n");
1652 show_auto_sync_source = 1;
1653 } else if (rme9652->control_register & RME9652_wsel) {
1654 if (status & RME9652_wsel_rd) {
1655 snd_iprintf(buffer, "Clock mode: word clock\n");
1656 } else {
1657 snd_iprintf(buffer, "Clock mode: word clock (no signal)\n");
1658 }
1659 } else {
1660 snd_iprintf(buffer, "Clock mode: master\n");
1661 }
1662
1663 if (show_auto_sync_source) {
1664 switch (rme9652->control_register & RME9652_SyncPref_Mask) {
1665 case RME9652_SyncPref_ADAT1:
1666 snd_iprintf(buffer, "Pref. sync source: ADAT1\n");
1667 break;
1668 case RME9652_SyncPref_ADAT2:
1669 snd_iprintf(buffer, "Pref. sync source: ADAT2\n");
1670 break;
1671 case RME9652_SyncPref_ADAT3:
1672 snd_iprintf(buffer, "Pref. sync source: ADAT3\n");
1673 break;
1674 case RME9652_SyncPref_SPDIF:
1675 snd_iprintf(buffer, "Pref. sync source: IEC958\n");
1676 break;
1677 default:
1678 snd_iprintf(buffer, "Pref. sync source: ???\n");
1679 }
1680 }
1681
1682 if (rme9652->hw_rev >= 15)
1683 snd_iprintf(buffer, "\nADAT1 Input source: %s\n",
1684 (rme9652->control_register & RME9652_ADAT1_INTERNAL) ?
1685 "Internal" : "ADAT1 optical");
1686
1687 snd_iprintf(buffer, "\n");
1688
1689 switch (rme9652_decode_spdif_in(rme9652->control_register &
1690 RME9652_inp)) {
1691 case RME9652_SPDIFIN_OPTICAL:
1692 snd_iprintf(buffer, "IEC958 input: ADAT1\n");
1693 break;
1694 case RME9652_SPDIFIN_COAXIAL:
1695 snd_iprintf(buffer, "IEC958 input: Coaxial\n");
1696 break;
1697 case RME9652_SPDIFIN_INTERN:
1698 snd_iprintf(buffer, "IEC958 input: Internal\n");
1699 break;
1700 default:
1701 snd_iprintf(buffer, "IEC958 input: ???\n");
1702 break;
1703 }
1704
1705 if (rme9652->control_register & RME9652_opt_out) {
1706 snd_iprintf(buffer, "IEC958 output: Coaxial & ADAT1\n");
1707 } else {
1708 snd_iprintf(buffer, "IEC958 output: Coaxial only\n");
1709 }
1710
1711 if (rme9652->control_register & RME9652_PRO) {
1712 snd_iprintf(buffer, "IEC958 quality: Professional\n");
1713 } else {
1714 snd_iprintf(buffer, "IEC958 quality: Consumer\n");
1715 }
1716
1717 if (rme9652->control_register & RME9652_EMP) {
1718 snd_iprintf(buffer, "IEC958 emphasis: on\n");
1719 } else {
1720 snd_iprintf(buffer, "IEC958 emphasis: off\n");
1721 }
1722
1723 if (rme9652->control_register & RME9652_Dolby) {
1724 snd_iprintf(buffer, "IEC958 Dolby: on\n");
1725 } else {
1726 snd_iprintf(buffer, "IEC958 Dolby: off\n");
1727 }
1728
1729 i = rme9652_spdif_sample_rate(rme9652);
1730
1731 if (i < 0) {
1732 snd_iprintf(buffer,
1733 "IEC958 sample rate: error flag set\n");
1734 } else if (i == 0) {
1735 snd_iprintf(buffer, "IEC958 sample rate: undetermined\n");
1736 } else {
1737 snd_iprintf(buffer, "IEC958 sample rate: %d\n", i);
1738 }
1739
1740 snd_iprintf(buffer, "\n");
1741
1742 snd_iprintf(buffer, "ADAT Sample rate: %dHz\n",
1743 rme9652_adat_sample_rate(rme9652));
1744
1745 /* Sync Check */
1746
1747 x = status & RME9652_sync_0;
1748 if (status & RME9652_lock_0) {
1749 snd_iprintf(buffer, "ADAT1: %s\n", x ? "Sync" : "Lock");
1750 } else {
1751 snd_iprintf(buffer, "ADAT1: No Lock\n");
1752 }
1753
1754 x = status & RME9652_sync_1;
1755 if (status & RME9652_lock_1) {
1756 snd_iprintf(buffer, "ADAT2: %s\n", x ? "Sync" : "Lock");
1757 } else {
1758 snd_iprintf(buffer, "ADAT2: No Lock\n");
1759 }
1760
1761 x = status & RME9652_sync_2;
1762 if (status & RME9652_lock_2) {
1763 snd_iprintf(buffer, "ADAT3: %s\n", x ? "Sync" : "Lock");
1764 } else {
1765 snd_iprintf(buffer, "ADAT3: No Lock\n");
1766 }
1767
1768 snd_iprintf(buffer, "\n");
1769
1770 snd_iprintf(buffer, "Timecode signal: %s\n",
1771 (status & RME9652_tc_valid) ? "yes" : "no");
1772
1773 /* thru modes */
1774
1775 snd_iprintf(buffer, "Punch Status:\n\n");
1776
1777 for (i = 0; i < rme9652->ss_channels; i++) {
1778 if (thru_bits & (1 << i)) {
1779 snd_iprintf(buffer, "%2d: on ", i + 1);
1780 } else {
1781 snd_iprintf(buffer, "%2d: off ", i + 1);
1782 }
1783
1784 if (((i + 1) % 8) == 0) {
1785 snd_iprintf(buffer, "\n");
1786 }
1787 }
1788
1789 snd_iprintf(buffer, "\n");
1790 }
1791
1792 static void __devinit snd_rme9652_proc_init(rme9652_t *rme9652)
1793 {
1794 snd_info_entry_t *entry;
1795
1796 if (! snd_card_proc_new(rme9652->card, "rme9652", &entry))
1797 snd_info_set_text_ops(entry, rme9652, 1024, snd_rme9652_proc_read);
1798 }
1799
1800 static void snd_rme9652_free_buffers(rme9652_t *rme9652)
1801 {
1802 snd_hammerfall_free_buffer(&rme9652->capture_dma_buf, rme9652->pci);
1803 snd_hammerfall_free_buffer(&rme9652->playback_dma_buf, rme9652->pci);
1804 }
1805
1806 static int snd_rme9652_free(rme9652_t *rme9652)
1807 {
1808 if (rme9652->irq >= 0)
1809 rme9652_stop(rme9652);
1810 snd_rme9652_free_buffers(rme9652);
1811
1812 if (rme9652->irq >= 0)
1813 free_irq(rme9652->irq, (void *)rme9652);
1814 if (rme9652->iobase)
1815 iounmap(rme9652->iobase);
1816 if (rme9652->port)
1817 pci_release_regions(rme9652->pci);
1818
1819 pci_disable_device(rme9652->pci);
1820 return 0;
1821 }
1822
1823 static int __devinit snd_rme9652_initialize_memory(rme9652_t *rme9652)
1824 {
1825 unsigned long pb_bus, cb_bus;
1826
1827 if (snd_hammerfall_get_buffer(rme9652->pci, &rme9652->capture_dma_buf, RME9652_DMA_AREA_BYTES) < 0 ||
1828 snd_hammerfall_get_buffer(rme9652->pci, &rme9652->playback_dma_buf, RME9652_DMA_AREA_BYTES) < 0) {
1829 if (rme9652->capture_dma_buf.area)
1830 snd_dma_free_pages(&rme9652->capture_dma_buf);
1831 printk(KERN_ERR "%s: no buffers available\n", rme9652->card_name);
1832 return -ENOMEM;
1833 }
1834
1835 /* Align to bus-space 64K boundary */
1836
1837 cb_bus = (rme9652->capture_dma_buf.addr + 0xFFFF) & ~0xFFFFl;
1838 pb_bus = (rme9652->playback_dma_buf.addr + 0xFFFF) & ~0xFFFFl;
1839
1840 /* Tell the card where it is */
1841
1842 rme9652_write(rme9652, RME9652_rec_buffer, cb_bus);
1843 rme9652_write(rme9652, RME9652_play_buffer, pb_bus);
1844
1845 rme9652->capture_buffer = rme9652->capture_dma_buf.area + (cb_bus - rme9652->capture_dma_buf.addr);
1846 rme9652->playback_buffer = rme9652->playback_dma_buf.area + (pb_bus - rme9652->playback_dma_buf.addr);
1847
1848 return 0;
1849 }
1850
1851 static void snd_rme9652_set_defaults(rme9652_t *rme9652)
1852 {
1853 unsigned int k;
1854
1855 /* ASSUMPTION: rme9652->lock is either held, or
1856 there is no need to hold it (e.g. during module
1857 initalization).
1858 */
1859
1860 /* set defaults:
1861
1862 SPDIF Input via Coax
1863 autosync clock mode
1864 maximum latency (7 = 8192 samples, 64Kbyte buffer,
1865 which implies 2 4096 sample, 32Kbyte periods).
1866
1867 if rev 1.5, initialize the S/PDIF receiver.
1868
1869 */
1870
1871 rme9652->control_register =
1872 RME9652_inp_0 | rme9652_encode_latency(7);
1873
1874 rme9652_write(rme9652, RME9652_control_register, rme9652->control_register);
1875
1876 rme9652_reset_hw_pointer(rme9652);
1877 rme9652_compute_period_size(rme9652);
1878
1879 /* default: thru off for all channels */
1880
1881 for (k = 0; k < RME9652_NCHANNELS; ++k)
1882 rme9652_write(rme9652, RME9652_thru_base + k * 4, 0);
1883
1884 rme9652->thru_bits = 0;
1885 rme9652->passthru = 0;
1886
1887 /* set a default rate so that the channel map is set up */
1888
1889 rme9652_set_rate(rme9652, 48000);
1890 }
1891
1892 static irqreturn_t snd_rme9652_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1893 {
1894 rme9652_t *rme9652 = (rme9652_t *) dev_id;
1895
1896 if (!(rme9652_read(rme9652, RME9652_status_register) & RME9652_IRQ)) {
1897 return IRQ_NONE;
1898 }
1899
1900 rme9652_write(rme9652, RME9652_irq_clear, 0);
1901
1902 if (rme9652->capture_substream) {
1903 snd_pcm_period_elapsed(rme9652->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream);
1904 }
1905
1906 if (rme9652->playback_substream) {
1907 snd_pcm_period_elapsed(rme9652->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream);
1908 }
1909 return IRQ_HANDLED;
1910 }
1911
1912 static snd_pcm_uframes_t snd_rme9652_hw_pointer(snd_pcm_substream_t *substream)
1913 {
1914 rme9652_t *rme9652 = snd_pcm_substream_chip(substream);
1915 return rme9652_hw_pointer(rme9652);
1916 }
1917
1918 static char *rme9652_channel_buffer_location(rme9652_t *rme9652,
1919 int stream,
1920 int channel)
1921
1922 {
1923 int mapped_channel;
1924
1925 snd_assert(channel >= 0 || channel < RME9652_NCHANNELS, return NULL);
1926
1927 if ((mapped_channel = rme9652->channel_map[channel]) < 0) {
1928 return NULL;
1929 }
1930
1931 if (stream == SNDRV_PCM_STREAM_CAPTURE) {
1932 return rme9652->capture_buffer +
1933 (mapped_channel * RME9652_CHANNEL_BUFFER_BYTES);
1934 } else {
1935 return rme9652->playback_buffer +
1936 (mapped_channel * RME9652_CHANNEL_BUFFER_BYTES);
1937 }
1938 }
1939
1940 static int snd_rme9652_playback_copy(snd_pcm_substream_t *substream, int channel,
1941 snd_pcm_uframes_t pos, void __user *src, snd_pcm_uframes_t count)
1942 {
1943 rme9652_t *rme9652 = snd_pcm_substream_chip(substream);
1944 char *channel_buf;
1945
1946 snd_assert(pos + count <= RME9652_CHANNEL_BUFFER_BYTES / 4, return -EINVAL);
1947
1948 channel_buf = rme9652_channel_buffer_location (rme9652,
1949 substream->pstr->stream,
1950 channel);
1951 snd_assert(channel_buf != NULL, return -EIO);
1952 if (copy_from_user(channel_buf + pos * 4, src, count * 4))
1953 return -EFAULT;
1954 return count;
1955 }
1956
1957 static int snd_rme9652_capture_copy(snd_pcm_substream_t *substream, int channel,
1958 snd_pcm_uframes_t pos, void __user *dst, snd_pcm_uframes_t count)
1959 {
1960 rme9652_t *rme9652 = snd_pcm_substream_chip(substream);
1961 char *channel_buf;
1962
1963 snd_assert(pos + count <= RME9652_CHANNEL_BUFFER_BYTES / 4, return -EINVAL);
1964
1965 channel_buf = rme9652_channel_buffer_location (rme9652,
1966 substream->pstr->stream,
1967 channel);
1968 snd_assert(channel_buf != NULL, return -EIO);
1969 if (copy_to_user(dst, channel_buf + pos * 4, count * 4))
1970 return -EFAULT;
1971 return count;
1972 }
1973
1974 static int snd_rme9652_hw_silence(snd_pcm_substream_t *substream, int channel,
1975 snd_pcm_uframes_t pos, snd_pcm_uframes_t count)
1976 {
1977 rme9652_t *rme9652 = snd_pcm_substream_chip(substream);
1978 char *channel_buf;
1979
1980 channel_buf = rme9652_channel_buffer_location (rme9652,
1981 substream->pstr->stream,
1982 channel);
1983 snd_assert(channel_buf != NULL, return -EIO);
1984 memset(channel_buf + pos * 4, 0, count * 4);
1985 return count;
1986 }
1987
1988 static int snd_rme9652_reset(snd_pcm_substream_t *substream)
1989 {
1990 snd_pcm_runtime_t *runtime = substream->runtime;
1991 rme9652_t *rme9652 = snd_pcm_substream_chip(substream);
1992 snd_pcm_substream_t *other;
1993 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1994 other = rme9652->capture_substream;
1995 else
1996 other = rme9652->playback_substream;
1997 if (rme9652->running)
1998 runtime->status->hw_ptr = rme9652_hw_pointer(rme9652);
1999 else
2000 runtime->status->hw_ptr = 0;
2001 if (other) {
2002 struct list_head *pos;
2003 snd_pcm_substream_t *s;
2004 snd_pcm_runtime_t *oruntime = other->runtime;
2005 snd_pcm_group_for_each(pos, substream) {
2006 s = snd_pcm_group_substream_entry(pos);
2007 if (s == other) {
2008 oruntime->status->hw_ptr = runtime->status->hw_ptr;
2009 break;
2010 }
2011 }
2012 }
2013 return 0;
2014 }
2015
2016 static int snd_rme9652_hw_params(snd_pcm_substream_t *substream,
2017 snd_pcm_hw_params_t *params)
2018 {
2019 rme9652_t *rme9652 = snd_pcm_substream_chip(substream);
2020 int err;
2021 pid_t this_pid;
2022 pid_t other_pid;
2023
2024 spin_lock_irq(&rme9652->lock);
2025
2026 if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2027 rme9652->control_register &= ~(RME9652_PRO | RME9652_Dolby | RME9652_EMP);
2028 rme9652_write(rme9652, RME9652_control_register, rme9652->control_register |= rme9652->creg_spdif_stream);
2029 this_pid = rme9652->playback_pid;
2030 other_pid = rme9652->capture_pid;
2031 } else {
2032 this_pid = rme9652->capture_pid;
2033 other_pid = rme9652->playback_pid;
2034 }
2035
2036 if ((other_pid > 0) && (this_pid != other_pid)) {
2037
2038 /* The other stream is open, and not by the same
2039 task as this one. Make sure that the parameters
2040 that matter are the same.
2041 */
2042
2043 if ((int)params_rate(params) !=
2044 rme9652_adat_sample_rate(rme9652)) {
2045 spin_unlock_irq(&rme9652->lock);
2046 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
2047 return -EBUSY;
2048 }
2049
2050 if (params_period_size(params) != rme9652->period_bytes / 4) {
2051 spin_unlock_irq(&rme9652->lock);
2052 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
2053 return -EBUSY;
2054 }
2055
2056 /* We're fine. */
2057
2058 spin_unlock_irq(&rme9652->lock);
2059 return 0;
2060
2061 } else {
2062 spin_unlock_irq(&rme9652->lock);
2063 }
2064
2065 /* how to make sure that the rate matches an externally-set one ?
2066 */
2067
2068 if ((err = rme9652_set_rate(rme9652, params_rate(params))) < 0) {
2069 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
2070 return err;
2071 }
2072
2073 if ((err = rme9652_set_interrupt_interval(rme9652, params_period_size(params))) < 0) {
2074 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
2075 return err;
2076 }
2077
2078 return 0;
2079 }
2080
2081 static int snd_rme9652_channel_info(snd_pcm_substream_t *substream,
2082 snd_pcm_channel_info_t *info)
2083 {
2084 rme9652_t *rme9652 = snd_pcm_substream_chip(substream);
2085 int chn;
2086
2087 snd_assert(info->channel < RME9652_NCHANNELS, return -EINVAL);
2088
2089 if ((chn = rme9652->channel_map[info->channel]) < 0) {
2090 return -EINVAL;
2091 }
2092
2093 info->offset = chn * RME9652_CHANNEL_BUFFER_BYTES;
2094 info->first = 0;
2095 info->step = 32;
2096 return 0;
2097 }
2098
2099 static int snd_rme9652_ioctl(snd_pcm_substream_t *substream,
2100 unsigned int cmd, void *arg)
2101 {
2102 switch (cmd) {
2103 case SNDRV_PCM_IOCTL1_RESET:
2104 {
2105 return snd_rme9652_reset(substream);
2106 }
2107 case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
2108 {
2109 snd_pcm_channel_info_t *info = arg;
2110 return snd_rme9652_channel_info(substream, info);
2111 }
2112 default:
2113 break;
2114 }
2115
2116 return snd_pcm_lib_ioctl(substream, cmd, arg);
2117 }
2118
2119 static void rme9652_silence_playback(rme9652_t *rme9652)
2120 {
2121 memset(rme9652->playback_buffer, 0, RME9652_DMA_AREA_BYTES);
2122 }
2123
2124 static int snd_rme9652_trigger(snd_pcm_substream_t *substream,
2125 int cmd)
2126 {
2127 rme9652_t *rme9652 = snd_pcm_substream_chip(substream);
2128 snd_pcm_substream_t *other;
2129 int running;
2130 spin_lock(&rme9652->lock);
2131 running = rme9652->running;
2132 switch (cmd) {
2133 case SNDRV_PCM_TRIGGER_START:
2134 running |= 1 << substream->stream;
2135 break;
2136 case SNDRV_PCM_TRIGGER_STOP:
2137 running &= ~(1 << substream->stream);
2138 break;
2139 default:
2140 snd_BUG();
2141 spin_unlock(&rme9652->lock);
2142 return -EINVAL;
2143 }
2144 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
2145 other = rme9652->capture_substream;
2146 else
2147 other = rme9652->playback_substream;
2148
2149 if (other) {
2150 struct list_head *pos;
2151 snd_pcm_substream_t *s;
2152 snd_pcm_group_for_each(pos, substream) {
2153 s = snd_pcm_group_substream_entry(pos);
2154 if (s == other) {
2155 snd_pcm_trigger_done(s, substream);
2156 if (cmd == SNDRV_PCM_TRIGGER_START)
2157 running |= 1 << s->stream;
2158 else
2159 running &= ~(1 << s->stream);
2160 goto _ok;
2161 }
2162 }
2163 if (cmd == SNDRV_PCM_TRIGGER_START) {
2164 if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) &&
2165 substream->stream == SNDRV_PCM_STREAM_CAPTURE)
2166 rme9652_silence_playback(rme9652);
2167 } else {
2168 if (running &&
2169 substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
2170 rme9652_silence_playback(rme9652);
2171 }
2172 } else {
2173 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
2174 rme9652_silence_playback(rme9652);
2175 }
2176 _ok:
2177 snd_pcm_trigger_done(substream, substream);
2178 if (!rme9652->running && running)
2179 rme9652_start(rme9652);
2180 else if (rme9652->running && !running)
2181 rme9652_stop(rme9652);
2182 rme9652->running = running;
2183 spin_unlock(&rme9652->lock);
2184
2185 return 0;
2186 }
2187
2188 static int snd_rme9652_prepare(snd_pcm_substream_t *substream)
2189 {
2190 rme9652_t *rme9652 = snd_pcm_substream_chip(substream);
2191 unsigned long flags;
2192 int result = 0;
2193
2194 spin_lock_irqsave(&rme9652->lock, flags);
2195 if (!rme9652->running)
2196 rme9652_reset_hw_pointer(rme9652);
2197 spin_unlock_irqrestore(&rme9652->lock, flags);
2198 return result;
2199 }
2200
2201 static snd_pcm_hardware_t snd_rme9652_playback_subinfo =
2202 {
2203 .info = (SNDRV_PCM_INFO_MMAP |
2204 SNDRV_PCM_INFO_MMAP_VALID |
2205 SNDRV_PCM_INFO_NONINTERLEAVED |
2206 SNDRV_PCM_INFO_SYNC_START |
2207 SNDRV_PCM_INFO_DOUBLE),
2208 .formats = SNDRV_PCM_FMTBIT_S32_LE,
2209 .rates = (SNDRV_PCM_RATE_44100 |
2210 SNDRV_PCM_RATE_48000 |
2211 SNDRV_PCM_RATE_88200 |
2212 SNDRV_PCM_RATE_96000),
2213 .rate_min = 44100,
2214 .rate_max = 96000,
2215 .channels_min = 10,
2216 .channels_max = 26,
2217 .buffer_bytes_max = RME9652_CHANNEL_BUFFER_BYTES * 26,
2218 .period_bytes_min = (64 * 4) * 10,
2219 .period_bytes_max = (8192 * 4) * 26,
2220 .periods_min = 2,
2221 .periods_max = 2,
2222 .fifo_size = 0,
2223 };
2224
2225 static snd_pcm_hardware_t snd_rme9652_capture_subinfo =
2226 {
2227 .info = (SNDRV_PCM_INFO_MMAP |
2228 SNDRV_PCM_INFO_MMAP_VALID |
2229 SNDRV_PCM_INFO_NONINTERLEAVED |
2230 SNDRV_PCM_INFO_SYNC_START),
2231 .formats = SNDRV_PCM_FMTBIT_S32_LE,
2232 .rates = (SNDRV_PCM_RATE_44100 |
2233 SNDRV_PCM_RATE_48000 |
2234 SNDRV_PCM_RATE_88200 |
2235 SNDRV_PCM_RATE_96000),
2236 .rate_min = 44100,
2237 .rate_max = 96000,
2238 .channels_min = 10,
2239 .channels_max = 26,
2240 .buffer_bytes_max = RME9652_CHANNEL_BUFFER_BYTES *26,
2241 .period_bytes_min = (64 * 4) * 10,
2242 .period_bytes_max = (8192 * 4) * 26,
2243 .periods_min = 2,
2244 .periods_max = 2,
2245 .fifo_size = 0,
2246 };
2247
2248 static unsigned int period_sizes[] = { 64, 128, 256, 512, 1024, 2048, 4096, 8192 };
2249
2250 static snd_pcm_hw_constraint_list_t hw_constraints_period_sizes = {
2251 .count = ARRAY_SIZE(period_sizes),
2252 .list = period_sizes,
2253 .mask = 0
2254 };
2255
2256 static int snd_rme9652_hw_rule_channels(snd_pcm_hw_params_t *params,
2257 snd_pcm_hw_rule_t *rule)
2258 {
2259 rme9652_t *rme9652 = rule->private;
2260 snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
2261 unsigned int list[2] = { rme9652->ds_channels, rme9652->ss_channels };
2262 return snd_interval_list(c, 2, list, 0);
2263 }
2264
2265 static int snd_rme9652_hw_rule_channels_rate(snd_pcm_hw_params_t *params,
2266 snd_pcm_hw_rule_t *rule)
2267 {
2268 rme9652_t *rme9652 = rule->private;
2269 snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
2270 snd_interval_t *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
2271 if (r->min > 48000) {
2272 snd_interval_t t = {
2273 .min = rme9652->ds_channels,
2274 .max = rme9652->ds_channels,
2275 .integer = 1,
2276 };
2277 return snd_interval_refine(c, &t);
2278 } else if (r->max < 88200) {
2279 snd_interval_t t = {
2280 .min = rme9652->ss_channels,
2281 .max = rme9652->ss_channels,
2282 .integer = 1,
2283 };
2284 return snd_interval_refine(c, &t);
2285 }
2286 return 0;
2287 }
2288
2289 static int snd_rme9652_hw_rule_rate_channels(snd_pcm_hw_params_t *params,
2290 snd_pcm_hw_rule_t *rule)
2291 {
2292 rme9652_t *rme9652 = rule->private;
2293 snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
2294 snd_interval_t *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
2295 if (c->min >= rme9652->ss_channels) {
2296 snd_interval_t t = {
2297 .min = 44100,
2298 .max = 48000,
2299 .integer = 1,
2300 };
2301 return snd_interval_refine(r, &t);
2302 } else if (c->max <= rme9652->ds_channels) {
2303 snd_interval_t t = {
2304 .min = 88200,
2305 .max = 96000,
2306 .integer = 1,
2307 };
2308 return snd_interval_refine(r, &t);
2309 }
2310 return 0;
2311 }
2312
2313 static int snd_rme9652_playback_open(snd_pcm_substream_t *substream)
2314 {
2315 rme9652_t *rme9652 = snd_pcm_substream_chip(substream);
2316 snd_pcm_runtime_t *runtime = substream->runtime;
2317
2318 spin_lock_irq(&rme9652->lock);
2319
2320 snd_pcm_set_sync(substream);
2321
2322 runtime->hw = snd_rme9652_playback_subinfo;
2323 runtime->dma_area = rme9652->playback_buffer;
2324 runtime->dma_bytes = RME9652_DMA_AREA_BYTES;
2325
2326 if (rme9652->capture_substream == NULL) {
2327 rme9652_stop(rme9652);
2328 rme9652_set_thru(rme9652, -1, 0);
2329 }
2330
2331 rme9652->playback_pid = current->pid;
2332 rme9652->playback_substream = substream;
2333
2334 spin_unlock_irq(&rme9652->lock);
2335
2336 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
2337 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hw_constraints_period_sizes);
2338 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
2339 snd_rme9652_hw_rule_channels, rme9652,
2340 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
2341 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
2342 snd_rme9652_hw_rule_channels_rate, rme9652,
2343 SNDRV_PCM_HW_PARAM_RATE, -1);
2344 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
2345 snd_rme9652_hw_rule_rate_channels, rme9652,
2346 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
2347
2348 rme9652->creg_spdif_stream = rme9652->creg_spdif;
2349 rme9652->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
2350 snd_ctl_notify(rme9652->card, SNDRV_CTL_EVENT_MASK_VALUE |
2351 SNDRV_CTL_EVENT_MASK_INFO, &rme9652->spdif_ctl->id);
2352 return 0;
2353 }
2354
2355 static int snd_rme9652_playback_release(snd_pcm_substream_t *substream)
2356 {
2357 rme9652_t *rme9652 = snd_pcm_substream_chip(substream);
2358
2359 spin_lock_irq(&rme9652->lock);
2360
2361 rme9652->playback_pid = -1;
2362 rme9652->playback_substream = NULL;
2363
2364 spin_unlock_irq(&rme9652->lock);
2365
2366 rme9652->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
2367 snd_ctl_notify(rme9652->card, SNDRV_CTL_EVENT_MASK_VALUE |
2368 SNDRV_CTL_EVENT_MASK_INFO, &rme9652->spdif_ctl->id);
2369 return 0;
2370 }
2371
2372
2373 static int snd_rme9652_capture_open(snd_pcm_substream_t *substream)
2374 {
2375 rme9652_t *rme9652 = snd_pcm_substream_chip(substream);
2376 snd_pcm_runtime_t *runtime = substream->runtime;
2377
2378 spin_lock_irq(&rme9652->lock);
2379
2380 snd_pcm_set_sync(substream);
2381
2382 runtime->hw = snd_rme9652_capture_subinfo;
2383 runtime->dma_area = rme9652->capture_buffer;
2384 runtime->dma_bytes = RME9652_DMA_AREA_BYTES;
2385
2386 if (rme9652->playback_substream == NULL) {
2387 rme9652_stop(rme9652);
2388 rme9652_set_thru(rme9652, -1, 0);
2389 }
2390
2391 rme9652->capture_pid = current->pid;
2392 rme9652->capture_substream = substream;
2393
2394 spin_unlock_irq(&rme9652->lock);
2395
2396 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
2397 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hw_constraints_period_sizes);
2398 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
2399 snd_rme9652_hw_rule_channels, rme9652,
2400 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
2401 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
2402 snd_rme9652_hw_rule_channels_rate, rme9652,
2403 SNDRV_PCM_HW_PARAM_RATE, -1);
2404 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
2405 snd_rme9652_hw_rule_rate_channels, rme9652,
2406 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
2407 return 0;
2408 }
2409
2410 static int snd_rme9652_capture_release(snd_pcm_substream_t *substream)
2411 {
2412 rme9652_t *rme9652 = snd_pcm_substream_chip(substream);
2413
2414 spin_lock_irq(&rme9652->lock);
2415
2416 rme9652->capture_pid = -1;
2417 rme9652->capture_substream = NULL;
2418
2419 spin_unlock_irq(&rme9652->lock);
2420 return 0;
2421 }
2422
2423 static snd_pcm_ops_t snd_rme9652_playback_ops = {
2424 .open = snd_rme9652_playback_open,
2425 .close = snd_rme9652_playback_release,
2426 .ioctl = snd_rme9652_ioctl,
2427 .hw_params = snd_rme9652_hw_params,
2428 .prepare = snd_rme9652_prepare,
2429 .trigger = snd_rme9652_trigger,
2430 .pointer = snd_rme9652_hw_pointer,
2431 .copy = snd_rme9652_playback_copy,
2432 .silence = snd_rme9652_hw_silence,
2433 };
2434
2435 static snd_pcm_ops_t snd_rme9652_capture_ops = {
2436 .open = snd_rme9652_capture_open,
2437 .close = snd_rme9652_capture_release,
2438 .ioctl = snd_rme9652_ioctl,
2439 .hw_params = snd_rme9652_hw_params,
2440 .prepare = snd_rme9652_prepare,
2441 .trigger = snd_rme9652_trigger,
2442 .pointer = snd_rme9652_hw_pointer,
2443 .copy = snd_rme9652_capture_copy,
2444 };
2445
2446 static int __devinit snd_rme9652_create_pcm(snd_card_t *card,
2447 rme9652_t *rme9652)
2448 {
2449 snd_pcm_t *pcm;
2450 int err;
2451
2452 if ((err = snd_pcm_new(card,
2453 rme9652->card_name,
2454 0, 1, 1, &pcm)) < 0) {
2455 return err;
2456 }
2457
2458 rme9652->pcm = pcm;
2459 pcm->private_data = rme9652;
2460 strcpy(pcm->name, rme9652->card_name);
2461
2462 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme9652_playback_ops);
2463 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme9652_capture_ops);
2464
2465 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
2466
2467 return 0;
2468 }
2469
2470 static int __devinit snd_rme9652_create(snd_card_t *card,
2471 rme9652_t *rme9652,
2472 int precise_ptr)
2473 {
2474 struct pci_dev *pci = rme9652->pci;
2475 int err;
2476 int status;
2477 unsigned short rev;
2478
2479 rme9652->irq = -1;
2480 rme9652->card = card;
2481
2482 pci_read_config_word(rme9652->pci, PCI_CLASS_REVISION, &rev);
2483
2484 switch (rev & 0xff) {
2485 case 3:
2486 case 4:
2487 case 8:
2488 case 9:
2489 break;
2490
2491 default:
2492 /* who knows? */
2493 return -ENODEV;
2494 }
2495
2496 if ((err = pci_enable_device(pci)) < 0)
2497 return err;
2498
2499 spin_lock_init(&rme9652->lock);
2500
2501 if ((err = pci_request_regions(pci, "rme9652")) < 0)
2502 return err;
2503 rme9652->port = pci_resource_start(pci, 0);
2504 rme9652->iobase = ioremap_nocache(rme9652->port, RME9652_IO_EXTENT);
2505 if (rme9652->iobase == NULL) {
2506 snd_printk("unable to remap region 0x%lx-0x%lx\n", rme9652->port, rme9652->port + RME9652_IO_EXTENT - 1);
2507 return -EBUSY;
2508 }
2509
2510 if (request_irq(pci->irq, snd_rme9652_interrupt, SA_INTERRUPT|SA_SHIRQ, "rme9652", (void *)rme9652)) {
2511 snd_printk("unable to request IRQ %d\n", pci->irq);
2512 return -EBUSY;
2513 }
2514 rme9652->irq = pci->irq;
2515 rme9652->precise_ptr = precise_ptr;
2516
2517 /* Determine the h/w rev level of the card. This seems like
2518 a particularly kludgy way to encode it, but its what RME
2519 chose to do, so we follow them ...
2520 */
2521
2522 status = rme9652_read(rme9652, RME9652_status_register);
2523 if (rme9652_decode_spdif_rate(status&RME9652_F) == 1) {
2524 rme9652->hw_rev = 15;
2525 } else {
2526 rme9652->hw_rev = 11;
2527 }
2528
2529 /* Differentiate between the standard Hammerfall, and the
2530 "Light", which does not have the expansion board. This
2531 method comes from information received from Mathhias
2532 Clausen at RME. Display the EEPROM and h/w revID where
2533 relevant.
2534 */
2535
2536 switch (rev) {
2537 case 8: /* original eprom */
2538 strcpy(card->driver, "RME9636");
2539 if (rme9652->hw_rev == 15) {
2540 rme9652->card_name = "RME Digi9636 (Rev 1.5)";
2541 } else {
2542 rme9652->card_name = "RME Digi9636";
2543 }
2544 rme9652->ss_channels = RME9636_NCHANNELS;
2545 break;
2546 case 9: /* W36_G EPROM */
2547 strcpy(card->driver, "RME9636");
2548 rme9652->card_name = "RME Digi9636 (Rev G)";
2549 rme9652->ss_channels = RME9636_NCHANNELS;
2550 break;
2551 case 4: /* W52_G EPROM */
2552 strcpy(card->driver, "RME9652");
2553 rme9652->card_name = "RME Digi9652 (Rev G)";
2554 rme9652->ss_channels = RME9652_NCHANNELS;
2555 break;
2556 case 3: /* original eprom */
2557 strcpy(card->driver, "RME9652");
2558 if (rme9652->hw_rev == 15) {
2559 rme9652->card_name = "RME Digi9652 (Rev 1.5)";
2560 } else {
2561 rme9652->card_name = "RME Digi9652";
2562 }
2563 rme9652->ss_channels = RME9652_NCHANNELS;
2564 break;
2565 }
2566
2567 rme9652->ds_channels = (rme9652->ss_channels - 2) / 2 + 2;
2568
2569 pci_set_master(rme9652->pci);
2570
2571 if ((err = snd_rme9652_initialize_memory(rme9652)) < 0) {
2572 return err;
2573 }
2574
2575 if ((err = snd_rme9652_create_pcm(card, rme9652)) < 0) {
2576 return err;
2577 }
2578
2579 if ((err = snd_rme9652_create_controls(card, rme9652)) < 0) {
2580 return err;
2581 }
2582
2583 snd_rme9652_proc_init(rme9652);
2584
2585 rme9652->last_spdif_sample_rate = -1;
2586 rme9652->last_adat_sample_rate = -1;
2587 rme9652->playback_pid = -1;
2588 rme9652->capture_pid = -1;
2589 rme9652->capture_substream = NULL;
2590 rme9652->playback_substream = NULL;
2591
2592 snd_rme9652_set_defaults(rme9652);
2593
2594 if (rme9652->hw_rev == 15) {
2595 rme9652_initialize_spdif_receiver (rme9652);
2596 }
2597
2598 return 0;
2599 }
2600
2601 static void snd_rme9652_card_free(snd_card_t *card)
2602 {
2603 rme9652_t *rme9652 = (rme9652_t *) card->private_data;
2604
2605 if (rme9652)
2606 snd_rme9652_free(rme9652);
2607 }
2608
2609 static int __devinit snd_rme9652_probe(struct pci_dev *pci,
2610 const struct pci_device_id *pci_id)
2611 {
2612 static int dev;
2613 rme9652_t *rme9652;
2614 snd_card_t *card;
2615 int err;
2616
2617 if (dev >= SNDRV_CARDS)
2618 return -ENODEV;
2619 if (!enable[dev]) {
2620 dev++;
2621 return -ENOENT;
2622 }
2623
2624 card = snd_card_new(index[dev], id[dev], THIS_MODULE,
2625 sizeof(rme9652_t));
2626
2627 if (!card)
2628 return -ENOMEM;
2629
2630 rme9652 = (rme9652_t *) card->private_data;
2631 card->private_free = snd_rme9652_card_free;
2632 rme9652->dev = dev;
2633 rme9652->pci = pci;
2634 snd_card_set_dev(card, &pci->dev);
2635
2636 if ((err = snd_rme9652_create(card, rme9652, precise_ptr[dev])) < 0) {
2637 snd_card_free(card);
2638 return err;
2639 }
2640
2641 strcpy(card->shortname, rme9652->card_name);
2642
2643 sprintf(card->longname, "%s at 0x%lx, irq %d",
2644 card->shortname, rme9652->port, rme9652->irq);
2645
2646
2647 if ((err = snd_card_register(card)) < 0) {
2648 snd_card_free(card);
2649 return err;
2650 }
2651 pci_set_drvdata(pci, card);
2652 dev++;
2653 return 0;
2654 }
2655
2656 static void __devexit snd_rme9652_remove(struct pci_dev *pci)
2657 {
2658 snd_card_free(pci_get_drvdata(pci));
2659 pci_set_drvdata(pci, NULL);
2660 }
2661
2662 static struct pci_driver driver = {
2663 .name = "RME Digi9652 (Hammerfall)",
2664 .id_table = snd_rme9652_ids,
2665 .probe = snd_rme9652_probe,
2666 .remove = __devexit_p(snd_rme9652_remove),
2667 };
2668
2669 static int __init alsa_card_hammerfall_init(void)
2670 {
2671 return pci_register_driver(&driver);
2672 }
2673
2674 static void __exit alsa_card_hammerfall_exit(void)
2675 {
2676 pci_unregister_driver(&driver);
2677 }
2678
2679 module_init(alsa_card_hammerfall_init)
2680 module_exit(alsa_card_hammerfall_exit)
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