drivers/mmc/host/sdhci.c

   1 /*
   2  *  linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
   3  *
   4  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or (at
   9  * your option) any later version.
  10  *
  11  * Thanks to the following companies for their support:
  12  *
  13  *     - JMicron (hardware and technical support)
  14  */
  15
  16 #include <linux/delay.h>
  17 #include <linux/highmem.h>
  18 #include <linux/io.h>
  19 #include <linux/dma-mapping.h>
  20 #include <linux/slab.h>
  21 #include <linux/scatterlist.h>
  22 #include <linux/regulator/consumer.h>
  23
  24 #include <linux/leds.h>
  25
  26 #include <linux/mmc/mmc.h>
  27 #include <linux/mmc/host.h>
  28
  29 #include "sdhci.h"
  30
  31 #define DRIVER_NAME "sdhci"
  32
  33 #define DBG(f, x...) \
  34         pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
  35
  36 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
  37         defined(CONFIG_MMC_SDHCI_MODULE))
  38 #define SDHCI_USE_LEDS_CLASS
  39 #endif
  40
  41 static unsigned int debug_quirks = 0;
  42
  43 static void sdhci_finish_data(struct sdhci_host *);
  44
  45 static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
  46 static void sdhci_finish_command(struct sdhci_host *);
  47
  48 static void sdhci_dumpregs(struct sdhci_host *host)
  49 {
  50         printk(KERN_DEBUG DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
  51                 mmc_hostname(host->mmc));
  52
  53         printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version:  0x%08x\n",
  54                 sdhci_readl(host, SDHCI_DMA_ADDRESS),
  55                 sdhci_readw(host, SDHCI_HOST_VERSION));
  56         printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt:  0x%08x\n",
  57                 sdhci_readw(host, SDHCI_BLOCK_SIZE),
  58                 sdhci_readw(host, SDHCI_BLOCK_COUNT));
  59         printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
  60                 sdhci_readl(host, SDHCI_ARGUMENT),
  61                 sdhci_readw(host, SDHCI_TRANSFER_MODE));
  62         printk(KERN_DEBUG DRIVER_NAME ": Present:  0x%08x | Host ctl: 0x%08x\n",
  63                 sdhci_readl(host, SDHCI_PRESENT_STATE),
  64                 sdhci_readb(host, SDHCI_HOST_CONTROL));
  65         printk(KERN_DEBUG DRIVER_NAME ": Power:    0x%08x | Blk gap:  0x%08x\n",
  66                 sdhci_readb(host, SDHCI_POWER_CONTROL),
  67                 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
  68         printk(KERN_DEBUG DRIVER_NAME ": Wake-up:  0x%08x | Clock:    0x%08x\n",
  69                 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
  70                 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
  71         printk(KERN_DEBUG DRIVER_NAME ": Timeout:  0x%08x | Int stat: 0x%08x\n",
  72                 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
  73                 sdhci_readl(host, SDHCI_INT_STATUS));
  74         printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
  75                 sdhci_readl(host, SDHCI_INT_ENABLE),
  76                 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
  77         printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
  78                 sdhci_readw(host, SDHCI_ACMD12_ERR),
  79                 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
  80         printk(KERN_DEBUG DRIVER_NAME ": Caps:     0x%08x | Caps_1:   0x%08x\n",
  81                 sdhci_readl(host, SDHCI_CAPABILITIES),
  82                 sdhci_readl(host, SDHCI_CAPABILITIES_1));
  83         printk(KERN_DEBUG DRIVER_NAME ": Cmd:      0x%08x | Max curr: 0x%08x\n",
  84                 sdhci_readw(host, SDHCI_COMMAND),
  85                 sdhci_readl(host, SDHCI_MAX_CURRENT));
  86         printk(KERN_DEBUG DRIVER_NAME ": Host ctl2: 0x%08x\n",
  87                 sdhci_readw(host, SDHCI_HOST_CONTROL2));
  88
  89         if (host->flags & SDHCI_USE_ADMA)
  90                 printk(KERN_DEBUG DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
  91                        readl(host->ioaddr + SDHCI_ADMA_ERROR),
  92                        readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
  93
  94         printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
  95 }
  96
  97 /*****************************************************************************\
  98  *                                                                           *
  99  * Low level functions                                                       *
 100  *                                                                           *
 101 \*****************************************************************************/
 102
 103 static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
 104 {
 105         u32 ier;
 106
 107         ier = sdhci_readl(host, SDHCI_INT_ENABLE);
 108         ier &= ~clear;
 109         ier |= set;
 110         sdhci_writel(host, ier, SDHCI_INT_ENABLE);
 111         sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
 112 }
 113
 114 static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
 115 {
 116         sdhci_clear_set_irqs(host, 0, irqs);
 117 }
 118
 119 static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
 120 {
 121         sdhci_clear_set_irqs(host, irqs, 0);
 122 }
 123
 124 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
 125 {
 126         u32 irqs = SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT;
 127
 128         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
 129                 return;
 130
 131         if (enable)
 132                 sdhci_unmask_irqs(host, irqs);
 133         else
 134                 sdhci_mask_irqs(host, irqs);
 135 }
 136
 137 static void sdhci_enable_card_detection(struct sdhci_host *host)
 138 {
 139         sdhci_set_card_detection(host, true);
 140 }
 141
 142 static void sdhci_disable_card_detection(struct sdhci_host *host)
 143 {
 144         sdhci_set_card_detection(host, false);
 145 }
 146
 147 static void sdhci_reset(struct sdhci_host *host, u8 mask)
 148 {
 149         unsigned long timeout;
 150         u32 uninitialized_var(ier);
 151
 152         if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
 153                 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
 154                         SDHCI_CARD_PRESENT))
 155                         return;
 156         }
 157
 158         if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
 159                 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
 160
 161         if (host->ops->platform_reset_enter)
 162                 host->ops->platform_reset_enter(host, mask);
 163
 164         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
 165
 166         if (mask & SDHCI_RESET_ALL)
 167                 host->clock = 0;
 168
 169         /* Wait max 100 ms */
 170         timeout = 100;
 171
 172         /* hw clears the bit when it's done */
 173         while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
 174                 if (timeout == 0) {
 175                         printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
 176                                 mmc_hostname(host->mmc), (int)mask);
 177                         sdhci_dumpregs(host);
 178                         return;
 179                 }
 180                 timeout--;
 181                 mdelay(1);
 182         }
 183
 184         if (host->ops->platform_reset_exit)
 185                 host->ops->platform_reset_exit(host, mask);
 186
 187         if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
 188                 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
 189 }
 190
 191 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
 192
 193 static void sdhci_init(struct sdhci_host *host, int soft)
 194 {
 195         if (soft)
 196                 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
 197         else
 198                 sdhci_reset(host, SDHCI_RESET_ALL);
 199
 200         sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
 201                 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
 202                 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
 203                 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
 204                 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
 205
 206         if (soft) {
 207                 /* force clock reconfiguration */
 208                 host->clock = 0;
 209                 sdhci_set_ios(host->mmc, &host->mmc->ios);
 210         }
 211 }
 212
 213 static void sdhci_reinit(struct sdhci_host *host)
 214 {
 215         sdhci_init(host, 0);
 216         sdhci_enable_card_detection(host);
 217 }
 218
 219 static void sdhci_activate_led(struct sdhci_host *host)
 220 {
 221         u8 ctrl;
 222
 223         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 224         ctrl |= SDHCI_CTRL_LED;
 225         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 226 }
 227
 228 static void sdhci_deactivate_led(struct sdhci_host *host)
 229 {
 230         u8 ctrl;
 231
 232         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 233         ctrl &= ~SDHCI_CTRL_LED;
 234         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 235 }
 236
 237 #ifdef SDHCI_USE_LEDS_CLASS
 238 static void sdhci_led_control(struct led_classdev *led,
 239         enum led_brightness brightness)
 240 {
 241         struct sdhci_host *host = container_of(led, struct sdhci_host, led);
 242         unsigned long flags;
 243
 244         spin_lock_irqsave(&host->lock, flags);
 245
 246         if (brightness == LED_OFF)
 247                 sdhci_deactivate_led(host);
 248         else
 249                 sdhci_activate_led(host);
 250
 251         spin_unlock_irqrestore(&host->lock, flags);
 252 }
 253 #endif
 254
 255 /*****************************************************************************\
 256  *                                                                           *
 257  * Core functions                                                            *
 258  *                                                                           *
 259 \*****************************************************************************/
 260
 261 static void sdhci_read_block_pio(struct sdhci_host *host)
 262 {
 263         unsigned long flags;
 264         size_t blksize, len, chunk;
 265         u32 uninitialized_var(scratch);
 266         u8 *buf;
 267
 268         DBG("PIO reading\n");
 269
 270         blksize = host->data->blksz;
 271         chunk = 0;
 272
 273         local_irq_save(flags);
 274
 275         while (blksize) {
 276                 if (!sg_miter_next(&host->sg_miter))
 277                         BUG();
 278
 279                 len = min(host->sg_miter.length, blksize);
 280
 281                 blksize -= len;
 282                 host->sg_miter.consumed = len;
 283
 284                 buf = host->sg_miter.addr;
 285
 286                 while (len) {
 287                         if (chunk == 0) {
 288                                 scratch = sdhci_readl(host, SDHCI_BUFFER);
 289                                 chunk = 4;
 290                         }
 291
 292                         *buf = scratch & 0xFF;
 293
 294                         buf++;
 295                         scratch >>= 8;
 296                         chunk--;
 297                         len--;
 298                 }
 299         }
 300
 301         sg_miter_stop(&host->sg_miter);
 302
 303         local_irq_restore(flags);
 304 }
 305
 306 static void sdhci_write_block_pio(struct sdhci_host *host)
 307 {
 308         unsigned long flags;
 309         size_t blksize, len, chunk;
 310         u32 scratch;
 311         u8 *buf;
 312
 313         DBG("PIO writing\n");
 314
 315         blksize = host->data->blksz;
 316         chunk = 0;
 317         scratch = 0;
 318
 319         local_irq_save(flags);
 320
 321         while (blksize) {
 322                 if (!sg_miter_next(&host->sg_miter))
 323                         BUG();
 324
 325                 len = min(host->sg_miter.length, blksize);
 326
 327                 blksize -= len;
 328                 host->sg_miter.consumed = len;
 329
 330                 buf = host->sg_miter.addr;
 331
 332                 while (len) {
 333                         scratch |= (u32)*buf << (chunk * 8);
 334
 335                         buf++;
 336                         chunk++;
 337                         len--;
 338
 339                         if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
 340                                 sdhci_writel(host, scratch, SDHCI_BUFFER);
 341                                 chunk = 0;
 342                                 scratch = 0;
 343                         }
 344                 }
 345         }
 346
 347         sg_miter_stop(&host->sg_miter);
 348
 349         local_irq_restore(flags);
 350 }
 351
 352 static void sdhci_transfer_pio(struct sdhci_host *host)
 353 {
 354         u32 mask;
 355
 356         BUG_ON(!host->data);
 357
 358         if (host->blocks == 0)
 359                 return;
 360
 361         if (host->data->flags & MMC_DATA_READ)
 362                 mask = SDHCI_DATA_AVAILABLE;
 363         else
 364                 mask = SDHCI_SPACE_AVAILABLE;
 365
 366         /*
 367          * Some controllers (JMicron JMB38x) mess up the buffer bits
 368          * for transfers < 4 bytes. As long as it is just one block,
 369          * we can ignore the bits.
 370          */
 371         if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
 372                 (host->data->blocks == 1))
 373                 mask = ~0;
 374
 375         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 376                 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
 377                         udelay(100);
 378
 379                 if (host->data->flags & MMC_DATA_READ)
 380                         sdhci_read_block_pio(host);
 381                 else
 382                         sdhci_write_block_pio(host);
 383
 384                 host->blocks--;
 385                 if (host->blocks == 0)
 386                         break;
 387         }
 388
 389         DBG("PIO transfer complete.\n");
 390 }
 391
 392 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
 393 {
 394         local_irq_save(*flags);
 395         return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
 396 }
 397
 398 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
 399 {
 400         kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
 401         local_irq_restore(*flags);
 402 }
 403
 404 static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
 405 {
 406         __le32 *dataddr = (__le32 __force *)(desc + 4);
 407         __le16 *cmdlen = (__le16 __force *)desc;
 408
 409         /* SDHCI specification says ADMA descriptors should be 4 byte
 410          * aligned, so using 16 or 32bit operations should be safe. */
 411
 412         cmdlen[0] = cpu_to_le16(cmd);
 413         cmdlen[1] = cpu_to_le16(len);
 414
 415         dataddr[0] = cpu_to_le32(addr);
 416 }
 417
 418 static int sdhci_adma_table_pre(struct sdhci_host *host,
 419         struct mmc_data *data)
 420 {
 421         int direction;
 422
 423         u8 *desc;
 424         u8 *align;
 425         dma_addr_t addr;
 426         dma_addr_t align_addr;
 427         int len, offset;
 428
 429         struct scatterlist *sg;
 430         int i;
 431         char *buffer;
 432         unsigned long flags;
 433
 434         /*
 435          * The spec does not specify endianness of descriptor table.
 436          * We currently guess that it is LE.
 437          */
 438
 439         if (data->flags & MMC_DATA_READ)
 440                 direction = DMA_FROM_DEVICE;
 441         else
 442                 direction = DMA_TO_DEVICE;
 443
 444         /*
 445          * The ADMA descriptor table is mapped further down as we
 446          * need to fill it with data first.
 447          */
 448
 449         host->align_addr = dma_map_single(mmc_dev(host->mmc),
 450                 host->align_buffer, 128 * 4, direction);
 451         if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
 452                 goto fail;
 453         BUG_ON(host->align_addr & 0x3);
 454
 455         host->sg_count = dma_map_sg(mmc_dev(host->mmc),
 456                 data->sg, data->sg_len, direction);
 457         if (host->sg_count == 0)
 458                 goto unmap_align;
 459
 460         desc = host->adma_desc;
 461         align = host->align_buffer;
 462
 463         align_addr = host->align_addr;
 464
 465         for_each_sg(data->sg, sg, host->sg_count, i) {
 466                 addr = sg_dma_address(sg);
 467                 len = sg_dma_len(sg);
 468
 469                 /*
 470                  * The SDHCI specification states that ADMA
 471                  * addresses must be 32-bit aligned. If they
 472                  * aren't, then we use a bounce buffer for
 473                  * the (up to three) bytes that screw up the
 474                  * alignment.
 475                  */
 476                 offset = (4 - (addr & 0x3)) & 0x3;
 477                 if (offset) {
 478                         if (data->flags & MMC_DATA_WRITE) {
 479                                 buffer = sdhci_kmap_atomic(sg, &flags);
 480                                 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
 481                                 memcpy(align, buffer, offset);
 482                                 sdhci_kunmap_atomic(buffer, &flags);
 483                         }
 484
 485                         /* tran, valid */
 486                         sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
 487
 488                         BUG_ON(offset > 65536);
 489
 490                         align += 4;
 491                         align_addr += 4;
 492
 493                         desc += 8;
 494
 495                         addr += offset;
 496                         len -= offset;
 497                 }
 498
 499                 BUG_ON(len > 65536);
 500
 501                 /* tran, valid */
 502                 sdhci_set_adma_desc(desc, addr, len, 0x21);
 503                 desc += 8;
 504
 505                 /*
 506                  * If this triggers then we have a calculation bug
 507                  * somewhere. :/
 508                  */
 509                 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
 510         }
 511
 512         if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
 513                 /*
 514                 * Mark the last descriptor as the terminating descriptor
 515                 */
 516                 if (desc != host->adma_desc) {
 517                         desc -= 8;
 518                         desc[0] |= 0x2; /* end */
 519                 }
 520         } else {
 521                 /*
 522                 * Add a terminating entry.
 523                 */
 524
 525                 /* nop, end, valid */
 526                 sdhci_set_adma_desc(desc, 0, 0, 0x3);
 527         }
 528
 529         /*
 530          * Resync align buffer as we might have changed it.
 531          */
 532         if (data->flags & MMC_DATA_WRITE) {
 533                 dma_sync_single_for_device(mmc_dev(host->mmc),
 534                         host->align_addr, 128 * 4, direction);
 535         }
 536
 537         host->adma_addr = dma_map_single(mmc_dev(host->mmc),
 538                 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
 539         if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
 540                 goto unmap_entries;
 541         BUG_ON(host->adma_addr & 0x3);
 542
 543         return 0;
 544
 545 unmap_entries:
 546         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 547                 data->sg_len, direction);
 548 unmap_align:
 549         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
 550                 128 * 4, direction);
 551 fail:
 552         return -EINVAL;
 553 }
 554
 555 static void sdhci_adma_table_post(struct sdhci_host *host,
 556         struct mmc_data *data)
 557 {
 558         int direction;
 559
 560         struct scatterlist *sg;
 561         int i, size;
 562         u8 *align;
 563         char *buffer;
 564         unsigned long flags;
 565
 566         if (data->flags & MMC_DATA_READ)
 567                 direction = DMA_FROM_DEVICE;
 568         else
 569                 direction = DMA_TO_DEVICE;
 570
 571         dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
 572                 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
 573
 574         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
 575                 128 * 4, direction);
 576
 577         if (data->flags & MMC_DATA_READ) {
 578                 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
 579                         data->sg_len, direction);
 580
 581                 align = host->align_buffer;
 582
 583                 for_each_sg(data->sg, sg, host->sg_count, i) {
 584                         if (sg_dma_address(sg) & 0x3) {
 585                                 size = 4 - (sg_dma_address(sg) & 0x3);
 586
 587                                 buffer = sdhci_kmap_atomic(sg, &flags);
 588                                 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
 589                                 memcpy(buffer, align, size);
 590                                 sdhci_kunmap_atomic(buffer, &flags);
 591
 592                                 align += 4;
 593                         }
 594                 }
 595         }
 596
 597         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 598                 data->sg_len, direction);
 599 }
 600
 601 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
 602 {
 603         u8 count;
 604         struct mmc_data *data = cmd->data;
 605         unsigned target_timeout, current_timeout;
 606
 607         /*
 608          * If the host controller provides us with an incorrect timeout
 609          * value, just skip the check and use 0xE.  The hardware may take
 610          * longer to time out, but that's much better than having a too-short
 611          * timeout value.
 612          */
 613         if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
 614                 return 0xE;
 615
 616         /* Unspecified timeout, assume max */
 617         if (!data && !cmd->cmd_timeout_ms)
 618                 return 0xE;
 619
 620         /* timeout in us */
 621         if (!data)
 622                 target_timeout = cmd->cmd_timeout_ms * 1000;
 623         else
 624                 target_timeout = data->timeout_ns / 1000 +
 625                         data->timeout_clks / host->clock;
 626
 627         if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
 628                 host->timeout_clk = host->clock / 1000;
 629
 630         /*
 631          * Figure out needed cycles.
 632          * We do this in steps in order to fit inside a 32 bit int.
 633          * The first step is the minimum timeout, which will have a
 634          * minimum resolution of 6 bits:
 635          * (1) 2^13*1000 > 2^22,
 636          * (2) host->timeout_clk < 2^16
 637          *     =>
 638          *     (1) / (2) > 2^6
 639          */
 640         BUG_ON(!host->timeout_clk);
 641         count = 0;
 642         current_timeout = (1 << 13) * 1000 / host->timeout_clk;
 643         while (current_timeout < target_timeout) {
 644                 count++;
 645                 current_timeout <<= 1;
 646                 if (count >= 0xF)
 647                         break;
 648         }
 649
 650         if (count >= 0xF) {
 651                 printk(KERN_WARNING "%s: Too large timeout requested for CMD%d!\n",
 652                        mmc_hostname(host->mmc), cmd->opcode);
 653                 count = 0xE;
 654         }
 655
 656         return count;
 657 }
 658
 659 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
 660 {
 661         u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
 662         u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
 663
 664         if (host->flags & SDHCI_REQ_USE_DMA)
 665                 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
 666         else
 667                 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
 668 }
 669
 670 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
 671 {
 672         u8 count;
 673         u8 ctrl;
 674         struct mmc_data *data = cmd->data;
 675         int ret;
 676
 677         WARN_ON(host->data);
 678
 679         if (data || (cmd->flags & MMC_RSP_BUSY)) {
 680                 count = sdhci_calc_timeout(host, cmd);
 681                 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
 682         }
 683
 684         if (!data)
 685                 return;
 686
 687         /* Sanity checks */
 688         BUG_ON(data->blksz * data->blocks > 524288);
 689         BUG_ON(data->blksz > host->mmc->max_blk_size);
 690         BUG_ON(data->blocks > 65535);
 691
 692         host->data = data;
 693         host->data_early = 0;
 694         host->data->bytes_xfered = 0;
 695
 696         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
 697                 host->flags |= SDHCI_REQ_USE_DMA;
 698
 699         /*
 700          * FIXME: This doesn't account for merging when mapping the
 701          * scatterlist.
 702          */
 703         if (host->flags & SDHCI_REQ_USE_DMA) {
 704                 int broken, i;
 705                 struct scatterlist *sg;
 706
 707                 broken = 0;
 708                 if (host->flags & SDHCI_USE_ADMA) {
 709                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
 710                                 broken = 1;
 711                 } else {
 712                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
 713                                 broken = 1;
 714                 }
 715
 716                 if (unlikely(broken)) {
 717                         for_each_sg(data->sg, sg, data->sg_len, i) {
 718                                 if (sg->length & 0x3) {
 719                                         DBG("Reverting to PIO because of "
 720                                                 "transfer size (%d)\n",
 721                                                 sg->length);
 722                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 723                                         break;
 724                                 }
 725                         }
 726                 }
 727         }
 728
 729         /*
 730          * The assumption here being that alignment is the same after
 731          * translation to device address space.
 732          */
 733         if (host->flags & SDHCI_REQ_USE_DMA) {
 734                 int broken, i;
 735                 struct scatterlist *sg;
 736
 737                 broken = 0;
 738                 if (host->flags & SDHCI_USE_ADMA) {
 739                         /*
 740                          * As we use 3 byte chunks to work around
 741                          * alignment problems, we need to check this
 742                          * quirk.
 743                          */
 744                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
 745                                 broken = 1;
 746                 } else {
 747                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
 748                                 broken = 1;
 749                 }
 750
 751                 if (unlikely(broken)) {
 752                         for_each_sg(data->sg, sg, data->sg_len, i) {
 753                                 if (sg->offset & 0x3) {
 754                                         DBG("Reverting to PIO because of "
 755                                                 "bad alignment\n");
 756                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 757                                         break;
 758                                 }
 759                         }
 760                 }
 761         }
 762
 763         if (host->flags & SDHCI_REQ_USE_DMA) {
 764                 if (host->flags & SDHCI_USE_ADMA) {
 765                         ret = sdhci_adma_table_pre(host, data);
 766                         if (ret) {
 767                                 /*
 768                                  * This only happens when someone fed
 769                                  * us an invalid request.
 770                                  */
 771                                 WARN_ON(1);
 772                                 host->flags &= ~SDHCI_REQ_USE_DMA;
 773                         } else {
 774                                 sdhci_writel(host, host->adma_addr,
 775                                         SDHCI_ADMA_ADDRESS);
 776                         }
 777                 } else {
 778                         int sg_cnt;
 779
 780                         sg_cnt = dma_map_sg(mmc_dev(host->mmc),
 781                                         data->sg, data->sg_len,
 782                                         (data->flags & MMC_DATA_READ) ?
 783                                                 DMA_FROM_DEVICE :
 784                                                 DMA_TO_DEVICE);
 785                         if (sg_cnt == 0) {
 786                                 /*
 787                                  * This only happens when someone fed
 788                                  * us an invalid request.
 789                                  */
 790                                 WARN_ON(1);
 791                                 host->flags &= ~SDHCI_REQ_USE_DMA;
 792                         } else {
 793                                 WARN_ON(sg_cnt != 1);
 794                                 sdhci_writel(host, sg_dma_address(data->sg),
 795                                         SDHCI_DMA_ADDRESS);
 796                         }
 797                 }
 798         }
 799
 800         /*
 801          * Always adjust the DMA selection as some controllers
 802          * (e.g. JMicron) can't do PIO properly when the selection
 803          * is ADMA.
 804          */
 805         if (host->version >= SDHCI_SPEC_200) {
 806                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 807                 ctrl &= ~SDHCI_CTRL_DMA_MASK;
 808                 if ((host->flags & SDHCI_REQ_USE_DMA) &&
 809                         (host->flags & SDHCI_USE_ADMA))
 810                         ctrl |= SDHCI_CTRL_ADMA32;
 811                 else
 812                         ctrl |= SDHCI_CTRL_SDMA;
 813                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 814         }
 815
 816         if (!(host->flags & SDHCI_REQ_USE_DMA)) {
 817                 int flags;
 818
 819                 flags = SG_MITER_ATOMIC;
 820                 if (host->data->flags & MMC_DATA_READ)
 821                         flags |= SG_MITER_TO_SG;
 822                 else
 823                         flags |= SG_MITER_FROM_SG;
 824                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
 825                 host->blocks = data->blocks;
 826         }
 827
 828         sdhci_set_transfer_irqs(host);
 829
 830         /* Set the DMA boundary value and block size */
 831         sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
 832                 data->blksz), SDHCI_BLOCK_SIZE);
 833         sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
 834 }
 835
 836 static void sdhci_set_transfer_mode(struct sdhci_host *host,
 837         struct mmc_data *data)
 838 {
 839         u16 mode;
 840
 841         if (data == NULL)
 842                 return;
 843
 844         WARN_ON(!host->data);
 845
 846         mode = SDHCI_TRNS_BLK_CNT_EN;
 847         if (data->blocks > 1) {
 848                 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
 849                         mode |= SDHCI_TRNS_MULTI | SDHCI_TRNS_ACMD12;
 850                 else
 851                         mode |= SDHCI_TRNS_MULTI;
 852         }
 853         if (data->flags & MMC_DATA_READ)
 854                 mode |= SDHCI_TRNS_READ;
 855         if (host->flags & SDHCI_REQ_USE_DMA)
 856                 mode |= SDHCI_TRNS_DMA;
 857
 858         sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
 859 }
 860
 861 static void sdhci_finish_data(struct sdhci_host *host)
 862 {
 863         struct mmc_data *data;
 864
 865         BUG_ON(!host->data);
 866
 867         data = host->data;
 868         host->data = NULL;
 869
 870         if (host->flags & SDHCI_REQ_USE_DMA) {
 871                 if (host->flags & SDHCI_USE_ADMA)
 872                         sdhci_adma_table_post(host, data);
 873                 else {
 874                         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 875                                 data->sg_len, (data->flags & MMC_DATA_READ) ?
 876                                         DMA_FROM_DEVICE : DMA_TO_DEVICE);
 877                 }
 878         }
 879
 880         /*
 881          * The specification states that the block count register must
 882          * be updated, but it does not specify at what point in the
 883          * data flow. That makes the register entirely useless to read
 884          * back so we have to assume that nothing made it to the card
 885          * in the event of an error.
 886          */
 887         if (data->error)
 888                 data->bytes_xfered = 0;
 889         else
 890                 data->bytes_xfered = data->blksz * data->blocks;
 891
 892         if (data->stop) {
 893                 /*
 894                  * The controller needs a reset of internal state machines
 895                  * upon error conditions.
 896                  */
 897                 if (data->error) {
 898                         sdhci_reset(host, SDHCI_RESET_CMD);
 899                         sdhci_reset(host, SDHCI_RESET_DATA);
 900                 }
 901
 902                 sdhci_send_command(host, data->stop);
 903         } else
 904                 tasklet_schedule(&host->finish_tasklet);
 905 }
 906
 907 static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
 908 {
 909         int flags;
 910         u32 mask;
 911         unsigned long timeout;
 912
 913         WARN_ON(host->cmd);
 914
 915         /* Wait max 10 ms */
 916         timeout = 10;
 917
 918         mask = SDHCI_CMD_INHIBIT;
 919         if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
 920                 mask |= SDHCI_DATA_INHIBIT;
 921
 922         /* We shouldn't wait for data inihibit for stop commands, even
 923            though they might use busy signaling */
 924         if (host->mrq->data && (cmd == host->mrq->data->stop))
 925                 mask &= ~SDHCI_DATA_INHIBIT;
 926
 927         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 928                 if (timeout == 0) {
 929                         printk(KERN_ERR "%s: Controller never released "
 930                                 "inhibit bit(s).\n", mmc_hostname(host->mmc));
 931                         sdhci_dumpregs(host);
 932                         cmd->error = -EIO;
 933                         tasklet_schedule(&host->finish_tasklet);
 934                         return;
 935                 }
 936                 timeout--;
 937                 mdelay(1);
 938         }
 939
 940         mod_timer(&host->timer, jiffies + 10 * HZ);
 941
 942         host->cmd = cmd;
 943
 944         sdhci_prepare_data(host, cmd);
 945
 946         sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
 947
 948         sdhci_set_transfer_mode(host, cmd->data);
 949
 950         if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
 951                 printk(KERN_ERR "%s: Unsupported response type!\n",
 952                         mmc_hostname(host->mmc));
 953                 cmd->error = -EINVAL;
 954                 tasklet_schedule(&host->finish_tasklet);
 955                 return;
 956         }
 957
 958         if (!(cmd->flags & MMC_RSP_PRESENT))
 959                 flags = SDHCI_CMD_RESP_NONE;
 960         else if (cmd->flags & MMC_RSP_136)
 961                 flags = SDHCI_CMD_RESP_LONG;
 962         else if (cmd->flags & MMC_RSP_BUSY)
 963                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
 964         else
 965                 flags = SDHCI_CMD_RESP_SHORT;
 966
 967         if (cmd->flags & MMC_RSP_CRC)
 968                 flags |= SDHCI_CMD_CRC;
 969         if (cmd->flags & MMC_RSP_OPCODE)
 970                 flags |= SDHCI_CMD_INDEX;
 971         if (cmd->data)
 972                 flags |= SDHCI_CMD_DATA;
 973
 974         sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
 975 }
 976
 977 static void sdhci_finish_command(struct sdhci_host *host)
 978 {
 979         int i;
 980
 981         BUG_ON(host->cmd == NULL);
 982
 983         if (host->cmd->flags & MMC_RSP_PRESENT) {
 984                 if (host->cmd->flags & MMC_RSP_136) {
 985                         /* CRC is stripped so we need to do some shifting. */
 986                         for (i = 0;i < 4;i++) {
 987                                 host->cmd->resp[i] = sdhci_readl(host,
 988                                         SDHCI_RESPONSE + (3-i)*4) << 8;
 989                                 if (i != 3)
 990                                         host->cmd->resp[i] |=
 991                                                 sdhci_readb(host,
 992                                                 SDHCI_RESPONSE + (3-i)*4-1);
 993                         }
 994                 } else {
 995                         host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
 996                 }
 997         }
 998
 999         host->cmd->error = 0;
1000
1001         if (host->data && host->data_early)
1002                 sdhci_finish_data(host);
1003
1004         if (!host->cmd->data)
1005                 tasklet_schedule(&host->finish_tasklet);
1006
1007         host->cmd = NULL;
1008 }
1009
1010 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1011 {
1012         int div;
1013         u16 clk;
1014         unsigned long timeout;
1015
1016         if (clock == host->clock)
1017                 return;
1018
1019         if (host->ops->set_clock) {
1020                 host->ops->set_clock(host, clock);
1021                 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
1022                         return;
1023         }
1024
1025         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1026
1027         if (clock == 0)
1028                 goto out;
1029
1030         if (host->version >= SDHCI_SPEC_300) {
1031                 /* Version 3.00 divisors must be a multiple of 2. */
1032                 if (host->max_clk <= clock)
1033                         div = 1;
1034                 else {
1035                         for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; div += 2) {
1036                                 if ((host->max_clk / div) <= clock)
1037                                         break;
1038                         }
1039                 }
1040         } else {
1041                 /* Version 2.00 divisors must be a power of 2. */
1042                 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1043                         if ((host->max_clk / div) <= clock)
1044                                 break;
1045                 }
1046         }
1047         div >>= 1;
1048
1049         clk = (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1050         clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1051                 << SDHCI_DIVIDER_HI_SHIFT;
1052         clk |= SDHCI_CLOCK_INT_EN;
1053         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1054
1055         /* Wait max 20 ms */
1056         timeout = 20;
1057         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1058                 & SDHCI_CLOCK_INT_STABLE)) {
1059                 if (timeout == 0) {
1060                         printk(KERN_ERR "%s: Internal clock never "
1061                                 "stabilised.\n", mmc_hostname(host->mmc));
1062                         sdhci_dumpregs(host);
1063                         return;
1064                 }
1065                 timeout--;
1066                 mdelay(1);
1067         }
1068
1069         clk |= SDHCI_CLOCK_CARD_EN;
1070         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1071
1072 out:
1073         host->clock = clock;
1074 }
1075
1076 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
1077 {
1078         u8 pwr = 0;
1079
1080         if (power != (unsigned short)-1) {
1081                 switch (1 << power) {
1082                 case MMC_VDD_165_195:
1083                         pwr = SDHCI_POWER_180;
1084                         break;
1085                 case MMC_VDD_29_30:
1086                 case MMC_VDD_30_31:
1087                         pwr = SDHCI_POWER_300;
1088                         break;
1089                 case MMC_VDD_32_33:
1090                 case MMC_VDD_33_34:
1091                         pwr = SDHCI_POWER_330;
1092                         break;
1093                 default:
1094                         BUG();
1095                 }
1096         }
1097
1098         if (host->pwr == pwr)
1099                 return;
1100
1101         host->pwr = pwr;
1102
1103         if (pwr == 0) {
1104                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1105                 return;
1106         }
1107
1108         /*
1109          * Spec says that we should clear the power reg before setting
1110          * a new value. Some controllers don't seem to like this though.
1111          */
1112         if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1113                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1114
1115         /*
1116          * At least the Marvell CaFe chip gets confused if we set the voltage
1117          * and set turn on power at the same time, so set the voltage first.
1118          */
1119         if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1120                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1121
1122         pwr |= SDHCI_POWER_ON;
1123
1124         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1125
1126         /*
1127          * Some controllers need an extra 10ms delay of 10ms before they
1128          * can apply clock after applying power
1129          */
1130         if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1131                 mdelay(10);
1132 }
1133
1134 /*****************************************************************************\
1135  *                                                                           *
1136  * MMC callbacks                                                             *
1137  *                                                                           *
1138 \*****************************************************************************/
1139
1140 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1141 {
1142         struct sdhci_host *host;
1143         bool present;
1144         unsigned long flags;
1145
1146         host = mmc_priv(mmc);
1147
1148         spin_lock_irqsave(&host->lock, flags);
1149
1150         WARN_ON(host->mrq != NULL);
1151
1152 #ifndef SDHCI_USE_LEDS_CLASS
1153         sdhci_activate_led(host);
1154 #endif
1155         if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12) {
1156                 if (mrq->stop) {
1157                         mrq->data->stop = NULL;
1158                         mrq->stop = NULL;
1159                 }
1160         }
1161
1162         host->mrq = mrq;
1163
1164         /* If polling, assume that the card is always present. */
1165         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1166                 present = true;
1167         else
1168                 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1169                                 SDHCI_CARD_PRESENT;
1170
1171         if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1172                 host->mrq->cmd->error = -ENOMEDIUM;
1173                 tasklet_schedule(&host->finish_tasklet);
1174         } else
1175                 sdhci_send_command(host, mrq->cmd);
1176
1177         mmiowb();
1178         spin_unlock_irqrestore(&host->lock, flags);
1179 }
1180
1181 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1182 {
1183         struct sdhci_host *host;
1184         unsigned long flags;
1185         u8 ctrl;
1186
1187         host = mmc_priv(mmc);
1188
1189         spin_lock_irqsave(&host->lock, flags);
1190
1191         if (host->flags & SDHCI_DEVICE_DEAD)
1192                 goto out;
1193
1194         /*
1195          * Reset the chip on each power off.
1196          * Should clear out any weird states.
1197          */
1198         if (ios->power_mode == MMC_POWER_OFF) {
1199                 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1200                 sdhci_reinit(host);
1201         }
1202
1203         sdhci_set_clock(host, ios->clock);
1204
1205         if (ios->power_mode == MMC_POWER_OFF)
1206                 sdhci_set_power(host, -1);
1207         else
1208                 sdhci_set_power(host, ios->vdd);
1209
1210         if (host->ops->platform_send_init_74_clocks)
1211                 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1212
1213         /*
1214          * If your platform has 8-bit width support but is not a v3 controller,
1215          * or if it requires special setup code, you should implement that in
1216          * platform_8bit_width().
1217          */
1218         if (host->ops->platform_8bit_width)
1219                 host->ops->platform_8bit_width(host, ios->bus_width);
1220         else {
1221                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1222                 if (ios->bus_width == MMC_BUS_WIDTH_8) {
1223                         ctrl &= ~SDHCI_CTRL_4BITBUS;
1224                         if (host->version >= SDHCI_SPEC_300)
1225                                 ctrl |= SDHCI_CTRL_8BITBUS;
1226                 } else {
1227                         if (host->version >= SDHCI_SPEC_300)
1228                                 ctrl &= ~SDHCI_CTRL_8BITBUS;
1229                         if (ios->bus_width == MMC_BUS_WIDTH_4)
1230                                 ctrl |= SDHCI_CTRL_4BITBUS;
1231                         else
1232                                 ctrl &= ~SDHCI_CTRL_4BITBUS;
1233                 }
1234                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1235         }
1236
1237         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1238
1239         if ((ios->timing == MMC_TIMING_SD_HS ||
1240              ios->timing == MMC_TIMING_MMC_HS)
1241             && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1242                 ctrl |= SDHCI_CTRL_HISPD;
1243         else
1244                 ctrl &= ~SDHCI_CTRL_HISPD;
1245
1246         if (host->version >= SDHCI_SPEC_300) {
1247                 u16 ctrl_2;
1248
1249                 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1250                 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1251                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1252                         /*
1253                          * We only need to set Driver Strength if the
1254                          * preset value enable is not set.
1255                          */
1256                         ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1257                         if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1258                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1259                         else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1260                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1261
1262                         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1263                 } else {
1264                         /*
1265                          * According to SDHC Spec v3.00, if the Preset Value
1266                          * Enable in the Host Control 2 register is set, we
1267                          * need to reset SD Clock Enable before changing High
1268                          * Speed Enable to avoid generating clock gliches.
1269                          */
1270                         u16 clk;
1271                         unsigned int clock;
1272
1273                         /* Reset SD Clock Enable */
1274                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1275                         clk &= ~SDHCI_CLOCK_CARD_EN;
1276                         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1277
1278                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1279
1280                         /* Re-enable SD Clock */
1281                         clock = host->clock;
1282                         host->clock = 0;
1283                         sdhci_set_clock(host, clock);
1284                 }
1285         } else
1286                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1287
1288         /*
1289          * Some (ENE) controllers go apeshit on some ios operation,
1290          * signalling timeout and CRC errors even on CMD0. Resetting
1291          * it on each ios seems to solve the problem.
1292          */
1293         if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1294                 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1295
1296 out:
1297         mmiowb();
1298         spin_unlock_irqrestore(&host->lock, flags);
1299 }
1300
1301 static int check_ro(struct sdhci_host *host)
1302 {
1303         unsigned long flags;
1304         int is_readonly;
1305
1306         spin_lock_irqsave(&host->lock, flags);
1307
1308         if (host->flags & SDHCI_DEVICE_DEAD)
1309                 is_readonly = 0;
1310         else if (host->ops->get_ro)
1311                 is_readonly = host->ops->get_ro(host);
1312         else
1313                 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1314                                 & SDHCI_WRITE_PROTECT);
1315
1316         spin_unlock_irqrestore(&host->lock, flags);
1317
1318         /* This quirk needs to be replaced by a callback-function later */
1319         return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1320                 !is_readonly : is_readonly;
1321 }
1322
1323 #define SAMPLE_COUNT    5
1324
1325 static int sdhci_get_ro(struct mmc_host *mmc)
1326 {
1327         struct sdhci_host *host;
1328         int i, ro_count;
1329
1330         host = mmc_priv(mmc);
1331
1332         if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1333                 return check_ro(host);
1334
1335         ro_count = 0;
1336         for (i = 0; i < SAMPLE_COUNT; i++) {
1337                 if (check_ro(host)) {
1338                         if (++ro_count > SAMPLE_COUNT / 2)
1339                                 return 1;
1340                 }
1341                 msleep(30);
1342         }
1343         return 0;
1344 }
1345
1346 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1347 {
1348         struct sdhci_host *host;
1349         unsigned long flags;
1350
1351         host = mmc_priv(mmc);
1352
1353         spin_lock_irqsave(&host->lock, flags);
1354
1355         if (host->flags & SDHCI_DEVICE_DEAD)
1356                 goto out;
1357
1358         if (enable)
1359                 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1360         else
1361                 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1362 out:
1363         mmiowb();
1364
1365         spin_unlock_irqrestore(&host->lock, flags);
1366 }
1367
1368 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1369         struct mmc_ios *ios)
1370 {
1371         struct sdhci_host *host;
1372         u8 pwr;
1373         u16 clk, ctrl;
1374         u32 present_state;
1375
1376         host = mmc_priv(mmc);
1377
1378         /*
1379          * Signal Voltage Switching is only applicable for Host Controllers
1380          * v3.00 and above.
1381          */
1382         if (host->version < SDHCI_SPEC_300)
1383                 return 0;
1384
1385         /*
1386          * We first check whether the request is to set signalling voltage
1387          * to 3.3V. If so, we change the voltage to 3.3V and return quickly.
1388          */
1389         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1390         if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
1391                 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1392                 ctrl &= ~SDHCI_CTRL_VDD_180;
1393                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1394
1395                 /* Wait for 5ms */
1396                 usleep_range(5000, 5500);
1397
1398                 /* 3.3V regulator output should be stable within 5 ms */
1399                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1400                 if (!(ctrl & SDHCI_CTRL_VDD_180))
1401                         return 0;
1402                 else {
1403                         printk(KERN_INFO DRIVER_NAME ": Switching to 3.3V "
1404                                 "signalling voltage failed\n");
1405                         return -EIO;
1406                 }
1407         } else if (!(ctrl & SDHCI_CTRL_VDD_180) &&
1408                   (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)) {
1409                 /* Stop SDCLK */
1410                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1411                 clk &= ~SDHCI_CLOCK_CARD_EN;
1412                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1413
1414                 /* Check whether DAT[3:0] is 0000 */
1415                 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1416                 if (!((present_state & SDHCI_DATA_LVL_MASK) >>
1417                        SDHCI_DATA_LVL_SHIFT)) {
1418                         /*
1419                          * Enable 1.8V Signal Enable in the Host Control2
1420                          * register
1421                          */
1422                         ctrl |= SDHCI_CTRL_VDD_180;
1423                         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1424
1425                         /* Wait for 5ms */
1426                         usleep_range(5000, 5500);
1427
1428                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1429                         if (ctrl & SDHCI_CTRL_VDD_180) {
1430                                 /* Provide SDCLK again and wait for 1ms*/
1431                                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1432                                 clk |= SDHCI_CLOCK_CARD_EN;
1433                                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1434                                 usleep_range(1000, 1500);
1435
1436                                 /*
1437                                  * If DAT[3:0] level is 1111b, then the card
1438                                  * was successfully switched to 1.8V signaling.
1439                                  */
1440                                 present_state = sdhci_readl(host,
1441                                                         SDHCI_PRESENT_STATE);
1442                                 if ((present_state & SDHCI_DATA_LVL_MASK) ==
1443                                      SDHCI_DATA_LVL_MASK)
1444                                         return 0;
1445                         }
1446                 }
1447
1448                 /*
1449                  * If we are here, that means the switch to 1.8V signaling
1450                  * failed. We power cycle the card, and retry initialization
1451                  * sequence by setting S18R to 0.
1452                  */
1453                 pwr = sdhci_readb(host, SDHCI_POWER_CONTROL);
1454                 pwr &= ~SDHCI_POWER_ON;
1455                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1456
1457                 /* Wait for 1ms as per the spec */
1458                 usleep_range(1000, 1500);
1459                 pwr |= SDHCI_POWER_ON;
1460                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1461
1462                 printk(KERN_INFO DRIVER_NAME ": Switching to 1.8V signalling "
1463                         "voltage failed, retrying with S18R set to 0\n");
1464                 return -EAGAIN;
1465         } else
1466                 /* No signal voltage switch required */
1467                 return 0;
1468 }
1469
1470 static const struct mmc_host_ops sdhci_ops = {
1471         .request        = sdhci_request,
1472         .set_ios        = sdhci_set_ios,
1473         .get_ro         = sdhci_get_ro,
1474         .enable_sdio_irq = sdhci_enable_sdio_irq,
1475         .start_signal_voltage_switch    = sdhci_start_signal_voltage_switch,
1476 };
1477
1478 /*****************************************************************************\
1479  *                                                                           *
1480  * Tasklets                                                                  *
1481  *                                                                           *
1482 \*****************************************************************************/
1483
1484 static void sdhci_tasklet_card(unsigned long param)
1485 {
1486         struct sdhci_host *host;
1487         unsigned long flags;
1488
1489         host = (struct sdhci_host*)param;
1490
1491         spin_lock_irqsave(&host->lock, flags);
1492
1493         if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
1494                 if (host->mrq) {
1495                         printk(KERN_ERR "%s: Card removed during transfer!\n",
1496                                 mmc_hostname(host->mmc));
1497                         printk(KERN_ERR "%s: Resetting controller.\n",
1498                                 mmc_hostname(host->mmc));
1499
1500                         sdhci_reset(host, SDHCI_RESET_CMD);
1501                         sdhci_reset(host, SDHCI_RESET_DATA);
1502
1503                         host->mrq->cmd->error = -ENOMEDIUM;
1504                         tasklet_schedule(&host->finish_tasklet);
1505                 }
1506         }
1507
1508         spin_unlock_irqrestore(&host->lock, flags);
1509
1510         mmc_detect_change(host->mmc, msecs_to_jiffies(200));
1511 }
1512
1513 static void sdhci_tasklet_finish(unsigned long param)
1514 {
1515         struct sdhci_host *host;
1516         unsigned long flags;
1517         struct mmc_request *mrq;
1518
1519         host = (struct sdhci_host*)param;
1520
1521         /*
1522          * If this tasklet gets rescheduled while running, it will
1523          * be run again afterwards but without any active request.
1524          */
1525         if (!host->mrq)
1526                 return;
1527
1528         spin_lock_irqsave(&host->lock, flags);
1529
1530         del_timer(&host->timer);
1531
1532         mrq = host->mrq;
1533
1534         /*
1535          * The controller needs a reset of internal state machines
1536          * upon error conditions.
1537          */
1538         if (!(host->flags & SDHCI_DEVICE_DEAD) &&
1539             ((mrq->cmd && mrq->cmd->error) ||
1540                  (mrq->data && (mrq->data->error ||
1541                   (mrq->data->stop && mrq->data->stop->error))) ||
1542                    (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
1543
1544                 /* Some controllers need this kick or reset won't work here */
1545                 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
1546                         unsigned int clock;
1547
1548                         /* This is to force an update */
1549                         clock = host->clock;
1550                         host->clock = 0;
1551                         sdhci_set_clock(host, clock);
1552                 }
1553
1554                 /* Spec says we should do both at the same time, but Ricoh
1555                    controllers do not like that. */
1556                 sdhci_reset(host, SDHCI_RESET_CMD);
1557                 sdhci_reset(host, SDHCI_RESET_DATA);
1558         }
1559
1560         host->mrq = NULL;
1561         host->cmd = NULL;
1562         host->data = NULL;
1563
1564 #ifndef SDHCI_USE_LEDS_CLASS
1565         sdhci_deactivate_led(host);
1566 #endif
1567
1568         mmiowb();
1569         spin_unlock_irqrestore(&host->lock, flags);
1570
1571         mmc_request_done(host->mmc, mrq);
1572 }
1573
1574 static void sdhci_timeout_timer(unsigned long data)
1575 {
1576         struct sdhci_host *host;
1577         unsigned long flags;
1578
1579         host = (struct sdhci_host*)data;
1580
1581         spin_lock_irqsave(&host->lock, flags);
1582
1583         if (host->mrq) {
1584                 printk(KERN_ERR "%s: Timeout waiting for hardware "
1585                         "interrupt.\n", mmc_hostname(host->mmc));
1586                 sdhci_dumpregs(host);
1587
1588                 if (host->data) {
1589                         host->data->error = -ETIMEDOUT;
1590                         sdhci_finish_data(host);
1591                 } else {
1592                         if (host->cmd)
1593                                 host->cmd->error = -ETIMEDOUT;
1594                         else
1595                                 host->mrq->cmd->error = -ETIMEDOUT;
1596
1597                         tasklet_schedule(&host->finish_tasklet);
1598                 }
1599         }
1600
1601         mmiowb();
1602         spin_unlock_irqrestore(&host->lock, flags);
1603 }
1604
1605 /*****************************************************************************\
1606  *                                                                           *
1607  * Interrupt handling                                                        *
1608  *                                                                           *
1609 \*****************************************************************************/
1610
1611 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
1612 {
1613         BUG_ON(intmask == 0);
1614
1615         if (!host->cmd) {
1616                 printk(KERN_ERR "%s: Got command interrupt 0x%08x even "
1617                         "though no command operation was in progress.\n",
1618                         mmc_hostname(host->mmc), (unsigned)intmask);
1619                 sdhci_dumpregs(host);
1620                 return;
1621         }
1622
1623         if (intmask & SDHCI_INT_TIMEOUT)
1624                 host->cmd->error = -ETIMEDOUT;
1625         else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
1626                         SDHCI_INT_INDEX))
1627                 host->cmd->error = -EILSEQ;
1628
1629         if (host->cmd->error) {
1630                 tasklet_schedule(&host->finish_tasklet);
1631                 return;
1632         }
1633
1634         /*
1635          * The host can send and interrupt when the busy state has
1636          * ended, allowing us to wait without wasting CPU cycles.
1637          * Unfortunately this is overloaded on the "data complete"
1638          * interrupt, so we need to take some care when handling
1639          * it.
1640          *
1641          * Note: The 1.0 specification is a bit ambiguous about this
1642          *       feature so there might be some problems with older
1643          *       controllers.
1644          */
1645         if (host->cmd->flags & MMC_RSP_BUSY) {
1646                 if (host->cmd->data)
1647                         DBG("Cannot wait for busy signal when also "
1648                                 "doing a data transfer");
1649                 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
1650                         return;
1651
1652                 /* The controller does not support the end-of-busy IRQ,
1653                  * fall through and take the SDHCI_INT_RESPONSE */
1654         }
1655
1656         if (intmask & SDHCI_INT_RESPONSE)
1657                 sdhci_finish_command(host);
1658 }
1659
1660 #ifdef CONFIG_MMC_DEBUG
1661 static void sdhci_show_adma_error(struct sdhci_host *host)
1662 {
1663         const char *name = mmc_hostname(host->mmc);
1664         u8 *desc = host->adma_desc;
1665         __le32 *dma;
1666         __le16 *len;
1667         u8 attr;
1668
1669         sdhci_dumpregs(host);
1670
1671         while (true) {
1672                 dma = (__le32 *)(desc + 4);
1673                 len = (__le16 *)(desc + 2);
1674                 attr = *desc;
1675
1676                 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
1677                     name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
1678
1679                 desc += 8;
1680
1681                 if (attr & 2)
1682                         break;
1683         }
1684 }
1685 #else
1686 static void sdhci_show_adma_error(struct sdhci_host *host) { }
1687 #endif
1688
1689 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
1690 {
1691         BUG_ON(intmask == 0);
1692
1693         if (!host->data) {
1694                 /*
1695                  * The "data complete" interrupt is also used to
1696                  * indicate that a busy state has ended. See comment
1697                  * above in sdhci_cmd_irq().
1698                  */
1699                 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
1700                         if (intmask & SDHCI_INT_DATA_END) {
1701                                 sdhci_finish_command(host);
1702                                 return;
1703                         }
1704                 }
1705
1706                 printk(KERN_ERR "%s: Got data interrupt 0x%08x even "
1707                         "though no data operation was in progress.\n",
1708                         mmc_hostname(host->mmc), (unsigned)intmask);
1709                 sdhci_dumpregs(host);
1710
1711                 return;
1712         }
1713
1714         if (intmask & SDHCI_INT_DATA_TIMEOUT)
1715                 host->data->error = -ETIMEDOUT;
1716         else if (intmask & SDHCI_INT_DATA_END_BIT)
1717                 host->data->error = -EILSEQ;
1718         else if ((intmask & SDHCI_INT_DATA_CRC) &&
1719                 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
1720                         != MMC_BUS_TEST_R)
1721                 host->data->error = -EILSEQ;
1722         else if (intmask & SDHCI_INT_ADMA_ERROR) {
1723                 printk(KERN_ERR "%s: ADMA error\n", mmc_hostname(host->mmc));
1724                 sdhci_show_adma_error(host);
1725                 host->data->error = -EIO;
1726         }
1727
1728         if (host->data->error)
1729                 sdhci_finish_data(host);
1730         else {
1731                 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
1732                         sdhci_transfer_pio(host);
1733
1734                 /*
1735                  * We currently don't do anything fancy with DMA
1736                  * boundaries, but as we can't disable the feature
1737                  * we need to at least restart the transfer.
1738                  *
1739                  * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
1740                  * should return a valid address to continue from, but as
1741                  * some controllers are faulty, don't trust them.
1742                  */
1743                 if (intmask & SDHCI_INT_DMA_END) {
1744                         u32 dmastart, dmanow;
1745                         dmastart = sg_dma_address(host->data->sg);
1746                         dmanow = dmastart + host->data->bytes_xfered;
1747                         /*
1748                          * Force update to the next DMA block boundary.
1749                          */
1750                         dmanow = (dmanow &
1751                                 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
1752                                 SDHCI_DEFAULT_BOUNDARY_SIZE;
1753                         host->data->bytes_xfered = dmanow - dmastart;
1754                         DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
1755                                 " next 0x%08x\n",
1756                                 mmc_hostname(host->mmc), dmastart,
1757                                 host->data->bytes_xfered, dmanow);
1758                         sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
1759                 }
1760
1761                 if (intmask & SDHCI_INT_DATA_END) {
1762                         if (host->cmd) {
1763                                 /*
1764                                  * Data managed to finish before the
1765                                  * command completed. Make sure we do
1766                                  * things in the proper order.
1767                                  */
1768                                 host->data_early = 1;
1769                         } else {
1770                                 sdhci_finish_data(host);
1771                         }
1772                 }
1773         }
1774 }
1775
1776 static irqreturn_t sdhci_irq(int irq, void *dev_id)
1777 {
1778         irqreturn_t result;
1779         struct sdhci_host* host = dev_id;
1780         u32 intmask;
1781         int cardint = 0;
1782
1783         spin_lock(&host->lock);
1784
1785         intmask = sdhci_readl(host, SDHCI_INT_STATUS);
1786
1787         if (!intmask || intmask == 0xffffffff) {
1788                 result = IRQ_NONE;
1789                 goto out;
1790         }
1791
1792         DBG("*** %s got interrupt: 0x%08x\n",
1793                 mmc_hostname(host->mmc), intmask);
1794
1795         if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
1796                 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
1797                         SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
1798                 tasklet_schedule(&host->card_tasklet);
1799         }
1800
1801         intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
1802
1803         if (intmask & SDHCI_INT_CMD_MASK) {
1804                 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
1805                         SDHCI_INT_STATUS);
1806                 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
1807         }
1808
1809         if (intmask & SDHCI_INT_DATA_MASK) {
1810                 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
1811                         SDHCI_INT_STATUS);
1812                 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
1813         }
1814
1815         intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1816
1817         intmask &= ~SDHCI_INT_ERROR;
1818
1819         if (intmask & SDHCI_INT_BUS_POWER) {
1820                 printk(KERN_ERR "%s: Card is consuming too much power!\n",
1821                         mmc_hostname(host->mmc));
1822                 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
1823         }
1824
1825         intmask &= ~SDHCI_INT_BUS_POWER;
1826
1827         if (intmask & SDHCI_INT_CARD_INT)
1828                 cardint = 1;
1829
1830         intmask &= ~SDHCI_INT_CARD_INT;
1831
1832         if (intmask) {
1833                 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
1834                         mmc_hostname(host->mmc), intmask);
1835                 sdhci_dumpregs(host);
1836
1837                 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
1838         }
1839
1840         result = IRQ_HANDLED;
1841
1842         mmiowb();
1843 out:
1844         spin_unlock(&host->lock);
1845
1846         /*
1847          * We have to delay this as it calls back into the driver.
1848          */
1849         if (cardint)
1850                 mmc_signal_sdio_irq(host->mmc);
1851
1852         return result;
1853 }
1854
1855 /*****************************************************************************\
1856  *                                                                           *
1857  * Suspend/resume                                                            *
1858  *                                                                           *
1859 \*****************************************************************************/
1860
1861 #ifdef CONFIG_PM
1862
1863 int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state)
1864 {
1865         int ret;
1866
1867         sdhci_disable_card_detection(host);
1868
1869         ret = mmc_suspend_host(host->mmc);
1870         if (ret)
1871                 return ret;
1872
1873         free_irq(host->irq, host);
1874
1875         if (host->vmmc)
1876                 ret = regulator_disable(host->vmmc);
1877
1878         return ret;
1879 }
1880
1881 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
1882
1883 int sdhci_resume_host(struct sdhci_host *host)
1884 {
1885         int ret;
1886
1887         if (host->vmmc) {
1888                 int ret = regulator_enable(host->vmmc);
1889                 if (ret)
1890                         return ret;
1891         }
1892
1893
1894         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
1895                 if (host->ops->enable_dma)
1896                         host->ops->enable_dma(host);
1897         }
1898
1899         ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
1900                           mmc_hostname(host->mmc), host);
1901         if (ret)
1902                 return ret;
1903
1904         sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
1905         mmiowb();
1906
1907         ret = mmc_resume_host(host->mmc);
1908         sdhci_enable_card_detection(host);
1909
1910         return ret;
1911 }
1912
1913 EXPORT_SYMBOL_GPL(sdhci_resume_host);
1914
1915 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
1916 {
1917         u8 val;
1918         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
1919         val |= SDHCI_WAKE_ON_INT;
1920         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
1921 }
1922
1923 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
1924
1925 #endif /* CONFIG_PM */
1926
1927 /*****************************************************************************\
1928  *                                                                           *
1929  * Device allocation/registration                                            *
1930  *                                                                           *
1931 \*****************************************************************************/
1932
1933 struct sdhci_host *sdhci_alloc_host(struct device *dev,
1934         size_t priv_size)
1935 {
1936         struct mmc_host *mmc;
1937         struct sdhci_host *host;
1938
1939         WARN_ON(dev == NULL);
1940
1941         mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
1942         if (!mmc)
1943                 return ERR_PTR(-ENOMEM);
1944
1945         host = mmc_priv(mmc);
1946         host->mmc = mmc;
1947
1948         return host;
1949 }
1950
1951 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
1952
1953 int sdhci_add_host(struct sdhci_host *host)
1954 {
1955         struct mmc_host *mmc;
1956         u32 caps[2];
1957         u32 max_current_caps;
1958         unsigned int ocr_avail;
1959         int ret;
1960
1961         WARN_ON(host == NULL);
1962         if (host == NULL)
1963                 return -EINVAL;
1964
1965         mmc = host->mmc;
1966
1967         if (debug_quirks)
1968                 host->quirks = debug_quirks;
1969
1970         sdhci_reset(host, SDHCI_RESET_ALL);
1971
1972         host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
1973         host->version = (host->version & SDHCI_SPEC_VER_MASK)
1974                                 >> SDHCI_SPEC_VER_SHIFT;
1975         if (host->version > SDHCI_SPEC_300) {
1976                 printk(KERN_ERR "%s: Unknown controller version (%d). "
1977                         "You may experience problems.\n", mmc_hostname(mmc),
1978                         host->version);
1979         }
1980
1981         caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
1982                 sdhci_readl(host, SDHCI_CAPABILITIES);
1983
1984         caps[1] = (host->version >= SDHCI_SPEC_300) ?
1985                 sdhci_readl(host, SDHCI_CAPABILITIES_1) : 0;
1986
1987         if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
1988                 host->flags |= SDHCI_USE_SDMA;
1989         else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
1990                 DBG("Controller doesn't have SDMA capability\n");
1991         else
1992                 host->flags |= SDHCI_USE_SDMA;
1993
1994         if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
1995                 (host->flags & SDHCI_USE_SDMA)) {
1996                 DBG("Disabling DMA as it is marked broken\n");
1997                 host->flags &= ~SDHCI_USE_SDMA;
1998         }
1999
2000         if ((host->version >= SDHCI_SPEC_200) &&
2001                 (caps[0] & SDHCI_CAN_DO_ADMA2))
2002                 host->flags |= SDHCI_USE_ADMA;
2003
2004         if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2005                 (host->flags & SDHCI_USE_ADMA)) {
2006                 DBG("Disabling ADMA as it is marked broken\n");
2007                 host->flags &= ~SDHCI_USE_ADMA;
2008         }
2009
2010         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2011                 if (host->ops->enable_dma) {
2012                         if (host->ops->enable_dma(host)) {
2013                                 printk(KERN_WARNING "%s: No suitable DMA "
2014                                         "available. Falling back to PIO.\n",
2015                                         mmc_hostname(mmc));
2016                                 host->flags &=
2017                                         ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2018                         }
2019                 }
2020         }
2021
2022         if (host->flags & SDHCI_USE_ADMA) {
2023                 /*
2024                  * We need to allocate descriptors for all sg entries
2025                  * (128) and potentially one alignment transfer for
2026                  * each of those entries.
2027                  */
2028                 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
2029                 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2030                 if (!host->adma_desc || !host->align_buffer) {
2031                         kfree(host->adma_desc);
2032                         kfree(host->align_buffer);
2033                         printk(KERN_WARNING "%s: Unable to allocate ADMA "
2034                                 "buffers. Falling back to standard DMA.\n",
2035                                 mmc_hostname(mmc));
2036                         host->flags &= ~SDHCI_USE_ADMA;
2037                 }
2038         }
2039
2040         /*
2041          * If we use DMA, then it's up to the caller to set the DMA
2042          * mask, but PIO does not need the hw shim so we set a new
2043          * mask here in that case.
2044          */
2045         if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
2046                 host->dma_mask = DMA_BIT_MASK(64);
2047                 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
2048         }
2049
2050         if (host->version >= SDHCI_SPEC_300)
2051                 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
2052                         >> SDHCI_CLOCK_BASE_SHIFT;
2053         else
2054                 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
2055                         >> SDHCI_CLOCK_BASE_SHIFT;
2056
2057         host->max_clk *= 1000000;
2058         if (host->max_clk == 0 || host->quirks &
2059                         SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
2060                 if (!host->ops->get_max_clock) {
2061                         printk(KERN_ERR
2062                                "%s: Hardware doesn't specify base clock "
2063                                "frequency.\n", mmc_hostname(mmc));
2064                         return -ENODEV;
2065                 }
2066                 host->max_clk = host->ops->get_max_clock(host);
2067         }
2068
2069         host->timeout_clk =
2070                 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
2071         if (host->timeout_clk == 0) {
2072                 if (host->ops->get_timeout_clock) {
2073                         host->timeout_clk = host->ops->get_timeout_clock(host);
2074                 } else if (!(host->quirks &
2075                                 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
2076                         printk(KERN_ERR
2077                                "%s: Hardware doesn't specify timeout clock "
2078                                "frequency.\n", mmc_hostname(mmc));
2079                         return -ENODEV;
2080                 }
2081         }
2082         if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
2083                 host->timeout_clk *= 1000;
2084
2085         /*
2086          * Set host parameters.
2087          */
2088         mmc->ops = &sdhci_ops;
2089         if (host->ops->get_min_clock)
2090                 mmc->f_min = host->ops->get_min_clock(host);
2091         else if (host->version >= SDHCI_SPEC_300)
2092                 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2093         else
2094                 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
2095
2096         mmc->f_max = host->max_clk;
2097         mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE;
2098
2099         /*
2100          * A controller may support 8-bit width, but the board itself
2101          * might not have the pins brought out.  Boards that support
2102          * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
2103          * their platform code before calling sdhci_add_host(), and we
2104          * won't assume 8-bit width for hosts without that CAP.
2105          */
2106         if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
2107                 mmc->caps |= MMC_CAP_4_BIT_DATA;
2108
2109         if (caps[0] & SDHCI_CAN_DO_HISPD)
2110                 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
2111
2112         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
2113             mmc_card_is_removable(mmc))
2114                 mmc->caps |= MMC_CAP_NEEDS_POLL;
2115
2116         /* UHS-I mode(s) supported by the host controller. */
2117         if (host->version >= SDHCI_SPEC_300)
2118                 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
2119
2120         /* SDR104 supports also implies SDR50 support */
2121         if (caps[1] & SDHCI_SUPPORT_SDR104)
2122                 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
2123         else if (caps[1] & SDHCI_SUPPORT_SDR50)
2124                 mmc->caps |= MMC_CAP_UHS_SDR50;
2125
2126         if (caps[1] & SDHCI_SUPPORT_DDR50)
2127                 mmc->caps |= MMC_CAP_UHS_DDR50;
2128
2129         /* Driver Type(s) (A, C, D) supported by the host */
2130         if (caps[1] & SDHCI_DRIVER_TYPE_A)
2131                 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
2132         if (caps[1] & SDHCI_DRIVER_TYPE_C)
2133                 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
2134         if (caps[1] & SDHCI_DRIVER_TYPE_D)
2135                 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
2136
2137         ocr_avail = 0;
2138         /*
2139          * According to SD Host Controller spec v3.00, if the Host System
2140          * can afford more than 150mA, Host Driver should set XPC to 1. Also
2141          * the value is meaningful only if Voltage Support in the Capabilities
2142          * register is set. The actual current value is 4 times the register
2143          * value.
2144          */
2145         max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
2146
2147         if (caps[0] & SDHCI_CAN_VDD_330) {
2148                 int max_current_330;
2149
2150                 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
2151
2152                 max_current_330 = ((max_current_caps &
2153                                    SDHCI_MAX_CURRENT_330_MASK) >>
2154                                    SDHCI_MAX_CURRENT_330_SHIFT) *
2155                                    SDHCI_MAX_CURRENT_MULTIPLIER;
2156
2157                 if (max_current_330 > 150)
2158                         mmc->caps |= MMC_CAP_SET_XPC_330;
2159         }
2160         if (caps[0] & SDHCI_CAN_VDD_300) {
2161                 int max_current_300;
2162
2163                 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
2164
2165                 max_current_300 = ((max_current_caps &
2166                                    SDHCI_MAX_CURRENT_300_MASK) >>
2167                                    SDHCI_MAX_CURRENT_300_SHIFT) *
2168                                    SDHCI_MAX_CURRENT_MULTIPLIER;
2169
2170                 if (max_current_300 > 150)
2171                         mmc->caps |= MMC_CAP_SET_XPC_300;
2172         }
2173         if (caps[0] & SDHCI_CAN_VDD_180) {
2174                 int max_current_180;
2175
2176                 ocr_avail |= MMC_VDD_165_195;
2177
2178                 max_current_180 = ((max_current_caps &
2179                                    SDHCI_MAX_CURRENT_180_MASK) >>
2180                                    SDHCI_MAX_CURRENT_180_SHIFT) *
2181                                    SDHCI_MAX_CURRENT_MULTIPLIER;
2182
2183                 if (max_current_180 > 150)
2184                         mmc->caps |= MMC_CAP_SET_XPC_180;
2185         }
2186
2187         mmc->ocr_avail = ocr_avail;
2188         mmc->ocr_avail_sdio = ocr_avail;
2189         if (host->ocr_avail_sdio)
2190                 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
2191         mmc->ocr_avail_sd = ocr_avail;
2192         if (host->ocr_avail_sd)
2193                 mmc->ocr_avail_sd &= host->ocr_avail_sd;
2194         else /* normal SD controllers don't support 1.8V */
2195                 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
2196         mmc->ocr_avail_mmc = ocr_avail;
2197         if (host->ocr_avail_mmc)
2198                 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
2199
2200         if (mmc->ocr_avail == 0) {
2201                 printk(KERN_ERR "%s: Hardware doesn't report any "
2202                         "support voltages.\n", mmc_hostname(mmc));
2203                 return -ENODEV;
2204         }
2205
2206         spin_lock_init(&host->lock);
2207
2208         /*
2209          * Maximum number of segments. Depends on if the hardware
2210          * can do scatter/gather or not.
2211          */
2212         if (host->flags & SDHCI_USE_ADMA)
2213                 mmc->max_segs = 128;
2214         else if (host->flags & SDHCI_USE_SDMA)
2215                 mmc->max_segs = 1;
2216         else /* PIO */
2217                 mmc->max_segs = 128;
2218
2219         /*
2220          * Maximum number of sectors in one transfer. Limited by DMA boundary
2221          * size (512KiB).
2222          */
2223         mmc->max_req_size = 524288;
2224
2225         /*
2226          * Maximum segment size. Could be one segment with the maximum number
2227          * of bytes. When doing hardware scatter/gather, each entry cannot
2228          * be larger than 64 KiB though.
2229          */
2230         if (host->flags & SDHCI_USE_ADMA) {
2231                 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
2232                         mmc->max_seg_size = 65535;
2233                 else
2234                         mmc->max_seg_size = 65536;
2235         } else {
2236                 mmc->max_seg_size = mmc->max_req_size;
2237         }
2238
2239         /*
2240          * Maximum block size. This varies from controller to controller and
2241          * is specified in the capabilities register.
2242          */
2243         if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
2244                 mmc->max_blk_size = 2;
2245         } else {
2246                 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
2247                                 SDHCI_MAX_BLOCK_SHIFT;
2248                 if (mmc->max_blk_size >= 3) {
2249                         printk(KERN_WARNING "%s: Invalid maximum block size, "
2250                                 "assuming 512 bytes\n", mmc_hostname(mmc));
2251                         mmc->max_blk_size = 0;
2252                 }
2253         }
2254
2255         mmc->max_blk_size = 512 << mmc->max_blk_size;
2256
2257         /*
2258          * Maximum block count.
2259          */
2260         mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
2261
2262         /*
2263          * Init tasklets.
2264          */
2265         tasklet_init(&host->card_tasklet,
2266                 sdhci_tasklet_card, (unsigned long)host);
2267         tasklet_init(&host->finish_tasklet,
2268                 sdhci_tasklet_finish, (unsigned long)host);
2269
2270         setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
2271
2272         ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
2273                 mmc_hostname(mmc), host);
2274         if (ret)
2275                 goto untasklet;
2276
2277         host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
2278         if (IS_ERR(host->vmmc)) {
2279                 printk(KERN_INFO "%s: no vmmc regulator found\n", mmc_hostname(mmc));
2280                 host->vmmc = NULL;
2281         } else {
2282                 regulator_enable(host->vmmc);
2283         }
2284
2285         sdhci_init(host, 0);
2286
2287 #ifdef CONFIG_MMC_DEBUG
2288         sdhci_dumpregs(host);
2289 #endif
2290
2291 #ifdef SDHCI_USE_LEDS_CLASS
2292         snprintf(host->led_name, sizeof(host->led_name),
2293                 "%s::", mmc_hostname(mmc));
2294         host->led.name = host->led_name;
2295         host->led.brightness = LED_OFF;
2296         host->led.default_trigger = mmc_hostname(mmc);
2297         host->led.brightness_set = sdhci_led_control;
2298
2299         ret = led_classdev_register(mmc_dev(mmc), &host->led);
2300         if (ret)
2301                 goto reset;
2302 #endif
2303
2304         mmiowb();
2305
2306         mmc_add_host(mmc);
2307
2308         printk(KERN_INFO "%s: SDHCI controller on %s [%s] using %s\n",
2309                 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
2310                 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
2311                 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
2312
2313         sdhci_enable_card_detection(host);
2314
2315         return 0;
2316
2317 #ifdef SDHCI_USE_LEDS_CLASS
2318 reset:
2319         sdhci_reset(host, SDHCI_RESET_ALL);
2320         free_irq(host->irq, host);
2321 #endif
2322 untasklet:
2323         tasklet_kill(&host->card_tasklet);
2324         tasklet_kill(&host->finish_tasklet);
2325
2326         return ret;
2327 }
2328
2329 EXPORT_SYMBOL_GPL(sdhci_add_host);
2330
2331 void sdhci_remove_host(struct sdhci_host *host, int dead)
2332 {
2333         unsigned long flags;
2334
2335         if (dead) {
2336                 spin_lock_irqsave(&host->lock, flags);
2337
2338                 host->flags |= SDHCI_DEVICE_DEAD;
2339
2340                 if (host->mrq) {
2341                         printk(KERN_ERR "%s: Controller removed during "
2342                                 " transfer!\n", mmc_hostname(host->mmc));
2343
2344                         host->mrq->cmd->error = -ENOMEDIUM;
2345                         tasklet_schedule(&host->finish_tasklet);
2346                 }
2347
2348                 spin_unlock_irqrestore(&host->lock, flags);
2349         }
2350
2351         sdhci_disable_card_detection(host);
2352
2353         mmc_remove_host(host->mmc);
2354
2355 #ifdef SDHCI_USE_LEDS_CLASS
2356         led_classdev_unregister(&host->led);
2357 #endif
2358
2359         if (!dead)
2360                 sdhci_reset(host, SDHCI_RESET_ALL);
2361
2362         free_irq(host->irq, host);
2363
2364         del_timer_sync(&host->timer);
2365
2366         tasklet_kill(&host->card_tasklet);
2367         tasklet_kill(&host->finish_tasklet);
2368
2369         if (host->vmmc) {
2370                 regulator_disable(host->vmmc);
2371                 regulator_put(host->vmmc);
2372         }
2373
2374         kfree(host->adma_desc);
2375         kfree(host->align_buffer);
2376
2377         host->adma_desc = NULL;
2378         host->align_buffer = NULL;
2379 }
2380
2381 EXPORT_SYMBOL_GPL(sdhci_remove_host);
2382
2383 void sdhci_free_host(struct sdhci_host *host)
2384 {
2385         mmc_free_host(host->mmc);
2386 }
2387
2388 EXPORT_SYMBOL_GPL(sdhci_free_host);
2389
2390 /*****************************************************************************\
2391  *                                                                           *
2392  * Driver init/exit                                                          *
2393  *                                                                           *
2394 \*****************************************************************************/
2395
2396 static int __init sdhci_drv_init(void)
2397 {
2398         printk(KERN_INFO DRIVER_NAME
2399                 ": Secure Digital Host Controller Interface driver\n");
2400         printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
2401
2402         return 0;
2403 }
2404
2405 static void __exit sdhci_drv_exit(void)
2406 {
2407 }
2408
2409 module_init(sdhci_drv_init);
2410 module_exit(sdhci_drv_exit);
2411
2412 module_param(debug_quirks, uint, 0444);
2413
2414 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
2415 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
2416 MODULE_LICENSE("GPL");
2417
2418 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");