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[PATCH] 8139cp - add netpoll support
[linux-2.6.git] / drivers / net / 8139cp.c
blob050d7602bbe9a3888bb50d686b827e626415f263
1 /* 8139cp.c: A Linux PCI Ethernet driver for the RealTek 8139C+ chips. */
2 /*
3 Copyright 2001-2004 Jeff Garzik <jgarzik@pobox.com>
4
5 Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com) [tg3.c]
6 Copyright (C) 2000, 2001 David S. Miller (davem@redhat.com) [sungem.c]
7 Copyright 2001 Manfred Spraul [natsemi.c]
8 Copyright 1999-2001 by Donald Becker. [natsemi.c]
9 Written 1997-2001 by Donald Becker. [8139too.c]
10 Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. [acenic.c]
11
12 This software may be used and distributed according to the terms of
13 the GNU General Public License (GPL), incorporated herein by reference.
14 Drivers based on or derived from this code fall under the GPL and must
15 retain the authorship, copyright and license notice. This file is not
16 a complete program and may only be used when the entire operating
17 system is licensed under the GPL.
18
19 See the file COPYING in this distribution for more information.
20
21 Contributors:
22
23 Wake-on-LAN support - Felipe Damasio <felipewd@terra.com.br>
24 PCI suspend/resume - Felipe Damasio <felipewd@terra.com.br>
25 LinkChg interrupt - Felipe Damasio <felipewd@terra.com.br>
26
27 TODO:
28 * Test Tx checksumming thoroughly
29 * Implement dev->tx_timeout
30
31 Low priority TODO:
32 * Complete reset on PciErr
33 * Consider Rx interrupt mitigation using TimerIntr
34 * Investigate using skb->priority with h/w VLAN priority
35 * Investigate using High Priority Tx Queue with skb->priority
36 * Adjust Rx FIFO threshold and Max Rx DMA burst on Rx FIFO error
37 * Adjust Tx FIFO threshold and Max Tx DMA burst on Tx FIFO error
38 * Implement Tx software interrupt mitigation via
39 Tx descriptor bit
40 * The real minimum of CP_MIN_MTU is 4 bytes. However,
41 for this to be supported, one must(?) turn on packet padding.
42 * Support external MII transceivers (patch available)
43
44 NOTES:
45 * TX checksumming is considered experimental. It is off by
46 default, use ethtool to turn it on.
47
48 */
49
50 #define DRV_NAME "8139cp"
51 #define DRV_VERSION "1.2"
52 #define DRV_RELDATE "Mar 22, 2004"
53
54
55 #include <linux/config.h>
56 #include <linux/module.h>
57 #include <linux/moduleparam.h>
58 #include <linux/kernel.h>
59 #include <linux/compiler.h>
60 #include <linux/netdevice.h>
61 #include <linux/etherdevice.h>
62 #include <linux/init.h>
63 #include <linux/pci.h>
64 #include <linux/delay.h>
65 #include <linux/ethtool.h>
66 #include <linux/mii.h>
67 #include <linux/if_vlan.h>
68 #include <linux/crc32.h>
69 #include <linux/in.h>
70 #include <linux/ip.h>
71 #include <linux/tcp.h>
72 #include <linux/udp.h>
73 #include <linux/cache.h>
74 #include <asm/io.h>
75 #include <asm/irq.h>
76 #include <asm/uaccess.h>
77
78 /* VLAN tagging feature enable/disable */
79 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
80 #define CP_VLAN_TAG_USED 1
81 #define CP_VLAN_TX_TAG(tx_desc,vlan_tag_value) \
82 do { (tx_desc)->opts2 = (vlan_tag_value); } while (0)
83 #else
84 #define CP_VLAN_TAG_USED 0
85 #define CP_VLAN_TX_TAG(tx_desc,vlan_tag_value) \
86 do { (tx_desc)->opts2 = 0; } while (0)
87 #endif
88
89 /* These identify the driver base version and may not be removed. */
90 static char version[] =
91 KERN_INFO DRV_NAME ": 10/100 PCI Ethernet driver v" DRV_VERSION " (" DRV_RELDATE ")\n";
92
93 MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>");
94 MODULE_DESCRIPTION("RealTek RTL-8139C+ series 10/100 PCI Ethernet driver");
95 MODULE_LICENSE("GPL");
96
97 static int debug = -1;
98 module_param(debug, int, 0);
99 MODULE_PARM_DESC (debug, "8139cp: bitmapped message enable number");
100
101 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
102 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
103 static int multicast_filter_limit = 32;
104 module_param(multicast_filter_limit, int, 0);
105 MODULE_PARM_DESC (multicast_filter_limit, "8139cp: maximum number of filtered multicast addresses");
106
107 #define PFX DRV_NAME ": "
108
109 #ifndef TRUE
110 #define FALSE 0
111 #define TRUE (!FALSE)
112 #endif
113
114 #define CP_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
115 NETIF_MSG_PROBE | \
116 NETIF_MSG_LINK)
117 #define CP_NUM_STATS 14 /* struct cp_dma_stats, plus one */
118 #define CP_STATS_SIZE 64 /* size in bytes of DMA stats block */
119 #define CP_REGS_SIZE (0xff + 1)
120 #define CP_REGS_VER 1 /* version 1 */
121 #define CP_RX_RING_SIZE 64
122 #define CP_TX_RING_SIZE 64
123 #define CP_RING_BYTES \
124 ((sizeof(struct cp_desc) * CP_RX_RING_SIZE) + \
125 (sizeof(struct cp_desc) * CP_TX_RING_SIZE) + \
126 CP_STATS_SIZE)
127 #define NEXT_TX(N) (((N) + 1) & (CP_TX_RING_SIZE - 1))
128 #define NEXT_RX(N) (((N) + 1) & (CP_RX_RING_SIZE - 1))
129 #define TX_BUFFS_AVAIL(CP) \
130 (((CP)->tx_tail <= (CP)->tx_head) ? \
131 (CP)->tx_tail + (CP_TX_RING_SIZE - 1) - (CP)->tx_head : \
132 (CP)->tx_tail - (CP)->tx_head - 1)
133
134 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
135 #define RX_OFFSET 2
136 #define CP_INTERNAL_PHY 32
137
138 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
139 #define RX_FIFO_THRESH 5 /* Rx buffer level before first PCI xfer. */
140 #define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 */
141 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
142 #define TX_EARLY_THRESH 256 /* Early Tx threshold, in bytes */
143
144 /* Time in jiffies before concluding the transmitter is hung. */
145 #define TX_TIMEOUT (6*HZ)
146
147 /* hardware minimum and maximum for a single frame's data payload */
148 #define CP_MIN_MTU 60 /* TODO: allow lower, but pad */
149 #define CP_MAX_MTU 4096
150
151 enum {
152 /* NIC register offsets */
153 MAC0 = 0x00, /* Ethernet hardware address. */
154 MAR0 = 0x08, /* Multicast filter. */
155 StatsAddr = 0x10, /* 64-bit start addr of 64-byte DMA stats blk */
156 TxRingAddr = 0x20, /* 64-bit start addr of Tx ring */
157 HiTxRingAddr = 0x28, /* 64-bit start addr of high priority Tx ring */
158 Cmd = 0x37, /* Command register */
159 IntrMask = 0x3C, /* Interrupt mask */
160 IntrStatus = 0x3E, /* Interrupt status */
161 TxConfig = 0x40, /* Tx configuration */
162 ChipVersion = 0x43, /* 8-bit chip version, inside TxConfig */
163 RxConfig = 0x44, /* Rx configuration */
164 RxMissed = 0x4C, /* 24 bits valid, write clears */
165 Cfg9346 = 0x50, /* EEPROM select/control; Cfg reg [un]lock */
166 Config1 = 0x52, /* Config1 */
167 Config3 = 0x59, /* Config3 */
168 Config4 = 0x5A, /* Config4 */
169 MultiIntr = 0x5C, /* Multiple interrupt select */
170 BasicModeCtrl = 0x62, /* MII BMCR */
171 BasicModeStatus = 0x64, /* MII BMSR */
172 NWayAdvert = 0x66, /* MII ADVERTISE */
173 NWayLPAR = 0x68, /* MII LPA */
174 NWayExpansion = 0x6A, /* MII Expansion */
175 Config5 = 0xD8, /* Config5 */
176 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
177 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
178 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
179 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
180 RxRingAddr = 0xE4, /* 64-bit start addr of Rx ring */
181 TxThresh = 0xEC, /* Early Tx threshold */
182 OldRxBufAddr = 0x30, /* DMA address of Rx ring buffer (C mode) */
183 OldTSD0 = 0x10, /* DMA address of first Tx desc (C mode) */
184
185 /* Tx and Rx status descriptors */
186 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
187 RingEnd = (1 << 30), /* End of descriptor ring */
188 FirstFrag = (1 << 29), /* First segment of a packet */
189 LastFrag = (1 << 28), /* Final segment of a packet */
190 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
191 MSSShift = 16, /* MSS value position */
192 MSSMask = 0xfff, /* MSS value: 11 bits */
193 TxError = (1 << 23), /* Tx error summary */
194 RxError = (1 << 20), /* Rx error summary */
195 IPCS = (1 << 18), /* Calculate IP checksum */
196 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
197 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
198 TxVlanTag = (1 << 17), /* Add VLAN tag */
199 RxVlanTagged = (1 << 16), /* Rx VLAN tag available */
200 IPFail = (1 << 15), /* IP checksum failed */
201 UDPFail = (1 << 14), /* UDP/IP checksum failed */
202 TCPFail = (1 << 13), /* TCP/IP checksum failed */
203 NormalTxPoll = (1 << 6), /* One or more normal Tx packets to send */
204 PID1 = (1 << 17), /* 2 protocol id bits: 0==non-IP, */
205 PID0 = (1 << 16), /* 1==UDP/IP, 2==TCP/IP, 3==IP */
206 RxProtoTCP = 1,
207 RxProtoUDP = 2,
208 RxProtoIP = 3,
209 TxFIFOUnder = (1 << 25), /* Tx FIFO underrun */
210 TxOWC = (1 << 22), /* Tx Out-of-window collision */
211 TxLinkFail = (1 << 21), /* Link failed during Tx of packet */
212 TxMaxCol = (1 << 20), /* Tx aborted due to excessive collisions */
213 TxColCntShift = 16, /* Shift, to get 4-bit Tx collision cnt */
214 TxColCntMask = 0x01 | 0x02 | 0x04 | 0x08, /* 4-bit collision count */
215 RxErrFrame = (1 << 27), /* Rx frame alignment error */
216 RxMcast = (1 << 26), /* Rx multicast packet rcv'd */
217 RxErrCRC = (1 << 18), /* Rx CRC error */
218 RxErrRunt = (1 << 19), /* Rx error, packet < 64 bytes */
219 RxErrLong = (1 << 21), /* Rx error, packet > 4096 bytes */
220 RxErrFIFO = (1 << 22), /* Rx error, FIFO overflowed, pkt bad */
221
222 /* StatsAddr register */
223 DumpStats = (1 << 3), /* Begin stats dump */
224
225 /* RxConfig register */
226 RxCfgFIFOShift = 13, /* Shift, to get Rx FIFO thresh value */
227 RxCfgDMAShift = 8, /* Shift, to get Rx Max DMA value */
228 AcceptErr = 0x20, /* Accept packets with CRC errors */
229 AcceptRunt = 0x10, /* Accept runt (<64 bytes) packets */
230 AcceptBroadcast = 0x08, /* Accept broadcast packets */
231 AcceptMulticast = 0x04, /* Accept multicast packets */
232 AcceptMyPhys = 0x02, /* Accept pkts with our MAC as dest */
233 AcceptAllPhys = 0x01, /* Accept all pkts w/ physical dest */
234
235 /* IntrMask / IntrStatus registers */
236 PciErr = (1 << 15), /* System error on the PCI bus */
237 TimerIntr = (1 << 14), /* Asserted when TCTR reaches TimerInt value */
238 LenChg = (1 << 13), /* Cable length change */
239 SWInt = (1 << 8), /* Software-requested interrupt */
240 TxEmpty = (1 << 7), /* No Tx descriptors available */
241 RxFIFOOvr = (1 << 6), /* Rx FIFO Overflow */
242 LinkChg = (1 << 5), /* Packet underrun, or link change */
243 RxEmpty = (1 << 4), /* No Rx descriptors available */
244 TxErr = (1 << 3), /* Tx error */
245 TxOK = (1 << 2), /* Tx packet sent */
246 RxErr = (1 << 1), /* Rx error */
247 RxOK = (1 << 0), /* Rx packet received */
248 IntrResvd = (1 << 10), /* reserved, according to RealTek engineers,
249 but hardware likes to raise it */
250
251 IntrAll = PciErr | TimerIntr | LenChg | SWInt | TxEmpty |
252 RxFIFOOvr | LinkChg | RxEmpty | TxErr | TxOK |
253 RxErr | RxOK | IntrResvd,
254
255 /* C mode command register */
256 CmdReset = (1 << 4), /* Enable to reset; self-clearing */
257 RxOn = (1 << 3), /* Rx mode enable */
258 TxOn = (1 << 2), /* Tx mode enable */
259
260 /* C+ mode command register */
261 RxVlanOn = (1 << 6), /* Rx VLAN de-tagging enable */
262 RxChkSum = (1 << 5), /* Rx checksum offload enable */
263 PCIDAC = (1 << 4), /* PCI Dual Address Cycle (64-bit PCI) */
264 PCIMulRW = (1 << 3), /* Enable PCI read/write multiple */
265 CpRxOn = (1 << 1), /* Rx mode enable */
266 CpTxOn = (1 << 0), /* Tx mode enable */
267
268 /* Cfg9436 EEPROM control register */
269 Cfg9346_Lock = 0x00, /* Lock ConfigX/MII register access */
270 Cfg9346_Unlock = 0xC0, /* Unlock ConfigX/MII register access */
271
272 /* TxConfig register */
273 IFG = (1 << 25) | (1 << 24), /* standard IEEE interframe gap */
274 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
275
276 /* Early Tx Threshold register */
277 TxThreshMask = 0x3f, /* Mask bits 5-0 */
278 TxThreshMax = 2048, /* Max early Tx threshold */
279
280 /* Config1 register */
281 DriverLoaded = (1 << 5), /* Software marker, driver is loaded */
282 LWACT = (1 << 4), /* LWAKE active mode */
283 PMEnable = (1 << 0), /* Enable various PM features of chip */
284
285 /* Config3 register */
286 PARMEnable = (1 << 6), /* Enable auto-loading of PHY parms */
287 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
288 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
289
290 /* Config4 register */
291 LWPTN = (1 << 1), /* LWAKE Pattern */
292 LWPME = (1 << 4), /* LANWAKE vs PMEB */
293
294 /* Config5 register */
295 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
296 MWF = (1 << 5), /* Accept Multicast wakeup frame */
297 UWF = (1 << 4), /* Accept Unicast wakeup frame */
298 LANWake = (1 << 1), /* Enable LANWake signal */
299 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
300
301 cp_norx_intr_mask = PciErr | LinkChg | TxOK | TxErr | TxEmpty,
302 cp_rx_intr_mask = RxOK | RxErr | RxEmpty | RxFIFOOvr,
303 cp_intr_mask = cp_rx_intr_mask | cp_norx_intr_mask,
304 };
305
306 static const unsigned int cp_rx_config =
307 (RX_FIFO_THRESH << RxCfgFIFOShift) |
308 (RX_DMA_BURST << RxCfgDMAShift);
309
310 struct cp_desc {
311 u32 opts1;
312 u32 opts2;
313 u64 addr;
314 };
315
316 struct ring_info {
317 struct sk_buff *skb;
318 dma_addr_t mapping;
319 u32 len;
320 };
321
322 struct cp_dma_stats {
323 u64 tx_ok;
324 u64 rx_ok;
325 u64 tx_err;
326 u32 rx_err;
327 u16 rx_fifo;
328 u16 frame_align;
329 u32 tx_ok_1col;
330 u32 tx_ok_mcol;
331 u64 rx_ok_phys;
332 u64 rx_ok_bcast;
333 u32 rx_ok_mcast;
334 u16 tx_abort;
335 u16 tx_underrun;
336 } __attribute__((packed));
337
338 struct cp_extra_stats {
339 unsigned long rx_frags;
340 };
341
342 struct cp_private {
343 void __iomem *regs;
344 struct net_device *dev;
345 spinlock_t lock;
346 u32 msg_enable;
347
348 struct pci_dev *pdev;
349 u32 rx_config;
350 u16 cpcmd;
351
352 struct net_device_stats net_stats;
353 struct cp_extra_stats cp_stats;
354 struct cp_dma_stats *nic_stats;
355 dma_addr_t nic_stats_dma;
356
357 unsigned rx_tail ____cacheline_aligned;
358 struct cp_desc *rx_ring;
359 struct ring_info rx_skb[CP_RX_RING_SIZE];
360 unsigned rx_buf_sz;
361
362 unsigned tx_head ____cacheline_aligned;
363 unsigned tx_tail;
364
365 struct cp_desc *tx_ring;
366 struct ring_info tx_skb[CP_TX_RING_SIZE];
367 dma_addr_t ring_dma;
368
369 #if CP_VLAN_TAG_USED
370 struct vlan_group *vlgrp;
371 #endif
372
373 unsigned int wol_enabled : 1; /* Is Wake-on-LAN enabled? */
374
375 struct mii_if_info mii_if;
376 };
377
378 #define cpr8(reg) readb(cp->regs + (reg))
379 #define cpr16(reg) readw(cp->regs + (reg))
380 #define cpr32(reg) readl(cp->regs + (reg))
381 #define cpw8(reg,val) writeb((val), cp->regs + (reg))
382 #define cpw16(reg,val) writew((val), cp->regs + (reg))
383 #define cpw32(reg,val) writel((val), cp->regs + (reg))
384 #define cpw8_f(reg,val) do { \
385 writeb((val), cp->regs + (reg)); \
386 readb(cp->regs + (reg)); \
387 } while (0)
388 #define cpw16_f(reg,val) do { \
389 writew((val), cp->regs + (reg)); \
390 readw(cp->regs + (reg)); \
391 } while (0)
392 #define cpw32_f(reg,val) do { \
393 writel((val), cp->regs + (reg)); \
394 readl(cp->regs + (reg)); \
395 } while (0)
396
397
398 static void __cp_set_rx_mode (struct net_device *dev);
399 static void cp_tx (struct cp_private *cp);
400 static void cp_clean_rings (struct cp_private *cp);
401 #ifdef CONFIG_NET_POLL_CONTROLLER
402 static void cp_poll_controller(struct net_device *dev);
403 #endif
404
405 static struct pci_device_id cp_pci_tbl[] = {
406 { PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139,
407 PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
408 { PCI_VENDOR_ID_TTTECH, PCI_DEVICE_ID_TTTECH_MC322,
409 PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
410 { },
411 };
412 MODULE_DEVICE_TABLE(pci, cp_pci_tbl);
413
414 static struct {
415 const char str[ETH_GSTRING_LEN];
416 } ethtool_stats_keys[] = {
417 { "tx_ok" },
418 { "rx_ok" },
419 { "tx_err" },
420 { "rx_err" },
421 { "rx_fifo" },
422 { "frame_align" },
423 { "tx_ok_1col" },
424 { "tx_ok_mcol" },
425 { "rx_ok_phys" },
426 { "rx_ok_bcast" },
427 { "rx_ok_mcast" },
428 { "tx_abort" },
429 { "tx_underrun" },
430 { "rx_frags" },
431 };
432
433
434 #if CP_VLAN_TAG_USED
435 static void cp_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
436 {
437 struct cp_private *cp = netdev_priv(dev);
438 unsigned long flags;
439
440 spin_lock_irqsave(&cp->lock, flags);
441 cp->vlgrp = grp;
442 cp->cpcmd |= RxVlanOn;
443 cpw16(CpCmd, cp->cpcmd);
444 spin_unlock_irqrestore(&cp->lock, flags);
445 }
446
447 static void cp_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
448 {
449 struct cp_private *cp = netdev_priv(dev);
450 unsigned long flags;
451
452 spin_lock_irqsave(&cp->lock, flags);
453 cp->cpcmd &= ~RxVlanOn;
454 cpw16(CpCmd, cp->cpcmd);
455 if (cp->vlgrp)
456 cp->vlgrp->vlan_devices[vid] = NULL;
457 spin_unlock_irqrestore(&cp->lock, flags);
458 }
459 #endif /* CP_VLAN_TAG_USED */
460
461 static inline void cp_set_rxbufsize (struct cp_private *cp)
462 {
463 unsigned int mtu = cp->dev->mtu;
464
465 if (mtu > ETH_DATA_LEN)
466 /* MTU + ethernet header + FCS + optional VLAN tag */
467 cp->rx_buf_sz = mtu + ETH_HLEN + 8;
468 else
469 cp->rx_buf_sz = PKT_BUF_SZ;
470 }
471
472 static inline void cp_rx_skb (struct cp_private *cp, struct sk_buff *skb,
473 struct cp_desc *desc)
474 {
475 skb->protocol = eth_type_trans (skb, cp->dev);
476
477 cp->net_stats.rx_packets++;
478 cp->net_stats.rx_bytes += skb->len;
479 cp->dev->last_rx = jiffies;
480
481 #if CP_VLAN_TAG_USED
482 if (cp->vlgrp && (desc->opts2 & RxVlanTagged)) {
483 vlan_hwaccel_receive_skb(skb, cp->vlgrp,
484 be16_to_cpu(desc->opts2 & 0xffff));
485 } else
486 #endif
487 netif_receive_skb(skb);
488 }
489
490 static void cp_rx_err_acct (struct cp_private *cp, unsigned rx_tail,
491 u32 status, u32 len)
492 {
493 if (netif_msg_rx_err (cp))
494 printk (KERN_DEBUG
495 "%s: rx err, slot %d status 0x%x len %d\n",
496 cp->dev->name, rx_tail, status, len);
497 cp->net_stats.rx_errors++;
498 if (status & RxErrFrame)
499 cp->net_stats.rx_frame_errors++;
500 if (status & RxErrCRC)
501 cp->net_stats.rx_crc_errors++;
502 if ((status & RxErrRunt) || (status & RxErrLong))
503 cp->net_stats.rx_length_errors++;
504 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag))
505 cp->net_stats.rx_length_errors++;
506 if (status & RxErrFIFO)
507 cp->net_stats.rx_fifo_errors++;
508 }
509
510 static inline unsigned int cp_rx_csum_ok (u32 status)
511 {
512 unsigned int protocol = (status >> 16) & 0x3;
513
514 if (likely((protocol == RxProtoTCP) && (!(status & TCPFail))))
515 return 1;
516 else if ((protocol == RxProtoUDP) && (!(status & UDPFail)))
517 return 1;
518 else if ((protocol == RxProtoIP) && (!(status & IPFail)))
519 return 1;
520 return 0;
521 }
522
523 static int cp_rx_poll (struct net_device *dev, int *budget)
524 {
525 struct cp_private *cp = netdev_priv(dev);
526 unsigned rx_tail = cp->rx_tail;
527 unsigned rx_work = dev->quota;
528 unsigned rx;
529
530 rx_status_loop:
531 rx = 0;
532 cpw16(IntrStatus, cp_rx_intr_mask);
533
534 while (1) {
535 u32 status, len;
536 dma_addr_t mapping;
537 struct sk_buff *skb, *new_skb;
538 struct cp_desc *desc;
539 unsigned buflen;
540
541 skb = cp->rx_skb[rx_tail].skb;
542 if (!skb)
543 BUG();
544
545 desc = &cp->rx_ring[rx_tail];
546 status = le32_to_cpu(desc->opts1);
547 if (status & DescOwn)
548 break;
549
550 len = (status & 0x1fff) - 4;
551 mapping = cp->rx_skb[rx_tail].mapping;
552
553 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag)) {
554 /* we don't support incoming fragmented frames.
555 * instead, we attempt to ensure that the
556 * pre-allocated RX skbs are properly sized such
557 * that RX fragments are never encountered
558 */
559 cp_rx_err_acct(cp, rx_tail, status, len);
560 cp->net_stats.rx_dropped++;
561 cp->cp_stats.rx_frags++;
562 goto rx_next;
563 }
564
565 if (status & (RxError | RxErrFIFO)) {
566 cp_rx_err_acct(cp, rx_tail, status, len);
567 goto rx_next;
568 }
569
570 if (netif_msg_rx_status(cp))
571 printk(KERN_DEBUG "%s: rx slot %d status 0x%x len %d\n",
572 cp->dev->name, rx_tail, status, len);
573
574 buflen = cp->rx_buf_sz + RX_OFFSET;
575 new_skb = dev_alloc_skb (buflen);
576 if (!new_skb) {
577 cp->net_stats.rx_dropped++;
578 goto rx_next;
579 }
580
581 skb_reserve(new_skb, RX_OFFSET);
582 new_skb->dev = cp->dev;
583
584 pci_unmap_single(cp->pdev, mapping,
585 buflen, PCI_DMA_FROMDEVICE);
586
587 /* Handle checksum offloading for incoming packets. */
588 if (cp_rx_csum_ok(status))
589 skb->ip_summed = CHECKSUM_UNNECESSARY;
590 else
591 skb->ip_summed = CHECKSUM_NONE;
592
593 skb_put(skb, len);
594
595 mapping =
596 cp->rx_skb[rx_tail].mapping =
597 pci_map_single(cp->pdev, new_skb->tail,
598 buflen, PCI_DMA_FROMDEVICE);
599 cp->rx_skb[rx_tail].skb = new_skb;
600
601 cp_rx_skb(cp, skb, desc);
602 rx++;
603
604 rx_next:
605 cp->rx_ring[rx_tail].opts2 = 0;
606 cp->rx_ring[rx_tail].addr = cpu_to_le64(mapping);
607 if (rx_tail == (CP_RX_RING_SIZE - 1))
608 desc->opts1 = cpu_to_le32(DescOwn | RingEnd |
609 cp->rx_buf_sz);
610 else
611 desc->opts1 = cpu_to_le32(DescOwn | cp->rx_buf_sz);
612 rx_tail = NEXT_RX(rx_tail);
613
614 if (!rx_work--)
615 break;
616 }
617
618 cp->rx_tail = rx_tail;
619
620 dev->quota -= rx;
621 *budget -= rx;
622
623 /* if we did not reach work limit, then we're done with
624 * this round of polling
625 */
626 if (rx_work) {
627 if (cpr16(IntrStatus) & cp_rx_intr_mask)
628 goto rx_status_loop;
629
630 local_irq_disable();
631 cpw16_f(IntrMask, cp_intr_mask);
632 __netif_rx_complete(dev);
633 local_irq_enable();
634
635 return 0; /* done */
636 }
637
638 return 1; /* not done */
639 }
640
641 static irqreturn_t
642 cp_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
643 {
644 struct net_device *dev = dev_instance;
645 struct cp_private *cp;
646 u16 status;
647
648 if (unlikely(dev == NULL))
649 return IRQ_NONE;
650 cp = netdev_priv(dev);
651
652 status = cpr16(IntrStatus);
653 if (!status || (status == 0xFFFF))
654 return IRQ_NONE;
655
656 if (netif_msg_intr(cp))
657 printk(KERN_DEBUG "%s: intr, status %04x cmd %02x cpcmd %04x\n",
658 dev->name, status, cpr8(Cmd), cpr16(CpCmd));
659
660 cpw16(IntrStatus, status & ~cp_rx_intr_mask);
661
662 spin_lock(&cp->lock);
663
664 /* close possible race's with dev_close */
665 if (unlikely(!netif_running(dev))) {
666 cpw16(IntrMask, 0);
667 spin_unlock(&cp->lock);
668 return IRQ_HANDLED;
669 }
670
671 if (status & (RxOK | RxErr | RxEmpty | RxFIFOOvr))
672 if (netif_rx_schedule_prep(dev)) {
673 cpw16_f(IntrMask, cp_norx_intr_mask);
674 __netif_rx_schedule(dev);
675 }
676
677 if (status & (TxOK | TxErr | TxEmpty | SWInt))
678 cp_tx(cp);
679 if (status & LinkChg)
680 mii_check_media(&cp->mii_if, netif_msg_link(cp), FALSE);
681
682 spin_unlock(&cp->lock);
683
684 if (status & PciErr) {
685 u16 pci_status;
686
687 pci_read_config_word(cp->pdev, PCI_STATUS, &pci_status);
688 pci_write_config_word(cp->pdev, PCI_STATUS, pci_status);
689 printk(KERN_ERR "%s: PCI bus error, status=%04x, PCI status=%04x\n",
690 dev->name, status, pci_status);
691
692 /* TODO: reset hardware */
693 }
694
695 return IRQ_HANDLED;
696 }
697
698 #ifdef CONFIG_NET_POLL_CONTROLLER
699 /*
700 * Polling receive - used by netconsole and other diagnostic tools
701 * to allow network i/o with interrupts disabled.
702 */
703 static void cp_poll_controller(struct net_device *dev)
704 {
705 disable_irq(dev->irq);
706 cp_interrupt(dev->irq, dev, NULL);
707 enable_irq(dev->irq);
708 }
709 #endif
710
711 static void cp_tx (struct cp_private *cp)
712 {
713 unsigned tx_head = cp->tx_head;
714 unsigned tx_tail = cp->tx_tail;
715
716 while (tx_tail != tx_head) {
717 struct sk_buff *skb;
718 u32 status;
719
720 rmb();
721 status = le32_to_cpu(cp->tx_ring[tx_tail].opts1);
722 if (status & DescOwn)
723 break;
724
725 skb = cp->tx_skb[tx_tail].skb;
726 if (!skb)
727 BUG();
728
729 pci_unmap_single(cp->pdev, cp->tx_skb[tx_tail].mapping,
730 cp->tx_skb[tx_tail].len, PCI_DMA_TODEVICE);
731
732 if (status & LastFrag) {
733 if (status & (TxError | TxFIFOUnder)) {
734 if (netif_msg_tx_err(cp))
735 printk(KERN_DEBUG "%s: tx err, status 0x%x\n",
736 cp->dev->name, status);
737 cp->net_stats.tx_errors++;
738 if (status & TxOWC)
739 cp->net_stats.tx_window_errors++;
740 if (status & TxMaxCol)
741 cp->net_stats.tx_aborted_errors++;
742 if (status & TxLinkFail)
743 cp->net_stats.tx_carrier_errors++;
744 if (status & TxFIFOUnder)
745 cp->net_stats.tx_fifo_errors++;
746 } else {
747 cp->net_stats.collisions +=
748 ((status >> TxColCntShift) & TxColCntMask);
749 cp->net_stats.tx_packets++;
750 cp->net_stats.tx_bytes += skb->len;
751 if (netif_msg_tx_done(cp))
752 printk(KERN_DEBUG "%s: tx done, slot %d\n", cp->dev->name, tx_tail);
753 }
754 dev_kfree_skb_irq(skb);
755 }
756
757 cp->tx_skb[tx_tail].skb = NULL;
758
759 tx_tail = NEXT_TX(tx_tail);
760 }
761
762 cp->tx_tail = tx_tail;
763
764 if (TX_BUFFS_AVAIL(cp) > (MAX_SKB_FRAGS + 1))
765 netif_wake_queue(cp->dev);
766 }
767
768 static int cp_start_xmit (struct sk_buff *skb, struct net_device *dev)
769 {
770 struct cp_private *cp = netdev_priv(dev);
771 unsigned entry;
772 u32 eor, flags;
773 #if CP_VLAN_TAG_USED
774 u32 vlan_tag = 0;
775 #endif
776 int mss = 0;
777
778 spin_lock_irq(&cp->lock);
779
780 /* This is a hard error, log it. */
781 if (TX_BUFFS_AVAIL(cp) <= (skb_shinfo(skb)->nr_frags + 1)) {
782 netif_stop_queue(dev);
783 spin_unlock_irq(&cp->lock);
784 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
785 dev->name);
786 return 1;
787 }
788
789 #if CP_VLAN_TAG_USED
790 if (cp->vlgrp && vlan_tx_tag_present(skb))
791 vlan_tag = TxVlanTag | cpu_to_be16(vlan_tx_tag_get(skb));
792 #endif
793
794 entry = cp->tx_head;
795 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
796 if (dev->features & NETIF_F_TSO)
797 mss = skb_shinfo(skb)->tso_size;
798
799 if (skb_shinfo(skb)->nr_frags == 0) {
800 struct cp_desc *txd = &cp->tx_ring[entry];
801 u32 len;
802 dma_addr_t mapping;
803
804 len = skb->len;
805 mapping = pci_map_single(cp->pdev, skb->data, len, PCI_DMA_TODEVICE);
806 CP_VLAN_TX_TAG(txd, vlan_tag);
807 txd->addr = cpu_to_le64(mapping);
808 wmb();
809
810 flags = eor | len | DescOwn | FirstFrag | LastFrag;
811
812 if (mss)
813 flags |= LargeSend | ((mss & MSSMask) << MSSShift);
814 else if (skb->ip_summed == CHECKSUM_HW) {
815 const struct iphdr *ip = skb->nh.iph;
816 if (ip->protocol == IPPROTO_TCP)
817 flags |= IPCS | TCPCS;
818 else if (ip->protocol == IPPROTO_UDP)
819 flags |= IPCS | UDPCS;
820 else
821 WARN_ON(1); /* we need a WARN() */
822 }
823
824 txd->opts1 = cpu_to_le32(flags);
825 wmb();
826
827 cp->tx_skb[entry].skb = skb;
828 cp->tx_skb[entry].mapping = mapping;
829 cp->tx_skb[entry].len = len;
830 entry = NEXT_TX(entry);
831 } else {
832 struct cp_desc *txd;
833 u32 first_len, first_eor;
834 dma_addr_t first_mapping;
835 int frag, first_entry = entry;
836 const struct iphdr *ip = skb->nh.iph;
837
838 /* We must give this initial chunk to the device last.
839 * Otherwise we could race with the device.
840 */
841 first_eor = eor;
842 first_len = skb_headlen(skb);
843 first_mapping = pci_map_single(cp->pdev, skb->data,
844 first_len, PCI_DMA_TODEVICE);
845 cp->tx_skb[entry].skb = skb;
846 cp->tx_skb[entry].mapping = first_mapping;
847 cp->tx_skb[entry].len = first_len;
848 entry = NEXT_TX(entry);
849
850 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
851 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
852 u32 len;
853 u32 ctrl;
854 dma_addr_t mapping;
855
856 len = this_frag->size;
857 mapping = pci_map_single(cp->pdev,
858 ((void *) page_address(this_frag->page) +
859 this_frag->page_offset),
860 len, PCI_DMA_TODEVICE);
861 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
862
863 ctrl = eor | len | DescOwn;
864
865 if (mss)
866 ctrl |= LargeSend |
867 ((mss & MSSMask) << MSSShift);
868 else if (skb->ip_summed == CHECKSUM_HW) {
869 if (ip->protocol == IPPROTO_TCP)
870 ctrl |= IPCS | TCPCS;
871 else if (ip->protocol == IPPROTO_UDP)
872 ctrl |= IPCS | UDPCS;
873 else
874 BUG();
875 }
876
877 if (frag == skb_shinfo(skb)->nr_frags - 1)
878 ctrl |= LastFrag;
879
880 txd = &cp->tx_ring[entry];
881 CP_VLAN_TX_TAG(txd, vlan_tag);
882 txd->addr = cpu_to_le64(mapping);
883 wmb();
884
885 txd->opts1 = cpu_to_le32(ctrl);
886 wmb();
887
888 cp->tx_skb[entry].skb = skb;
889 cp->tx_skb[entry].mapping = mapping;
890 cp->tx_skb[entry].len = len;
891 entry = NEXT_TX(entry);
892 }
893
894 txd = &cp->tx_ring[first_entry];
895 CP_VLAN_TX_TAG(txd, vlan_tag);
896 txd->addr = cpu_to_le64(first_mapping);
897 wmb();
898
899 if (skb->ip_summed == CHECKSUM_HW) {
900 if (ip->protocol == IPPROTO_TCP)
901 txd->opts1 = cpu_to_le32(first_eor | first_len |
902 FirstFrag | DescOwn |
903 IPCS | TCPCS);
904 else if (ip->protocol == IPPROTO_UDP)
905 txd->opts1 = cpu_to_le32(first_eor | first_len |
906 FirstFrag | DescOwn |
907 IPCS | UDPCS);
908 else
909 BUG();
910 } else
911 txd->opts1 = cpu_to_le32(first_eor | first_len |
912 FirstFrag | DescOwn);
913 wmb();
914 }
915 cp->tx_head = entry;
916 if (netif_msg_tx_queued(cp))
917 printk(KERN_DEBUG "%s: tx queued, slot %d, skblen %d\n",
918 dev->name, entry, skb->len);
919 if (TX_BUFFS_AVAIL(cp) <= (MAX_SKB_FRAGS + 1))
920 netif_stop_queue(dev);
921
922 spin_unlock_irq(&cp->lock);
923
924 cpw8(TxPoll, NormalTxPoll);
925 dev->trans_start = jiffies;
926
927 return 0;
928 }
929
930 /* Set or clear the multicast filter for this adaptor.
931 This routine is not state sensitive and need not be SMP locked. */
932
933 static void __cp_set_rx_mode (struct net_device *dev)
934 {
935 struct cp_private *cp = netdev_priv(dev);
936 u32 mc_filter[2]; /* Multicast hash filter */
937 int i, rx_mode;
938 u32 tmp;
939
940 /* Note: do not reorder, GCC is clever about common statements. */
941 if (dev->flags & IFF_PROMISC) {
942 /* Unconditionally log net taps. */
943 printk (KERN_NOTICE "%s: Promiscuous mode enabled.\n",
944 dev->name);
945 rx_mode =
946 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
947 AcceptAllPhys;
948 mc_filter[1] = mc_filter[0] = 0xffffffff;
949 } else if ((dev->mc_count > multicast_filter_limit)
950 || (dev->flags & IFF_ALLMULTI)) {
951 /* Too many to filter perfectly -- accept all multicasts. */
952 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
953 mc_filter[1] = mc_filter[0] = 0xffffffff;
954 } else {
955 struct dev_mc_list *mclist;
956 rx_mode = AcceptBroadcast | AcceptMyPhys;
957 mc_filter[1] = mc_filter[0] = 0;
958 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
959 i++, mclist = mclist->next) {
960 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
961
962 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
963 rx_mode |= AcceptMulticast;
964 }
965 }
966
967 /* We can safely update without stopping the chip. */
968 tmp = cp_rx_config | rx_mode;
969 if (cp->rx_config != tmp) {
970 cpw32_f (RxConfig, tmp);
971 cp->rx_config = tmp;
972 }
973 cpw32_f (MAR0 + 0, mc_filter[0]);
974 cpw32_f (MAR0 + 4, mc_filter[1]);
975 }
976
977 static void cp_set_rx_mode (struct net_device *dev)
978 {
979 unsigned long flags;
980 struct cp_private *cp = netdev_priv(dev);
981
982 spin_lock_irqsave (&cp->lock, flags);
983 __cp_set_rx_mode(dev);
984 spin_unlock_irqrestore (&cp->lock, flags);
985 }
986
987 static void __cp_get_stats(struct cp_private *cp)
988 {
989 /* only lower 24 bits valid; write any value to clear */
990 cp->net_stats.rx_missed_errors += (cpr32 (RxMissed) & 0xffffff);
991 cpw32 (RxMissed, 0);
992 }
993
994 static struct net_device_stats *cp_get_stats(struct net_device *dev)
995 {
996 struct cp_private *cp = netdev_priv(dev);
997 unsigned long flags;
998
999 /* The chip only need report frame silently dropped. */
1000 spin_lock_irqsave(&cp->lock, flags);
1001 if (netif_running(dev) && netif_device_present(dev))
1002 __cp_get_stats(cp);
1003 spin_unlock_irqrestore(&cp->lock, flags);
1004
1005 return &cp->net_stats;
1006 }
1007
1008 static void cp_stop_hw (struct cp_private *cp)
1009 {
1010 cpw16(IntrStatus, ~(cpr16(IntrStatus)));
1011 cpw16_f(IntrMask, 0);
1012 cpw8(Cmd, 0);
1013 cpw16_f(CpCmd, 0);
1014 cpw16_f(IntrStatus, ~(cpr16(IntrStatus)));
1015
1016 cp->rx_tail = 0;
1017 cp->tx_head = cp->tx_tail = 0;
1018 }
1019
1020 static void cp_reset_hw (struct cp_private *cp)
1021 {
1022 unsigned work = 1000;
1023
1024 cpw8(Cmd, CmdReset);
1025
1026 while (work--) {
1027 if (!(cpr8(Cmd) & CmdReset))
1028 return;
1029
1030 set_current_state(TASK_UNINTERRUPTIBLE);
1031 schedule_timeout(10);
1032 }
1033
1034 printk(KERN_ERR "%s: hardware reset timeout\n", cp->dev->name);
1035 }
1036
1037 static inline void cp_start_hw (struct cp_private *cp)
1038 {
1039 cpw16(CpCmd, cp->cpcmd);
1040 cpw8(Cmd, RxOn | TxOn);
1041 }
1042
1043 static void cp_init_hw (struct cp_private *cp)
1044 {
1045 struct net_device *dev = cp->dev;
1046 dma_addr_t ring_dma;
1047
1048 cp_reset_hw(cp);
1049
1050 cpw8_f (Cfg9346, Cfg9346_Unlock);
1051
1052 /* Restore our idea of the MAC address. */
1053 cpw32_f (MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
1054 cpw32_f (MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
1055
1056 cp_start_hw(cp);
1057 cpw8(TxThresh, 0x06); /* XXX convert magic num to a constant */
1058
1059 __cp_set_rx_mode(dev);
1060 cpw32_f (TxConfig, IFG | (TX_DMA_BURST << TxDMAShift));
1061
1062 cpw8(Config1, cpr8(Config1) | DriverLoaded | PMEnable);
1063 /* Disable Wake-on-LAN. Can be turned on with ETHTOOL_SWOL */
1064 cpw8(Config3, PARMEnable);
1065 cp->wol_enabled = 0;
1066
1067 cpw8(Config5, cpr8(Config5) & PMEStatus);
1068
1069 cpw32_f(HiTxRingAddr, 0);
1070 cpw32_f(HiTxRingAddr + 4, 0);
1071
1072 ring_dma = cp->ring_dma;
1073 cpw32_f(RxRingAddr, ring_dma & 0xffffffff);
1074 cpw32_f(RxRingAddr + 4, (ring_dma >> 16) >> 16);
1075
1076 ring_dma += sizeof(struct cp_desc) * CP_RX_RING_SIZE;
1077 cpw32_f(TxRingAddr, ring_dma & 0xffffffff);
1078 cpw32_f(TxRingAddr + 4, (ring_dma >> 16) >> 16);
1079
1080 cpw16(MultiIntr, 0);
1081
1082 cpw16_f(IntrMask, cp_intr_mask);
1083
1084 cpw8_f(Cfg9346, Cfg9346_Lock);
1085 }
1086
1087 static int cp_refill_rx (struct cp_private *cp)
1088 {
1089 unsigned i;
1090
1091 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1092 struct sk_buff *skb;
1093
1094 skb = dev_alloc_skb(cp->rx_buf_sz + RX_OFFSET);
1095 if (!skb)
1096 goto err_out;
1097
1098 skb->dev = cp->dev;
1099 skb_reserve(skb, RX_OFFSET);
1100
1101 cp->rx_skb[i].mapping = pci_map_single(cp->pdev,
1102 skb->tail, cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1103 cp->rx_skb[i].skb = skb;
1104
1105 cp->rx_ring[i].opts2 = 0;
1106 cp->rx_ring[i].addr = cpu_to_le64(cp->rx_skb[i].mapping);
1107 if (i == (CP_RX_RING_SIZE - 1))
1108 cp->rx_ring[i].opts1 =
1109 cpu_to_le32(DescOwn | RingEnd | cp->rx_buf_sz);
1110 else
1111 cp->rx_ring[i].opts1 =
1112 cpu_to_le32(DescOwn | cp->rx_buf_sz);
1113 }
1114
1115 return 0;
1116
1117 err_out:
1118 cp_clean_rings(cp);
1119 return -ENOMEM;
1120 }
1121
1122 static int cp_init_rings (struct cp_private *cp)
1123 {
1124 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1125 cp->tx_ring[CP_TX_RING_SIZE - 1].opts1 = cpu_to_le32(RingEnd);
1126
1127 cp->rx_tail = 0;
1128 cp->tx_head = cp->tx_tail = 0;
1129
1130 return cp_refill_rx (cp);
1131 }
1132
1133 static int cp_alloc_rings (struct cp_private *cp)
1134 {
1135 void *mem;
1136
1137 mem = pci_alloc_consistent(cp->pdev, CP_RING_BYTES, &cp->ring_dma);
1138 if (!mem)
1139 return -ENOMEM;
1140
1141 cp->rx_ring = mem;
1142 cp->tx_ring = &cp->rx_ring[CP_RX_RING_SIZE];
1143
1144 mem += (CP_RING_BYTES - CP_STATS_SIZE);
1145 cp->nic_stats = mem;
1146 cp->nic_stats_dma = cp->ring_dma + (CP_RING_BYTES - CP_STATS_SIZE);
1147
1148 return cp_init_rings(cp);
1149 }
1150
1151 static void cp_clean_rings (struct cp_private *cp)
1152 {
1153 unsigned i;
1154
1155 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1156 if (cp->rx_skb[i].skb) {
1157 pci_unmap_single(cp->pdev, cp->rx_skb[i].mapping,
1158 cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1159 dev_kfree_skb(cp->rx_skb[i].skb);
1160 }
1161 }
1162
1163 for (i = 0; i < CP_TX_RING_SIZE; i++) {
1164 if (cp->tx_skb[i].skb) {
1165 struct sk_buff *skb = cp->tx_skb[i].skb;
1166
1167 pci_unmap_single(cp->pdev, cp->tx_skb[i].mapping,
1168 cp->tx_skb[i].len, PCI_DMA_TODEVICE);
1169 if (le32_to_cpu(cp->tx_ring[i].opts1) & LastFrag)
1170 dev_kfree_skb(skb);
1171 cp->net_stats.tx_dropped++;
1172 }
1173 }
1174
1175 memset(cp->rx_ring, 0, sizeof(struct cp_desc) * CP_RX_RING_SIZE);
1176 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1177
1178 memset(&cp->rx_skb, 0, sizeof(struct ring_info) * CP_RX_RING_SIZE);
1179 memset(&cp->tx_skb, 0, sizeof(struct ring_info) * CP_TX_RING_SIZE);
1180 }
1181
1182 static void cp_free_rings (struct cp_private *cp)
1183 {
1184 cp_clean_rings(cp);
1185 pci_free_consistent(cp->pdev, CP_RING_BYTES, cp->rx_ring, cp->ring_dma);
1186 cp->rx_ring = NULL;
1187 cp->tx_ring = NULL;
1188 cp->nic_stats = NULL;
1189 }
1190
1191 static int cp_open (struct net_device *dev)
1192 {
1193 struct cp_private *cp = netdev_priv(dev);
1194 int rc;
1195
1196 if (netif_msg_ifup(cp))
1197 printk(KERN_DEBUG "%s: enabling interface\n", dev->name);
1198
1199 rc = cp_alloc_rings(cp);
1200 if (rc)
1201 return rc;
1202
1203 cp_init_hw(cp);
1204
1205 rc = request_irq(dev->irq, cp_interrupt, SA_SHIRQ, dev->name, dev);
1206 if (rc)
1207 goto err_out_hw;
1208
1209 netif_carrier_off(dev);
1210 mii_check_media(&cp->mii_if, netif_msg_link(cp), TRUE);
1211 netif_start_queue(dev);
1212
1213 return 0;
1214
1215 err_out_hw:
1216 cp_stop_hw(cp);
1217 cp_free_rings(cp);
1218 return rc;
1219 }
1220
1221 static int cp_close (struct net_device *dev)
1222 {
1223 struct cp_private *cp = netdev_priv(dev);
1224 unsigned long flags;
1225
1226 if (netif_msg_ifdown(cp))
1227 printk(KERN_DEBUG "%s: disabling interface\n", dev->name);
1228
1229 spin_lock_irqsave(&cp->lock, flags);
1230
1231 netif_stop_queue(dev);
1232 netif_carrier_off(dev);
1233
1234 cp_stop_hw(cp);
1235
1236 spin_unlock_irqrestore(&cp->lock, flags);
1237
1238 synchronize_irq(dev->irq);
1239 free_irq(dev->irq, dev);
1240
1241 cp_free_rings(cp);
1242 return 0;
1243 }
1244
1245 #ifdef BROKEN
1246 static int cp_change_mtu(struct net_device *dev, int new_mtu)
1247 {
1248 struct cp_private *cp = netdev_priv(dev);
1249 int rc;
1250 unsigned long flags;
1251
1252 /* check for invalid MTU, according to hardware limits */
1253 if (new_mtu < CP_MIN_MTU || new_mtu > CP_MAX_MTU)
1254 return -EINVAL;
1255
1256 /* if network interface not up, no need for complexity */
1257 if (!netif_running(dev)) {
1258 dev->mtu = new_mtu;
1259 cp_set_rxbufsize(cp); /* set new rx buf size */
1260 return 0;
1261 }
1262
1263 spin_lock_irqsave(&cp->lock, flags);
1264
1265 cp_stop_hw(cp); /* stop h/w and free rings */
1266 cp_clean_rings(cp);
1267
1268 dev->mtu = new_mtu;
1269 cp_set_rxbufsize(cp); /* set new rx buf size */
1270
1271 rc = cp_init_rings(cp); /* realloc and restart h/w */
1272 cp_start_hw(cp);
1273
1274 spin_unlock_irqrestore(&cp->lock, flags);
1275
1276 return rc;
1277 }
1278 #endif /* BROKEN */
1279
1280 static char mii_2_8139_map[8] = {
1281 BasicModeCtrl,
1282 BasicModeStatus,
1283 0,
1284 0,
1285 NWayAdvert,
1286 NWayLPAR,
1287 NWayExpansion,
1288 0
1289 };
1290
1291 static int mdio_read(struct net_device *dev, int phy_id, int location)
1292 {
1293 struct cp_private *cp = netdev_priv(dev);
1294
1295 return location < 8 && mii_2_8139_map[location] ?
1296 readw(cp->regs + mii_2_8139_map[location]) : 0;
1297 }
1298
1299
1300 static void mdio_write(struct net_device *dev, int phy_id, int location,
1301 int value)
1302 {
1303 struct cp_private *cp = netdev_priv(dev);
1304
1305 if (location == 0) {
1306 cpw8(Cfg9346, Cfg9346_Unlock);
1307 cpw16(BasicModeCtrl, value);
1308 cpw8(Cfg9346, Cfg9346_Lock);
1309 } else if (location < 8 && mii_2_8139_map[location])
1310 cpw16(mii_2_8139_map[location], value);
1311 }
1312
1313 /* Set the ethtool Wake-on-LAN settings */
1314 static int netdev_set_wol (struct cp_private *cp,
1315 const struct ethtool_wolinfo *wol)
1316 {
1317 u8 options;
1318
1319 options = cpr8 (Config3) & ~(LinkUp | MagicPacket);
1320 /* If WOL is being disabled, no need for complexity */
1321 if (wol->wolopts) {
1322 if (wol->wolopts & WAKE_PHY) options |= LinkUp;
1323 if (wol->wolopts & WAKE_MAGIC) options |= MagicPacket;
1324 }
1325
1326 cpw8 (Cfg9346, Cfg9346_Unlock);
1327 cpw8 (Config3, options);
1328 cpw8 (Cfg9346, Cfg9346_Lock);
1329
1330 options = 0; /* Paranoia setting */
1331 options = cpr8 (Config5) & ~(UWF | MWF | BWF);
1332 /* If WOL is being disabled, no need for complexity */
1333 if (wol->wolopts) {
1334 if (wol->wolopts & WAKE_UCAST) options |= UWF;
1335 if (wol->wolopts & WAKE_BCAST) options |= BWF;
1336 if (wol->wolopts & WAKE_MCAST) options |= MWF;
1337 }
1338
1339 cpw8 (Config5, options);
1340
1341 cp->wol_enabled = (wol->wolopts) ? 1 : 0;
1342
1343 return 0;
1344 }
1345
1346 /* Get the ethtool Wake-on-LAN settings */
1347 static void netdev_get_wol (struct cp_private *cp,
1348 struct ethtool_wolinfo *wol)
1349 {
1350 u8 options;
1351
1352 wol->wolopts = 0; /* Start from scratch */
1353 wol->supported = WAKE_PHY | WAKE_BCAST | WAKE_MAGIC |
1354 WAKE_MCAST | WAKE_UCAST;
1355 /* We don't need to go on if WOL is disabled */
1356 if (!cp->wol_enabled) return;
1357
1358 options = cpr8 (Config3);
1359 if (options & LinkUp) wol->wolopts |= WAKE_PHY;
1360 if (options & MagicPacket) wol->wolopts |= WAKE_MAGIC;
1361
1362 options = 0; /* Paranoia setting */
1363 options = cpr8 (Config5);
1364 if (options & UWF) wol->wolopts |= WAKE_UCAST;
1365 if (options & BWF) wol->wolopts |= WAKE_BCAST;
1366 if (options & MWF) wol->wolopts |= WAKE_MCAST;
1367 }
1368
1369 static void cp_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1370 {
1371 struct cp_private *cp = netdev_priv(dev);
1372
1373 strcpy (info->driver, DRV_NAME);
1374 strcpy (info->version, DRV_VERSION);
1375 strcpy (info->bus_info, pci_name(cp->pdev));
1376 }
1377
1378 static int cp_get_regs_len(struct net_device *dev)
1379 {
1380 return CP_REGS_SIZE;
1381 }
1382
1383 static int cp_get_stats_count (struct net_device *dev)
1384 {
1385 return CP_NUM_STATS;
1386 }
1387
1388 static int cp_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1389 {
1390 struct cp_private *cp = netdev_priv(dev);
1391 int rc;
1392 unsigned long flags;
1393
1394 spin_lock_irqsave(&cp->lock, flags);
1395 rc = mii_ethtool_gset(&cp->mii_if, cmd);
1396 spin_unlock_irqrestore(&cp->lock, flags);
1397
1398 return rc;
1399 }
1400
1401 static int cp_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1402 {
1403 struct cp_private *cp = netdev_priv(dev);
1404 int rc;
1405 unsigned long flags;
1406
1407 spin_lock_irqsave(&cp->lock, flags);
1408 rc = mii_ethtool_sset(&cp->mii_if, cmd);
1409 spin_unlock_irqrestore(&cp->lock, flags);
1410
1411 return rc;
1412 }
1413
1414 static int cp_nway_reset(struct net_device *dev)
1415 {
1416 struct cp_private *cp = netdev_priv(dev);
1417 return mii_nway_restart(&cp->mii_if);
1418 }
1419
1420 static u32 cp_get_msglevel(struct net_device *dev)
1421 {
1422 struct cp_private *cp = netdev_priv(dev);
1423 return cp->msg_enable;
1424 }
1425
1426 static void cp_set_msglevel(struct net_device *dev, u32 value)
1427 {
1428 struct cp_private *cp = netdev_priv(dev);
1429 cp->msg_enable = value;
1430 }
1431
1432 static u32 cp_get_rx_csum(struct net_device *dev)
1433 {
1434 struct cp_private *cp = netdev_priv(dev);
1435 return (cpr16(CpCmd) & RxChkSum) ? 1 : 0;
1436 }
1437
1438 static int cp_set_rx_csum(struct net_device *dev, u32 data)
1439 {
1440 struct cp_private *cp = netdev_priv(dev);
1441 u16 cmd = cp->cpcmd, newcmd;
1442
1443 newcmd = cmd;
1444
1445 if (data)
1446 newcmd |= RxChkSum;
1447 else
1448 newcmd &= ~RxChkSum;
1449
1450 if (newcmd != cmd) {
1451 unsigned long flags;
1452
1453 spin_lock_irqsave(&cp->lock, flags);
1454 cp->cpcmd = newcmd;
1455 cpw16_f(CpCmd, newcmd);
1456 spin_unlock_irqrestore(&cp->lock, flags);
1457 }
1458
1459 return 0;
1460 }
1461
1462 static void cp_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1463 void *p)
1464 {
1465 struct cp_private *cp = netdev_priv(dev);
1466 unsigned long flags;
1467
1468 if (regs->len < CP_REGS_SIZE)
1469 return /* -EINVAL */;
1470
1471 regs->version = CP_REGS_VER;
1472
1473 spin_lock_irqsave(&cp->lock, flags);
1474 memcpy_fromio(p, cp->regs, CP_REGS_SIZE);
1475 spin_unlock_irqrestore(&cp->lock, flags);
1476 }
1477
1478 static void cp_get_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1479 {
1480 struct cp_private *cp = netdev_priv(dev);
1481 unsigned long flags;
1482
1483 spin_lock_irqsave (&cp->lock, flags);
1484 netdev_get_wol (cp, wol);
1485 spin_unlock_irqrestore (&cp->lock, flags);
1486 }
1487
1488 static int cp_set_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1489 {
1490 struct cp_private *cp = netdev_priv(dev);
1491 unsigned long flags;
1492 int rc;
1493
1494 spin_lock_irqsave (&cp->lock, flags);
1495 rc = netdev_set_wol (cp, wol);
1496 spin_unlock_irqrestore (&cp->lock, flags);
1497
1498 return rc;
1499 }
1500
1501 static void cp_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
1502 {
1503 switch (stringset) {
1504 case ETH_SS_STATS:
1505 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
1506 break;
1507 default:
1508 BUG();
1509 break;
1510 }
1511 }
1512
1513 static void cp_get_ethtool_stats (struct net_device *dev,
1514 struct ethtool_stats *estats, u64 *tmp_stats)
1515 {
1516 struct cp_private *cp = netdev_priv(dev);
1517 unsigned int work = 100;
1518 int i;
1519
1520 /* begin NIC statistics dump */
1521 cpw32(StatsAddr + 4, (cp->nic_stats_dma >> 16) >> 16);
1522 cpw32(StatsAddr, (cp->nic_stats_dma & 0xffffffff) | DumpStats);
1523 cpr32(StatsAddr);
1524
1525 while (work-- > 0) {
1526 if ((cpr32(StatsAddr) & DumpStats) == 0)
1527 break;
1528 cpu_relax();
1529 }
1530
1531 if (cpr32(StatsAddr) & DumpStats)
1532 return /* -EIO */;
1533
1534 i = 0;
1535 tmp_stats[i++] = le64_to_cpu(cp->nic_stats->tx_ok);
1536 tmp_stats[i++] = le64_to_cpu(cp->nic_stats->rx_ok);
1537 tmp_stats[i++] = le64_to_cpu(cp->nic_stats->tx_err);
1538 tmp_stats[i++] = le32_to_cpu(cp->nic_stats->rx_err);
1539 tmp_stats[i++] = le16_to_cpu(cp->nic_stats->rx_fifo);
1540 tmp_stats[i++] = le16_to_cpu(cp->nic_stats->frame_align);
1541 tmp_stats[i++] = le32_to_cpu(cp->nic_stats->tx_ok_1col);
1542 tmp_stats[i++] = le32_to_cpu(cp->nic_stats->tx_ok_mcol);
1543 tmp_stats[i++] = le64_to_cpu(cp->nic_stats->rx_ok_phys);
1544 tmp_stats[i++] = le64_to_cpu(cp->nic_stats->rx_ok_bcast);
1545 tmp_stats[i++] = le32_to_cpu(cp->nic_stats->rx_ok_mcast);
1546 tmp_stats[i++] = le16_to_cpu(cp->nic_stats->tx_abort);
1547 tmp_stats[i++] = le16_to_cpu(cp->nic_stats->tx_underrun);
1548 tmp_stats[i++] = cp->cp_stats.rx_frags;
1549 if (i != CP_NUM_STATS)
1550 BUG();
1551 }
1552
1553 static struct ethtool_ops cp_ethtool_ops = {
1554 .get_drvinfo = cp_get_drvinfo,
1555 .get_regs_len = cp_get_regs_len,
1556 .get_stats_count = cp_get_stats_count,
1557 .get_settings = cp_get_settings,
1558 .set_settings = cp_set_settings,
1559 .nway_reset = cp_nway_reset,
1560 .get_link = ethtool_op_get_link,
1561 .get_msglevel = cp_get_msglevel,
1562 .set_msglevel = cp_set_msglevel,
1563 .get_rx_csum = cp_get_rx_csum,
1564 .set_rx_csum = cp_set_rx_csum,
1565 .get_tx_csum = ethtool_op_get_tx_csum,
1566 .set_tx_csum = ethtool_op_set_tx_csum, /* local! */
1567 .get_sg = ethtool_op_get_sg,
1568 .set_sg = ethtool_op_set_sg,
1569 .get_tso = ethtool_op_get_tso,
1570 .set_tso = ethtool_op_set_tso,
1571 .get_regs = cp_get_regs,
1572 .get_wol = cp_get_wol,
1573 .set_wol = cp_set_wol,
1574 .get_strings = cp_get_strings,
1575 .get_ethtool_stats = cp_get_ethtool_stats,
1576 };
1577
1578 static int cp_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1579 {
1580 struct cp_private *cp = netdev_priv(dev);
1581 int rc;
1582 unsigned long flags;
1583
1584 if (!netif_running(dev))
1585 return -EINVAL;
1586
1587 spin_lock_irqsave(&cp->lock, flags);
1588 rc = generic_mii_ioctl(&cp->mii_if, if_mii(rq), cmd, NULL);
1589 spin_unlock_irqrestore(&cp->lock, flags);
1590 return rc;
1591 }
1592
1593 /* Serial EEPROM section. */
1594
1595 /* EEPROM_Ctrl bits. */
1596 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1597 #define EE_CS 0x08 /* EEPROM chip select. */
1598 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1599 #define EE_WRITE_0 0x00
1600 #define EE_WRITE_1 0x02
1601 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1602 #define EE_ENB (0x80 | EE_CS)
1603
1604 /* Delay between EEPROM clock transitions.
1605 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1606 */
1607
1608 #define eeprom_delay() readl(ee_addr)
1609
1610 /* The EEPROM commands include the alway-set leading bit. */
1611 #define EE_WRITE_CMD (5)
1612 #define EE_READ_CMD (6)
1613 #define EE_ERASE_CMD (7)
1614
1615 static int read_eeprom (void __iomem *ioaddr, int location, int addr_len)
1616 {
1617 int i;
1618 unsigned retval = 0;
1619 void __iomem *ee_addr = ioaddr + Cfg9346;
1620 int read_cmd = location | (EE_READ_CMD << addr_len);
1621
1622 writeb (EE_ENB & ~EE_CS, ee_addr);
1623 writeb (EE_ENB, ee_addr);
1624 eeprom_delay ();
1625
1626 /* Shift the read command bits out. */
1627 for (i = 4 + addr_len; i >= 0; i--) {
1628 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1629 writeb (EE_ENB | dataval, ee_addr);
1630 eeprom_delay ();
1631 writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
1632 eeprom_delay ();
1633 }
1634 writeb (EE_ENB, ee_addr);
1635 eeprom_delay ();
1636
1637 for (i = 16; i > 0; i--) {
1638 writeb (EE_ENB | EE_SHIFT_CLK, ee_addr);
1639 eeprom_delay ();
1640 retval =
1641 (retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 :
1642 0);
1643 writeb (EE_ENB, ee_addr);
1644 eeprom_delay ();
1645 }
1646
1647 /* Terminate the EEPROM access. */
1648 writeb (~EE_CS, ee_addr);
1649 eeprom_delay ();
1650
1651 return retval;
1652 }
1653
1654 /* Put the board into D3cold state and wait for WakeUp signal */
1655 static void cp_set_d3_state (struct cp_private *cp)
1656 {
1657 pci_enable_wake (cp->pdev, 0, 1); /* Enable PME# generation */
1658 pci_set_power_state (cp->pdev, PCI_D3hot);
1659 }
1660
1661 static int cp_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1662 {
1663 struct net_device *dev;
1664 struct cp_private *cp;
1665 int rc;
1666 void __iomem *regs;
1667 long pciaddr;
1668 unsigned int addr_len, i, pci_using_dac;
1669 u8 pci_rev;
1670
1671 #ifndef MODULE
1672 static int version_printed;
1673 if (version_printed++ == 0)
1674 printk("%s", version);
1675 #endif
1676
1677 pci_read_config_byte(pdev, PCI_REVISION_ID, &pci_rev);
1678
1679 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
1680 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pci_rev < 0x20) {
1681 printk(KERN_ERR PFX "pci dev %s (id %04x:%04x rev %02x) is not an 8139C+ compatible chip\n",
1682 pci_name(pdev), pdev->vendor, pdev->device, pci_rev);
1683 printk(KERN_ERR PFX "Try the \"8139too\" driver instead.\n");
1684 return -ENODEV;
1685 }
1686
1687 dev = alloc_etherdev(sizeof(struct cp_private));
1688 if (!dev)
1689 return -ENOMEM;
1690 SET_MODULE_OWNER(dev);
1691 SET_NETDEV_DEV(dev, &pdev->dev);
1692
1693 cp = netdev_priv(dev);
1694 cp->pdev = pdev;
1695 cp->dev = dev;
1696 cp->msg_enable = (debug < 0 ? CP_DEF_MSG_ENABLE : debug);
1697 spin_lock_init (&cp->lock);
1698 cp->mii_if.dev = dev;
1699 cp->mii_if.mdio_read = mdio_read;
1700 cp->mii_if.mdio_write = mdio_write;
1701 cp->mii_if.phy_id = CP_INTERNAL_PHY;
1702 cp->mii_if.phy_id_mask = 0x1f;
1703 cp->mii_if.reg_num_mask = 0x1f;
1704 cp_set_rxbufsize(cp);
1705
1706 rc = pci_enable_device(pdev);
1707 if (rc)
1708 goto err_out_free;
1709
1710 rc = pci_set_mwi(pdev);
1711 if (rc)
1712 goto err_out_disable;
1713
1714 rc = pci_request_regions(pdev, DRV_NAME);
1715 if (rc)
1716 goto err_out_mwi;
1717
1718 pciaddr = pci_resource_start(pdev, 1);
1719 if (!pciaddr) {
1720 rc = -EIO;
1721 printk(KERN_ERR PFX "no MMIO resource for pci dev %s\n",
1722 pci_name(pdev));
1723 goto err_out_res;
1724 }
1725 if (pci_resource_len(pdev, 1) < CP_REGS_SIZE) {
1726 rc = -EIO;
1727 printk(KERN_ERR PFX "MMIO resource (%lx) too small on pci dev %s\n",
1728 pci_resource_len(pdev, 1), pci_name(pdev));
1729 goto err_out_res;
1730 }
1731
1732 /* Configure DMA attributes. */
1733 if ((sizeof(dma_addr_t) > 4) &&
1734 !pci_set_consistent_dma_mask(pdev, 0xffffffffffffffffULL) &&
1735 !pci_set_dma_mask(pdev, 0xffffffffffffffffULL)) {
1736 pci_using_dac = 1;
1737 } else {
1738 pci_using_dac = 0;
1739
1740 rc = pci_set_dma_mask(pdev, 0xffffffffULL);
1741 if (rc) {
1742 printk(KERN_ERR PFX "No usable DMA configuration, "
1743 "aborting.\n");
1744 goto err_out_res;
1745 }
1746 rc = pci_set_consistent_dma_mask(pdev, 0xffffffffULL);
1747 if (rc) {
1748 printk(KERN_ERR PFX "No usable consistent DMA configuration, "
1749 "aborting.\n");
1750 goto err_out_res;
1751 }
1752 }
1753
1754 cp->cpcmd = (pci_using_dac ? PCIDAC : 0) |
1755 PCIMulRW | RxChkSum | CpRxOn | CpTxOn;
1756
1757 regs = ioremap(pciaddr, CP_REGS_SIZE);
1758 if (!regs) {
1759 rc = -EIO;
1760 printk(KERN_ERR PFX "Cannot map PCI MMIO (%lx@%lx) on pci dev %s\n",
1761 pci_resource_len(pdev, 1), pciaddr, pci_name(pdev));
1762 goto err_out_res;
1763 }
1764 dev->base_addr = (unsigned long) regs;
1765 cp->regs = regs;
1766
1767 cp_stop_hw(cp);
1768
1769 /* read MAC address from EEPROM */
1770 addr_len = read_eeprom (regs, 0, 8) == 0x8129 ? 8 : 6;
1771 for (i = 0; i < 3; i++)
1772 ((u16 *) (dev->dev_addr))[i] =
1773 le16_to_cpu (read_eeprom (regs, i + 7, addr_len));
1774
1775 dev->open = cp_open;
1776 dev->stop = cp_close;
1777 dev->set_multicast_list = cp_set_rx_mode;
1778 dev->hard_start_xmit = cp_start_xmit;
1779 dev->get_stats = cp_get_stats;
1780 dev->do_ioctl = cp_ioctl;
1781 dev->poll = cp_rx_poll;
1782 #ifdef CONFIG_NET_POLL_CONTROLLER
1783 dev->poll_controller = cp_poll_controller;
1784 #endif
1785 dev->weight = 16; /* arbitrary? from NAPI_HOWTO.txt. */
1786 #ifdef BROKEN
1787 dev->change_mtu = cp_change_mtu;
1788 #endif
1789 dev->ethtool_ops = &cp_ethtool_ops;
1790 #if 0
1791 dev->tx_timeout = cp_tx_timeout;
1792 dev->watchdog_timeo = TX_TIMEOUT;
1793 #endif
1794
1795 #if CP_VLAN_TAG_USED
1796 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1797 dev->vlan_rx_register = cp_vlan_rx_register;
1798 dev->vlan_rx_kill_vid = cp_vlan_rx_kill_vid;
1799 #endif
1800
1801 if (pci_using_dac)
1802 dev->features |= NETIF_F_HIGHDMA;
1803
1804 #if 0 /* disabled by default until verified */
1805 dev->features |= NETIF_F_TSO;
1806 #endif
1807
1808 dev->irq = pdev->irq;
1809
1810 rc = register_netdev(dev);
1811 if (rc)
1812 goto err_out_iomap;
1813
1814 printk (KERN_INFO "%s: RTL-8139C+ at 0x%lx, "
1815 "%02x:%02x:%02x:%02x:%02x:%02x, "
1816 "IRQ %d\n",
1817 dev->name,
1818 dev->base_addr,
1819 dev->dev_addr[0], dev->dev_addr[1],
1820 dev->dev_addr[2], dev->dev_addr[3],
1821 dev->dev_addr[4], dev->dev_addr[5],
1822 dev->irq);
1823
1824 pci_set_drvdata(pdev, dev);
1825
1826 /* enable busmastering and memory-write-invalidate */
1827 pci_set_master(pdev);
1828
1829 if (cp->wol_enabled) cp_set_d3_state (cp);
1830
1831 return 0;
1832
1833 err_out_iomap:
1834 iounmap(regs);
1835 err_out_res:
1836 pci_release_regions(pdev);
1837 err_out_mwi:
1838 pci_clear_mwi(pdev);
1839 err_out_disable:
1840 pci_disable_device(pdev);
1841 err_out_free:
1842 free_netdev(dev);
1843 return rc;
1844 }
1845
1846 static void cp_remove_one (struct pci_dev *pdev)
1847 {
1848 struct net_device *dev = pci_get_drvdata(pdev);
1849 struct cp_private *cp = netdev_priv(dev);
1850
1851 if (!dev)
1852 BUG();
1853 unregister_netdev(dev);
1854 iounmap(cp->regs);
1855 if (cp->wol_enabled) pci_set_power_state (pdev, PCI_D0);
1856 pci_release_regions(pdev);
1857 pci_clear_mwi(pdev);
1858 pci_disable_device(pdev);
1859 pci_set_drvdata(pdev, NULL);
1860 free_netdev(dev);
1861 }
1862
1863 #ifdef CONFIG_PM
1864 static int cp_suspend (struct pci_dev *pdev, pm_message_t state)
1865 {
1866 struct net_device *dev;
1867 struct cp_private *cp;
1868 unsigned long flags;
1869
1870 dev = pci_get_drvdata (pdev);
1871 cp = netdev_priv(dev);
1872
1873 if (!dev || !netif_running (dev)) return 0;
1874
1875 netif_device_detach (dev);
1876 netif_stop_queue (dev);
1877
1878 spin_lock_irqsave (&cp->lock, flags);
1879
1880 /* Disable Rx and Tx */
1881 cpw16 (IntrMask, 0);
1882 cpw8 (Cmd, cpr8 (Cmd) & (~RxOn | ~TxOn));
1883
1884 spin_unlock_irqrestore (&cp->lock, flags);
1885
1886 if (cp->pdev && cp->wol_enabled) {
1887 pci_save_state (cp->pdev);
1888 cp_set_d3_state (cp);
1889 }
1890
1891 return 0;
1892 }
1893
1894 static int cp_resume (struct pci_dev *pdev)
1895 {
1896 struct net_device *dev;
1897 struct cp_private *cp;
1898
1899 dev = pci_get_drvdata (pdev);
1900 cp = netdev_priv(dev);
1901
1902 netif_device_attach (dev);
1903
1904 if (cp->pdev && cp->wol_enabled) {
1905 pci_set_power_state (cp->pdev, PCI_D0);
1906 pci_restore_state (cp->pdev);
1907 }
1908
1909 cp_init_hw (cp);
1910 netif_start_queue (dev);
1911
1912 return 0;
1913 }
1914 #endif /* CONFIG_PM */
1915
1916 static struct pci_driver cp_driver = {
1917 .name = DRV_NAME,
1918 .id_table = cp_pci_tbl,
1919 .probe = cp_init_one,
1920 .remove = cp_remove_one,
1921 #ifdef CONFIG_PM
1922 .resume = cp_resume,
1923 .suspend = cp_suspend,
1924 #endif
1925 };
1926
1927 static int __init cp_init (void)
1928 {
1929 #ifdef MODULE
1930 printk("%s", version);
1931 #endif
1932 return pci_module_init (&cp_driver);
1933 }
1934
1935 static void __exit cp_exit (void)
1936 {
1937 pci_unregister_driver (&cp_driver);
1938 }
1939
1940 module_init(cp_init);
1941 module_exit(cp_exit);
Linus' kernel tree