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arch/sparc/kernel/sys_sparc_64.c: s/COLOUR/COLOR/
[linux-2.6.git] / drivers / i2c / busses / i2c-omap.c
blob3525c9e62cb0f9bf23f47705fd86d3bba9707b45
1 /*
2 * TI OMAP I2C master mode driver
3 *
4 * Copyright (C) 2003 MontaVista Software, Inc.
5 * Copyright (C) 2005 Nokia Corporation
6 * Copyright (C) 2004 - 2007 Texas Instruments.
7 *
8 * Originally written by MontaVista Software, Inc.
9 * Additional contributions by:
10 * Tony Lindgren <tony@atomide.com>
11 * Imre Deak <imre.deak@nokia.com>
12 * Juha Yrjölä <juha.yrjola@solidboot.com>
13 * Syed Khasim <x0khasim@ti.com>
14 * Nishant Menon <nm@ti.com>
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30
31 #include <linux/module.h>
32 #include <linux/delay.h>
33 #include <linux/i2c.h>
34 #include <linux/err.h>
35 #include <linux/interrupt.h>
36 #include <linux/completion.h>
37 #include <linux/platform_device.h>
38 #include <linux/clk.h>
39 #include <linux/io.h>
40 #include <linux/of.h>
41 #include <linux/of_i2c.h>
42 #include <linux/of_device.h>
43 #include <linux/slab.h>
44 #include <linux/i2c-omap.h>
45 #include <linux/pm_runtime.h>
46
47 /* I2C controller revisions */
48 #define OMAP_I2C_OMAP1_REV_2 0x20
49
50 /* I2C controller revisions present on specific hardware */
51 #define OMAP_I2C_REV_ON_2430 0x36
52 #define OMAP_I2C_REV_ON_3430_3530 0x3C
53 #define OMAP_I2C_REV_ON_3630_4430 0x40
54
55 /* timeout waiting for the controller to respond */
56 #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
57
58 /* timeout for pm runtime autosuspend */
59 #define OMAP_I2C_PM_TIMEOUT 1000 /* ms */
60
61 /* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */
62 enum {
63 OMAP_I2C_REV_REG = 0,
64 OMAP_I2C_IE_REG,
65 OMAP_I2C_STAT_REG,
66 OMAP_I2C_IV_REG,
67 OMAP_I2C_WE_REG,
68 OMAP_I2C_SYSS_REG,
69 OMAP_I2C_BUF_REG,
70 OMAP_I2C_CNT_REG,
71 OMAP_I2C_DATA_REG,
72 OMAP_I2C_SYSC_REG,
73 OMAP_I2C_CON_REG,
74 OMAP_I2C_OA_REG,
75 OMAP_I2C_SA_REG,
76 OMAP_I2C_PSC_REG,
77 OMAP_I2C_SCLL_REG,
78 OMAP_I2C_SCLH_REG,
79 OMAP_I2C_SYSTEST_REG,
80 OMAP_I2C_BUFSTAT_REG,
81 /* only on OMAP4430 */
82 OMAP_I2C_IP_V2_REVNB_LO,
83 OMAP_I2C_IP_V2_REVNB_HI,
84 OMAP_I2C_IP_V2_IRQSTATUS_RAW,
85 OMAP_I2C_IP_V2_IRQENABLE_SET,
86 OMAP_I2C_IP_V2_IRQENABLE_CLR,
87 };
88
89 /* I2C Interrupt Enable Register (OMAP_I2C_IE): */
90 #define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */
91 #define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer drain int enable */
92 #define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */
93 #define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */
94 #define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */
95 #define OMAP_I2C_IE_NACK (1 << 1) /* No ack interrupt enable */
96 #define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */
97
98 /* I2C Status Register (OMAP_I2C_STAT): */
99 #define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */
100 #define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */
101 #define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */
102 #define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */
103 #define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
104 #define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */
105 #define OMAP_I2C_STAT_AD0 (1 << 8) /* Address zero */
106 #define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
107 #define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */
108 #define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */
109 #define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */
110 #define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */
111
112 /* I2C WE wakeup enable register */
113 #define OMAP_I2C_WE_XDR_WE (1 << 14) /* TX drain wakup */
114 #define OMAP_I2C_WE_RDR_WE (1 << 13) /* RX drain wakeup */
115 #define OMAP_I2C_WE_AAS_WE (1 << 9) /* Address as slave wakeup*/
116 #define OMAP_I2C_WE_BF_WE (1 << 8) /* Bus free wakeup */
117 #define OMAP_I2C_WE_STC_WE (1 << 6) /* Start condition wakeup */
118 #define OMAP_I2C_WE_GC_WE (1 << 5) /* General call wakeup */
119 #define OMAP_I2C_WE_DRDY_WE (1 << 3) /* TX/RX data ready wakeup */
120 #define OMAP_I2C_WE_ARDY_WE (1 << 2) /* Reg access ready wakeup */
121 #define OMAP_I2C_WE_NACK_WE (1 << 1) /* No acknowledgment wakeup */
122 #define OMAP_I2C_WE_AL_WE (1 << 0) /* Arbitration lost wakeup */
123
124 #define OMAP_I2C_WE_ALL (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \
125 OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \
126 OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \
127 OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \
128 OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE)
129
130 /* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
131 #define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */
132 #define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */
133 #define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */
134 #define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */
135
136 /* I2C Configuration Register (OMAP_I2C_CON): */
137 #define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */
138 #define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */
139 #define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */
140 #define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */
141 #define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */
142 #define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */
143 #define OMAP_I2C_CON_XA (1 << 8) /* Expand address */
144 #define OMAP_I2C_CON_RM (1 << 2) /* Repeat mode (master only) */
145 #define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */
146 #define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */
147
148 /* I2C SCL time value when Master */
149 #define OMAP_I2C_SCLL_HSSCLL 8
150 #define OMAP_I2C_SCLH_HSSCLH 8
151
152 /* I2C System Test Register (OMAP_I2C_SYSTEST): */
153 #ifdef DEBUG
154 #define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
155 #define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */
156 #define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
157 #define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */
158 #define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */
159 #define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */
160 #define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */
161 #define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */
162 #endif
163
164 /* OCP_SYSSTATUS bit definitions */
165 #define SYSS_RESETDONE_MASK (1 << 0)
166
167 /* OCP_SYSCONFIG bit definitions */
168 #define SYSC_CLOCKACTIVITY_MASK (0x3 << 8)
169 #define SYSC_SIDLEMODE_MASK (0x3 << 3)
170 #define SYSC_ENAWAKEUP_MASK (1 << 2)
171 #define SYSC_SOFTRESET_MASK (1 << 1)
172 #define SYSC_AUTOIDLE_MASK (1 << 0)
173
174 #define SYSC_IDLEMODE_SMART 0x2
175 #define SYSC_CLOCKACTIVITY_FCLK 0x2
176
177 /* Errata definitions */
178 #define I2C_OMAP_ERRATA_I207 (1 << 0)
179 #define I2C_OMAP_ERRATA_I462 (1 << 1)
180
181 struct omap_i2c_dev {
182 spinlock_t lock; /* IRQ synchronization */
183 struct device *dev;
184 void __iomem *base; /* virtual */
185 int irq;
186 int reg_shift; /* bit shift for I2C register addresses */
187 struct completion cmd_complete;
188 struct resource *ioarea;
189 u32 latency; /* maximum mpu wkup latency */
190 void (*set_mpu_wkup_lat)(struct device *dev,
191 long latency);
192 u32 speed; /* Speed of bus in kHz */
193 u32 dtrev; /* extra revision from DT */
194 u32 flags;
195 u16 cmd_err;
196 u8 *buf;
197 u8 *regs;
198 size_t buf_len;
199 struct i2c_adapter adapter;
200 u8 threshold;
201 u8 fifo_size; /* use as flag and value
202 * fifo_size==0 implies no fifo
203 * if set, should be trsh+1
204 */
205 u8 rev;
206 unsigned b_hw:1; /* bad h/w fixes */
207 unsigned receiver:1; /* true when we're in receiver mode */
208 u16 iestate; /* Saved interrupt register */
209 u16 pscstate;
210 u16 scllstate;
211 u16 sclhstate;
212 u16 bufstate;
213 u16 syscstate;
214 u16 westate;
215 u16 errata;
216 };
217
218 static const u8 reg_map_ip_v1[] = {
219 [OMAP_I2C_REV_REG] = 0x00,
220 [OMAP_I2C_IE_REG] = 0x01,
221 [OMAP_I2C_STAT_REG] = 0x02,
222 [OMAP_I2C_IV_REG] = 0x03,
223 [OMAP_I2C_WE_REG] = 0x03,
224 [OMAP_I2C_SYSS_REG] = 0x04,
225 [OMAP_I2C_BUF_REG] = 0x05,
226 [OMAP_I2C_CNT_REG] = 0x06,
227 [OMAP_I2C_DATA_REG] = 0x07,
228 [OMAP_I2C_SYSC_REG] = 0x08,
229 [OMAP_I2C_CON_REG] = 0x09,
230 [OMAP_I2C_OA_REG] = 0x0a,
231 [OMAP_I2C_SA_REG] = 0x0b,
232 [OMAP_I2C_PSC_REG] = 0x0c,
233 [OMAP_I2C_SCLL_REG] = 0x0d,
234 [OMAP_I2C_SCLH_REG] = 0x0e,
235 [OMAP_I2C_SYSTEST_REG] = 0x0f,
236 [OMAP_I2C_BUFSTAT_REG] = 0x10,
237 };
238
239 static const u8 reg_map_ip_v2[] = {
240 [OMAP_I2C_REV_REG] = 0x04,
241 [OMAP_I2C_IE_REG] = 0x2c,
242 [OMAP_I2C_STAT_REG] = 0x28,
243 [OMAP_I2C_IV_REG] = 0x34,
244 [OMAP_I2C_WE_REG] = 0x34,
245 [OMAP_I2C_SYSS_REG] = 0x90,
246 [OMAP_I2C_BUF_REG] = 0x94,
247 [OMAP_I2C_CNT_REG] = 0x98,
248 [OMAP_I2C_DATA_REG] = 0x9c,
249 [OMAP_I2C_SYSC_REG] = 0x10,
250 [OMAP_I2C_CON_REG] = 0xa4,
251 [OMAP_I2C_OA_REG] = 0xa8,
252 [OMAP_I2C_SA_REG] = 0xac,
253 [OMAP_I2C_PSC_REG] = 0xb0,
254 [OMAP_I2C_SCLL_REG] = 0xb4,
255 [OMAP_I2C_SCLH_REG] = 0xb8,
256 [OMAP_I2C_SYSTEST_REG] = 0xbC,
257 [OMAP_I2C_BUFSTAT_REG] = 0xc0,
258 [OMAP_I2C_IP_V2_REVNB_LO] = 0x00,
259 [OMAP_I2C_IP_V2_REVNB_HI] = 0x04,
260 [OMAP_I2C_IP_V2_IRQSTATUS_RAW] = 0x24,
261 [OMAP_I2C_IP_V2_IRQENABLE_SET] = 0x2c,
262 [OMAP_I2C_IP_V2_IRQENABLE_CLR] = 0x30,
263 };
264
265 static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
266 int reg, u16 val)
267 {
268 __raw_writew(val, i2c_dev->base +
269 (i2c_dev->regs[reg] << i2c_dev->reg_shift));
270 }
271
272 static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
273 {
274 return __raw_readw(i2c_dev->base +
275 (i2c_dev->regs[reg] << i2c_dev->reg_shift));
276 }
277
278 static int omap_i2c_init(struct omap_i2c_dev *dev)
279 {
280 u16 psc = 0, scll = 0, sclh = 0, buf = 0;
281 u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
282 unsigned long fclk_rate = 12000000;
283 unsigned long timeout;
284 unsigned long internal_clk = 0;
285 struct clk *fclk;
286
287 if (dev->rev >= OMAP_I2C_OMAP1_REV_2) {
288 /* Disable I2C controller before soft reset */
289 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
290 omap_i2c_read_reg(dev, OMAP_I2C_CON_REG) &
291 ~(OMAP_I2C_CON_EN));
292
293 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK);
294 /* For some reason we need to set the EN bit before the
295 * reset done bit gets set. */
296 timeout = jiffies + OMAP_I2C_TIMEOUT;
297 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
298 while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
299 SYSS_RESETDONE_MASK)) {
300 if (time_after(jiffies, timeout)) {
301 dev_warn(dev->dev, "timeout waiting "
302 "for controller reset\n");
303 return -ETIMEDOUT;
304 }
305 msleep(1);
306 }
307
308 /* SYSC register is cleared by the reset; rewrite it */
309 if (dev->rev == OMAP_I2C_REV_ON_2430) {
310
311 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG,
312 SYSC_AUTOIDLE_MASK);
313
314 } else if (dev->rev >= OMAP_I2C_REV_ON_3430_3530) {
315 dev->syscstate = SYSC_AUTOIDLE_MASK;
316 dev->syscstate |= SYSC_ENAWAKEUP_MASK;
317 dev->syscstate |= (SYSC_IDLEMODE_SMART <<
318 __ffs(SYSC_SIDLEMODE_MASK));
319 dev->syscstate |= (SYSC_CLOCKACTIVITY_FCLK <<
320 __ffs(SYSC_CLOCKACTIVITY_MASK));
321
322 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG,
323 dev->syscstate);
324 /*
325 * Enabling all wakup sources to stop I2C freezing on
326 * WFI instruction.
327 * REVISIT: Some wkup sources might not be needed.
328 */
329 dev->westate = OMAP_I2C_WE_ALL;
330 omap_i2c_write_reg(dev, OMAP_I2C_WE_REG,
331 dev->westate);
332 }
333 }
334 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
335
336 if (dev->flags & OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK) {
337 /*
338 * The I2C functional clock is the armxor_ck, so there's
339 * no need to get "armxor_ck" separately. Now, if OMAP2420
340 * always returns 12MHz for the functional clock, we can
341 * do this bit unconditionally.
342 */
343 fclk = clk_get(dev->dev, "fck");
344 fclk_rate = clk_get_rate(fclk);
345 clk_put(fclk);
346
347 /* TRM for 5912 says the I2C clock must be prescaled to be
348 * between 7 - 12 MHz. The XOR input clock is typically
349 * 12, 13 or 19.2 MHz. So we should have code that produces:
350 *
351 * XOR MHz Divider Prescaler
352 * 12 1 0
353 * 13 2 1
354 * 19.2 2 1
355 */
356 if (fclk_rate > 12000000)
357 psc = fclk_rate / 12000000;
358 }
359
360 if (!(dev->flags & OMAP_I2C_FLAG_SIMPLE_CLOCK)) {
361
362 /*
363 * HSI2C controller internal clk rate should be 19.2 Mhz for
364 * HS and for all modes on 2430. On 34xx we can use lower rate
365 * to get longer filter period for better noise suppression.
366 * The filter is iclk (fclk for HS) period.
367 */
368 if (dev->speed > 400 ||
369 dev->flags & OMAP_I2C_FLAG_FORCE_19200_INT_CLK)
370 internal_clk = 19200;
371 else if (dev->speed > 100)
372 internal_clk = 9600;
373 else
374 internal_clk = 4000;
375 fclk = clk_get(dev->dev, "fck");
376 fclk_rate = clk_get_rate(fclk) / 1000;
377 clk_put(fclk);
378
379 /* Compute prescaler divisor */
380 psc = fclk_rate / internal_clk;
381 psc = psc - 1;
382
383 /* If configured for High Speed */
384 if (dev->speed > 400) {
385 unsigned long scl;
386
387 /* For first phase of HS mode */
388 scl = internal_clk / 400;
389 fsscll = scl - (scl / 3) - 7;
390 fssclh = (scl / 3) - 5;
391
392 /* For second phase of HS mode */
393 scl = fclk_rate / dev->speed;
394 hsscll = scl - (scl / 3) - 7;
395 hssclh = (scl / 3) - 5;
396 } else if (dev->speed > 100) {
397 unsigned long scl;
398
399 /* Fast mode */
400 scl = internal_clk / dev->speed;
401 fsscll = scl - (scl / 3) - 7;
402 fssclh = (scl / 3) - 5;
403 } else {
404 /* Standard mode */
405 fsscll = internal_clk / (dev->speed * 2) - 7;
406 fssclh = internal_clk / (dev->speed * 2) - 5;
407 }
408 scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
409 sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
410 } else {
411 /* Program desired operating rate */
412 fclk_rate /= (psc + 1) * 1000;
413 if (psc > 2)
414 psc = 2;
415 scll = fclk_rate / (dev->speed * 2) - 7 + psc;
416 sclh = fclk_rate / (dev->speed * 2) - 7 + psc;
417 }
418
419 /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
420 omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc);
421
422 /* SCL low and high time values */
423 omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll);
424 omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh);
425
426 /* Take the I2C module out of reset: */
427 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
428
429 /* Enable interrupts */
430 dev->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
431 OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
432 OMAP_I2C_IE_AL) | ((dev->fifo_size) ?
433 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0);
434 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
435 if (dev->flags & OMAP_I2C_FLAG_RESET_REGS_POSTIDLE) {
436 dev->pscstate = psc;
437 dev->scllstate = scll;
438 dev->sclhstate = sclh;
439 dev->bufstate = buf;
440 }
441 return 0;
442 }
443
444 /*
445 * Waiting on Bus Busy
446 */
447 static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
448 {
449 unsigned long timeout;
450
451 timeout = jiffies + OMAP_I2C_TIMEOUT;
452 while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
453 if (time_after(jiffies, timeout)) {
454 dev_warn(dev->dev, "timeout waiting for bus ready\n");
455 return -ETIMEDOUT;
456 }
457 msleep(1);
458 }
459
460 return 0;
461 }
462
463 static void omap_i2c_resize_fifo(struct omap_i2c_dev *dev, u8 size, bool is_rx)
464 {
465 u16 buf;
466
467 if (dev->flags & OMAP_I2C_FLAG_NO_FIFO)
468 return;
469
470 /*
471 * Set up notification threshold based on message size. We're doing
472 * this to try and avoid draining feature as much as possible. Whenever
473 * we have big messages to transfer (bigger than our total fifo size)
474 * then we might use draining feature to transfer the remaining bytes.
475 */
476
477 dev->threshold = clamp(size, (u8) 1, dev->fifo_size);
478
479 buf = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
480
481 if (is_rx) {
482 /* Clear RX Threshold */
483 buf &= ~(0x3f << 8);
484 buf |= ((dev->threshold - 1) << 8) | OMAP_I2C_BUF_RXFIF_CLR;
485 } else {
486 /* Clear TX Threshold */
487 buf &= ~0x3f;
488 buf |= (dev->threshold - 1) | OMAP_I2C_BUF_TXFIF_CLR;
489 }
490
491 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, buf);
492
493 if (dev->rev < OMAP_I2C_REV_ON_3630_4430)
494 dev->b_hw = 1; /* Enable hardware fixes */
495
496 /* calculate wakeup latency constraint for MPU */
497 if (dev->set_mpu_wkup_lat != NULL)
498 dev->latency = (1000000 * dev->threshold) /
499 (1000 * dev->speed / 8);
500 }
501
502 /*
503 * Low level master read/write transaction.
504 */
505 static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
506 struct i2c_msg *msg, int stop)
507 {
508 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
509 unsigned long timeout;
510 u16 w;
511
512 dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
513 msg->addr, msg->len, msg->flags, stop);
514
515 if (msg->len == 0)
516 return -EINVAL;
517
518 dev->receiver = !!(msg->flags & I2C_M_RD);
519 omap_i2c_resize_fifo(dev, msg->len, dev->receiver);
520
521 omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
522
523 /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
524 dev->buf = msg->buf;
525 dev->buf_len = msg->len;
526
527 /* make sure writes to dev->buf_len are ordered */
528 barrier();
529
530 omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);
531
532 /* Clear the FIFO Buffers */
533 w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
534 w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
535 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w);
536
537 INIT_COMPLETION(dev->cmd_complete);
538 dev->cmd_err = 0;
539
540 w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
541
542 /* High speed configuration */
543 if (dev->speed > 400)
544 w |= OMAP_I2C_CON_OPMODE_HS;
545
546 if (msg->flags & I2C_M_STOP)
547 stop = 1;
548 if (msg->flags & I2C_M_TEN)
549 w |= OMAP_I2C_CON_XA;
550 if (!(msg->flags & I2C_M_RD))
551 w |= OMAP_I2C_CON_TRX;
552
553 if (!dev->b_hw && stop)
554 w |= OMAP_I2C_CON_STP;
555
556 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
557
558 /*
559 * Don't write stt and stp together on some hardware.
560 */
561 if (dev->b_hw && stop) {
562 unsigned long delay = jiffies + OMAP_I2C_TIMEOUT;
563 u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
564 while (con & OMAP_I2C_CON_STT) {
565 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
566
567 /* Let the user know if i2c is in a bad state */
568 if (time_after(jiffies, delay)) {
569 dev_err(dev->dev, "controller timed out "
570 "waiting for start condition to finish\n");
571 return -ETIMEDOUT;
572 }
573 cpu_relax();
574 }
575
576 w |= OMAP_I2C_CON_STP;
577 w &= ~OMAP_I2C_CON_STT;
578 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
579 }
580
581 /*
582 * REVISIT: We should abort the transfer on signals, but the bus goes
583 * into arbitration and we're currently unable to recover from it.
584 */
585 timeout = wait_for_completion_timeout(&dev->cmd_complete,
586 OMAP_I2C_TIMEOUT);
587 if (timeout == 0) {
588 dev_err(dev->dev, "controller timed out\n");
589 omap_i2c_init(dev);
590 return -ETIMEDOUT;
591 }
592
593 if (likely(!dev->cmd_err))
594 return 0;
595
596 /* We have an error */
597 if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR |
598 OMAP_I2C_STAT_XUDF)) {
599 omap_i2c_init(dev);
600 return -EIO;
601 }
602
603 if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
604 if (msg->flags & I2C_M_IGNORE_NAK)
605 return 0;
606 if (stop) {
607 w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
608 w |= OMAP_I2C_CON_STP;
609 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
610 }
611 return -EREMOTEIO;
612 }
613 return -EIO;
614 }
615
616
617 /*
618 * Prepare controller for a transaction and call omap_i2c_xfer_msg
619 * to do the work during IRQ processing.
620 */
621 static int
622 omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
623 {
624 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
625 int i;
626 int r;
627
628 r = pm_runtime_get_sync(dev->dev);
629 if (IS_ERR_VALUE(r))
630 goto out;
631
632 r = omap_i2c_wait_for_bb(dev);
633 if (r < 0)
634 goto out;
635
636 if (dev->set_mpu_wkup_lat != NULL)
637 dev->set_mpu_wkup_lat(dev->dev, dev->latency);
638
639 for (i = 0; i < num; i++) {
640 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
641 if (r != 0)
642 break;
643 }
644
645 if (dev->set_mpu_wkup_lat != NULL)
646 dev->set_mpu_wkup_lat(dev->dev, -1);
647
648 if (r == 0)
649 r = num;
650
651 omap_i2c_wait_for_bb(dev);
652 out:
653 pm_runtime_mark_last_busy(dev->dev);
654 pm_runtime_put_autosuspend(dev->dev);
655 return r;
656 }
657
658 static u32
659 omap_i2c_func(struct i2c_adapter *adap)
660 {
661 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
662 I2C_FUNC_PROTOCOL_MANGLING;
663 }
664
665 static inline void
666 omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err)
667 {
668 dev->cmd_err |= err;
669 complete(&dev->cmd_complete);
670 }
671
672 static inline void
673 omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)
674 {
675 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
676 }
677
678 static inline void i2c_omap_errata_i207(struct omap_i2c_dev *dev, u16 stat)
679 {
680 /*
681 * I2C Errata(Errata Nos. OMAP2: 1.67, OMAP3: 1.8)
682 * Not applicable for OMAP4.
683 * Under certain rare conditions, RDR could be set again
684 * when the bus is busy, then ignore the interrupt and
685 * clear the interrupt.
686 */
687 if (stat & OMAP_I2C_STAT_RDR) {
688 /* Step 1: If RDR is set, clear it */
689 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
690
691 /* Step 2: */
692 if (!(omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG)
693 & OMAP_I2C_STAT_BB)) {
694
695 /* Step 3: */
696 if (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG)
697 & OMAP_I2C_STAT_RDR) {
698 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
699 dev_dbg(dev->dev, "RDR when bus is busy.\n");
700 }
701
702 }
703 }
704 }
705
706 /* rev1 devices are apparently only on some 15xx */
707 #ifdef CONFIG_ARCH_OMAP15XX
708
709 static irqreturn_t
710 omap_i2c_omap1_isr(int this_irq, void *dev_id)
711 {
712 struct omap_i2c_dev *dev = dev_id;
713 u16 iv, w;
714
715 if (pm_runtime_suspended(dev->dev))
716 return IRQ_NONE;
717
718 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
719 switch (iv) {
720 case 0x00: /* None */
721 break;
722 case 0x01: /* Arbitration lost */
723 dev_err(dev->dev, "Arbitration lost\n");
724 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
725 break;
726 case 0x02: /* No acknowledgement */
727 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
728 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
729 break;
730 case 0x03: /* Register access ready */
731 omap_i2c_complete_cmd(dev, 0);
732 break;
733 case 0x04: /* Receive data ready */
734 if (dev->buf_len) {
735 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
736 *dev->buf++ = w;
737 dev->buf_len--;
738 if (dev->buf_len) {
739 *dev->buf++ = w >> 8;
740 dev->buf_len--;
741 }
742 } else
743 dev_err(dev->dev, "RRDY IRQ while no data requested\n");
744 break;
745 case 0x05: /* Transmit data ready */
746 if (dev->buf_len) {
747 w = *dev->buf++;
748 dev->buf_len--;
749 if (dev->buf_len) {
750 w |= *dev->buf++ << 8;
751 dev->buf_len--;
752 }
753 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
754 } else
755 dev_err(dev->dev, "XRDY IRQ while no data to send\n");
756 break;
757 default:
758 return IRQ_NONE;
759 }
760
761 return IRQ_HANDLED;
762 }
763 #else
764 #define omap_i2c_omap1_isr NULL
765 #endif
766
767 /*
768 * OMAP3430 Errata i462: When an XRDY/XDR is hit, wait for XUDF before writing
769 * data to DATA_REG. Otherwise some data bytes can be lost while transferring
770 * them from the memory to the I2C interface.
771 */
772 static int errata_omap3_i462(struct omap_i2c_dev *dev)
773 {
774 unsigned long timeout = 10000;
775 u16 stat;
776
777 do {
778 stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
779 if (stat & OMAP_I2C_STAT_XUDF)
780 break;
781
782 if (stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {
783 omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_XRDY |
784 OMAP_I2C_STAT_XDR));
785 if (stat & OMAP_I2C_STAT_NACK) {
786 dev->cmd_err |= OMAP_I2C_STAT_NACK;
787 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK);
788 }
789
790 if (stat & OMAP_I2C_STAT_AL) {
791 dev_err(dev->dev, "Arbitration lost\n");
792 dev->cmd_err |= OMAP_I2C_STAT_AL;
793 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK);
794 }
795
796 return -EIO;
797 }
798
799 cpu_relax();
800 } while (--timeout);
801
802 if (!timeout) {
803 dev_err(dev->dev, "timeout waiting on XUDF bit\n");
804 return 0;
805 }
806
807 return 0;
808 }
809
810 static void omap_i2c_receive_data(struct omap_i2c_dev *dev, u8 num_bytes,
811 bool is_rdr)
812 {
813 u16 w;
814
815 while (num_bytes--) {
816 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
817 *dev->buf++ = w;
818 dev->buf_len--;
819
820 /*
821 * Data reg in 2430, omap3 and
822 * omap4 is 8 bit wide
823 */
824 if (dev->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {
825 *dev->buf++ = w >> 8;
826 dev->buf_len--;
827 }
828 }
829 }
830
831 static int omap_i2c_transmit_data(struct omap_i2c_dev *dev, u8 num_bytes,
832 bool is_xdr)
833 {
834 u16 w;
835
836 while (num_bytes--) {
837 w = *dev->buf++;
838 dev->buf_len--;
839
840 /*
841 * Data reg in 2430, omap3 and
842 * omap4 is 8 bit wide
843 */
844 if (dev->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {
845 w |= *dev->buf++ << 8;
846 dev->buf_len--;
847 }
848
849 if (dev->errata & I2C_OMAP_ERRATA_I462) {
850 int ret;
851
852 ret = errata_omap3_i462(dev);
853 if (ret < 0)
854 return ret;
855 }
856
857 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
858 }
859
860 return 0;
861 }
862
863 static irqreturn_t
864 omap_i2c_isr(int irq, void *dev_id)
865 {
866 struct omap_i2c_dev *dev = dev_id;
867 irqreturn_t ret = IRQ_HANDLED;
868 u16 mask;
869 u16 stat;
870
871 spin_lock(&dev->lock);
872 mask = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
873 stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
874
875 if (stat & mask)
876 ret = IRQ_WAKE_THREAD;
877
878 spin_unlock(&dev->lock);
879
880 return ret;
881 }
882
883 static irqreturn_t
884 omap_i2c_isr_thread(int this_irq, void *dev_id)
885 {
886 struct omap_i2c_dev *dev = dev_id;
887 unsigned long flags;
888 u16 bits;
889 u16 stat;
890 int err = 0, count = 0;
891
892 spin_lock_irqsave(&dev->lock, flags);
893 do {
894 bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
895 stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
896 stat &= bits;
897
898 /* If we're in receiver mode, ignore XDR/XRDY */
899 if (dev->receiver)
900 stat &= ~(OMAP_I2C_STAT_XDR | OMAP_I2C_STAT_XRDY);
901 else
902 stat &= ~(OMAP_I2C_STAT_RDR | OMAP_I2C_STAT_RRDY);
903
904 if (!stat) {
905 /* my work here is done */
906 goto out;
907 }
908
909 dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
910 if (count++ == 100) {
911 dev_warn(dev->dev, "Too much work in one IRQ\n");
912 break;
913 }
914
915 if (stat & OMAP_I2C_STAT_NACK) {
916 err |= OMAP_I2C_STAT_NACK;
917 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK);
918 break;
919 }
920
921 if (stat & OMAP_I2C_STAT_AL) {
922 dev_err(dev->dev, "Arbitration lost\n");
923 err |= OMAP_I2C_STAT_AL;
924 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_AL);
925 break;
926 }
927
928 /*
929 * ProDB0017052: Clear ARDY bit twice
930 */
931 if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
932 OMAP_I2C_STAT_AL)) {
933 omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_RRDY |
934 OMAP_I2C_STAT_RDR |
935 OMAP_I2C_STAT_XRDY |
936 OMAP_I2C_STAT_XDR |
937 OMAP_I2C_STAT_ARDY));
938 break;
939 }
940
941 if (stat & OMAP_I2C_STAT_RDR) {
942 u8 num_bytes = 1;
943
944 if (dev->fifo_size)
945 num_bytes = dev->buf_len;
946
947 omap_i2c_receive_data(dev, num_bytes, true);
948
949 if (dev->errata & I2C_OMAP_ERRATA_I207)
950 i2c_omap_errata_i207(dev, stat);
951
952 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
953 break;
954 }
955
956 if (stat & OMAP_I2C_STAT_RRDY) {
957 u8 num_bytes = 1;
958
959 if (dev->threshold)
960 num_bytes = dev->threshold;
961
962 omap_i2c_receive_data(dev, num_bytes, false);
963 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RRDY);
964 continue;
965 }
966
967 if (stat & OMAP_I2C_STAT_XDR) {
968 u8 num_bytes = 1;
969 int ret;
970
971 if (dev->fifo_size)
972 num_bytes = dev->buf_len;
973
974 ret = omap_i2c_transmit_data(dev, num_bytes, true);
975 if (ret < 0)
976 break;
977
978 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XDR);
979 break;
980 }
981
982 if (stat & OMAP_I2C_STAT_XRDY) {
983 u8 num_bytes = 1;
984 int ret;
985
986 if (dev->threshold)
987 num_bytes = dev->threshold;
988
989 ret = omap_i2c_transmit_data(dev, num_bytes, false);
990 if (ret < 0)
991 break;
992
993 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XRDY);
994 continue;
995 }
996
997 if (stat & OMAP_I2C_STAT_ROVR) {
998 dev_err(dev->dev, "Receive overrun\n");
999 err |= OMAP_I2C_STAT_ROVR;
1000 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_ROVR);
1001 break;
1002 }
1003
1004 if (stat & OMAP_I2C_STAT_XUDF) {
1005 dev_err(dev->dev, "Transmit underflow\n");
1006 err |= OMAP_I2C_STAT_XUDF;
1007 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XUDF);
1008 break;
1009 }
1010 } while (stat);
1011
1012 omap_i2c_complete_cmd(dev, err);
1013
1014 out:
1015 spin_unlock_irqrestore(&dev->lock, flags);
1016
1017 return IRQ_HANDLED;
1018 }
1019
1020 static const struct i2c_algorithm omap_i2c_algo = {
1021 .master_xfer = omap_i2c_xfer,
1022 .functionality = omap_i2c_func,
1023 };
1024
1025 #ifdef CONFIG_OF
1026 static struct omap_i2c_bus_platform_data omap3_pdata = {
1027 .rev = OMAP_I2C_IP_VERSION_1,
1028 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
1029 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
1030 OMAP_I2C_FLAG_BUS_SHIFT_2,
1031 };
1032
1033 static struct omap_i2c_bus_platform_data omap4_pdata = {
1034 .rev = OMAP_I2C_IP_VERSION_2,
1035 };
1036
1037 static const struct of_device_id omap_i2c_of_match[] = {
1038 {
1039 .compatible = "ti,omap4-i2c",
1040 .data = &omap4_pdata,
1041 },
1042 {
1043 .compatible = "ti,omap3-i2c",
1044 .data = &omap3_pdata,
1045 },
1046 { },
1047 };
1048 MODULE_DEVICE_TABLE(of, omap_i2c_of_match);
1049 #endif
1050
1051 static int __devinit
1052 omap_i2c_probe(struct platform_device *pdev)
1053 {
1054 struct omap_i2c_dev *dev;
1055 struct i2c_adapter *adap;
1056 struct resource *mem;
1057 const struct omap_i2c_bus_platform_data *pdata =
1058 pdev->dev.platform_data;
1059 struct device_node *node = pdev->dev.of_node;
1060 const struct of_device_id *match;
1061 int irq;
1062 int r;
1063
1064 /* NOTE: driver uses the static register mapping */
1065 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1066 if (!mem) {
1067 dev_err(&pdev->dev, "no mem resource?\n");
1068 return -ENODEV;
1069 }
1070
1071 irq = platform_get_irq(pdev, 0);
1072 if (irq < 0) {
1073 dev_err(&pdev->dev, "no irq resource?\n");
1074 return irq;
1075 }
1076
1077 dev = devm_kzalloc(&pdev->dev, sizeof(struct omap_i2c_dev), GFP_KERNEL);
1078 if (!dev) {
1079 dev_err(&pdev->dev, "Menory allocation failed\n");
1080 return -ENOMEM;
1081 }
1082
1083 dev->base = devm_request_and_ioremap(&pdev->dev, mem);
1084 if (!dev->base) {
1085 dev_err(&pdev->dev, "I2C region already claimed\n");
1086 return -ENOMEM;
1087 }
1088
1089 match = of_match_device(of_match_ptr(omap_i2c_of_match), &pdev->dev);
1090 if (match) {
1091 u32 freq = 100000; /* default to 100000 Hz */
1092
1093 pdata = match->data;
1094 dev->dtrev = pdata->rev;
1095 dev->flags = pdata->flags;
1096
1097 of_property_read_u32(node, "clock-frequency", &freq);
1098 /* convert DT freq value in Hz into kHz for speed */
1099 dev->speed = freq / 1000;
1100 } else if (pdata != NULL) {
1101 dev->speed = pdata->clkrate;
1102 dev->flags = pdata->flags;
1103 dev->set_mpu_wkup_lat = pdata->set_mpu_wkup_lat;
1104 dev->dtrev = pdata->rev;
1105 }
1106
1107 dev->dev = &pdev->dev;
1108 dev->irq = irq;
1109
1110 spin_lock_init(&dev->lock);
1111
1112 platform_set_drvdata(pdev, dev);
1113 init_completion(&dev->cmd_complete);
1114
1115 dev->reg_shift = (dev->flags >> OMAP_I2C_FLAG_BUS_SHIFT__SHIFT) & 3;
1116
1117 if (dev->dtrev == OMAP_I2C_IP_VERSION_2)
1118 dev->regs = (u8 *)reg_map_ip_v2;
1119 else
1120 dev->regs = (u8 *)reg_map_ip_v1;
1121
1122 pm_runtime_enable(dev->dev);
1123 pm_runtime_set_autosuspend_delay(dev->dev, OMAP_I2C_PM_TIMEOUT);
1124 pm_runtime_use_autosuspend(dev->dev);
1125
1126 r = pm_runtime_get_sync(dev->dev);
1127 if (IS_ERR_VALUE(r))
1128 goto err_free_mem;
1129
1130 dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;
1131
1132 dev->errata = 0;
1133
1134 if (dev->flags & OMAP_I2C_FLAG_APPLY_ERRATA_I207)
1135 dev->errata |= I2C_OMAP_ERRATA_I207;
1136
1137 if (dev->rev <= OMAP_I2C_REV_ON_3430_3530)
1138 dev->errata |= I2C_OMAP_ERRATA_I462;
1139
1140 if (!(dev->flags & OMAP_I2C_FLAG_NO_FIFO)) {
1141 u16 s;
1142
1143 /* Set up the fifo size - Get total size */
1144 s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
1145 dev->fifo_size = 0x8 << s;
1146
1147 /*
1148 * Set up notification threshold as half the total available
1149 * size. This is to ensure that we can handle the status on int
1150 * call back latencies.
1151 */
1152
1153 dev->fifo_size = (dev->fifo_size / 2);
1154
1155 if (dev->rev < OMAP_I2C_REV_ON_3630_4430)
1156 dev->b_hw = 1; /* Enable hardware fixes */
1157
1158 /* calculate wakeup latency constraint for MPU */
1159 if (dev->set_mpu_wkup_lat != NULL)
1160 dev->latency = (1000000 * dev->fifo_size) /
1161 (1000 * dev->speed / 8);
1162 }
1163
1164 /* reset ASAP, clearing any IRQs */
1165 omap_i2c_init(dev);
1166
1167 if (dev->rev < OMAP_I2C_OMAP1_REV_2)
1168 r = devm_request_irq(&pdev->dev, dev->irq, omap_i2c_omap1_isr,
1169 IRQF_NO_SUSPEND, pdev->name, dev);
1170 else
1171 r = devm_request_threaded_irq(&pdev->dev, dev->irq,
1172 omap_i2c_isr, omap_i2c_isr_thread,
1173 IRQF_NO_SUSPEND | IRQF_ONESHOT,
1174 pdev->name, dev);
1175
1176 if (r) {
1177 dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
1178 goto err_unuse_clocks;
1179 }
1180
1181 adap = &dev->adapter;
1182 i2c_set_adapdata(adap, dev);
1183 adap->owner = THIS_MODULE;
1184 adap->class = I2C_CLASS_HWMON;
1185 strlcpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
1186 adap->algo = &omap_i2c_algo;
1187 adap->dev.parent = &pdev->dev;
1188 adap->dev.of_node = pdev->dev.of_node;
1189
1190 /* i2c device drivers may be active on return from add_adapter() */
1191 adap->nr = pdev->id;
1192 r = i2c_add_numbered_adapter(adap);
1193 if (r) {
1194 dev_err(dev->dev, "failure adding adapter\n");
1195 goto err_unuse_clocks;
1196 }
1197
1198 dev_info(dev->dev, "bus %d rev%d.%d.%d at %d kHz\n", adap->nr,
1199 dev->dtrev, dev->rev >> 4, dev->rev & 0xf, dev->speed);
1200
1201 of_i2c_register_devices(adap);
1202
1203 pm_runtime_mark_last_busy(dev->dev);
1204 pm_runtime_put_autosuspend(dev->dev);
1205
1206 return 0;
1207
1208 err_unuse_clocks:
1209 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
1210 pm_runtime_put(dev->dev);
1211 pm_runtime_disable(&pdev->dev);
1212 err_free_mem:
1213 platform_set_drvdata(pdev, NULL);
1214
1215 return r;
1216 }
1217
1218 static int __devexit omap_i2c_remove(struct platform_device *pdev)
1219 {
1220 struct omap_i2c_dev *dev = platform_get_drvdata(pdev);
1221 int ret;
1222
1223 platform_set_drvdata(pdev, NULL);
1224
1225 i2c_del_adapter(&dev->adapter);
1226 ret = pm_runtime_get_sync(&pdev->dev);
1227 if (IS_ERR_VALUE(ret))
1228 return ret;
1229
1230 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
1231 pm_runtime_put(&pdev->dev);
1232 pm_runtime_disable(&pdev->dev);
1233 return 0;
1234 }
1235
1236 #ifdef CONFIG_PM
1237 #ifdef CONFIG_PM_RUNTIME
1238 static int omap_i2c_runtime_suspend(struct device *dev)
1239 {
1240 struct platform_device *pdev = to_platform_device(dev);
1241 struct omap_i2c_dev *_dev = platform_get_drvdata(pdev);
1242 u16 iv;
1243
1244 _dev->iestate = omap_i2c_read_reg(_dev, OMAP_I2C_IE_REG);
1245
1246 omap_i2c_write_reg(_dev, OMAP_I2C_IE_REG, 0);
1247
1248 if (_dev->rev < OMAP_I2C_OMAP1_REV_2) {
1249 iv = omap_i2c_read_reg(_dev, OMAP_I2C_IV_REG); /* Read clears */
1250 } else {
1251 omap_i2c_write_reg(_dev, OMAP_I2C_STAT_REG, _dev->iestate);
1252
1253 /* Flush posted write */
1254 omap_i2c_read_reg(_dev, OMAP_I2C_STAT_REG);
1255 }
1256
1257 return 0;
1258 }
1259
1260 static int omap_i2c_runtime_resume(struct device *dev)
1261 {
1262 struct platform_device *pdev = to_platform_device(dev);
1263 struct omap_i2c_dev *_dev = platform_get_drvdata(pdev);
1264
1265 if (_dev->flags & OMAP_I2C_FLAG_RESET_REGS_POSTIDLE) {
1266 omap_i2c_write_reg(_dev, OMAP_I2C_CON_REG, 0);
1267 omap_i2c_write_reg(_dev, OMAP_I2C_PSC_REG, _dev->pscstate);
1268 omap_i2c_write_reg(_dev, OMAP_I2C_SCLL_REG, _dev->scllstate);
1269 omap_i2c_write_reg(_dev, OMAP_I2C_SCLH_REG, _dev->sclhstate);
1270 omap_i2c_write_reg(_dev, OMAP_I2C_BUF_REG, _dev->bufstate);
1271 omap_i2c_write_reg(_dev, OMAP_I2C_SYSC_REG, _dev->syscstate);
1272 omap_i2c_write_reg(_dev, OMAP_I2C_WE_REG, _dev->westate);
1273 omap_i2c_write_reg(_dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
1274 }
1275
1276 /*
1277 * Don't write to this register if the IE state is 0 as it can
1278 * cause deadlock.
1279 */
1280 if (_dev->iestate)
1281 omap_i2c_write_reg(_dev, OMAP_I2C_IE_REG, _dev->iestate);
1282
1283 return 0;
1284 }
1285 #endif /* CONFIG_PM_RUNTIME */
1286
1287 static struct dev_pm_ops omap_i2c_pm_ops = {
1288 SET_RUNTIME_PM_OPS(omap_i2c_runtime_suspend,
1289 omap_i2c_runtime_resume, NULL)
1290 };
1291 #define OMAP_I2C_PM_OPS (&omap_i2c_pm_ops)
1292 #else
1293 #define OMAP_I2C_PM_OPS NULL
1294 #endif /* CONFIG_PM */
1295
1296 static struct platform_driver omap_i2c_driver = {
1297 .probe = omap_i2c_probe,
1298 .remove = __devexit_p(omap_i2c_remove),
1299 .driver = {
1300 .name = "omap_i2c",
1301 .owner = THIS_MODULE,
1302 .pm = OMAP_I2C_PM_OPS,
1303 .of_match_table = of_match_ptr(omap_i2c_of_match),
1304 },
1305 };
1306
1307 /* I2C may be needed to bring up other drivers */
1308 static int __init
1309 omap_i2c_init_driver(void)
1310 {
1311 return platform_driver_register(&omap_i2c_driver);
1312 }
1313 subsys_initcall(omap_i2c_init_driver);
1314
1315 static void __exit omap_i2c_exit_driver(void)
1316 {
1317 platform_driver_unregister(&omap_i2c_driver);
1318 }
1319 module_exit(omap_i2c_exit_driver);
1320
1321 MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
1322 MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
1323 MODULE_LICENSE("GPL");
1324 MODULE_ALIAS("platform:omap_i2c");
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