2 * Freescale MXS I2C bus driver
4 * Copyright (C) 2011-2012 Wolfram Sang, Pengutronix e.K.
6 * based on a (non-working) driver which was:
8 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
17 #include <linux/slab.h>
18 #include <linux/device.h>
19 #include <linux/module.h>
20 #include <linux/i2c.h>
21 #include <linux/err.h>
22 #include <linux/interrupt.h>
23 #include <linux/completion.h>
24 #include <linux/platform_device.h>
25 #include <linux/jiffies.h>
27 #include <linux/pinctrl/consumer.h>
28 #include <linux/stmp_device.h>
30 #include <linux/of_device.h>
31 #include <linux/of_i2c.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/dmaengine.h>
34 #include <linux/fsl/mxs-dma.h>
36 #define DRIVER_NAME "mxs-i2c"
38 #define MXS_I2C_CTRL0 (0x00)
39 #define MXS_I2C_CTRL0_SET (0x04)
41 #define MXS_I2C_CTRL0_SFTRST 0x80000000
42 #define MXS_I2C_CTRL0_SEND_NAK_ON_LAST 0x02000000
43 #define MXS_I2C_CTRL0_RETAIN_CLOCK 0x00200000
44 #define MXS_I2C_CTRL0_POST_SEND_STOP 0x00100000
45 #define MXS_I2C_CTRL0_PRE_SEND_START 0x00080000
46 #define MXS_I2C_CTRL0_MASTER_MODE 0x00020000
47 #define MXS_I2C_CTRL0_DIRECTION 0x00010000
48 #define MXS_I2C_CTRL0_XFER_COUNT(v) ((v) & 0x0000FFFF)
50 #define MXS_I2C_TIMING0 (0x10)
51 #define MXS_I2C_TIMING1 (0x20)
52 #define MXS_I2C_TIMING2 (0x30)
54 #define MXS_I2C_CTRL1 (0x40)
55 #define MXS_I2C_CTRL1_SET (0x44)
56 #define MXS_I2C_CTRL1_CLR (0x48)
58 #define MXS_I2C_CTRL1_BUS_FREE_IRQ 0x80
59 #define MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 0x40
60 #define MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ 0x20
61 #define MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ 0x10
62 #define MXS_I2C_CTRL1_EARLY_TERM_IRQ 0x08
63 #define MXS_I2C_CTRL1_MASTER_LOSS_IRQ 0x04
64 #define MXS_I2C_CTRL1_SLAVE_STOP_IRQ 0x02
65 #define MXS_I2C_CTRL1_SLAVE_IRQ 0x01
67 #define MXS_I2C_IRQ_MASK (MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ | \
68 MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ | \
69 MXS_I2C_CTRL1_EARLY_TERM_IRQ | \
70 MXS_I2C_CTRL1_MASTER_LOSS_IRQ | \
71 MXS_I2C_CTRL1_SLAVE_STOP_IRQ | \
72 MXS_I2C_CTRL1_SLAVE_IRQ)
75 #define MXS_CMD_I2C_SELECT (MXS_I2C_CTRL0_RETAIN_CLOCK | \
76 MXS_I2C_CTRL0_PRE_SEND_START | \
77 MXS_I2C_CTRL0_MASTER_MODE | \
78 MXS_I2C_CTRL0_DIRECTION | \
79 MXS_I2C_CTRL0_XFER_COUNT(1))
81 #define MXS_CMD_I2C_WRITE (MXS_I2C_CTRL0_PRE_SEND_START | \
82 MXS_I2C_CTRL0_MASTER_MODE | \
83 MXS_I2C_CTRL0_DIRECTION)
85 #define MXS_CMD_I2C_READ (MXS_I2C_CTRL0_SEND_NAK_ON_LAST | \
86 MXS_I2C_CTRL0_MASTER_MODE)
88 struct mxs_i2c_speed_config
{
95 * Timing values for the default 24MHz clock supplied into the i2c block.
97 * The bus can operate at 95kHz or at 400kHz with the following timing
98 * register configurations. The 100kHz mode isn't present because it's
99 * values are not stated in the i.MX233/i.MX28 datasheet. The 95kHz mode
100 * shall be close enough replacement. Therefore when the bus is configured
101 * for 100kHz operation, 95kHz timing settings are actually loaded.
103 * For details, see i.MX233 [25.4.2 - 25.4.4] and i.MX28 [27.5.2 - 27.5.4].
105 static const struct mxs_i2c_speed_config mxs_i2c_95kHz_config
= {
106 .timing0
= 0x00780030,
107 .timing1
= 0x00800030,
108 .timing2
= 0x00300030,
111 static const struct mxs_i2c_speed_config mxs_i2c_400kHz_config
= {
112 .timing0
= 0x000f0007,
113 .timing1
= 0x001f000f,
114 .timing2
= 0x00300030,
118 * struct mxs_i2c_dev - per device, private MXS-I2C data
120 * @dev: driver model device node
121 * @regs: IO registers pointer
122 * @cmd_complete: completion object for transaction wait
123 * @cmd_err: error code for last transaction
124 * @adapter: i2c subsystem adapter node
129 struct completion cmd_complete
;
131 struct i2c_adapter adapter
;
132 const struct mxs_i2c_speed_config
*speed
;
134 /* DMA support components */
136 struct dma_chan
*dmach
;
137 struct mxs_dma_data dma_data
;
138 uint32_t pio_data
[2];
140 struct scatterlist sg_io
[2];
144 static void mxs_i2c_reset(struct mxs_i2c_dev
*i2c
)
146 stmp_reset_block(i2c
->regs
);
148 writel(i2c
->speed
->timing0
, i2c
->regs
+ MXS_I2C_TIMING0
);
149 writel(i2c
->speed
->timing1
, i2c
->regs
+ MXS_I2C_TIMING1
);
150 writel(i2c
->speed
->timing2
, i2c
->regs
+ MXS_I2C_TIMING2
);
152 writel(MXS_I2C_IRQ_MASK
<< 8, i2c
->regs
+ MXS_I2C_CTRL1_SET
);
155 static void mxs_i2c_dma_finish(struct mxs_i2c_dev
*i2c
)
158 dma_unmap_sg(i2c
->dev
, &i2c
->sg_io
[0], 1, DMA_TO_DEVICE
);
159 dma_unmap_sg(i2c
->dev
, &i2c
->sg_io
[1], 1, DMA_FROM_DEVICE
);
161 dma_unmap_sg(i2c
->dev
, i2c
->sg_io
, 2, DMA_TO_DEVICE
);
165 static void mxs_i2c_dma_irq_callback(void *param
)
167 struct mxs_i2c_dev
*i2c
= param
;
169 complete(&i2c
->cmd_complete
);
170 mxs_i2c_dma_finish(i2c
);
173 static int mxs_i2c_dma_setup_xfer(struct i2c_adapter
*adap
,
174 struct i2c_msg
*msg
, uint32_t flags
)
176 struct dma_async_tx_descriptor
*desc
;
177 struct mxs_i2c_dev
*i2c
= i2c_get_adapdata(adap
);
179 if (msg
->flags
& I2C_M_RD
) {
181 i2c
->addr_data
= (msg
->addr
<< 1) | I2C_SMBUS_READ
;
187 /* Queue the PIO register write transfer. */
188 i2c
->pio_data
[0] = MXS_CMD_I2C_SELECT
;
189 desc
= dmaengine_prep_slave_sg(i2c
->dmach
,
190 (struct scatterlist
*)&i2c
->pio_data
[0],
191 1, DMA_TRANS_NONE
, 0);
194 "Failed to get PIO reg. write descriptor.\n");
195 goto select_init_pio_fail
;
198 /* Queue the DMA data transfer. */
199 sg_init_one(&i2c
->sg_io
[0], &i2c
->addr_data
, 1);
200 dma_map_sg(i2c
->dev
, &i2c
->sg_io
[0], 1, DMA_TO_DEVICE
);
201 desc
= dmaengine_prep_slave_sg(i2c
->dmach
, &i2c
->sg_io
[0], 1,
203 DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
206 "Failed to get DMA data write descriptor.\n");
207 goto select_init_dma_fail
;
214 /* Queue the PIO register write transfer. */
215 i2c
->pio_data
[1] = flags
| MXS_CMD_I2C_READ
|
216 MXS_I2C_CTRL0_XFER_COUNT(msg
->len
);
217 desc
= dmaengine_prep_slave_sg(i2c
->dmach
,
218 (struct scatterlist
*)&i2c
->pio_data
[1],
219 1, DMA_TRANS_NONE
, DMA_PREP_INTERRUPT
);
222 "Failed to get PIO reg. write descriptor.\n");
223 goto select_init_dma_fail
;
226 /* Queue the DMA data transfer. */
227 sg_init_one(&i2c
->sg_io
[1], msg
->buf
, msg
->len
);
228 dma_map_sg(i2c
->dev
, &i2c
->sg_io
[1], 1, DMA_FROM_DEVICE
);
229 desc
= dmaengine_prep_slave_sg(i2c
->dmach
, &i2c
->sg_io
[1], 1,
231 DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
234 "Failed to get DMA data write descriptor.\n");
235 goto read_init_dma_fail
;
239 i2c
->addr_data
= (msg
->addr
<< 1) | I2C_SMBUS_WRITE
;
245 /* Queue the PIO register write transfer. */
246 i2c
->pio_data
[0] = flags
| MXS_CMD_I2C_WRITE
|
247 MXS_I2C_CTRL0_XFER_COUNT(msg
->len
+ 1);
248 desc
= dmaengine_prep_slave_sg(i2c
->dmach
,
249 (struct scatterlist
*)&i2c
->pio_data
[0],
250 1, DMA_TRANS_NONE
, 0);
253 "Failed to get PIO reg. write descriptor.\n");
254 goto write_init_pio_fail
;
257 /* Queue the DMA data transfer. */
258 sg_init_table(i2c
->sg_io
, 2);
259 sg_set_buf(&i2c
->sg_io
[0], &i2c
->addr_data
, 1);
260 sg_set_buf(&i2c
->sg_io
[1], msg
->buf
, msg
->len
);
261 dma_map_sg(i2c
->dev
, i2c
->sg_io
, 2, DMA_TO_DEVICE
);
262 desc
= dmaengine_prep_slave_sg(i2c
->dmach
, i2c
->sg_io
, 2,
264 DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
267 "Failed to get DMA data write descriptor.\n");
268 goto write_init_dma_fail
;
273 * The last descriptor must have this callback,
274 * to finish the DMA transaction.
276 desc
->callback
= mxs_i2c_dma_irq_callback
;
277 desc
->callback_param
= i2c
;
279 /* Start the transfer. */
280 dmaengine_submit(desc
);
281 dma_async_issue_pending(i2c
->dmach
);
286 dma_unmap_sg(i2c
->dev
, &i2c
->sg_io
[1], 1, DMA_FROM_DEVICE
);
287 select_init_dma_fail
:
288 dma_unmap_sg(i2c
->dev
, &i2c
->sg_io
[0], 1, DMA_TO_DEVICE
);
289 select_init_pio_fail
:
290 dmaengine_terminate_all(i2c
->dmach
);
293 /* Write failpath. */
295 dma_unmap_sg(i2c
->dev
, i2c
->sg_io
, 2, DMA_TO_DEVICE
);
297 dmaengine_terminate_all(i2c
->dmach
);
302 * Low level master read/write transaction.
304 static int mxs_i2c_xfer_msg(struct i2c_adapter
*adap
, struct i2c_msg
*msg
,
307 struct mxs_i2c_dev
*i2c
= i2c_get_adapdata(adap
);
311 flags
= stop
? MXS_I2C_CTRL0_POST_SEND_STOP
: 0;
313 dev_dbg(i2c
->dev
, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
314 msg
->addr
, msg
->len
, msg
->flags
, stop
);
319 init_completion(&i2c
->cmd_complete
);
322 ret
= mxs_i2c_dma_setup_xfer(adap
, msg
, flags
);
326 ret
= wait_for_completion_timeout(&i2c
->cmd_complete
,
327 msecs_to_jiffies(1000));
331 if (i2c
->cmd_err
== -ENXIO
)
334 dev_dbg(i2c
->dev
, "Done with err=%d\n", i2c
->cmd_err
);
339 dev_dbg(i2c
->dev
, "Timeout!\n");
340 mxs_i2c_dma_finish(i2c
);
345 static int mxs_i2c_xfer(struct i2c_adapter
*adap
, struct i2c_msg msgs
[],
351 for (i
= 0; i
< num
; i
++) {
352 err
= mxs_i2c_xfer_msg(adap
, &msgs
[i
], i
== (num
- 1));
360 static u32
mxs_i2c_func(struct i2c_adapter
*adap
)
362 return I2C_FUNC_I2C
| (I2C_FUNC_SMBUS_EMUL
& ~I2C_FUNC_SMBUS_QUICK
);
365 static irqreturn_t
mxs_i2c_isr(int this_irq
, void *dev_id
)
367 struct mxs_i2c_dev
*i2c
= dev_id
;
368 u32 stat
= readl(i2c
->regs
+ MXS_I2C_CTRL1
) & MXS_I2C_IRQ_MASK
;
373 if (stat
& MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ
)
374 i2c
->cmd_err
= -ENXIO
;
375 else if (stat
& (MXS_I2C_CTRL1_EARLY_TERM_IRQ
|
376 MXS_I2C_CTRL1_MASTER_LOSS_IRQ
|
377 MXS_I2C_CTRL1_SLAVE_STOP_IRQ
| MXS_I2C_CTRL1_SLAVE_IRQ
))
378 /* MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ is only for slaves */
381 writel(stat
, i2c
->regs
+ MXS_I2C_CTRL1_CLR
);
386 static const struct i2c_algorithm mxs_i2c_algo
= {
387 .master_xfer
= mxs_i2c_xfer
,
388 .functionality
= mxs_i2c_func
,
391 static bool mxs_i2c_dma_filter(struct dma_chan
*chan
, void *param
)
393 struct mxs_i2c_dev
*i2c
= param
;
395 if (!mxs_dma_is_apbx(chan
))
398 if (chan
->chan_id
!= i2c
->dma_channel
)
401 chan
->private = &i2c
->dma_data
;
406 static int mxs_i2c_get_ofdata(struct mxs_i2c_dev
*i2c
)
409 struct device
*dev
= i2c
->dev
;
410 struct device_node
*node
= dev
->of_node
;
414 * TODO: This is a temporary solution and should be changed
415 * to use generic DMA binding later when the helpers get in.
417 ret
= of_property_read_u32(node
, "fsl,i2c-dma-channel",
420 dev_err(dev
, "Failed to get DMA channel!\n");
424 ret
= of_property_read_u32(node
, "clock-frequency", &speed
);
426 dev_warn(dev
, "No I2C speed selected, using 100kHz\n");
427 else if (speed
== 400000)
428 i2c
->speed
= &mxs_i2c_400kHz_config
;
429 else if (speed
!= 100000)
430 dev_warn(dev
, "Unsupported I2C speed selected, using 100kHz\n");
435 static int __devinit
mxs_i2c_probe(struct platform_device
*pdev
)
437 struct device
*dev
= &pdev
->dev
;
438 struct mxs_i2c_dev
*i2c
;
439 struct i2c_adapter
*adap
;
440 struct pinctrl
*pinctrl
;
441 struct resource
*res
;
442 resource_size_t res_size
;
443 int err
, irq
, dmairq
;
446 pinctrl
= devm_pinctrl_get_select_default(dev
);
448 return PTR_ERR(pinctrl
);
450 i2c
= devm_kzalloc(dev
, sizeof(struct mxs_i2c_dev
), GFP_KERNEL
);
454 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
455 irq
= platform_get_irq(pdev
, 0);
456 dmairq
= platform_get_irq(pdev
, 1);
458 if (!res
|| irq
< 0 || dmairq
< 0)
461 res_size
= resource_size(res
);
462 if (!devm_request_mem_region(dev
, res
->start
, res_size
, res
->name
))
465 i2c
->regs
= devm_ioremap_nocache(dev
, res
->start
, res_size
);
469 err
= devm_request_irq(dev
, irq
, mxs_i2c_isr
, 0, dev_name(dev
), i2c
);
474 i2c
->speed
= &mxs_i2c_95kHz_config
;
477 err
= mxs_i2c_get_ofdata(i2c
);
484 dma_cap_set(DMA_SLAVE
, mask
);
485 i2c
->dma_data
.chan_irq
= dmairq
;
486 i2c
->dmach
= dma_request_channel(mask
, mxs_i2c_dma_filter
, i2c
);
488 dev_err(dev
, "Failed to request dma\n");
492 platform_set_drvdata(pdev
, i2c
);
494 /* Do reset to enforce correct startup after pinmuxing */
497 adap
= &i2c
->adapter
;
498 strlcpy(adap
->name
, "MXS I2C adapter", sizeof(adap
->name
));
499 adap
->owner
= THIS_MODULE
;
500 adap
->algo
= &mxs_i2c_algo
;
501 adap
->dev
.parent
= dev
;
503 adap
->dev
.of_node
= pdev
->dev
.of_node
;
504 i2c_set_adapdata(adap
, i2c
);
505 err
= i2c_add_numbered_adapter(adap
);
507 dev_err(dev
, "Failed to add adapter (%d)\n", err
);
508 writel(MXS_I2C_CTRL0_SFTRST
,
509 i2c
->regs
+ MXS_I2C_CTRL0_SET
);
513 of_i2c_register_devices(adap
);
518 static int __devexit
mxs_i2c_remove(struct platform_device
*pdev
)
520 struct mxs_i2c_dev
*i2c
= platform_get_drvdata(pdev
);
523 ret
= i2c_del_adapter(&i2c
->adapter
);
528 dma_release_channel(i2c
->dmach
);
530 writel(MXS_I2C_CTRL0_SFTRST
, i2c
->regs
+ MXS_I2C_CTRL0_SET
);
532 platform_set_drvdata(pdev
, NULL
);
537 static const struct of_device_id mxs_i2c_dt_ids
[] = {
538 { .compatible
= "fsl,imx28-i2c", },
541 MODULE_DEVICE_TABLE(of
, mxs_i2c_dt_ids
);
543 static struct platform_driver mxs_i2c_driver
= {
546 .owner
= THIS_MODULE
,
547 .of_match_table
= mxs_i2c_dt_ids
,
549 .remove
= __devexit_p(mxs_i2c_remove
),
552 static int __init
mxs_i2c_init(void)
554 return platform_driver_probe(&mxs_i2c_driver
, mxs_i2c_probe
);
556 subsys_initcall(mxs_i2c_init
);
558 static void __exit
mxs_i2c_exit(void)
560 platform_driver_unregister(&mxs_i2c_driver
);
562 module_exit(mxs_i2c_exit
);
564 MODULE_AUTHOR("Wolfram Sang <w.sang@pengutronix.de>");
565 MODULE_DESCRIPTION("MXS I2C Bus Driver");
566 MODULE_LICENSE("GPL");
567 MODULE_ALIAS("platform:" DRIVER_NAME
);