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ARM: plat-nomadik: Introduce new DB8540 GPIO registers
[linux-2.6.git] / lib / mpi / longlong.h
blob678ce4f1e124b4be4c255f297cef1e29477e7ce0
1 /* longlong.h -- definitions for mixed size 32/64 bit arithmetic.
2 * Note: I added some stuff for use with gnupg
3 *
4 * Copyright (C) 1991, 1992, 1993, 1994, 1996, 1998,
5 * 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
6 *
7 * This file is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU Library General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * This file is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Library General Public
15 * License for more details.
16 *
17 * You should have received a copy of the GNU Library General Public License
18 * along with this file; see the file COPYING.LIB. If not, write to
19 * the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston,
20 * MA 02111-1307, USA. */
21
22 #include <asm-generic/bitops/count_zeros.h>
23
24 /* You have to define the following before including this file:
25 *
26 * UWtype -- An unsigned type, default type for operations (typically a "word")
27 * UHWtype -- An unsigned type, at least half the size of UWtype.
28 * UDWtype -- An unsigned type, at least twice as large a UWtype
29 * W_TYPE_SIZE -- size in bits of UWtype
30 *
31 * SItype, USItype -- Signed and unsigned 32 bit types.
32 * DItype, UDItype -- Signed and unsigned 64 bit types.
33 *
34 * On a 32 bit machine UWtype should typically be USItype;
35 * on a 64 bit machine, UWtype should typically be UDItype.
36 */
37
38 #define __BITS4 (W_TYPE_SIZE / 4)
39 #define __ll_B ((UWtype) 1 << (W_TYPE_SIZE / 2))
40 #define __ll_lowpart(t) ((UWtype) (t) & (__ll_B - 1))
41 #define __ll_highpart(t) ((UWtype) (t) >> (W_TYPE_SIZE / 2))
42
43 /* This is used to make sure no undesirable sharing between different libraries
44 that use this file takes place. */
45 #ifndef __MPN
46 #define __MPN(x) __##x
47 #endif
48
49 /* Define auxiliary asm macros.
50 *
51 * 1) umul_ppmm(high_prod, low_prod, multipler, multiplicand) multiplies two
52 * UWtype integers MULTIPLER and MULTIPLICAND, and generates a two UWtype
53 * word product in HIGH_PROD and LOW_PROD.
54 *
55 * 2) __umulsidi3(a,b) multiplies two UWtype integers A and B, and returns a
56 * UDWtype product. This is just a variant of umul_ppmm.
57
58 * 3) udiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
59 * denominator) divides a UDWtype, composed by the UWtype integers
60 * HIGH_NUMERATOR and LOW_NUMERATOR, by DENOMINATOR and places the quotient
61 * in QUOTIENT and the remainder in REMAINDER. HIGH_NUMERATOR must be less
62 * than DENOMINATOR for correct operation. If, in addition, the most
63 * significant bit of DENOMINATOR must be 1, then the pre-processor symbol
64 * UDIV_NEEDS_NORMALIZATION is defined to 1.
65 * 4) sdiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
66 * denominator). Like udiv_qrnnd but the numbers are signed. The quotient
67 * is rounded towards 0.
68 *
69 * 5) count_leading_zeros(count, x) counts the number of zero-bits from the
70 * msb to the first non-zero bit in the UWtype X. This is the number of
71 * steps X needs to be shifted left to set the msb. Undefined for X == 0,
72 * unless the symbol COUNT_LEADING_ZEROS_0 is defined to some value.
73 *
74 * 6) count_trailing_zeros(count, x) like count_leading_zeros, but counts
75 * from the least significant end.
76 *
77 * 7) add_ssaaaa(high_sum, low_sum, high_addend_1, low_addend_1,
78 * high_addend_2, low_addend_2) adds two UWtype integers, composed by
79 * HIGH_ADDEND_1 and LOW_ADDEND_1, and HIGH_ADDEND_2 and LOW_ADDEND_2
80 * respectively. The result is placed in HIGH_SUM and LOW_SUM. Overflow
81 * (i.e. carry out) is not stored anywhere, and is lost.
82 *
83 * 8) sub_ddmmss(high_difference, low_difference, high_minuend, low_minuend,
84 * high_subtrahend, low_subtrahend) subtracts two two-word UWtype integers,
85 * composed by HIGH_MINUEND_1 and LOW_MINUEND_1, and HIGH_SUBTRAHEND_2 and
86 * LOW_SUBTRAHEND_2 respectively. The result is placed in HIGH_DIFFERENCE
87 * and LOW_DIFFERENCE. Overflow (i.e. carry out) is not stored anywhere,
88 * and is lost.
89 *
90 * If any of these macros are left undefined for a particular CPU,
91 * C macros are used. */
92
93 /* The CPUs come in alphabetical order below.
94 *
95 * Please add support for more CPUs here, or improve the current support
96 * for the CPUs below! */
97
98 #if defined(__GNUC__) && !defined(NO_ASM)
99
100 /* We sometimes need to clobber "cc" with gcc2, but that would not be
101 understood by gcc1. Use cpp to avoid major code duplication. */
102 #if __GNUC__ < 2
103 #define __CLOBBER_CC
104 #define __AND_CLOBBER_CC
105 #else /* __GNUC__ >= 2 */
106 #define __CLOBBER_CC : "cc"
107 #define __AND_CLOBBER_CC , "cc"
108 #endif /* __GNUC__ < 2 */
109
110 /***************************************
111 ************** A29K *****************
112 ***************************************/
113 #if (defined(__a29k__) || defined(_AM29K)) && W_TYPE_SIZE == 32
114 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
115 __asm__ ("add %1,%4,%5\n" \
116 "addc %0,%2,%3" \
117 : "=r" ((USItype)(sh)), \
118 "=&r" ((USItype)(sl)) \
119 : "%r" ((USItype)(ah)), \
120 "rI" ((USItype)(bh)), \
121 "%r" ((USItype)(al)), \
122 "rI" ((USItype)(bl)))
123 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
124 __asm__ ("sub %1,%4,%5\n" \
125 "subc %0,%2,%3" \
126 : "=r" ((USItype)(sh)), \
127 "=&r" ((USItype)(sl)) \
128 : "r" ((USItype)(ah)), \
129 "rI" ((USItype)(bh)), \
130 "r" ((USItype)(al)), \
131 "rI" ((USItype)(bl)))
132 #define umul_ppmm(xh, xl, m0, m1) \
133 do { \
134 USItype __m0 = (m0), __m1 = (m1); \
135 __asm__ ("multiplu %0,%1,%2" \
136 : "=r" ((USItype)(xl)) \
137 : "r" (__m0), \
138 "r" (__m1)); \
139 __asm__ ("multmu %0,%1,%2" \
140 : "=r" ((USItype)(xh)) \
141 : "r" (__m0), \
142 "r" (__m1)); \
143 } while (0)
144 #define udiv_qrnnd(q, r, n1, n0, d) \
145 __asm__ ("dividu %0,%3,%4" \
146 : "=r" ((USItype)(q)), \
147 "=q" ((USItype)(r)) \
148 : "1" ((USItype)(n1)), \
149 "r" ((USItype)(n0)), \
150 "r" ((USItype)(d)))
151 #endif /* __a29k__ */
152
153 #if defined(__alpha) && W_TYPE_SIZE == 64
154 #define umul_ppmm(ph, pl, m0, m1) \
155 do { \
156 UDItype __m0 = (m0), __m1 = (m1); \
157 __asm__ ("umulh %r1,%2,%0" \
158 : "=r" ((UDItype) ph) \
159 : "%rJ" (__m0), \
160 "rI" (__m1)); \
161 (pl) = __m0 * __m1; \
162 } while (0)
163 #define UMUL_TIME 46
164 #ifndef LONGLONG_STANDALONE
165 #define udiv_qrnnd(q, r, n1, n0, d) \
166 do { UDItype __r; \
167 (q) = __udiv_qrnnd(&__r, (n1), (n0), (d)); \
168 (r) = __r; \
169 } while (0)
170 extern UDItype __udiv_qrnnd();
171 #define UDIV_TIME 220
172 #endif /* LONGLONG_STANDALONE */
173 #endif /* __alpha */
174
175 /***************************************
176 ************** ARM ******************
177 ***************************************/
178 #if defined(__arm__) && W_TYPE_SIZE == 32
179 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
180 __asm__ ("adds %1, %4, %5\n" \
181 "adc %0, %2, %3" \
182 : "=r" ((USItype)(sh)), \
183 "=&r" ((USItype)(sl)) \
184 : "%r" ((USItype)(ah)), \
185 "rI" ((USItype)(bh)), \
186 "%r" ((USItype)(al)), \
187 "rI" ((USItype)(bl)))
188 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
189 __asm__ ("subs %1, %4, %5\n" \
190 "sbc %0, %2, %3" \
191 : "=r" ((USItype)(sh)), \
192 "=&r" ((USItype)(sl)) \
193 : "r" ((USItype)(ah)), \
194 "rI" ((USItype)(bh)), \
195 "r" ((USItype)(al)), \
196 "rI" ((USItype)(bl)))
197 #if defined __ARM_ARCH_2__ || defined __ARM_ARCH_3__
198 #define umul_ppmm(xh, xl, a, b) \
199 __asm__ ("%@ Inlined umul_ppmm\n" \
200 "mov %|r0, %2, lsr #16 @ AAAA\n" \
201 "mov %|r2, %3, lsr #16 @ BBBB\n" \
202 "bic %|r1, %2, %|r0, lsl #16 @ aaaa\n" \
203 "bic %0, %3, %|r2, lsl #16 @ bbbb\n" \
204 "mul %1, %|r1, %|r2 @ aaaa * BBBB\n" \
205 "mul %|r2, %|r0, %|r2 @ AAAA * BBBB\n" \
206 "mul %|r1, %0, %|r1 @ aaaa * bbbb\n" \
207 "mul %0, %|r0, %0 @ AAAA * bbbb\n" \
208 "adds %|r0, %1, %0 @ central sum\n" \
209 "addcs %|r2, %|r2, #65536\n" \
210 "adds %1, %|r1, %|r0, lsl #16\n" \
211 "adc %0, %|r2, %|r0, lsr #16" \
212 : "=&r" ((USItype)(xh)), \
213 "=r" ((USItype)(xl)) \
214 : "r" ((USItype)(a)), \
215 "r" ((USItype)(b)) \
216 : "r0", "r1", "r2")
217 #else
218 #define umul_ppmm(xh, xl, a, b) \
219 __asm__ ("%@ Inlined umul_ppmm\n" \
220 "umull %r1, %r0, %r2, %r3" \
221 : "=&r" ((USItype)(xh)), \
222 "=r" ((USItype)(xl)) \
223 : "r" ((USItype)(a)), \
224 "r" ((USItype)(b)) \
225 : "r0", "r1")
226 #endif
227 #define UMUL_TIME 20
228 #define UDIV_TIME 100
229 #endif /* __arm__ */
230
231 /***************************************
232 ************** CLIPPER **************
233 ***************************************/
234 #if defined(__clipper__) && W_TYPE_SIZE == 32
235 #define umul_ppmm(w1, w0, u, v) \
236 ({union {UDItype __ll; \
237 struct {USItype __l, __h; } __i; \
238 } __xx; \
239 __asm__ ("mulwux %2,%0" \
240 : "=r" (__xx.__ll) \
241 : "%0" ((USItype)(u)), \
242 "r" ((USItype)(v))); \
243 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l; })
244 #define smul_ppmm(w1, w0, u, v) \
245 ({union {DItype __ll; \
246 struct {SItype __l, __h; } __i; \
247 } __xx; \
248 __asm__ ("mulwx %2,%0" \
249 : "=r" (__xx.__ll) \
250 : "%0" ((SItype)(u)), \
251 "r" ((SItype)(v))); \
252 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l; })
253 #define __umulsidi3(u, v) \
254 ({UDItype __w; \
255 __asm__ ("mulwux %2,%0" \
256 : "=r" (__w) \
257 : "%0" ((USItype)(u)), \
258 "r" ((USItype)(v))); \
259 __w; })
260 #endif /* __clipper__ */
261
262 /***************************************
263 ************** GMICRO ***************
264 ***************************************/
265 #if defined(__gmicro__) && W_TYPE_SIZE == 32
266 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
267 __asm__ ("add.w %5,%1\n" \
268 "addx %3,%0" \
269 : "=g" ((USItype)(sh)), \
270 "=&g" ((USItype)(sl)) \
271 : "%0" ((USItype)(ah)), \
272 "g" ((USItype)(bh)), \
273 "%1" ((USItype)(al)), \
274 "g" ((USItype)(bl)))
275 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
276 __asm__ ("sub.w %5,%1\n" \
277 "subx %3,%0" \
278 : "=g" ((USItype)(sh)), \
279 "=&g" ((USItype)(sl)) \
280 : "0" ((USItype)(ah)), \
281 "g" ((USItype)(bh)), \
282 "1" ((USItype)(al)), \
283 "g" ((USItype)(bl)))
284 #define umul_ppmm(ph, pl, m0, m1) \
285 __asm__ ("mulx %3,%0,%1" \
286 : "=g" ((USItype)(ph)), \
287 "=r" ((USItype)(pl)) \
288 : "%0" ((USItype)(m0)), \
289 "g" ((USItype)(m1)))
290 #define udiv_qrnnd(q, r, nh, nl, d) \
291 __asm__ ("divx %4,%0,%1" \
292 : "=g" ((USItype)(q)), \
293 "=r" ((USItype)(r)) \
294 : "1" ((USItype)(nh)), \
295 "0" ((USItype)(nl)), \
296 "g" ((USItype)(d)))
297 #endif
298
299 /***************************************
300 ************** HPPA *****************
301 ***************************************/
302 #if defined(__hppa) && W_TYPE_SIZE == 32
303 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
304 __asm__ ("add %4,%5,%1\n" \
305 "addc %2,%3,%0" \
306 : "=r" ((USItype)(sh)), \
307 "=&r" ((USItype)(sl)) \
308 : "%rM" ((USItype)(ah)), \
309 "rM" ((USItype)(bh)), \
310 "%rM" ((USItype)(al)), \
311 "rM" ((USItype)(bl)))
312 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
313 __asm__ ("sub %4,%5,%1\n" \
314 "subb %2,%3,%0" \
315 : "=r" ((USItype)(sh)), \
316 "=&r" ((USItype)(sl)) \
317 : "rM" ((USItype)(ah)), \
318 "rM" ((USItype)(bh)), \
319 "rM" ((USItype)(al)), \
320 "rM" ((USItype)(bl)))
321 #if defined(_PA_RISC1_1)
322 #define umul_ppmm(wh, wl, u, v) \
323 do { \
324 union {UDItype __ll; \
325 struct {USItype __h, __l; } __i; \
326 } __xx; \
327 __asm__ ("xmpyu %1,%2,%0" \
328 : "=*f" (__xx.__ll) \
329 : "*f" ((USItype)(u)), \
330 "*f" ((USItype)(v))); \
331 (wh) = __xx.__i.__h; \
332 (wl) = __xx.__i.__l; \
333 } while (0)
334 #define UMUL_TIME 8
335 #define UDIV_TIME 60
336 #else
337 #define UMUL_TIME 40
338 #define UDIV_TIME 80
339 #endif
340 #ifndef LONGLONG_STANDALONE
341 #define udiv_qrnnd(q, r, n1, n0, d) \
342 do { USItype __r; \
343 (q) = __udiv_qrnnd(&__r, (n1), (n0), (d)); \
344 (r) = __r; \
345 } while (0)
346 extern USItype __udiv_qrnnd();
347 #endif /* LONGLONG_STANDALONE */
348 #endif /* hppa */
349
350 /***************************************
351 ************** I370 *****************
352 ***************************************/
353 #if (defined(__i370__) || defined(__mvs__)) && W_TYPE_SIZE == 32
354 #define umul_ppmm(xh, xl, m0, m1) \
355 do { \
356 union {UDItype __ll; \
357 struct {USItype __h, __l; } __i; \
358 } __xx; \
359 USItype __m0 = (m0), __m1 = (m1); \
360 __asm__ ("mr %0,%3" \
361 : "=r" (__xx.__i.__h), \
362 "=r" (__xx.__i.__l) \
363 : "%1" (__m0), \
364 "r" (__m1)); \
365 (xh) = __xx.__i.__h; (xl) = __xx.__i.__l; \
366 (xh) += ((((SItype) __m0 >> 31) & __m1) \
367 + (((SItype) __m1 >> 31) & __m0)); \
368 } while (0)
369 #define smul_ppmm(xh, xl, m0, m1) \
370 do { \
371 union {DItype __ll; \
372 struct {USItype __h, __l; } __i; \
373 } __xx; \
374 __asm__ ("mr %0,%3" \
375 : "=r" (__xx.__i.__h), \
376 "=r" (__xx.__i.__l) \
377 : "%1" (m0), \
378 "r" (m1)); \
379 (xh) = __xx.__i.__h; (xl) = __xx.__i.__l; \
380 } while (0)
381 #define sdiv_qrnnd(q, r, n1, n0, d) \
382 do { \
383 union {DItype __ll; \
384 struct {USItype __h, __l; } __i; \
385 } __xx; \
386 __xx.__i.__h = n1; __xx.__i.__l = n0; \
387 __asm__ ("dr %0,%2" \
388 : "=r" (__xx.__ll) \
389 : "0" (__xx.__ll), "r" (d)); \
390 (q) = __xx.__i.__l; (r) = __xx.__i.__h; \
391 } while (0)
392 #endif
393
394 /***************************************
395 ************** I386 *****************
396 ***************************************/
397 #undef __i386__
398 #if (defined(__i386__) || defined(__i486__)) && W_TYPE_SIZE == 32
399 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
400 __asm__ ("addl %5,%1\n" \
401 "adcl %3,%0" \
402 : "=r" ((USItype)(sh)), \
403 "=&r" ((USItype)(sl)) \
404 : "%0" ((USItype)(ah)), \
405 "g" ((USItype)(bh)), \
406 "%1" ((USItype)(al)), \
407 "g" ((USItype)(bl)))
408 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
409 __asm__ ("subl %5,%1\n" \
410 "sbbl %3,%0" \
411 : "=r" ((USItype)(sh)), \
412 "=&r" ((USItype)(sl)) \
413 : "0" ((USItype)(ah)), \
414 "g" ((USItype)(bh)), \
415 "1" ((USItype)(al)), \
416 "g" ((USItype)(bl)))
417 #define umul_ppmm(w1, w0, u, v) \
418 __asm__ ("mull %3" \
419 : "=a" ((USItype)(w0)), \
420 "=d" ((USItype)(w1)) \
421 : "%0" ((USItype)(u)), \
422 "rm" ((USItype)(v)))
423 #define udiv_qrnnd(q, r, n1, n0, d) \
424 __asm__ ("divl %4" \
425 : "=a" ((USItype)(q)), \
426 "=d" ((USItype)(r)) \
427 : "0" ((USItype)(n0)), \
428 "1" ((USItype)(n1)), \
429 "rm" ((USItype)(d)))
430 #ifndef UMUL_TIME
431 #define UMUL_TIME 40
432 #endif
433 #ifndef UDIV_TIME
434 #define UDIV_TIME 40
435 #endif
436 #endif /* 80x86 */
437
438 /***************************************
439 ************** I860 *****************
440 ***************************************/
441 #if defined(__i860__) && W_TYPE_SIZE == 32
442 #define rshift_rhlc(r, h, l, c) \
443 __asm__ ("shr %3,r0,r0\n" \
444 "shrd %1,%2,%0" \
445 "=r" (r) : "r" (h), "r" (l), "rn" (c))
446 #endif /* i860 */
447
448 /***************************************
449 ************** I960 *****************
450 ***************************************/
451 #if defined(__i960__) && W_TYPE_SIZE == 32
452 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
453 __asm__ ("cmpo 1,0\n" \
454 "addc %5,%4,%1\n" \
455 "addc %3,%2,%0" \
456 : "=r" ((USItype)(sh)), \
457 "=&r" ((USItype)(sl)) \
458 : "%dI" ((USItype)(ah)), \
459 "dI" ((USItype)(bh)), \
460 "%dI" ((USItype)(al)), \
461 "dI" ((USItype)(bl)))
462 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
463 __asm__ ("cmpo 0,0\n" \
464 "subc %5,%4,%1\n" \
465 "subc %3,%2,%0" \
466 : "=r" ((USItype)(sh)), \
467 "=&r" ((USItype)(sl)) \
468 : "dI" ((USItype)(ah)), \
469 "dI" ((USItype)(bh)), \
470 "dI" ((USItype)(al)), \
471 "dI" ((USItype)(bl)))
472 #define umul_ppmm(w1, w0, u, v) \
473 ({union {UDItype __ll; \
474 struct {USItype __l, __h; } __i; \
475 } __xx; \
476 __asm__ ("emul %2,%1,%0" \
477 : "=d" (__xx.__ll) \
478 : "%dI" ((USItype)(u)), \
479 "dI" ((USItype)(v))); \
480 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l; })
481 #define __umulsidi3(u, v) \
482 ({UDItype __w; \
483 __asm__ ("emul %2,%1,%0" \
484 : "=d" (__w) \
485 : "%dI" ((USItype)(u)), \
486 "dI" ((USItype)(v))); \
487 __w; })
488 #define udiv_qrnnd(q, r, nh, nl, d) \
489 do { \
490 union {UDItype __ll; \
491 struct {USItype __l, __h; } __i; \
492 } __nn; \
493 __nn.__i.__h = (nh); __nn.__i.__l = (nl); \
494 __asm__ ("ediv %d,%n,%0" \
495 : "=d" (__rq.__ll) \
496 : "dI" (__nn.__ll), \
497 "dI" ((USItype)(d))); \
498 (r) = __rq.__i.__l; (q) = __rq.__i.__h; \
499 } while (0)
500 #if defined(__i960mx) /* what is the proper symbol to test??? */
501 #define rshift_rhlc(r, h, l, c) \
502 do { \
503 union {UDItype __ll; \
504 struct {USItype __l, __h; } __i; \
505 } __nn; \
506 __nn.__i.__h = (h); __nn.__i.__l = (l); \
507 __asm__ ("shre %2,%1,%0" \
508 : "=d" (r) : "dI" (__nn.__ll), "dI" (c)); \
509 }
510 #endif /* i960mx */
511 #endif /* i960 */
512
513 /***************************************
514 ************** 68000 ****************
515 ***************************************/
516 #if (defined(__mc68000__) || defined(__mc68020__) || defined(__NeXT__) || defined(mc68020)) && W_TYPE_SIZE == 32
517 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
518 __asm__ ("add%.l %5,%1\n" \
519 "addx%.l %3,%0" \
520 : "=d" ((USItype)(sh)), \
521 "=&d" ((USItype)(sl)) \
522 : "%0" ((USItype)(ah)), \
523 "d" ((USItype)(bh)), \
524 "%1" ((USItype)(al)), \
525 "g" ((USItype)(bl)))
526 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
527 __asm__ ("sub%.l %5,%1\n" \
528 "subx%.l %3,%0" \
529 : "=d" ((USItype)(sh)), \
530 "=&d" ((USItype)(sl)) \
531 : "0" ((USItype)(ah)), \
532 "d" ((USItype)(bh)), \
533 "1" ((USItype)(al)), \
534 "g" ((USItype)(bl)))
535 #if (defined(__mc68020__) || defined(__NeXT__) || defined(mc68020))
536 #define umul_ppmm(w1, w0, u, v) \
537 __asm__ ("mulu%.l %3,%1:%0" \
538 : "=d" ((USItype)(w0)), \
539 "=d" ((USItype)(w1)) \
540 : "%0" ((USItype)(u)), \
541 "dmi" ((USItype)(v)))
542 #define UMUL_TIME 45
543 #define udiv_qrnnd(q, r, n1, n0, d) \
544 __asm__ ("divu%.l %4,%1:%0" \
545 : "=d" ((USItype)(q)), \
546 "=d" ((USItype)(r)) \
547 : "0" ((USItype)(n0)), \
548 "1" ((USItype)(n1)), \
549 "dmi" ((USItype)(d)))
550 #define UDIV_TIME 90
551 #define sdiv_qrnnd(q, r, n1, n0, d) \
552 __asm__ ("divs%.l %4,%1:%0" \
553 : "=d" ((USItype)(q)), \
554 "=d" ((USItype)(r)) \
555 : "0" ((USItype)(n0)), \
556 "1" ((USItype)(n1)), \
557 "dmi" ((USItype)(d)))
558 #else /* not mc68020 */
559 #define umul_ppmm(xh, xl, a, b) \
560 do { USItype __umul_tmp1, __umul_tmp2; \
561 __asm__ ("| Inlined umul_ppmm\n" \
562 "move%.l %5,%3\n" \
563 "move%.l %2,%0\n" \
564 "move%.w %3,%1\n" \
565 "swap %3\n" \
566 "swap %0\n" \
567 "mulu %2,%1\n" \
568 "mulu %3,%0\n" \
569 "mulu %2,%3\n" \
570 "swap %2\n" \
571 "mulu %5,%2\n" \
572 "add%.l %3,%2\n" \
573 "jcc 1f\n" \
574 "add%.l %#0x10000,%0\n" \
575 "1: move%.l %2,%3\n" \
576 "clr%.w %2\n" \
577 "swap %2\n" \
578 "swap %3\n" \
579 "clr%.w %3\n" \
580 "add%.l %3,%1\n" \
581 "addx%.l %2,%0\n" \
582 "| End inlined umul_ppmm" \
583 : "=&d" ((USItype)(xh)), "=&d" ((USItype)(xl)), \
584 "=d" (__umul_tmp1), "=&d" (__umul_tmp2) \
585 : "%2" ((USItype)(a)), "d" ((USItype)(b))); \
586 } while (0)
587 #define UMUL_TIME 100
588 #define UDIV_TIME 400
589 #endif /* not mc68020 */
590 #endif /* mc68000 */
591
592 /***************************************
593 ************** 88000 ****************
594 ***************************************/
595 #if defined(__m88000__) && W_TYPE_SIZE == 32
596 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
597 __asm__ ("addu.co %1,%r4,%r5\n" \
598 "addu.ci %0,%r2,%r3" \
599 : "=r" ((USItype)(sh)), \
600 "=&r" ((USItype)(sl)) \
601 : "%rJ" ((USItype)(ah)), \
602 "rJ" ((USItype)(bh)), \
603 "%rJ" ((USItype)(al)), \
604 "rJ" ((USItype)(bl)))
605 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
606 __asm__ ("subu.co %1,%r4,%r5\n" \
607 "subu.ci %0,%r2,%r3" \
608 : "=r" ((USItype)(sh)), \
609 "=&r" ((USItype)(sl)) \
610 : "rJ" ((USItype)(ah)), \
611 "rJ" ((USItype)(bh)), \
612 "rJ" ((USItype)(al)), \
613 "rJ" ((USItype)(bl)))
614 #if defined(__m88110__)
615 #define umul_ppmm(wh, wl, u, v) \
616 do { \
617 union {UDItype __ll; \
618 struct {USItype __h, __l; } __i; \
619 } __x; \
620 __asm__ ("mulu.d %0,%1,%2" : "=r" (__x.__ll) : "r" (u), "r" (v)); \
621 (wh) = __x.__i.__h; \
622 (wl) = __x.__i.__l; \
623 } while (0)
624 #define udiv_qrnnd(q, r, n1, n0, d) \
625 ({union {UDItype __ll; \
626 struct {USItype __h, __l; } __i; \
627 } __x, __q; \
628 __x.__i.__h = (n1); __x.__i.__l = (n0); \
629 __asm__ ("divu.d %0,%1,%2" \
630 : "=r" (__q.__ll) : "r" (__x.__ll), "r" (d)); \
631 (r) = (n0) - __q.__l * (d); (q) = __q.__l; })
632 #define UMUL_TIME 5
633 #define UDIV_TIME 25
634 #else
635 #define UMUL_TIME 17
636 #define UDIV_TIME 150
637 #endif /* __m88110__ */
638 #endif /* __m88000__ */
639
640 /***************************************
641 ************** MIPS *****************
642 ***************************************/
643 #if defined(__mips__) && W_TYPE_SIZE == 32
644 #if __GNUC__ > 2 || __GNUC_MINOR__ >= 7
645 #define umul_ppmm(w1, w0, u, v) \
646 __asm__ ("multu %2,%3" \
647 : "=l" ((USItype)(w0)), \
648 "=h" ((USItype)(w1)) \
649 : "d" ((USItype)(u)), \
650 "d" ((USItype)(v)))
651 #else
652 #define umul_ppmm(w1, w0, u, v) \
653 __asm__ ("multu %2,%3\n" \
654 "mflo %0\n" \
655 "mfhi %1" \
656 : "=d" ((USItype)(w0)), \
657 "=d" ((USItype)(w1)) \
658 : "d" ((USItype)(u)), \
659 "d" ((USItype)(v)))
660 #endif
661 #define UMUL_TIME 10
662 #define UDIV_TIME 100
663 #endif /* __mips__ */
664
665 /***************************************
666 ************** MIPS/64 **************
667 ***************************************/
668 #if (defined(__mips) && __mips >= 3) && W_TYPE_SIZE == 64
669 #if __GNUC__ > 2 || __GNUC_MINOR__ >= 7
670 #define umul_ppmm(w1, w0, u, v) \
671 __asm__ ("dmultu %2,%3" \
672 : "=l" ((UDItype)(w0)), \
673 "=h" ((UDItype)(w1)) \
674 : "d" ((UDItype)(u)), \
675 "d" ((UDItype)(v)))
676 #else
677 #define umul_ppmm(w1, w0, u, v) \
678 __asm__ ("dmultu %2,%3\n" \
679 "mflo %0\n" \
680 "mfhi %1" \
681 : "=d" ((UDItype)(w0)), \
682 "=d" ((UDItype)(w1)) \
683 : "d" ((UDItype)(u)), \
684 "d" ((UDItype)(v)))
685 #endif
686 #define UMUL_TIME 20
687 #define UDIV_TIME 140
688 #endif /* __mips__ */
689
690 /***************************************
691 ************** 32000 ****************
692 ***************************************/
693 #if defined(__ns32000__) && W_TYPE_SIZE == 32
694 #define umul_ppmm(w1, w0, u, v) \
695 ({union {UDItype __ll; \
696 struct {USItype __l, __h; } __i; \
697 } __xx; \
698 __asm__ ("meid %2,%0" \
699 : "=g" (__xx.__ll) \
700 : "%0" ((USItype)(u)), \
701 "g" ((USItype)(v))); \
702 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l; })
703 #define __umulsidi3(u, v) \
704 ({UDItype __w; \
705 __asm__ ("meid %2,%0" \
706 : "=g" (__w) \
707 : "%0" ((USItype)(u)), \
708 "g" ((USItype)(v))); \
709 __w; })
710 #define udiv_qrnnd(q, r, n1, n0, d) \
711 ({union {UDItype __ll; \
712 struct {USItype __l, __h; } __i; \
713 } __xx; \
714 __xx.__i.__h = (n1); __xx.__i.__l = (n0); \
715 __asm__ ("deid %2,%0" \
716 : "=g" (__xx.__ll) \
717 : "0" (__xx.__ll), \
718 "g" ((USItype)(d))); \
719 (r) = __xx.__i.__l; (q) = __xx.__i.__h; })
720 #endif /* __ns32000__ */
721
722 /***************************************
723 ************** PPC ******************
724 ***************************************/
725 #if (defined(_ARCH_PPC) || defined(_IBMR2)) && W_TYPE_SIZE == 32
726 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
727 do { \
728 if (__builtin_constant_p(bh) && (bh) == 0) \
729 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2" \
730 : "=r" ((USItype)(sh)), \
731 "=&r" ((USItype)(sl)) \
732 : "%r" ((USItype)(ah)), \
733 "%r" ((USItype)(al)), \
734 "rI" ((USItype)(bl))); \
735 else if (__builtin_constant_p(bh) && (bh) == ~(USItype) 0) \
736 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2" \
737 : "=r" ((USItype)(sh)), \
738 "=&r" ((USItype)(sl)) \
739 : "%r" ((USItype)(ah)), \
740 "%r" ((USItype)(al)), \
741 "rI" ((USItype)(bl))); \
742 else \
743 __asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3" \
744 : "=r" ((USItype)(sh)), \
745 "=&r" ((USItype)(sl)) \
746 : "%r" ((USItype)(ah)), \
747 "r" ((USItype)(bh)), \
748 "%r" ((USItype)(al)), \
749 "rI" ((USItype)(bl))); \
750 } while (0)
751 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
752 do { \
753 if (__builtin_constant_p(ah) && (ah) == 0) \
754 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2" \
755 : "=r" ((USItype)(sh)), \
756 "=&r" ((USItype)(sl)) \
757 : "r" ((USItype)(bh)), \
758 "rI" ((USItype)(al)), \
759 "r" ((USItype)(bl))); \
760 else if (__builtin_constant_p(ah) && (ah) == ~(USItype) 0) \
761 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2" \
762 : "=r" ((USItype)(sh)), \
763 "=&r" ((USItype)(sl)) \
764 : "r" ((USItype)(bh)), \
765 "rI" ((USItype)(al)), \
766 "r" ((USItype)(bl))); \
767 else if (__builtin_constant_p(bh) && (bh) == 0) \
768 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2" \
769 : "=r" ((USItype)(sh)), \
770 "=&r" ((USItype)(sl)) \
771 : "r" ((USItype)(ah)), \
772 "rI" ((USItype)(al)), \
773 "r" ((USItype)(bl))); \
774 else if (__builtin_constant_p(bh) && (bh) == ~(USItype) 0) \
775 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2" \
776 : "=r" ((USItype)(sh)), \
777 "=&r" ((USItype)(sl)) \
778 : "r" ((USItype)(ah)), \
779 "rI" ((USItype)(al)), \
780 "r" ((USItype)(bl))); \
781 else \
782 __asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2" \
783 : "=r" ((USItype)(sh)), \
784 "=&r" ((USItype)(sl)) \
785 : "r" ((USItype)(ah)), \
786 "r" ((USItype)(bh)), \
787 "rI" ((USItype)(al)), \
788 "r" ((USItype)(bl))); \
789 } while (0)
790 #if defined(_ARCH_PPC)
791 #define umul_ppmm(ph, pl, m0, m1) \
792 do { \
793 USItype __m0 = (m0), __m1 = (m1); \
794 __asm__ ("mulhwu %0,%1,%2" \
795 : "=r" ((USItype) ph) \
796 : "%r" (__m0), \
797 "r" (__m1)); \
798 (pl) = __m0 * __m1; \
799 } while (0)
800 #define UMUL_TIME 15
801 #define smul_ppmm(ph, pl, m0, m1) \
802 do { \
803 SItype __m0 = (m0), __m1 = (m1); \
804 __asm__ ("mulhw %0,%1,%2" \
805 : "=r" ((SItype) ph) \
806 : "%r" (__m0), \
807 "r" (__m1)); \
808 (pl) = __m0 * __m1; \
809 } while (0)
810 #define SMUL_TIME 14
811 #define UDIV_TIME 120
812 #else
813 #define umul_ppmm(xh, xl, m0, m1) \
814 do { \
815 USItype __m0 = (m0), __m1 = (m1); \
816 __asm__ ("mul %0,%2,%3" \
817 : "=r" ((USItype)(xh)), \
818 "=q" ((USItype)(xl)) \
819 : "r" (__m0), \
820 "r" (__m1)); \
821 (xh) += ((((SItype) __m0 >> 31) & __m1) \
822 + (((SItype) __m1 >> 31) & __m0)); \
823 } while (0)
824 #define UMUL_TIME 8
825 #define smul_ppmm(xh, xl, m0, m1) \
826 __asm__ ("mul %0,%2,%3" \
827 : "=r" ((SItype)(xh)), \
828 "=q" ((SItype)(xl)) \
829 : "r" (m0), \
830 "r" (m1))
831 #define SMUL_TIME 4
832 #define sdiv_qrnnd(q, r, nh, nl, d) \
833 __asm__ ("div %0,%2,%4" \
834 : "=r" ((SItype)(q)), "=q" ((SItype)(r)) \
835 : "r" ((SItype)(nh)), "1" ((SItype)(nl)), "r" ((SItype)(d)))
836 #define UDIV_TIME 100
837 #endif
838 #endif /* Power architecture variants. */
839
840 /***************************************
841 ************** PYR ******************
842 ***************************************/
843 #if defined(__pyr__) && W_TYPE_SIZE == 32
844 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
845 __asm__ ("addw %5,%1\n" \
846 "addwc %3,%0" \
847 : "=r" ((USItype)(sh)), \
848 "=&r" ((USItype)(sl)) \
849 : "%0" ((USItype)(ah)), \
850 "g" ((USItype)(bh)), \
851 "%1" ((USItype)(al)), \
852 "g" ((USItype)(bl)))
853 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
854 __asm__ ("subw %5,%1\n" \
855 "subwb %3,%0" \
856 : "=r" ((USItype)(sh)), \
857 "=&r" ((USItype)(sl)) \
858 : "0" ((USItype)(ah)), \
859 "g" ((USItype)(bh)), \
860 "1" ((USItype)(al)), \
861 "g" ((USItype)(bl)))
862 /* This insn works on Pyramids with AP, XP, or MI CPUs, but not with SP. */
863 #define umul_ppmm(w1, w0, u, v) \
864 ({union {UDItype __ll; \
865 struct {USItype __h, __l; } __i; \
866 } __xx; \
867 __asm__ ("movw %1,%R0\n" \
868 "uemul %2,%0" \
869 : "=&r" (__xx.__ll) \
870 : "g" ((USItype) (u)), \
871 "g" ((USItype)(v))); \
872 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l; })
873 #endif /* __pyr__ */
874
875 /***************************************
876 ************** RT/ROMP **************
877 ***************************************/
878 #if defined(__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32
879 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
880 __asm__ ("a %1,%5\n" \
881 "ae %0,%3" \
882 : "=r" ((USItype)(sh)), \
883 "=&r" ((USItype)(sl)) \
884 : "%0" ((USItype)(ah)), \
885 "r" ((USItype)(bh)), \
886 "%1" ((USItype)(al)), \
887 "r" ((USItype)(bl)))
888 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
889 __asm__ ("s %1,%5\n" \
890 "se %0,%3" \
891 : "=r" ((USItype)(sh)), \
892 "=&r" ((USItype)(sl)) \
893 : "0" ((USItype)(ah)), \
894 "r" ((USItype)(bh)), \
895 "1" ((USItype)(al)), \
896 "r" ((USItype)(bl)))
897 #define umul_ppmm(ph, pl, m0, m1) \
898 do { \
899 USItype __m0 = (m0), __m1 = (m1); \
900 __asm__ ( \
901 "s r2,r2\n" \
902 "mts r10,%2\n" \
903 "m r2,%3\n" \
904 "m r2,%3\n" \
905 "m r2,%3\n" \
906 "m r2,%3\n" \
907 "m r2,%3\n" \
908 "m r2,%3\n" \
909 "m r2,%3\n" \
910 "m r2,%3\n" \
911 "m r2,%3\n" \
912 "m r2,%3\n" \
913 "m r2,%3\n" \
914 "m r2,%3\n" \
915 "m r2,%3\n" \
916 "m r2,%3\n" \
917 "m r2,%3\n" \
918 "m r2,%3\n" \
919 "cas %0,r2,r0\n" \
920 "mfs r10,%1" \
921 : "=r" ((USItype)(ph)), \
922 "=r" ((USItype)(pl)) \
923 : "%r" (__m0), \
924 "r" (__m1) \
925 : "r2"); \
926 (ph) += ((((SItype) __m0 >> 31) & __m1) \
927 + (((SItype) __m1 >> 31) & __m0)); \
928 } while (0)
929 #define UMUL_TIME 20
930 #define UDIV_TIME 200
931 #endif /* RT/ROMP */
932
933 /***************************************
934 ************** SH2 ******************
935 ***************************************/
936 #if (defined(__sh2__) || defined(__sh3__) || defined(__SH4__)) \
937 && W_TYPE_SIZE == 32
938 #define umul_ppmm(w1, w0, u, v) \
939 __asm__ ( \
940 "dmulu.l %2,%3\n" \
941 "sts macl,%1\n" \
942 "sts mach,%0" \
943 : "=r" ((USItype)(w1)), \
944 "=r" ((USItype)(w0)) \
945 : "r" ((USItype)(u)), \
946 "r" ((USItype)(v)) \
947 : "macl", "mach")
948 #define UMUL_TIME 5
949 #endif
950
951 /***************************************
952 ************** SPARC ****************
953 ***************************************/
954 #if defined(__sparc__) && W_TYPE_SIZE == 32
955 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
956 __asm__ ("addcc %r4,%5,%1\n" \
957 "addx %r2,%3,%0" \
958 : "=r" ((USItype)(sh)), \
959 "=&r" ((USItype)(sl)) \
960 : "%rJ" ((USItype)(ah)), \
961 "rI" ((USItype)(bh)), \
962 "%rJ" ((USItype)(al)), \
963 "rI" ((USItype)(bl)) \
964 __CLOBBER_CC)
965 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
966 __asm__ ("subcc %r4,%5,%1\n" \
967 "subx %r2,%3,%0" \
968 : "=r" ((USItype)(sh)), \
969 "=&r" ((USItype)(sl)) \
970 : "rJ" ((USItype)(ah)), \
971 "rI" ((USItype)(bh)), \
972 "rJ" ((USItype)(al)), \
973 "rI" ((USItype)(bl)) \
974 __CLOBBER_CC)
975 #if defined(__sparc_v8__)
976 /* Don't match immediate range because, 1) it is not often useful,
977 2) the 'I' flag thinks of the range as a 13 bit signed interval,
978 while we want to match a 13 bit interval, sign extended to 32 bits,
979 but INTERPRETED AS UNSIGNED. */
980 #define umul_ppmm(w1, w0, u, v) \
981 __asm__ ("umul %2,%3,%1;rd %%y,%0" \
982 : "=r" ((USItype)(w1)), \
983 "=r" ((USItype)(w0)) \
984 : "r" ((USItype)(u)), \
985 "r" ((USItype)(v)))
986 #define UMUL_TIME 5
987 #ifndef SUPERSPARC /* SuperSPARC's udiv only handles 53 bit dividends */
988 #define udiv_qrnnd(q, r, n1, n0, d) \
989 do { \
990 USItype __q; \
991 __asm__ ("mov %1,%%y;nop;nop;nop;udiv %2,%3,%0" \
992 : "=r" ((USItype)(__q)) \
993 : "r" ((USItype)(n1)), \
994 "r" ((USItype)(n0)), \
995 "r" ((USItype)(d))); \
996 (r) = (n0) - __q * (d); \
997 (q) = __q; \
998 } while (0)
999 #define UDIV_TIME 25
1000 #endif /* SUPERSPARC */
1001 #else /* ! __sparc_v8__ */
1002 #if defined(__sparclite__)
1003 /* This has hardware multiply but not divide. It also has two additional
1004 instructions scan (ffs from high bit) and divscc. */
1005 #define umul_ppmm(w1, w0, u, v) \
1006 __asm__ ("umul %2,%3,%1;rd %%y,%0" \
1007 : "=r" ((USItype)(w1)), \
1008 "=r" ((USItype)(w0)) \
1009 : "r" ((USItype)(u)), \
1010 "r" ((USItype)(v)))
1011 #define UMUL_TIME 5
1012 #define udiv_qrnnd(q, r, n1, n0, d) \
1013 __asm__ ("! Inlined udiv_qrnnd\n" \
1014 "wr %%g0,%2,%%y ! Not a delayed write for sparclite\n" \
1015 "tst %%g0\n" \
1016 "divscc %3,%4,%%g1\n" \
1017 "divscc %%g1,%4,%%g1\n" \
1018 "divscc %%g1,%4,%%g1\n" \
1019 "divscc %%g1,%4,%%g1\n" \
1020 "divscc %%g1,%4,%%g1\n" \
1021 "divscc %%g1,%4,%%g1\n" \
1022 "divscc %%g1,%4,%%g1\n" \
1023 "divscc %%g1,%4,%%g1\n" \
1024 "divscc %%g1,%4,%%g1\n" \
1025 "divscc %%g1,%4,%%g1\n" \
1026 "divscc %%g1,%4,%%g1\n" \
1027 "divscc %%g1,%4,%%g1\n" \
1028 "divscc %%g1,%4,%%g1\n" \
1029 "divscc %%g1,%4,%%g1\n" \
1030 "divscc %%g1,%4,%%g1\n" \
1031 "divscc %%g1,%4,%%g1\n" \
1032 "divscc %%g1,%4,%%g1\n" \
1033 "divscc %%g1,%4,%%g1\n" \
1034 "divscc %%g1,%4,%%g1\n" \
1035 "divscc %%g1,%4,%%g1\n" \
1036 "divscc %%g1,%4,%%g1\n" \
1037 "divscc %%g1,%4,%%g1\n" \
1038 "divscc %%g1,%4,%%g1\n" \
1039 "divscc %%g1,%4,%%g1\n" \
1040 "divscc %%g1,%4,%%g1\n" \
1041 "divscc %%g1,%4,%%g1\n" \
1042 "divscc %%g1,%4,%%g1\n" \
1043 "divscc %%g1,%4,%%g1\n" \
1044 "divscc %%g1,%4,%%g1\n" \
1045 "divscc %%g1,%4,%%g1\n" \
1046 "divscc %%g1,%4,%%g1\n" \
1047 "divscc %%g1,%4,%0\n" \
1048 "rd %%y,%1\n" \
1049 "bl,a 1f\n" \
1050 "add %1,%4,%1\n" \
1051 "1: ! End of inline udiv_qrnnd" \
1052 : "=r" ((USItype)(q)), \
1053 "=r" ((USItype)(r)) \
1054 : "r" ((USItype)(n1)), \
1055 "r" ((USItype)(n0)), \
1056 "rI" ((USItype)(d)) \
1057 : "%g1" __AND_CLOBBER_CC)
1058 #define UDIV_TIME 37
1059 #endif /* __sparclite__ */
1060 #endif /* __sparc_v8__ */
1061 /* Default to sparc v7 versions of umul_ppmm and udiv_qrnnd. */
1062 #ifndef umul_ppmm
1063 #define umul_ppmm(w1, w0, u, v) \
1064 __asm__ ("! Inlined umul_ppmm\n" \
1065 "wr %%g0,%2,%%y ! SPARC has 0-3 delay insn after a wr\n" \
1066 "sra %3,31,%%g2 ! Don't move this insn\n" \
1067 "and %2,%%g2,%%g2 ! Don't move this insn\n" \
1068 "andcc %%g0,0,%%g1 ! Don't move this insn\n" \
1069 "mulscc %%g1,%3,%%g1\n" \
1070 "mulscc %%g1,%3,%%g1\n" \
1071 "mulscc %%g1,%3,%%g1\n" \
1072 "mulscc %%g1,%3,%%g1\n" \
1073 "mulscc %%g1,%3,%%g1\n" \
1074 "mulscc %%g1,%3,%%g1\n" \
1075 "mulscc %%g1,%3,%%g1\n" \
1076 "mulscc %%g1,%3,%%g1\n" \
1077 "mulscc %%g1,%3,%%g1\n" \
1078 "mulscc %%g1,%3,%%g1\n" \
1079 "mulscc %%g1,%3,%%g1\n" \
1080 "mulscc %%g1,%3,%%g1\n" \
1081 "mulscc %%g1,%3,%%g1\n" \
1082 "mulscc %%g1,%3,%%g1\n" \
1083 "mulscc %%g1,%3,%%g1\n" \
1084 "mulscc %%g1,%3,%%g1\n" \
1085 "mulscc %%g1,%3,%%g1\n" \
1086 "mulscc %%g1,%3,%%g1\n" \
1087 "mulscc %%g1,%3,%%g1\n" \
1088 "mulscc %%g1,%3,%%g1\n" \
1089 "mulscc %%g1,%3,%%g1\n" \
1090 "mulscc %%g1,%3,%%g1\n" \
1091 "mulscc %%g1,%3,%%g1\n" \
1092 "mulscc %%g1,%3,%%g1\n" \
1093 "mulscc %%g1,%3,%%g1\n" \
1094 "mulscc %%g1,%3,%%g1\n" \
1095 "mulscc %%g1,%3,%%g1\n" \
1096 "mulscc %%g1,%3,%%g1\n" \
1097 "mulscc %%g1,%3,%%g1\n" \
1098 "mulscc %%g1,%3,%%g1\n" \
1099 "mulscc %%g1,%3,%%g1\n" \
1100 "mulscc %%g1,%3,%%g1\n" \
1101 "mulscc %%g1,0,%%g1\n" \
1102 "add %%g1,%%g2,%0\n" \
1103 "rd %%y,%1" \
1104 : "=r" ((USItype)(w1)), \
1105 "=r" ((USItype)(w0)) \
1106 : "%rI" ((USItype)(u)), \
1107 "r" ((USItype)(v)) \
1108 : "%g1", "%g2" __AND_CLOBBER_CC)
1109 #define UMUL_TIME 39 /* 39 instructions */
1110 /* It's quite necessary to add this much assembler for the sparc.
1111 The default udiv_qrnnd (in C) is more than 10 times slower! */
1112 #define udiv_qrnnd(q, r, n1, n0, d) \
1113 __asm__ ("! Inlined udiv_qrnnd\n\t" \
1114 "mov 32,%%g1\n\t" \
1115 "subcc %1,%2,%%g0\n\t" \
1116 "1: bcs 5f\n\t" \
1117 "addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n\t" \
1118 "sub %1,%2,%1 ! this kills msb of n\n\t" \
1119 "addx %1,%1,%1 ! so this can't give carry\n\t" \
1120 "subcc %%g1,1,%%g1\n\t" \
1121 "2: bne 1b\n\t" \
1122 "subcc %1,%2,%%g0\n\t" \
1123 "bcs 3f\n\t" \
1124 "addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n\t" \
1125 "b 3f\n\t" \
1126 "sub %1,%2,%1 ! this kills msb of n\n\t" \
1127 "4: sub %1,%2,%1\n\t" \
1128 "5: addxcc %1,%1,%1\n\t" \
1129 "bcc 2b\n\t" \
1130 "subcc %%g1,1,%%g1\n\t" \
1131 "! Got carry from n. Subtract next step to cancel this carry.\n\t" \
1132 "bne 4b\n\t" \
1133 "addcc %0,%0,%0 ! shift n1n0 and a 0-bit in lsb\n\t" \
1134 "sub %1,%2,%1\n\t" \
1135 "3: xnor %0,0,%0\n\t" \
1136 "! End of inline udiv_qrnnd\n" \
1137 : "=&r" ((USItype)(q)), \
1138 "=&r" ((USItype)(r)) \
1139 : "r" ((USItype)(d)), \
1140 "1" ((USItype)(n1)), \
1141 "0" ((USItype)(n0)) : "%g1", "cc")
1142 #define UDIV_TIME (3+7*32) /* 7 instructions/iteration. 32 iterations. */
1143 #endif
1144 #endif /* __sparc__ */
1145
1146 /***************************************
1147 ************** VAX ******************
1148 ***************************************/
1149 #if defined(__vax__) && W_TYPE_SIZE == 32
1150 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1151 __asm__ ("addl2 %5,%1\n" \
1152 "adwc %3,%0" \
1153 : "=g" ((USItype)(sh)), \
1154 "=&g" ((USItype)(sl)) \
1155 : "%0" ((USItype)(ah)), \
1156 "g" ((USItype)(bh)), \
1157 "%1" ((USItype)(al)), \
1158 "g" ((USItype)(bl)))
1159 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1160 __asm__ ("subl2 %5,%1\n" \
1161 "sbwc %3,%0" \
1162 : "=g" ((USItype)(sh)), \
1163 "=&g" ((USItype)(sl)) \
1164 : "0" ((USItype)(ah)), \
1165 "g" ((USItype)(bh)), \
1166 "1" ((USItype)(al)), \
1167 "g" ((USItype)(bl)))
1168 #define umul_ppmm(xh, xl, m0, m1) \
1169 do { \
1170 union {UDItype __ll; \
1171 struct {USItype __l, __h; } __i; \
1172 } __xx; \
1173 USItype __m0 = (m0), __m1 = (m1); \
1174 __asm__ ("emul %1,%2,$0,%0" \
1175 : "=g" (__xx.__ll) \
1176 : "g" (__m0), \
1177 "g" (__m1)); \
1178 (xh) = __xx.__i.__h; (xl) = __xx.__i.__l; \
1179 (xh) += ((((SItype) __m0 >> 31) & __m1) \
1180 + (((SItype) __m1 >> 31) & __m0)); \
1181 } while (0)
1182 #define sdiv_qrnnd(q, r, n1, n0, d) \
1183 do { \
1184 union {DItype __ll; \
1185 struct {SItype __l, __h; } __i; \
1186 } __xx; \
1187 __xx.__i.__h = n1; __xx.__i.__l = n0; \
1188 __asm__ ("ediv %3,%2,%0,%1" \
1189 : "=g" (q), "=g" (r) \
1190 : "g" (__xx.__ll), "g" (d)); \
1191 } while (0)
1192 #endif /* __vax__ */
1193
1194 /***************************************
1195 ************** Z8000 ****************
1196 ***************************************/
1197 #if defined(__z8000__) && W_TYPE_SIZE == 16
1198 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1199 __asm__ ("add %H1,%H5\n\tadc %H0,%H3" \
1200 : "=r" ((unsigned int)(sh)), \
1201 "=&r" ((unsigned int)(sl)) \
1202 : "%0" ((unsigned int)(ah)), \
1203 "r" ((unsigned int)(bh)), \
1204 "%1" ((unsigned int)(al)), \
1205 "rQR" ((unsigned int)(bl)))
1206 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1207 __asm__ ("sub %H1,%H5\n\tsbc %H0,%H3" \
1208 : "=r" ((unsigned int)(sh)), \
1209 "=&r" ((unsigned int)(sl)) \
1210 : "0" ((unsigned int)(ah)), \
1211 "r" ((unsigned int)(bh)), \
1212 "1" ((unsigned int)(al)), \
1213 "rQR" ((unsigned int)(bl)))
1214 #define umul_ppmm(xh, xl, m0, m1) \
1215 do { \
1216 union {long int __ll; \
1217 struct {unsigned int __h, __l; } __i; \
1218 } __xx; \
1219 unsigned int __m0 = (m0), __m1 = (m1); \
1220 __asm__ ("mult %S0,%H3" \
1221 : "=r" (__xx.__i.__h), \
1222 "=r" (__xx.__i.__l) \
1223 : "%1" (__m0), \
1224 "rQR" (__m1)); \
1225 (xh) = __xx.__i.__h; (xl) = __xx.__i.__l; \
1226 (xh) += ((((signed int) __m0 >> 15) & __m1) \
1227 + (((signed int) __m1 >> 15) & __m0)); \
1228 } while (0)
1229 #endif /* __z8000__ */
1230
1231 #endif /* __GNUC__ */
1232
1233 /***************************************
1234 *********** Generic Versions ********
1235 ***************************************/
1236 #if !defined(umul_ppmm) && defined(__umulsidi3)
1237 #define umul_ppmm(ph, pl, m0, m1) \
1238 { \
1239 UDWtype __ll = __umulsidi3(m0, m1); \
1240 ph = (UWtype) (__ll >> W_TYPE_SIZE); \
1241 pl = (UWtype) __ll; \
1242 }
1243 #endif
1244
1245 #if !defined(__umulsidi3)
1246 #define __umulsidi3(u, v) \
1247 ({UWtype __hi, __lo; \
1248 umul_ppmm(__hi, __lo, u, v); \
1249 ((UDWtype) __hi << W_TYPE_SIZE) | __lo; })
1250 #endif
1251
1252 /* If this machine has no inline assembler, use C macros. */
1253
1254 #if !defined(add_ssaaaa)
1255 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1256 do { \
1257 UWtype __x; \
1258 __x = (al) + (bl); \
1259 (sh) = (ah) + (bh) + (__x < (al)); \
1260 (sl) = __x; \
1261 } while (0)
1262 #endif
1263
1264 #if !defined(sub_ddmmss)
1265 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1266 do { \
1267 UWtype __x; \
1268 __x = (al) - (bl); \
1269 (sh) = (ah) - (bh) - (__x > (al)); \
1270 (sl) = __x; \
1271 } while (0)
1272 #endif
1273
1274 #if !defined(umul_ppmm)
1275 #define umul_ppmm(w1, w0, u, v) \
1276 do { \
1277 UWtype __x0, __x1, __x2, __x3; \
1278 UHWtype __ul, __vl, __uh, __vh; \
1279 UWtype __u = (u), __v = (v); \
1280 \
1281 __ul = __ll_lowpart(__u); \
1282 __uh = __ll_highpart(__u); \
1283 __vl = __ll_lowpart(__v); \
1284 __vh = __ll_highpart(__v); \
1285 \
1286 __x0 = (UWtype) __ul * __vl; \
1287 __x1 = (UWtype) __ul * __vh; \
1288 __x2 = (UWtype) __uh * __vl; \
1289 __x3 = (UWtype) __uh * __vh; \
1290 \
1291 __x1 += __ll_highpart(__x0);/* this can't give carry */ \
1292 __x1 += __x2; /* but this indeed can */ \
1293 if (__x1 < __x2) /* did we get it? */ \
1294 __x3 += __ll_B; /* yes, add it in the proper pos. */ \
1295 \
1296 (w1) = __x3 + __ll_highpart(__x1); \
1297 (w0) = (__ll_lowpart(__x1) << W_TYPE_SIZE/2) + __ll_lowpart(__x0); \
1298 } while (0)
1299 #endif
1300
1301 #if !defined(umul_ppmm)
1302 #define smul_ppmm(w1, w0, u, v) \
1303 do { \
1304 UWtype __w1; \
1305 UWtype __m0 = (u), __m1 = (v); \
1306 umul_ppmm(__w1, w0, __m0, __m1); \
1307 (w1) = __w1 - (-(__m0 >> (W_TYPE_SIZE - 1)) & __m1) \
1308 - (-(__m1 >> (W_TYPE_SIZE - 1)) & __m0); \
1309 } while (0)
1310 #endif
1311
1312 /* Define this unconditionally, so it can be used for debugging. */
1313 #define __udiv_qrnnd_c(q, r, n1, n0, d) \
1314 do { \
1315 UWtype __d1, __d0, __q1, __q0, __r1, __r0, __m; \
1316 __d1 = __ll_highpart(d); \
1317 __d0 = __ll_lowpart(d); \
1318 \
1319 __r1 = (n1) % __d1; \
1320 __q1 = (n1) / __d1; \
1321 __m = (UWtype) __q1 * __d0; \
1322 __r1 = __r1 * __ll_B | __ll_highpart(n0); \
1323 if (__r1 < __m) { \
1324 __q1--, __r1 += (d); \
1325 if (__r1 >= (d)) /* i.e. we didn't get carry when adding to __r1 */ \
1326 if (__r1 < __m) \
1327 __q1--, __r1 += (d); \
1328 } \
1329 __r1 -= __m; \
1330 \
1331 __r0 = __r1 % __d1; \
1332 __q0 = __r1 / __d1; \
1333 __m = (UWtype) __q0 * __d0; \
1334 __r0 = __r0 * __ll_B | __ll_lowpart(n0); \
1335 if (__r0 < __m) { \
1336 __q0--, __r0 += (d); \
1337 if (__r0 >= (d)) \
1338 if (__r0 < __m) \
1339 __q0--, __r0 += (d); \
1340 } \
1341 __r0 -= __m; \
1342 \
1343 (q) = (UWtype) __q1 * __ll_B | __q0; \
1344 (r) = __r0; \
1345 } while (0)
1346
1347 /* If the processor has no udiv_qrnnd but sdiv_qrnnd, go through
1348 __udiv_w_sdiv (defined in libgcc or elsewhere). */
1349 #if !defined(udiv_qrnnd) && defined(sdiv_qrnnd)
1350 #define udiv_qrnnd(q, r, nh, nl, d) \
1351 do { \
1352 UWtype __r; \
1353 (q) = __MPN(udiv_w_sdiv) (&__r, nh, nl, d); \
1354 (r) = __r; \
1355 } while (0)
1356 #endif
1357
1358 /* If udiv_qrnnd was not defined for this processor, use __udiv_qrnnd_c. */
1359 #if !defined(udiv_qrnnd)
1360 #define UDIV_NEEDS_NORMALIZATION 1
1361 #define udiv_qrnnd __udiv_qrnnd_c
1362 #endif
1363
1364 #ifndef UDIV_NEEDS_NORMALIZATION
1365 #define UDIV_NEEDS_NORMALIZATION 0
1366 #endif
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