2 * Clock implementation for VIA/Wondermedia SoC's
3 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
18 #include <linux/slab.h>
19 #include <linux/bitops.h>
20 #include <linux/clkdev.h>
21 #include <linux/clk-provider.h>
23 /* All clocks share the same lock as none can be changed concurrently */
24 static DEFINE_SPINLOCK(_lock
);
28 void __iomem
*div_reg
;
29 unsigned int div_mask
;
36 * Add new PLL_TYPE_x definitions here as required. Use the first known model
37 * to support the new type as the name.
38 * Add case statements to vtwm_pll_recalc_rate(), vtwm_pll_round_round() and
39 * vtwm_pll_set_rate() to handle the new PLL_TYPE_x
42 #define PLL_TYPE_VT8500 0
43 #define PLL_TYPE_WM8650 1
52 static void __iomem
*pmc_base
;
54 #define to_clk_device(_hw) container_of(_hw, struct clk_device, hw)
56 #define VT8500_PMC_BUSY_MASK 0x18
58 static void vt8500_pmc_wait_busy(void)
60 while (readl(pmc_base
) & VT8500_PMC_BUSY_MASK
)
64 static int vt8500_dclk_enable(struct clk_hw
*hw
)
66 struct clk_device
*cdev
= to_clk_device(hw
);
68 unsigned long flags
= 0;
70 spin_lock_irqsave(cdev
->lock
, flags
);
72 en_val
= readl(cdev
->en_reg
);
73 en_val
|= BIT(cdev
->en_bit
);
74 writel(en_val
, cdev
->en_reg
);
76 spin_unlock_irqrestore(cdev
->lock
, flags
);
80 static void vt8500_dclk_disable(struct clk_hw
*hw
)
82 struct clk_device
*cdev
= to_clk_device(hw
);
84 unsigned long flags
= 0;
86 spin_lock_irqsave(cdev
->lock
, flags
);
88 en_val
= readl(cdev
->en_reg
);
89 en_val
&= ~BIT(cdev
->en_bit
);
90 writel(en_val
, cdev
->en_reg
);
92 spin_unlock_irqrestore(cdev
->lock
, flags
);
95 static int vt8500_dclk_is_enabled(struct clk_hw
*hw
)
97 struct clk_device
*cdev
= to_clk_device(hw
);
98 u32 en_val
= (readl(cdev
->en_reg
) & BIT(cdev
->en_bit
));
100 return en_val
? 1 : 0;
103 static unsigned long vt8500_dclk_recalc_rate(struct clk_hw
*hw
,
104 unsigned long parent_rate
)
106 struct clk_device
*cdev
= to_clk_device(hw
);
107 u32 div
= readl(cdev
->div_reg
) & cdev
->div_mask
;
109 /* Special case for SDMMC devices */
110 if ((cdev
->div_mask
== 0x3F) && (div
& BIT(5)))
111 div
= 64 * (div
& 0x1f);
113 /* div == 0 is actually the highest divisor */
115 div
= (cdev
->div_mask
+ 1);
117 return parent_rate
/ div
;
120 static long vt8500_dclk_round_rate(struct clk_hw
*hw
, unsigned long rate
,
121 unsigned long *prate
)
123 struct clk_device
*cdev
= to_clk_device(hw
);
124 u32 divisor
= *prate
/ rate
;
126 /* If prate / rate would be decimal, incr the divisor */
127 if (rate
* divisor
< *prate
)
131 * If this is a request for SDMMC we have to adjust the divisor
132 * when >31 to use the fixed predivisor
134 if ((cdev
->div_mask
== 0x3F) && (divisor
> 31)) {
135 divisor
= 64 * ((divisor
/ 64) + 1);
138 return *prate
/ divisor
;
141 static int vt8500_dclk_set_rate(struct clk_hw
*hw
, unsigned long rate
,
142 unsigned long parent_rate
)
144 struct clk_device
*cdev
= to_clk_device(hw
);
145 u32 divisor
= parent_rate
/ rate
;
146 unsigned long flags
= 0;
148 /* If prate / rate would be decimal, incr the divisor */
149 if (rate
* divisor
< *prate
)
152 if (divisor
== cdev
->div_mask
+ 1)
155 /* SDMMC mask may need to be corrected before testing if its valid */
156 if ((cdev
->div_mask
== 0x3F) && (divisor
> 31)) {
158 * Bit 5 is a fixed /64 predivisor. If the requested divisor
159 * is >31 then correct for the fixed divisor being required.
161 divisor
= 0x20 + (divisor
/ 64);
164 if (divisor
> cdev
->div_mask
) {
165 pr_err("%s: invalid divisor for clock\n", __func__
);
169 spin_lock_irqsave(cdev
->lock
, flags
);
171 vt8500_pmc_wait_busy();
172 writel(divisor
, cdev
->div_reg
);
173 vt8500_pmc_wait_busy();
175 spin_lock_irqsave(cdev
->lock
, flags
);
181 static const struct clk_ops vt8500_gated_clk_ops
= {
182 .enable
= vt8500_dclk_enable
,
183 .disable
= vt8500_dclk_disable
,
184 .is_enabled
= vt8500_dclk_is_enabled
,
187 static const struct clk_ops vt8500_divisor_clk_ops
= {
188 .round_rate
= vt8500_dclk_round_rate
,
189 .set_rate
= vt8500_dclk_set_rate
,
190 .recalc_rate
= vt8500_dclk_recalc_rate
,
193 static const struct clk_ops vt8500_gated_divisor_clk_ops
= {
194 .enable
= vt8500_dclk_enable
,
195 .disable
= vt8500_dclk_disable
,
196 .is_enabled
= vt8500_dclk_is_enabled
,
197 .round_rate
= vt8500_dclk_round_rate
,
198 .set_rate
= vt8500_dclk_set_rate
,
199 .recalc_rate
= vt8500_dclk_recalc_rate
,
202 #define CLK_INIT_GATED BIT(0)
203 #define CLK_INIT_DIVISOR BIT(1)
204 #define CLK_INIT_GATED_DIVISOR (CLK_INIT_DIVISOR | CLK_INIT_GATED)
206 static __init
void vtwm_device_clk_init(struct device_node
*node
)
210 struct clk_device
*dev_clk
;
211 const char *clk_name
= node
->name
;
212 const char *parent_name
;
213 struct clk_init_data init
;
215 int clk_init_flags
= 0;
217 dev_clk
= kzalloc(sizeof(*dev_clk
), GFP_KERNEL
);
218 if (WARN_ON(!dev_clk
))
221 dev_clk
->lock
= &_lock
;
223 rc
= of_property_read_u32(node
, "enable-reg", &en_reg
);
225 dev_clk
->en_reg
= pmc_base
+ en_reg
;
226 rc
= of_property_read_u32(node
, "enable-bit", &dev_clk
->en_bit
);
228 pr_err("%s: enable-bit property required for gated clock\n",
232 clk_init_flags
|= CLK_INIT_GATED
;
235 rc
= of_property_read_u32(node
, "divisor-reg", &div_reg
);
237 dev_clk
->div_reg
= pmc_base
+ div_reg
;
239 * use 0x1f as the default mask since it covers
240 * almost all the clocks and reduces dts properties
242 dev_clk
->div_mask
= 0x1f;
244 of_property_read_u32(node
, "divisor-mask", &dev_clk
->div_mask
);
245 clk_init_flags
|= CLK_INIT_DIVISOR
;
248 of_property_read_string(node
, "clock-output-names", &clk_name
);
250 switch (clk_init_flags
) {
252 init
.ops
= &vt8500_gated_clk_ops
;
254 case CLK_INIT_DIVISOR
:
255 init
.ops
= &vt8500_divisor_clk_ops
;
257 case CLK_INIT_GATED_DIVISOR
:
258 init
.ops
= &vt8500_gated_divisor_clk_ops
;
261 pr_err("%s: Invalid clock description in device tree\n",
267 init
.name
= clk_name
;
269 parent_name
= of_clk_get_parent_name(node
, 0);
270 init
.parent_names
= &parent_name
;
271 init
.num_parents
= 1;
273 dev_clk
->hw
.init
= &init
;
275 clk
= clk_register(NULL
, &dev_clk
->hw
);
276 if (WARN_ON(IS_ERR(clk
))) {
280 rc
= of_clk_add_provider(node
, of_clk_src_simple_get
, clk
);
281 clk_register_clkdev(clk
, clk_name
, NULL
);
285 /* PLL clock related functions */
287 #define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw)
289 /* Helper macros for PLL_VT8500 */
290 #define VT8500_PLL_MUL(x) ((x & 0x1F) << 1)
291 #define VT8500_PLL_DIV(x) ((x & 0x100) ? 1 : 2)
293 #define VT8500_BITS_TO_FREQ(r, m, d) \
296 #define VT8500_BITS_TO_VAL(m, d) \
297 ((d == 2 ? 0 : 0x100) | ((m >> 1) & 0x1F))
299 /* Helper macros for PLL_WM8650 */
300 #define WM8650_PLL_MUL(x) (x & 0x3FF)
301 #define WM8650_PLL_DIV(x) (((x >> 10) & 7) * (1 << ((x >> 13) & 3)))
303 #define WM8650_BITS_TO_FREQ(r, m, d1, d2) \
304 (r * m / (d1 * (1 << d2)))
306 #define WM8650_BITS_TO_VAL(m, d1, d2) \
307 ((d2 << 13) | (d1 << 10) | (m & 0x3FF))
310 static void vt8500_find_pll_bits(unsigned long rate
, unsigned long parent_rate
,
311 u32
*multiplier
, u32
*prediv
)
316 if ((rate
< parent_rate
* 4) || (rate
> parent_rate
* 62)) {
317 pr_err("%s: requested rate out of range\n", __func__
);
322 if (rate
<= parent_rate
* 31)
323 /* use the prediv to double the resolution */
328 *multiplier
= rate
/ (parent_rate
/ *prediv
);
329 tclk
= (parent_rate
/ *prediv
) * *multiplier
;
332 pr_warn("%s: requested rate %lu, found rate %lu\n", __func__
,
336 static void wm8650_find_pll_bits(unsigned long rate
, unsigned long parent_rate
,
337 u32
*multiplier
, u32
*divisor1
, u32
*divisor2
)
340 u32 best_mul
, best_div1
, best_div2
;
341 unsigned long tclk
, rate_err
, best_err
;
343 best_err
= (unsigned long)-1;
345 /* Find the closest match (lower or equal to requested) */
346 for (div1
= 5; div1
>= 3; div1
--)
347 for (div2
= 3; div2
>= 0; div2
--)
348 for (mul
= 3; mul
<= 1023; mul
++) {
349 tclk
= parent_rate
* mul
/ (div1
* (1 << div2
));
352 /* error will always be +ve */
353 rate_err
= rate
- tclk
;
361 if (rate_err
< best_err
) {
369 /* if we got here, it wasn't an exact match */
370 pr_warn("%s: requested rate %lu, found rate %lu\n", __func__
, rate
,
372 *multiplier
= best_mul
;
373 *divisor1
= best_div1
;
374 *divisor2
= best_div2
;
377 static int vtwm_pll_set_rate(struct clk_hw
*hw
, unsigned long rate
,
378 unsigned long parent_rate
)
380 struct clk_pll
*pll
= to_clk_pll(hw
);
383 unsigned long flags
= 0;
388 case PLL_TYPE_VT8500
:
389 vt8500_find_pll_bits(rate
, parent_rate
, &mul
, &div1
);
390 pll_val
= VT8500_BITS_TO_VAL(mul
, div1
);
392 case PLL_TYPE_WM8650
:
393 wm8650_find_pll_bits(rate
, parent_rate
, &mul
, &div1
, &div2
);
394 pll_val
= WM8650_BITS_TO_VAL(mul
, div1
, div2
);
397 pr_err("%s: invalid pll type\n", __func__
);
401 spin_lock_irqsave(pll
->lock
, flags
);
403 vt8500_pmc_wait_busy();
404 writel(pll_val
, pll
->reg
);
405 vt8500_pmc_wait_busy();
407 spin_unlock_irqrestore(pll
->lock
, flags
);
412 static long vtwm_pll_round_rate(struct clk_hw
*hw
, unsigned long rate
,
413 unsigned long *prate
)
415 struct clk_pll
*pll
= to_clk_pll(hw
);
420 case PLL_TYPE_VT8500
:
421 vt8500_find_pll_bits(rate
, *prate
, &mul
, &div1
);
422 round_rate
= VT8500_BITS_TO_FREQ(*prate
, mul
, div1
);
424 case PLL_TYPE_WM8650
:
425 wm8650_find_pll_bits(rate
, *prate
, &mul
, &div1
, &div2
);
426 round_rate
= WM8650_BITS_TO_FREQ(*prate
, mul
, div1
, div2
);
435 static unsigned long vtwm_pll_recalc_rate(struct clk_hw
*hw
,
436 unsigned long parent_rate
)
438 struct clk_pll
*pll
= to_clk_pll(hw
);
439 u32 pll_val
= readl(pll
->reg
);
440 unsigned long pll_freq
;
443 case PLL_TYPE_VT8500
:
444 pll_freq
= parent_rate
* VT8500_PLL_MUL(pll_val
);
445 pll_freq
/= VT8500_PLL_DIV(pll_val
);
447 case PLL_TYPE_WM8650
:
448 pll_freq
= parent_rate
* WM8650_PLL_MUL(pll_val
);
449 pll_freq
/= WM8650_PLL_DIV(pll_val
);
458 const struct clk_ops vtwm_pll_ops
= {
459 .round_rate
= vtwm_pll_round_rate
,
460 .set_rate
= vtwm_pll_set_rate
,
461 .recalc_rate
= vtwm_pll_recalc_rate
,
464 static __init
void vtwm_pll_clk_init(struct device_node
*node
, int pll_type
)
468 struct clk_pll
*pll_clk
;
469 const char *clk_name
= node
->name
;
470 const char *parent_name
;
471 struct clk_init_data init
;
474 rc
= of_property_read_u32(node
, "reg", ®
);
478 pll_clk
= kzalloc(sizeof(*pll_clk
), GFP_KERNEL
);
479 if (WARN_ON(!pll_clk
))
482 pll_clk
->reg
= pmc_base
+ reg
;
483 pll_clk
->lock
= &_lock
;
484 pll_clk
->type
= pll_type
;
486 of_property_read_string(node
, "clock-output-names", &clk_name
);
488 init
.name
= clk_name
;
489 init
.ops
= &vtwm_pll_ops
;
491 parent_name
= of_clk_get_parent_name(node
, 0);
492 init
.parent_names
= &parent_name
;
493 init
.num_parents
= 1;
495 pll_clk
->hw
.init
= &init
;
497 clk
= clk_register(NULL
, &pll_clk
->hw
);
498 if (WARN_ON(IS_ERR(clk
))) {
502 rc
= of_clk_add_provider(node
, of_clk_src_simple_get
, clk
);
503 clk_register_clkdev(clk
, clk_name
, NULL
);
507 /* Wrappers for initialization functions */
509 static void __init
vt8500_pll_init(struct device_node
*node
)
511 vtwm_pll_clk_init(node
, PLL_TYPE_VT8500
);
514 static void __init
wm8650_pll_init(struct device_node
*node
)
516 vtwm_pll_clk_init(node
, PLL_TYPE_WM8650
);
519 static const __initconst
struct of_device_id clk_match
[] = {
520 { .compatible
= "fixed-clock", .data
= of_fixed_clk_setup
, },
521 { .compatible
= "via,vt8500-pll-clock", .data
= vt8500_pll_init
, },
522 { .compatible
= "wm,wm8650-pll-clock", .data
= wm8650_pll_init
, },
523 { .compatible
= "via,vt8500-device-clock",
524 .data
= vtwm_device_clk_init
, },
528 void __init
vtwm_clk_init(void __iomem
*base
)
535 of_clk_init(clk_match
);