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KVM: s390: Fix problem state check for b2 intercepts
[linux-2.6.git] / drivers / pci / quirks.c
blob92b9efe9bcaf628faa260c0e919eece0d2610e9f
1 /*
2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
5 *
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
7 *
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
9 *
10 * Init/reset quirks for USB host controllers should be in the
11 * USB quirks file, where their drivers can access reuse it.
12 *
13 * The bridge optimization stuff has been removed. If you really
14 * have a silly BIOS which is unable to set your host bridge right,
15 * use the PowerTweak utility (see http://powertweak.sourceforge.net).
16 */
17
18 #include <linux/types.h>
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/init.h>
22 #include <linux/delay.h>
23 #include <linux/acpi.h>
24 #include <linux/kallsyms.h>
25 #include <linux/dmi.h>
26 #include <linux/pci-aspm.h>
27 #include "pci.h"
28
29 int isa_dma_bridge_buggy;
30 EXPORT_SYMBOL(isa_dma_bridge_buggy);
31 int pci_pci_problems;
32 EXPORT_SYMBOL(pci_pci_problems);
33 int pcie_mch_quirk;
34 EXPORT_SYMBOL(pcie_mch_quirk);
35
36 #ifdef CONFIG_PCI_QUIRKS
37 /* The Mellanox Tavor device gives false positive parity errors
38 * Mark this device with a broken_parity_status, to allow
39 * PCI scanning code to "skip" this now blacklisted device.
40 */
41 static void __devinit quirk_mellanox_tavor(struct pci_dev *dev)
42 {
43 dev->broken_parity_status = 1; /* This device gives false positives */
44 }
45 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor);
46 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor);
47
48 /* Deal with broken BIOS'es that neglect to enable passive release,
49 which can cause problems in combination with the 82441FX/PPro MTRRs */
50 static void quirk_passive_release(struct pci_dev *dev)
51 {
52 struct pci_dev *d = NULL;
53 unsigned char dlc;
54
55 /* We have to make sure a particular bit is set in the PIIX3
56 ISA bridge, so we have to go out and find it. */
57 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
58 pci_read_config_byte(d, 0x82, &dlc);
59 if (!(dlc & 1<<1)) {
60 dev_info(&d->dev, "PIIX3: Enabling Passive Release\n");
61 dlc |= 1<<1;
62 pci_write_config_byte(d, 0x82, dlc);
63 }
64 }
65 }
66 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
67 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
68
69 /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
70 but VIA don't answer queries. If you happen to have good contacts at VIA
71 ask them for me please -- Alan
72
73 This appears to be BIOS not version dependent. So presumably there is a
74 chipset level fix */
75
76 static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev)
77 {
78 if (!isa_dma_bridge_buggy) {
79 isa_dma_bridge_buggy=1;
80 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n");
81 }
82 }
83 /*
84 * Its not totally clear which chipsets are the problematic ones
85 * We know 82C586 and 82C596 variants are affected.
86 */
87 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
88 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
89 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
90 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
91 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
92 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
93 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
94
95 /*
96 * Chipsets where PCI->PCI transfers vanish or hang
97 */
98 static void __devinit quirk_nopcipci(struct pci_dev *dev)
99 {
100 if ((pci_pci_problems & PCIPCI_FAIL)==0) {
101 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n");
102 pci_pci_problems |= PCIPCI_FAIL;
103 }
104 }
105 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
106 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
107
108 static void __devinit quirk_nopciamd(struct pci_dev *dev)
109 {
110 u8 rev;
111 pci_read_config_byte(dev, 0x08, &rev);
112 if (rev == 0x13) {
113 /* Erratum 24 */
114 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
115 pci_pci_problems |= PCIAGP_FAIL;
116 }
117 }
118 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
119
120 /*
121 * Triton requires workarounds to be used by the drivers
122 */
123 static void __devinit quirk_triton(struct pci_dev *dev)
124 {
125 if ((pci_pci_problems&PCIPCI_TRITON)==0) {
126 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
127 pci_pci_problems |= PCIPCI_TRITON;
128 }
129 }
130 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
131 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
132 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
133 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
134
135 /*
136 * VIA Apollo KT133 needs PCI latency patch
137 * Made according to a windows driver based patch by George E. Breese
138 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
139 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
140 * the info on which Mr Breese based his work.
141 *
142 * Updated based on further information from the site and also on
143 * information provided by VIA
144 */
145 static void quirk_vialatency(struct pci_dev *dev)
146 {
147 struct pci_dev *p;
148 u8 busarb;
149 /* Ok we have a potential problem chipset here. Now see if we have
150 a buggy southbridge */
151
152 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
153 if (p!=NULL) {
154 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
155 /* Check for buggy part revisions */
156 if (p->revision < 0x40 || p->revision > 0x42)
157 goto exit;
158 } else {
159 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
160 if (p==NULL) /* No problem parts */
161 goto exit;
162 /* Check for buggy part revisions */
163 if (p->revision < 0x10 || p->revision > 0x12)
164 goto exit;
165 }
166
167 /*
168 * Ok we have the problem. Now set the PCI master grant to
169 * occur every master grant. The apparent bug is that under high
170 * PCI load (quite common in Linux of course) you can get data
171 * loss when the CPU is held off the bus for 3 bus master requests
172 * This happens to include the IDE controllers....
173 *
174 * VIA only apply this fix when an SB Live! is present but under
175 * both Linux and Windows this isnt enough, and we have seen
176 * corruption without SB Live! but with things like 3 UDMA IDE
177 * controllers. So we ignore that bit of the VIA recommendation..
178 */
179
180 pci_read_config_byte(dev, 0x76, &busarb);
181 /* Set bit 4 and bi 5 of byte 76 to 0x01
182 "Master priority rotation on every PCI master grant */
183 busarb &= ~(1<<5);
184 busarb |= (1<<4);
185 pci_write_config_byte(dev, 0x76, busarb);
186 dev_info(&dev->dev, "Applying VIA southbridge workaround\n");
187 exit:
188 pci_dev_put(p);
189 }
190 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
191 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
192 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
193 /* Must restore this on a resume from RAM */
194 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
195 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
196 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
197
198 /*
199 * VIA Apollo VP3 needs ETBF on BT848/878
200 */
201 static void __devinit quirk_viaetbf(struct pci_dev *dev)
202 {
203 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) {
204 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
205 pci_pci_problems |= PCIPCI_VIAETBF;
206 }
207 }
208 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
209
210 static void __devinit quirk_vsfx(struct pci_dev *dev)
211 {
212 if ((pci_pci_problems&PCIPCI_VSFX)==0) {
213 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
214 pci_pci_problems |= PCIPCI_VSFX;
215 }
216 }
217 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
218
219 /*
220 * Ali Magik requires workarounds to be used by the drivers
221 * that DMA to AGP space. Latency must be set to 0xA and triton
222 * workaround applied too
223 * [Info kindly provided by ALi]
224 */
225 static void __init quirk_alimagik(struct pci_dev *dev)
226 {
227 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
228 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
229 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
230 }
231 }
232 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
233 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
234
235 /*
236 * Natoma has some interesting boundary conditions with Zoran stuff
237 * at least
238 */
239 static void __devinit quirk_natoma(struct pci_dev *dev)
240 {
241 if ((pci_pci_problems&PCIPCI_NATOMA)==0) {
242 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
243 pci_pci_problems |= PCIPCI_NATOMA;
244 }
245 }
246 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
247 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
248 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
249 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
250 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
251 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
252
253 /*
254 * This chip can cause PCI parity errors if config register 0xA0 is read
255 * while DMAs are occurring.
256 */
257 static void __devinit quirk_citrine(struct pci_dev *dev)
258 {
259 dev->cfg_size = 0xA0;
260 }
261 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
262
263 /*
264 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
265 * If it's needed, re-allocate the region.
266 */
267 static void __devinit quirk_s3_64M(struct pci_dev *dev)
268 {
269 struct resource *r = &dev->resource[0];
270
271 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
272 r->start = 0;
273 r->end = 0x3ffffff;
274 }
275 }
276 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
277 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
278
279 static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region,
280 unsigned size, int nr, const char *name)
281 {
282 region &= ~(size-1);
283 if (region) {
284 struct pci_bus_region bus_region;
285 struct resource *res = dev->resource + nr;
286
287 res->name = pci_name(dev);
288 res->start = region;
289 res->end = region + size - 1;
290 res->flags = IORESOURCE_IO;
291
292 /* Convert from PCI bus to resource space. */
293 bus_region.start = res->start;
294 bus_region.end = res->end;
295 pcibios_bus_to_resource(dev, res, &bus_region);
296
297 pci_claim_resource(dev, nr);
298 dev_info(&dev->dev, "quirk: region %04x-%04x claimed by %s\n", region, region + size - 1, name);
299 }
300 }
301
302 /*
303 * ATI Northbridge setups MCE the processor if you even
304 * read somewhere between 0x3b0->0x3bb or read 0x3d3
305 */
306 static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev)
307 {
308 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
309 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
310 request_region(0x3b0, 0x0C, "RadeonIGP");
311 request_region(0x3d3, 0x01, "RadeonIGP");
312 }
313 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
314
315 /*
316 * Let's make the southbridge information explicit instead
317 * of having to worry about people probing the ACPI areas,
318 * for example.. (Yes, it happens, and if you read the wrong
319 * ACPI register it will put the machine to sleep with no
320 * way of waking it up again. Bummer).
321 *
322 * ALI M7101: Two IO regions pointed to by words at
323 * 0xE0 (64 bytes of ACPI registers)
324 * 0xE2 (32 bytes of SMB registers)
325 */
326 static void __devinit quirk_ali7101_acpi(struct pci_dev *dev)
327 {
328 u16 region;
329
330 pci_read_config_word(dev, 0xE0, &region);
331 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
332 pci_read_config_word(dev, 0xE2, &region);
333 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
334 }
335 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
336
337 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
338 {
339 u32 devres;
340 u32 mask, size, base;
341
342 pci_read_config_dword(dev, port, &devres);
343 if ((devres & enable) != enable)
344 return;
345 mask = (devres >> 16) & 15;
346 base = devres & 0xffff;
347 size = 16;
348 for (;;) {
349 unsigned bit = size >> 1;
350 if ((bit & mask) == bit)
351 break;
352 size = bit;
353 }
354 /*
355 * For now we only print it out. Eventually we'll want to
356 * reserve it (at least if it's in the 0x1000+ range), but
357 * let's get enough confirmation reports first.
358 */
359 base &= -size;
360 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
361 }
362
363 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
364 {
365 u32 devres;
366 u32 mask, size, base;
367
368 pci_read_config_dword(dev, port, &devres);
369 if ((devres & enable) != enable)
370 return;
371 base = devres & 0xffff0000;
372 mask = (devres & 0x3f) << 16;
373 size = 128 << 16;
374 for (;;) {
375 unsigned bit = size >> 1;
376 if ((bit & mask) == bit)
377 break;
378 size = bit;
379 }
380 /*
381 * For now we only print it out. Eventually we'll want to
382 * reserve it, but let's get enough confirmation reports first.
383 */
384 base &= -size;
385 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
386 }
387
388 /*
389 * PIIX4 ACPI: Two IO regions pointed to by longwords at
390 * 0x40 (64 bytes of ACPI registers)
391 * 0x90 (16 bytes of SMB registers)
392 * and a few strange programmable PIIX4 device resources.
393 */
394 static void __devinit quirk_piix4_acpi(struct pci_dev *dev)
395 {
396 u32 region, res_a;
397
398 pci_read_config_dword(dev, 0x40, &region);
399 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
400 pci_read_config_dword(dev, 0x90, &region);
401 quirk_io_region(dev, region, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
402
403 /* Device resource A has enables for some of the other ones */
404 pci_read_config_dword(dev, 0x5c, &res_a);
405
406 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
407 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
408
409 /* Device resource D is just bitfields for static resources */
410
411 /* Device 12 enabled? */
412 if (res_a & (1 << 29)) {
413 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
414 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
415 }
416 /* Device 13 enabled? */
417 if (res_a & (1 << 30)) {
418 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
419 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
420 }
421 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
422 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
423 }
424 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
425 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
426
427 /*
428 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
429 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
430 * 0x58 (64 bytes of GPIO I/O space)
431 */
432 static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev)
433 {
434 u32 region;
435
436 pci_read_config_dword(dev, 0x40, &region);
437 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH4 ACPI/GPIO/TCO");
438
439 pci_read_config_dword(dev, 0x58, &region);
440 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH4 GPIO");
441 }
442 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
443 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
444 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
445 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
446 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
447 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
448 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
449 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
450 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
451 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
452
453 static void __devinit ich6_lpc_acpi_gpio(struct pci_dev *dev)
454 {
455 u32 region;
456
457 pci_read_config_dword(dev, 0x40, &region);
458 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH6 ACPI/GPIO/TCO");
459
460 pci_read_config_dword(dev, 0x48, &region);
461 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH6 GPIO");
462 }
463
464 static void __devinit ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize)
465 {
466 u32 val;
467 u32 size, base;
468
469 pci_read_config_dword(dev, reg, &val);
470
471 /* Enabled? */
472 if (!(val & 1))
473 return;
474 base = val & 0xfffc;
475 if (dynsize) {
476 /*
477 * This is not correct. It is 16, 32 or 64 bytes depending on
478 * register D31:F0:ADh bits 5:4.
479 *
480 * But this gets us at least _part_ of it.
481 */
482 size = 16;
483 } else {
484 size = 128;
485 }
486 base &= ~(size-1);
487
488 /* Just print it out for now. We should reserve it after more debugging */
489 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
490 }
491
492 static void __devinit quirk_ich6_lpc(struct pci_dev *dev)
493 {
494 /* Shared ACPI/GPIO decode with all ICH6+ */
495 ich6_lpc_acpi_gpio(dev);
496
497 /* ICH6-specific generic IO decode */
498 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
499 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
500 }
501 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
502 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
503
504 static void __devinit ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name)
505 {
506 u32 val;
507 u32 mask, base;
508
509 pci_read_config_dword(dev, reg, &val);
510
511 /* Enabled? */
512 if (!(val & 1))
513 return;
514
515 /*
516 * IO base in bits 15:2, mask in bits 23:18, both
517 * are dword-based
518 */
519 base = val & 0xfffc;
520 mask = (val >> 16) & 0xfc;
521 mask |= 3;
522
523 /* Just print it out for now. We should reserve it after more debugging */
524 dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
525 }
526
527 /* ICH7-10 has the same common LPC generic IO decode registers */
528 static void __devinit quirk_ich7_lpc(struct pci_dev *dev)
529 {
530 /* We share the common ACPI/DPIO decode with ICH6 */
531 ich6_lpc_acpi_gpio(dev);
532
533 /* And have 4 ICH7+ generic decodes */
534 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
535 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
536 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
537 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
538 }
539 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
540 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
541 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
542 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
543 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
544 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
545 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
546 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
547 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
548 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
549 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
550 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
551 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
552
553 /*
554 * VIA ACPI: One IO region pointed to by longword at
555 * 0x48 or 0x20 (256 bytes of ACPI registers)
556 */
557 static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev)
558 {
559 u32 region;
560
561 if (dev->revision & 0x10) {
562 pci_read_config_dword(dev, 0x48, &region);
563 region &= PCI_BASE_ADDRESS_IO_MASK;
564 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI");
565 }
566 }
567 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
568
569 /*
570 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
571 * 0x48 (256 bytes of ACPI registers)
572 * 0x70 (128 bytes of hardware monitoring register)
573 * 0x90 (16 bytes of SMB registers)
574 */
575 static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev)
576 {
577 u16 hm;
578 u32 smb;
579
580 quirk_vt82c586_acpi(dev);
581
582 pci_read_config_word(dev, 0x70, &hm);
583 hm &= PCI_BASE_ADDRESS_IO_MASK;
584 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c686 HW-mon");
585
586 pci_read_config_dword(dev, 0x90, &smb);
587 smb &= PCI_BASE_ADDRESS_IO_MASK;
588 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB");
589 }
590 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
591
592 /*
593 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
594 * 0x88 (128 bytes of power management registers)
595 * 0xd0 (16 bytes of SMB registers)
596 */
597 static void __devinit quirk_vt8235_acpi(struct pci_dev *dev)
598 {
599 u16 pm, smb;
600
601 pci_read_config_word(dev, 0x88, &pm);
602 pm &= PCI_BASE_ADDRESS_IO_MASK;
603 quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
604
605 pci_read_config_word(dev, 0xd0, &smb);
606 smb &= PCI_BASE_ADDRESS_IO_MASK;
607 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1, "vt8235 SMB");
608 }
609 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
610
611
612 #ifdef CONFIG_X86_IO_APIC
613
614 #include <asm/io_apic.h>
615
616 /*
617 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
618 * devices to the external APIC.
619 *
620 * TODO: When we have device-specific interrupt routers,
621 * this code will go away from quirks.
622 */
623 static void quirk_via_ioapic(struct pci_dev *dev)
624 {
625 u8 tmp;
626
627 if (nr_ioapics < 1)
628 tmp = 0; /* nothing routed to external APIC */
629 else
630 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
631
632 dev_info(&dev->dev, "%sbling VIA external APIC routing\n",
633 tmp == 0 ? "Disa" : "Ena");
634
635 /* Offset 0x58: External APIC IRQ output control */
636 pci_write_config_byte (dev, 0x58, tmp);
637 }
638 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
639 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
640
641 /*
642 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit.
643 * This leads to doubled level interrupt rates.
644 * Set this bit to get rid of cycle wastage.
645 * Otherwise uncritical.
646 */
647 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
648 {
649 u8 misc_control2;
650 #define BYPASS_APIC_DEASSERT 8
651
652 pci_read_config_byte(dev, 0x5B, &misc_control2);
653 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
654 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
655 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
656 }
657 }
658 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
659 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
660
661 /*
662 * The AMD io apic can hang the box when an apic irq is masked.
663 * We check all revs >= B0 (yet not in the pre production!) as the bug
664 * is currently marked NoFix
665 *
666 * We have multiple reports of hangs with this chipset that went away with
667 * noapic specified. For the moment we assume it's the erratum. We may be wrong
668 * of course. However the advice is demonstrably good even if so..
669 */
670 static void __devinit quirk_amd_ioapic(struct pci_dev *dev)
671 {
672 if (dev->revision >= 0x02) {
673 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
674 dev_warn(&dev->dev, " : booting with the \"noapic\" option\n");
675 }
676 }
677 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
678
679 static void __init quirk_ioapic_rmw(struct pci_dev *dev)
680 {
681 if (dev->devfn == 0 && dev->bus->number == 0)
682 sis_apic_bug = 1;
683 }
684 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw);
685 #endif /* CONFIG_X86_IO_APIC */
686
687 /*
688 * Some settings of MMRBC can lead to data corruption so block changes.
689 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
690 */
691 static void __init quirk_amd_8131_mmrbc(struct pci_dev *dev)
692 {
693 if (dev->subordinate && dev->revision <= 0x12) {
694 dev_info(&dev->dev, "AMD8131 rev %x detected; "
695 "disabling PCI-X MMRBC\n", dev->revision);
696 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
697 }
698 }
699 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
700
701 /*
702 * FIXME: it is questionable that quirk_via_acpi
703 * is needed. It shows up as an ISA bridge, and does not
704 * support the PCI_INTERRUPT_LINE register at all. Therefore
705 * it seems like setting the pci_dev's 'irq' to the
706 * value of the ACPI SCI interrupt is only done for convenience.
707 * -jgarzik
708 */
709 static void __devinit quirk_via_acpi(struct pci_dev *d)
710 {
711 /*
712 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
713 */
714 u8 irq;
715 pci_read_config_byte(d, 0x42, &irq);
716 irq &= 0xf;
717 if (irq && (irq != 2))
718 d->irq = irq;
719 }
720 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
721 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
722
723
724 /*
725 * VIA bridges which have VLink
726 */
727
728 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
729
730 static void quirk_via_bridge(struct pci_dev *dev)
731 {
732 /* See what bridge we have and find the device ranges */
733 switch (dev->device) {
734 case PCI_DEVICE_ID_VIA_82C686:
735 /* The VT82C686 is special, it attaches to PCI and can have
736 any device number. All its subdevices are functions of
737 that single device. */
738 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
739 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
740 break;
741 case PCI_DEVICE_ID_VIA_8237:
742 case PCI_DEVICE_ID_VIA_8237A:
743 via_vlink_dev_lo = 15;
744 break;
745 case PCI_DEVICE_ID_VIA_8235:
746 via_vlink_dev_lo = 16;
747 break;
748 case PCI_DEVICE_ID_VIA_8231:
749 case PCI_DEVICE_ID_VIA_8233_0:
750 case PCI_DEVICE_ID_VIA_8233A:
751 case PCI_DEVICE_ID_VIA_8233C_0:
752 via_vlink_dev_lo = 17;
753 break;
754 }
755 }
756 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
757 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
758 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
759 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
760 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
761 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
762 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
763 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
764
765 /**
766 * quirk_via_vlink - VIA VLink IRQ number update
767 * @dev: PCI device
768 *
769 * If the device we are dealing with is on a PIC IRQ we need to
770 * ensure that the IRQ line register which usually is not relevant
771 * for PCI cards, is actually written so that interrupts get sent
772 * to the right place.
773 * We only do this on systems where a VIA south bridge was detected,
774 * and only for VIA devices on the motherboard (see quirk_via_bridge
775 * above).
776 */
777
778 static void quirk_via_vlink(struct pci_dev *dev)
779 {
780 u8 irq, new_irq;
781
782 /* Check if we have VLink at all */
783 if (via_vlink_dev_lo == -1)
784 return;
785
786 new_irq = dev->irq;
787
788 /* Don't quirk interrupts outside the legacy IRQ range */
789 if (!new_irq || new_irq > 15)
790 return;
791
792 /* Internal device ? */
793 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
794 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
795 return;
796
797 /* This is an internal VLink device on a PIC interrupt. The BIOS
798 ought to have set this but may not have, so we redo it */
799
800 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
801 if (new_irq != irq) {
802 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n",
803 irq, new_irq);
804 udelay(15); /* unknown if delay really needed */
805 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
806 }
807 }
808 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
809
810 /*
811 * VIA VT82C598 has its device ID settable and many BIOSes
812 * set it to the ID of VT82C597 for backward compatibility.
813 * We need to switch it off to be able to recognize the real
814 * type of the chip.
815 */
816 static void __devinit quirk_vt82c598_id(struct pci_dev *dev)
817 {
818 pci_write_config_byte(dev, 0xfc, 0);
819 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
820 }
821 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
822
823 /*
824 * CardBus controllers have a legacy base address that enables them
825 * to respond as i82365 pcmcia controllers. We don't want them to
826 * do this even if the Linux CardBus driver is not loaded, because
827 * the Linux i82365 driver does not (and should not) handle CardBus.
828 */
829 static void quirk_cardbus_legacy(struct pci_dev *dev)
830 {
831 if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class)
832 return;
833 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
834 }
835 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
836 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
837
838 /*
839 * Following the PCI ordering rules is optional on the AMD762. I'm not
840 * sure what the designers were smoking but let's not inhale...
841 *
842 * To be fair to AMD, it follows the spec by default, its BIOS people
843 * who turn it off!
844 */
845 static void quirk_amd_ordering(struct pci_dev *dev)
846 {
847 u32 pcic;
848 pci_read_config_dword(dev, 0x4C, &pcic);
849 if ((pcic&6)!=6) {
850 pcic |= 6;
851 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
852 pci_write_config_dword(dev, 0x4C, pcic);
853 pci_read_config_dword(dev, 0x84, &pcic);
854 pcic |= (1<<23); /* Required in this mode */
855 pci_write_config_dword(dev, 0x84, pcic);
856 }
857 }
858 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
859 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
860
861 /*
862 * DreamWorks provided workaround for Dunord I-3000 problem
863 *
864 * This card decodes and responds to addresses not apparently
865 * assigned to it. We force a larger allocation to ensure that
866 * nothing gets put too close to it.
867 */
868 static void __devinit quirk_dunord ( struct pci_dev * dev )
869 {
870 struct resource *r = &dev->resource [1];
871 r->start = 0;
872 r->end = 0xffffff;
873 }
874 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
875
876 /*
877 * i82380FB mobile docking controller: its PCI-to-PCI bridge
878 * is subtractive decoding (transparent), and does indicate this
879 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
880 * instead of 0x01.
881 */
882 static void __devinit quirk_transparent_bridge(struct pci_dev *dev)
883 {
884 dev->transparent = 1;
885 }
886 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
887 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
888
889 /*
890 * Common misconfiguration of the MediaGX/Geode PCI master that will
891 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
892 * datasheets found at http://www.national.com/ds/GX for info on what
893 * these bits do. <christer@weinigel.se>
894 */
895 static void quirk_mediagx_master(struct pci_dev *dev)
896 {
897 u8 reg;
898 pci_read_config_byte(dev, 0x41, &reg);
899 if (reg & 2) {
900 reg &= ~2;
901 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
902 pci_write_config_byte(dev, 0x41, reg);
903 }
904 }
905 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
906 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
907
908 /*
909 * Ensure C0 rev restreaming is off. This is normally done by
910 * the BIOS but in the odd case it is not the results are corruption
911 * hence the presence of a Linux check
912 */
913 static void quirk_disable_pxb(struct pci_dev *pdev)
914 {
915 u16 config;
916
917 if (pdev->revision != 0x04) /* Only C0 requires this */
918 return;
919 pci_read_config_word(pdev, 0x40, &config);
920 if (config & (1<<6)) {
921 config &= ~(1<<6);
922 pci_write_config_word(pdev, 0x40, config);
923 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n");
924 }
925 }
926 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
927 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
928
929 static void __devinit quirk_amd_ide_mode(struct pci_dev *pdev)
930 {
931 /* set sb600/sb700/sb800 sata to ahci mode */
932 u8 tmp;
933
934 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
935 if (tmp == 0x01) {
936 pci_read_config_byte(pdev, 0x40, &tmp);
937 pci_write_config_byte(pdev, 0x40, tmp|1);
938 pci_write_config_byte(pdev, 0x9, 1);
939 pci_write_config_byte(pdev, 0xa, 6);
940 pci_write_config_byte(pdev, 0x40, tmp);
941
942 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
943 dev_info(&pdev->dev, "set SATA to AHCI mode\n");
944 }
945 }
946 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
947 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
948 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
949 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
950
951 /*
952 * Serverworks CSB5 IDE does not fully support native mode
953 */
954 static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev)
955 {
956 u8 prog;
957 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
958 if (prog & 5) {
959 prog &= ~5;
960 pdev->class &= ~5;
961 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
962 /* PCI layer will sort out resources */
963 }
964 }
965 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
966
967 /*
968 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
969 */
970 static void __init quirk_ide_samemode(struct pci_dev *pdev)
971 {
972 u8 prog;
973
974 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
975
976 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
977 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n");
978 prog &= ~5;
979 pdev->class &= ~5;
980 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
981 }
982 }
983 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
984
985 /*
986 * Some ATA devices break if put into D3
987 */
988
989 static void __devinit quirk_no_ata_d3(struct pci_dev *pdev)
990 {
991 /* Quirk the legacy ATA devices only. The AHCI ones are ok */
992 if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE)
993 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
994 }
995 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID, quirk_no_ata_d3);
996 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID, quirk_no_ata_d3);
997
998 /* This was originally an Alpha specific thing, but it really fits here.
999 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1000 */
1001 static void __init quirk_eisa_bridge(struct pci_dev *dev)
1002 {
1003 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1004 }
1005 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
1006
1007
1008 /*
1009 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1010 * is not activated. The myth is that Asus said that they do not want the
1011 * users to be irritated by just another PCI Device in the Win98 device
1012 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
1013 * package 2.7.0 for details)
1014 *
1015 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1016 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
1017 * becomes necessary to do this tweak in two steps -- the chosen trigger
1018 * is either the Host bridge (preferred) or on-board VGA controller.
1019 *
1020 * Note that we used to unhide the SMBus that way on Toshiba laptops
1021 * (Satellite A40 and Tecra M2) but then found that the thermal management
1022 * was done by SMM code, which could cause unsynchronized concurrent
1023 * accesses to the SMBus registers, with potentially bad effects. Thus you
1024 * should be very careful when adding new entries: if SMM is accessing the
1025 * Intel SMBus, this is a very good reason to leave it hidden.
1026 *
1027 * Likewise, many recent laptops use ACPI for thermal management. If the
1028 * ACPI DSDT code accesses the SMBus, then Linux should not access it
1029 * natively, and keeping the SMBus hidden is the right thing to do. If you
1030 * are about to add an entry in the table below, please first disassemble
1031 * the DSDT and double-check that there is no code accessing the SMBus.
1032 */
1033 static int asus_hides_smbus;
1034
1035 static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
1036 {
1037 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1038 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
1039 switch(dev->subsystem_device) {
1040 case 0x8025: /* P4B-LX */
1041 case 0x8070: /* P4B */
1042 case 0x8088: /* P4B533 */
1043 case 0x1626: /* L3C notebook */
1044 asus_hides_smbus = 1;
1045 }
1046 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
1047 switch(dev->subsystem_device) {
1048 case 0x80b1: /* P4GE-V */
1049 case 0x80b2: /* P4PE */
1050 case 0x8093: /* P4B533-V */
1051 asus_hides_smbus = 1;
1052 }
1053 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
1054 switch(dev->subsystem_device) {
1055 case 0x8030: /* P4T533 */
1056 asus_hides_smbus = 1;
1057 }
1058 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1059 switch (dev->subsystem_device) {
1060 case 0x8070: /* P4G8X Deluxe */
1061 asus_hides_smbus = 1;
1062 }
1063 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
1064 switch (dev->subsystem_device) {
1065 case 0x80c9: /* PU-DLS */
1066 asus_hides_smbus = 1;
1067 }
1068 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1069 switch (dev->subsystem_device) {
1070 case 0x1751: /* M2N notebook */
1071 case 0x1821: /* M5N notebook */
1072 asus_hides_smbus = 1;
1073 }
1074 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1075 switch (dev->subsystem_device) {
1076 case 0x184b: /* W1N notebook */
1077 case 0x186a: /* M6Ne notebook */
1078 asus_hides_smbus = 1;
1079 }
1080 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1081 switch (dev->subsystem_device) {
1082 case 0x80f2: /* P4P800-X */
1083 asus_hides_smbus = 1;
1084 }
1085 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
1086 switch (dev->subsystem_device) {
1087 case 0x1882: /* M6V notebook */
1088 case 0x1977: /* A6VA notebook */
1089 asus_hides_smbus = 1;
1090 }
1091 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1092 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1093 switch(dev->subsystem_device) {
1094 case 0x088C: /* HP Compaq nc8000 */
1095 case 0x0890: /* HP Compaq nc6000 */
1096 asus_hides_smbus = 1;
1097 }
1098 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1099 switch (dev->subsystem_device) {
1100 case 0x12bc: /* HP D330L */
1101 case 0x12bd: /* HP D530 */
1102 asus_hides_smbus = 1;
1103 }
1104 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1105 switch (dev->subsystem_device) {
1106 case 0x12bf: /* HP xw4100 */
1107 asus_hides_smbus = 1;
1108 }
1109 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1110 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1111 switch(dev->subsystem_device) {
1112 case 0xC00C: /* Samsung P35 notebook */
1113 asus_hides_smbus = 1;
1114 }
1115 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1116 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1117 switch(dev->subsystem_device) {
1118 case 0x0058: /* Compaq Evo N620c */
1119 asus_hides_smbus = 1;
1120 }
1121 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1122 switch(dev->subsystem_device) {
1123 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1124 /* Motherboard doesn't have Host bridge
1125 * subvendor/subdevice IDs, therefore checking
1126 * its on-board VGA controller */
1127 asus_hides_smbus = 1;
1128 }
1129 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_IG)
1130 switch(dev->subsystem_device) {
1131 case 0x00b8: /* Compaq Evo D510 CMT */
1132 case 0x00b9: /* Compaq Evo D510 SFF */
1133 asus_hides_smbus = 1;
1134 }
1135 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1136 switch (dev->subsystem_device) {
1137 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1138 /* Motherboard doesn't have host bridge
1139 * subvendor/subdevice IDs, therefore checking
1140 * its on-board VGA controller */
1141 asus_hides_smbus = 1;
1142 }
1143 }
1144 }
1145 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1146 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1147 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1148 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
1149 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
1150 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1151 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1152 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1153 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1154 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1155
1156 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
1157 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_IG, asus_hides_smbus_hostbridge);
1158 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
1159
1160 static void asus_hides_smbus_lpc(struct pci_dev *dev)
1161 {
1162 u16 val;
1163
1164 if (likely(!asus_hides_smbus))
1165 return;
1166
1167 pci_read_config_word(dev, 0xF2, &val);
1168 if (val & 0x8) {
1169 pci_write_config_word(dev, 0xF2, val & (~0x8));
1170 pci_read_config_word(dev, 0xF2, &val);
1171 if (val & 0x8)
1172 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
1173 else
1174 dev_info(&dev->dev, "Enabled i801 SMBus device\n");
1175 }
1176 }
1177 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1178 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1179 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1180 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1181 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1182 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1183 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1184 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1185 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1186 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1187 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1188 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1189 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1190 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1191
1192 /* It appears we just have one such device. If not, we have a warning */
1193 static void __iomem *asus_rcba_base;
1194 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
1195 {
1196 u32 rcba;
1197
1198 if (likely(!asus_hides_smbus))
1199 return;
1200 WARN_ON(asus_rcba_base);
1201
1202 pci_read_config_dword(dev, 0xF0, &rcba);
1203 /* use bits 31:14, 16 kB aligned */
1204 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000);
1205 if (asus_rcba_base == NULL)
1206 return;
1207 }
1208
1209 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1210 {
1211 u32 val;
1212
1213 if (likely(!asus_hides_smbus || !asus_rcba_base))
1214 return;
1215 /* read the Function Disable register, dword mode only */
1216 val = readl(asus_rcba_base + 0x3418);
1217 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */
1218 }
1219
1220 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1221 {
1222 if (likely(!asus_hides_smbus || !asus_rcba_base))
1223 return;
1224 iounmap(asus_rcba_base);
1225 asus_rcba_base = NULL;
1226 dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n");
1227 }
1228
1229 static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1230 {
1231 asus_hides_smbus_lpc_ich6_suspend(dev);
1232 asus_hides_smbus_lpc_ich6_resume_early(dev);
1233 asus_hides_smbus_lpc_ich6_resume(dev);
1234 }
1235 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
1236 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1237 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1238 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
1239
1240 /*
1241 * SiS 96x south bridge: BIOS typically hides SMBus device...
1242 */
1243 static void quirk_sis_96x_smbus(struct pci_dev *dev)
1244 {
1245 u8 val = 0;
1246 pci_read_config_byte(dev, 0x77, &val);
1247 if (val & 0x10) {
1248 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n");
1249 pci_write_config_byte(dev, 0x77, val & ~0x10);
1250 }
1251 }
1252 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1253 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1254 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1255 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1256 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1257 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1258 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1259 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1260
1261 /*
1262 * ... This is further complicated by the fact that some SiS96x south
1263 * bridges pretend to be 85C503/5513 instead. In that case see if we
1264 * spotted a compatible north bridge to make sure.
1265 * (pci_find_device doesn't work yet)
1266 *
1267 * We can also enable the sis96x bit in the discovery register..
1268 */
1269 #define SIS_DETECT_REGISTER 0x40
1270
1271 static void quirk_sis_503(struct pci_dev *dev)
1272 {
1273 u8 reg;
1274 u16 devid;
1275
1276 pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
1277 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1278 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1279 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1280 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1281 return;
1282 }
1283
1284 /*
1285 * Ok, it now shows up as a 96x.. run the 96x quirk by
1286 * hand in case it has already been processed.
1287 * (depends on link order, which is apparently not guaranteed)
1288 */
1289 dev->device = devid;
1290 quirk_sis_96x_smbus(dev);
1291 }
1292 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1293 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1294
1295
1296 /*
1297 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1298 * and MC97 modem controller are disabled when a second PCI soundcard is
1299 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1300 * -- bjd
1301 */
1302 static void asus_hides_ac97_lpc(struct pci_dev *dev)
1303 {
1304 u8 val;
1305 int asus_hides_ac97 = 0;
1306
1307 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1308 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1309 asus_hides_ac97 = 1;
1310 }
1311
1312 if (!asus_hides_ac97)
1313 return;
1314
1315 pci_read_config_byte(dev, 0x50, &val);
1316 if (val & 0xc0) {
1317 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1318 pci_read_config_byte(dev, 0x50, &val);
1319 if (val & 0xc0)
1320 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val);
1321 else
1322 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n");
1323 }
1324 }
1325 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1326 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1327
1328 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1329
1330 /*
1331 * If we are using libata we can drive this chip properly but must
1332 * do this early on to make the additional device appear during
1333 * the PCI scanning.
1334 */
1335 static void quirk_jmicron_ata(struct pci_dev *pdev)
1336 {
1337 u32 conf1, conf5, class;
1338 u8 hdr;
1339
1340 /* Only poke fn 0 */
1341 if (PCI_FUNC(pdev->devfn))
1342 return;
1343
1344 pci_read_config_dword(pdev, 0x40, &conf1);
1345 pci_read_config_dword(pdev, 0x80, &conf5);
1346
1347 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1348 conf5 &= ~(1 << 24); /* Clear bit 24 */
1349
1350 switch (pdev->device) {
1351 case PCI_DEVICE_ID_JMICRON_JMB360:
1352 /* The controller should be in single function ahci mode */
1353 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1354 break;
1355
1356 case PCI_DEVICE_ID_JMICRON_JMB365:
1357 case PCI_DEVICE_ID_JMICRON_JMB366:
1358 /* Redirect IDE second PATA port to the right spot */
1359 conf5 |= (1 << 24);
1360 /* Fall through */
1361 case PCI_DEVICE_ID_JMICRON_JMB361:
1362 case PCI_DEVICE_ID_JMICRON_JMB363:
1363 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1364 /* Set the class codes correctly and then direct IDE 0 */
1365 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
1366 break;
1367
1368 case PCI_DEVICE_ID_JMICRON_JMB368:
1369 /* The controller should be in single function IDE mode */
1370 conf1 |= 0x00C00000; /* Set 22, 23 */
1371 break;
1372 }
1373
1374 pci_write_config_dword(pdev, 0x40, conf1);
1375 pci_write_config_dword(pdev, 0x80, conf5);
1376
1377 /* Update pdev accordingly */
1378 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1379 pdev->hdr_type = hdr & 0x7f;
1380 pdev->multifunction = !!(hdr & 0x80);
1381
1382 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1383 pdev->class = class >> 8;
1384 }
1385 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1386 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1387 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1388 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1389 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1390 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1391 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1392 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1393 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1394 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1395 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1396 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1397
1398 #endif
1399
1400 #ifdef CONFIG_X86_IO_APIC
1401 static void __init quirk_alder_ioapic(struct pci_dev *pdev)
1402 {
1403 int i;
1404
1405 if ((pdev->class >> 8) != 0xff00)
1406 return;
1407
1408 /* the first BAR is the location of the IO APIC...we must
1409 * not touch this (and it's already covered by the fixmap), so
1410 * forcibly insert it into the resource tree */
1411 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1412 insert_resource(&iomem_resource, &pdev->resource[0]);
1413
1414 /* The next five BARs all seem to be rubbish, so just clean
1415 * them out */
1416 for (i=1; i < 6; i++) {
1417 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1418 }
1419
1420 }
1421 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
1422 #endif
1423
1424 static void __devinit quirk_pcie_mch(struct pci_dev *pdev)
1425 {
1426 pcie_mch_quirk = 1;
1427 }
1428 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1429 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1430 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
1431
1432
1433 /*
1434 * It's possible for the MSI to get corrupted if shpc and acpi
1435 * are used together on certain PXH-based systems.
1436 */
1437 static void __devinit quirk_pcie_pxh(struct pci_dev *dev)
1438 {
1439 pci_msi_off(dev);
1440 dev->no_msi = 1;
1441 dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n");
1442 }
1443 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1444 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1445 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1446 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1447 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1448
1449 /*
1450 * Some Intel PCI Express chipsets have trouble with downstream
1451 * device power management.
1452 */
1453 static void quirk_intel_pcie_pm(struct pci_dev * dev)
1454 {
1455 pci_pm_d3_delay = 120;
1456 dev->no_d1d2 = 1;
1457 }
1458
1459 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1460 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1461 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1462 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1463 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1464 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1465 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1466 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1467 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1468 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1469 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1470 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1471 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1472 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1473 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1474 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1475 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1476 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1477 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1478 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1479 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
1480
1481 #ifdef CONFIG_X86_IO_APIC
1482 /*
1483 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1484 * remap the original interrupt in the linux kernel to the boot interrupt, so
1485 * that a PCI device's interrupt handler is installed on the boot interrupt
1486 * line instead.
1487 */
1488 static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
1489 {
1490 if (noioapicquirk || noioapicreroute)
1491 return;
1492
1493 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
1494
1495 printk(KERN_INFO "PCI quirk: reroute interrupts for 0x%04x:0x%04x\n",
1496 dev->vendor, dev->device);
1497 return;
1498 }
1499 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1500 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1501 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1502 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1503 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1504 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1505 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1506 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1507 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1508 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1509 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1510 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1511 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1512 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1513 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1514 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1515
1516 /*
1517 * On some chipsets we can disable the generation of legacy INTx boot
1518 * interrupts.
1519 */
1520
1521 /*
1522 * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no
1523 * 300641-004US, section 5.7.3.
1524 */
1525 #define INTEL_6300_IOAPIC_ABAR 0x40
1526 #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
1527
1528 static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
1529 {
1530 u16 pci_config_word;
1531
1532 if (noioapicquirk)
1533 return;
1534
1535 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word);
1536 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
1537 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);
1538
1539 printk(KERN_INFO "disabled boot interrupt on device 0x%04x:0x%04x\n",
1540 dev->vendor, dev->device);
1541 }
1542 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1543 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1544
1545 /*
1546 * disable boot interrupts on HT-1000
1547 */
1548 #define BC_HT1000_FEATURE_REG 0x64
1549 #define BC_HT1000_PIC_REGS_ENABLE (1<<0)
1550 #define BC_HT1000_MAP_IDX 0xC00
1551 #define BC_HT1000_MAP_DATA 0xC01
1552
1553 static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
1554 {
1555 u32 pci_config_dword;
1556 u8 irq;
1557
1558 if (noioapicquirk)
1559 return;
1560
1561 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
1562 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
1563 BC_HT1000_PIC_REGS_ENABLE);
1564
1565 for (irq = 0x10; irq < 0x10 + 32; irq++) {
1566 outb(irq, BC_HT1000_MAP_IDX);
1567 outb(0x00, BC_HT1000_MAP_DATA);
1568 }
1569
1570 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
1571
1572 printk(KERN_INFO "disabled boot interrupts on PCI device"
1573 "0x%04x:0x%04x\n", dev->vendor, dev->device);
1574 }
1575 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1576 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1577
1578 /*
1579 * disable boot interrupts on AMD and ATI chipsets
1580 */
1581 /*
1582 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
1583 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
1584 * (due to an erratum).
1585 */
1586 #define AMD_813X_MISC 0x40
1587 #define AMD_813X_NOIOAMODE (1<<0)
1588 #define AMD_813X_REV_B2 0x13
1589
1590 static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
1591 {
1592 u32 pci_config_dword;
1593
1594 if (noioapicquirk)
1595 return;
1596 if (dev->revision == AMD_813X_REV_B2)
1597 return;
1598
1599 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
1600 pci_config_dword &= ~AMD_813X_NOIOAMODE;
1601 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
1602
1603 printk(KERN_INFO "disabled boot interrupts on PCI device "
1604 "0x%04x:0x%04x\n", dev->vendor, dev->device);
1605 }
1606 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1607 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1608
1609 #define AMD_8111_PCI_IRQ_ROUTING 0x56
1610
1611 static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
1612 {
1613 u16 pci_config_word;
1614
1615 if (noioapicquirk)
1616 return;
1617
1618 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
1619 if (!pci_config_word) {
1620 printk(KERN_INFO "boot interrupts on PCI device 0x%04x:0x%04x "
1621 "already disabled\n",
1622 dev->vendor, dev->device);
1623 return;
1624 }
1625 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
1626 printk(KERN_INFO "disabled boot interrupts on PCI device "
1627 "0x%04x:0x%04x\n", dev->vendor, dev->device);
1628 }
1629 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1630 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1631 #endif /* CONFIG_X86_IO_APIC */
1632
1633 /*
1634 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
1635 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1636 * Re-allocate the region if needed...
1637 */
1638 static void __init quirk_tc86c001_ide(struct pci_dev *dev)
1639 {
1640 struct resource *r = &dev->resource[0];
1641
1642 if (r->start & 0x8) {
1643 r->start = 0;
1644 r->end = 0xf;
1645 }
1646 }
1647 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
1648 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
1649 quirk_tc86c001_ide);
1650
1651 static void __devinit quirk_netmos(struct pci_dev *dev)
1652 {
1653 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1654 unsigned int num_serial = dev->subsystem_device & 0xf;
1655
1656 /*
1657 * These Netmos parts are multiport serial devices with optional
1658 * parallel ports. Even when parallel ports are present, they
1659 * are identified as class SERIAL, which means the serial driver
1660 * will claim them. To prevent this, mark them as class OTHER.
1661 * These combo devices should be claimed by parport_serial.
1662 *
1663 * The subdevice ID is of the form 0x00PS, where <P> is the number
1664 * of parallel ports and <S> is the number of serial ports.
1665 */
1666 switch (dev->device) {
1667 case PCI_DEVICE_ID_NETMOS_9735:
1668 case PCI_DEVICE_ID_NETMOS_9745:
1669 case PCI_DEVICE_ID_NETMOS_9835:
1670 case PCI_DEVICE_ID_NETMOS_9845:
1671 case PCI_DEVICE_ID_NETMOS_9855:
1672 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL &&
1673 num_parallel) {
1674 dev_info(&dev->dev, "Netmos %04x (%u parallel, "
1675 "%u serial); changing class SERIAL to OTHER "
1676 "(use parport_serial)\n",
1677 dev->device, num_parallel, num_serial);
1678 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1679 (dev->class & 0xff);
1680 }
1681 }
1682 }
1683 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos);
1684
1685 static void __devinit quirk_e100_interrupt(struct pci_dev *dev)
1686 {
1687 u16 command, pmcsr;
1688 u8 __iomem *csr;
1689 u8 cmd_hi;
1690 int pm;
1691
1692 switch (dev->device) {
1693 /* PCI IDs taken from drivers/net/e100.c */
1694 case 0x1029:
1695 case 0x1030 ... 0x1034:
1696 case 0x1038 ... 0x103E:
1697 case 0x1050 ... 0x1057:
1698 case 0x1059:
1699 case 0x1064 ... 0x106B:
1700 case 0x1091 ... 0x1095:
1701 case 0x1209:
1702 case 0x1229:
1703 case 0x2449:
1704 case 0x2459:
1705 case 0x245D:
1706 case 0x27DC:
1707 break;
1708 default:
1709 return;
1710 }
1711
1712 /*
1713 * Some firmware hands off the e100 with interrupts enabled,
1714 * which can cause a flood of interrupts if packets are
1715 * received before the driver attaches to the device. So
1716 * disable all e100 interrupts here. The driver will
1717 * re-enable them when it's ready.
1718 */
1719 pci_read_config_word(dev, PCI_COMMAND, &command);
1720
1721 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
1722 return;
1723
1724 /*
1725 * Check that the device is in the D0 power state. If it's not,
1726 * there is no point to look any further.
1727 */
1728 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1729 if (pm) {
1730 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
1731 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
1732 return;
1733 }
1734
1735 /* Convert from PCI bus to resource space. */
1736 csr = ioremap(pci_resource_start(dev, 0), 8);
1737 if (!csr) {
1738 dev_warn(&dev->dev, "Can't map e100 registers\n");
1739 return;
1740 }
1741
1742 cmd_hi = readb(csr + 3);
1743 if (cmd_hi == 0) {
1744 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; "
1745 "disabling\n");
1746 writeb(1, csr + 3);
1747 }
1748
1749 iounmap(csr);
1750 }
1751 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_e100_interrupt);
1752
1753 /*
1754 * The 82575 and 82598 may experience data corruption issues when transitioning
1755 * out of L0S. To prevent this we need to disable L0S on the pci-e link
1756 */
1757 static void __devinit quirk_disable_aspm_l0s(struct pci_dev *dev)
1758 {
1759 dev_info(&dev->dev, "Disabling L0s\n");
1760 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
1761 }
1762 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
1763 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
1764 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
1765 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
1766 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
1767 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
1768 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
1769 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
1770 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
1771 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
1772 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
1773 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
1774 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
1775 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
1776
1777 static void __devinit fixup_rev1_53c810(struct pci_dev* dev)
1778 {
1779 /* rev 1 ncr53c810 chips don't set the class at all which means
1780 * they don't get their resources remapped. Fix that here.
1781 */
1782
1783 if (dev->class == PCI_CLASS_NOT_DEFINED) {
1784 dev_info(&dev->dev, "NCR 53c810 rev 1 detected; setting PCI class\n");
1785 dev->class = PCI_CLASS_STORAGE_SCSI;
1786 }
1787 }
1788 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
1789
1790 /* Enable 1k I/O space granularity on the Intel P64H2 */
1791 static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev)
1792 {
1793 u16 en1k;
1794 u8 io_base_lo, io_limit_lo;
1795 unsigned long base, limit;
1796 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1797
1798 pci_read_config_word(dev, 0x40, &en1k);
1799
1800 if (en1k & 0x200) {
1801 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n");
1802
1803 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
1804 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
1805 base = (io_base_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1806 limit = (io_limit_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1807
1808 if (base <= limit) {
1809 res->start = base;
1810 res->end = limit + 0x3ff;
1811 }
1812 }
1813 }
1814 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
1815
1816 /* Fix the IOBL_ADR for 1k I/O space granularity on the Intel P64H2
1817 * The IOBL_ADR gets re-written to 4k boundaries in pci_setup_bridge()
1818 * in drivers/pci/setup-bus.c
1819 */
1820 static void __devinit quirk_p64h2_1k_io_fix_iobl(struct pci_dev *dev)
1821 {
1822 u16 en1k, iobl_adr, iobl_adr_1k;
1823 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1824
1825 pci_read_config_word(dev, 0x40, &en1k);
1826
1827 if (en1k & 0x200) {
1828 pci_read_config_word(dev, PCI_IO_BASE, &iobl_adr);
1829
1830 iobl_adr_1k = iobl_adr | (res->start >> 8) | (res->end & 0xfc00);
1831
1832 if (iobl_adr != iobl_adr_1k) {
1833 dev_info(&dev->dev, "Fixing P64H2 IOBL_ADR from 0x%x to 0x%x for 1KB granularity\n",
1834 iobl_adr,iobl_adr_1k);
1835 pci_write_config_word(dev, PCI_IO_BASE, iobl_adr_1k);
1836 }
1837 }
1838 }
1839 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io_fix_iobl);
1840
1841 /* Under some circumstances, AER is not linked with extended capabilities.
1842 * Force it to be linked by setting the corresponding control bit in the
1843 * config space.
1844 */
1845 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
1846 {
1847 uint8_t b;
1848 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
1849 if (!(b & 0x20)) {
1850 pci_write_config_byte(dev, 0xf41, b | 0x20);
1851 dev_info(&dev->dev,
1852 "Linking AER extended capability\n");
1853 }
1854 }
1855 }
1856 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1857 quirk_nvidia_ck804_pcie_aer_ext_cap);
1858 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1859 quirk_nvidia_ck804_pcie_aer_ext_cap);
1860
1861 static void __devinit quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
1862 {
1863 /*
1864 * Disable PCI Bus Parking and PCI Master read caching on CX700
1865 * which causes unspecified timing errors with a VT6212L on the PCI
1866 * bus leading to USB2.0 packet loss. The defaults are that these
1867 * features are turned off but some BIOSes turn them on.
1868 */
1869
1870 uint8_t b;
1871 if (pci_read_config_byte(dev, 0x76, &b) == 0) {
1872 if (b & 0x40) {
1873 /* Turn off PCI Bus Parking */
1874 pci_write_config_byte(dev, 0x76, b ^ 0x40);
1875
1876 dev_info(&dev->dev,
1877 "Disabling VIA CX700 PCI parking\n");
1878 }
1879 }
1880
1881 if (pci_read_config_byte(dev, 0x72, &b) == 0) {
1882 if (b != 0) {
1883 /* Turn off PCI Master read caching */
1884 pci_write_config_byte(dev, 0x72, 0x0);
1885
1886 /* Set PCI Master Bus time-out to "1x16 PCLK" */
1887 pci_write_config_byte(dev, 0x75, 0x1);
1888
1889 /* Disable "Read FIFO Timer" */
1890 pci_write_config_byte(dev, 0x77, 0x0);
1891
1892 dev_info(&dev->dev,
1893 "Disabling VIA CX700 PCI caching\n");
1894 }
1895 }
1896 }
1897 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
1898
1899 /*
1900 * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the
1901 * VPD end tag will hang the device. This problem was initially
1902 * observed when a vpd entry was created in sysfs
1903 * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry
1904 * will dump 32k of data. Reading a full 32k will cause an access
1905 * beyond the VPD end tag causing the device to hang. Once the device
1906 * is hung, the bnx2 driver will not be able to reset the device.
1907 * We believe that it is legal to read beyond the end tag and
1908 * therefore the solution is to limit the read/write length.
1909 */
1910 static void __devinit quirk_brcm_570x_limit_vpd(struct pci_dev *dev)
1911 {
1912 /*
1913 * Only disable the VPD capability for 5706, 5706S, 5708,
1914 * 5708S and 5709 rev. A
1915 */
1916 if ((dev->device == PCI_DEVICE_ID_NX2_5706) ||
1917 (dev->device == PCI_DEVICE_ID_NX2_5706S) ||
1918 (dev->device == PCI_DEVICE_ID_NX2_5708) ||
1919 (dev->device == PCI_DEVICE_ID_NX2_5708S) ||
1920 ((dev->device == PCI_DEVICE_ID_NX2_5709) &&
1921 (dev->revision & 0xf0) == 0x0)) {
1922 if (dev->vpd)
1923 dev->vpd->len = 0x80;
1924 }
1925 }
1926
1927 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1928 PCI_DEVICE_ID_NX2_5706,
1929 quirk_brcm_570x_limit_vpd);
1930 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1931 PCI_DEVICE_ID_NX2_5706S,
1932 quirk_brcm_570x_limit_vpd);
1933 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1934 PCI_DEVICE_ID_NX2_5708,
1935 quirk_brcm_570x_limit_vpd);
1936 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1937 PCI_DEVICE_ID_NX2_5708S,
1938 quirk_brcm_570x_limit_vpd);
1939 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1940 PCI_DEVICE_ID_NX2_5709,
1941 quirk_brcm_570x_limit_vpd);
1942 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1943 PCI_DEVICE_ID_NX2_5709S,
1944 quirk_brcm_570x_limit_vpd);
1945
1946 #ifdef CONFIG_PCI_MSI
1947 /* Some chipsets do not support MSI. We cannot easily rely on setting
1948 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
1949 * some other busses controlled by the chipset even if Linux is not
1950 * aware of it. Instead of setting the flag on all busses in the
1951 * machine, simply disable MSI globally.
1952 */
1953 static void __init quirk_disable_all_msi(struct pci_dev *dev)
1954 {
1955 pci_no_msi();
1956 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n");
1957 }
1958 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
1959 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
1960 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
1961 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
1962 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
1963
1964 /* Disable MSI on chipsets that are known to not support it */
1965 static void __devinit quirk_disable_msi(struct pci_dev *dev)
1966 {
1967 if (dev->subordinate) {
1968 dev_warn(&dev->dev, "MSI quirk detected; "
1969 "subordinate MSI disabled\n");
1970 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
1971 }
1972 }
1973 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
1974
1975 /* Go through the list of Hypertransport capabilities and
1976 * return 1 if a HT MSI capability is found and enabled */
1977 static int __devinit msi_ht_cap_enabled(struct pci_dev *dev)
1978 {
1979 int pos, ttl = 48;
1980
1981 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
1982 while (pos && ttl--) {
1983 u8 flags;
1984
1985 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
1986 &flags) == 0)
1987 {
1988 dev_info(&dev->dev, "Found %s HT MSI Mapping\n",
1989 flags & HT_MSI_FLAGS_ENABLE ?
1990 "enabled" : "disabled");
1991 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
1992 }
1993
1994 pos = pci_find_next_ht_capability(dev, pos,
1995 HT_CAPTYPE_MSI_MAPPING);
1996 }
1997 return 0;
1998 }
1999
2000 /* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
2001 static void __devinit quirk_msi_ht_cap(struct pci_dev *dev)
2002 {
2003 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
2004 dev_warn(&dev->dev, "MSI quirk detected; "
2005 "subordinate MSI disabled\n");
2006 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2007 }
2008 }
2009 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
2010 quirk_msi_ht_cap);
2011
2012 /* The nVidia CK804 chipset may have 2 HT MSI mappings.
2013 * MSI are supported if the MSI capability set in any of these mappings.
2014 */
2015 static void __devinit quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
2016 {
2017 struct pci_dev *pdev;
2018
2019 if (!dev->subordinate)
2020 return;
2021
2022 /* check HT MSI cap on this chipset and the root one.
2023 * a single one having MSI is enough to be sure that MSI are supported.
2024 */
2025 pdev = pci_get_slot(dev->bus, 0);
2026 if (!pdev)
2027 return;
2028 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
2029 dev_warn(&dev->dev, "MSI quirk detected; "
2030 "subordinate MSI disabled\n");
2031 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2032 }
2033 pci_dev_put(pdev);
2034 }
2035 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2036 quirk_nvidia_ck804_msi_ht_cap);
2037
2038 /* Force enable MSI mapping capability on HT bridges */
2039 static void __devinit ht_enable_msi_mapping(struct pci_dev *dev)
2040 {
2041 int pos, ttl = 48;
2042
2043 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2044 while (pos && ttl--) {
2045 u8 flags;
2046
2047 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2048 &flags) == 0) {
2049 dev_info(&dev->dev, "Enabling HT MSI Mapping\n");
2050
2051 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2052 flags | HT_MSI_FLAGS_ENABLE);
2053 }
2054 pos = pci_find_next_ht_capability(dev, pos,
2055 HT_CAPTYPE_MSI_MAPPING);
2056 }
2057 }
2058 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2059 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2060 ht_enable_msi_mapping);
2061
2062 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2063 ht_enable_msi_mapping);
2064
2065 /* The P5N32-SLI Premium motherboard from Asus has a problem with msi
2066 * for the MCP55 NIC. It is not yet determined whether the msi problem
2067 * also affects other devices. As for now, turn off msi for this device.
2068 */
2069 static void __devinit nvenet_msi_disable(struct pci_dev *dev)
2070 {
2071 if (dmi_name_in_vendors("P5N32-SLI PREMIUM")) {
2072 dev_info(&dev->dev,
2073 "Disabling msi for MCP55 NIC on P5N32-SLI Premium\n");
2074 dev->no_msi = 1;
2075 }
2076 }
2077 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2078 PCI_DEVICE_ID_NVIDIA_NVENET_15,
2079 nvenet_msi_disable);
2080
2081 static void __devinit nv_ht_enable_msi_mapping(struct pci_dev *dev)
2082 {
2083 struct pci_dev *host_bridge;
2084 int pos;
2085 int i, dev_no;
2086 int found = 0;
2087
2088 dev_no = dev->devfn >> 3;
2089 for (i = dev_no; i >= 0; i--) {
2090 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
2091 if (!host_bridge)
2092 continue;
2093
2094 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2095 if (pos != 0) {
2096 found = 1;
2097 break;
2098 }
2099 pci_dev_put(host_bridge);
2100 }
2101
2102 if (!found)
2103 return;
2104
2105 /* root did that ! */
2106 if (msi_ht_cap_enabled(host_bridge))
2107 goto out;
2108
2109 ht_enable_msi_mapping(dev);
2110
2111 out:
2112 pci_dev_put(host_bridge);
2113 }
2114
2115 static void __devinit ht_disable_msi_mapping(struct pci_dev *dev)
2116 {
2117 int pos, ttl = 48;
2118
2119 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2120 while (pos && ttl--) {
2121 u8 flags;
2122
2123 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2124 &flags) == 0) {
2125 dev_info(&dev->dev, "Disabling HT MSI Mapping\n");
2126
2127 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2128 flags & ~HT_MSI_FLAGS_ENABLE);
2129 }
2130 pos = pci_find_next_ht_capability(dev, pos,
2131 HT_CAPTYPE_MSI_MAPPING);
2132 }
2133 }
2134
2135 static int __devinit ht_check_msi_mapping(struct pci_dev *dev)
2136 {
2137 int pos, ttl = 48;
2138 int found = 0;
2139
2140 /* check if there is HT MSI cap or enabled on this device */
2141 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2142 while (pos && ttl--) {
2143 u8 flags;
2144
2145 if (found < 1)
2146 found = 1;
2147 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2148 &flags) == 0) {
2149 if (flags & HT_MSI_FLAGS_ENABLE) {
2150 if (found < 2) {
2151 found = 2;
2152 break;
2153 }
2154 }
2155 }
2156 pos = pci_find_next_ht_capability(dev, pos,
2157 HT_CAPTYPE_MSI_MAPPING);
2158 }
2159
2160 return found;
2161 }
2162
2163 static void __devinit nv_msi_ht_cap_quirk(struct pci_dev *dev)
2164 {
2165 struct pci_dev *host_bridge;
2166 int pos;
2167 int found;
2168
2169 /* Enabling HT MSI mapping on this device breaks MCP51 */
2170 if (dev->device == 0x270)
2171 return;
2172
2173 /* check if there is HT MSI cap or enabled on this device */
2174 found = ht_check_msi_mapping(dev);
2175
2176 /* no HT MSI CAP */
2177 if (found == 0)
2178 return;
2179
2180 /*
2181 * HT MSI mapping should be disabled on devices that are below
2182 * a non-Hypertransport host bridge. Locate the host bridge...
2183 */
2184 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
2185 if (host_bridge == NULL) {
2186 dev_warn(&dev->dev,
2187 "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2188 return;
2189 }
2190
2191 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2192 if (pos != 0) {
2193 /* Host bridge is to HT */
2194 if (found == 1) {
2195 /* it is not enabled, try to enable it */
2196 nv_ht_enable_msi_mapping(dev);
2197 }
2198 return;
2199 }
2200
2201 /* HT MSI is not enabled */
2202 if (found == 1)
2203 return;
2204
2205 /* Host bridge is not to HT, disable HT MSI mapping on this device */
2206 ht_disable_msi_mapping(dev);
2207 }
2208 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk);
2209 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk);
2210
2211 static void __devinit quirk_msi_intx_disable_bug(struct pci_dev *dev)
2212 {
2213 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2214 }
2215 static void __devinit quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
2216 {
2217 struct pci_dev *p;
2218
2219 /* SB700 MSI issue will be fixed at HW level from revision A21,
2220 * we need check PCI REVISION ID of SMBus controller to get SB700
2221 * revision.
2222 */
2223 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2224 NULL);
2225 if (!p)
2226 return;
2227
2228 if ((p->revision < 0x3B) && (p->revision >= 0x30))
2229 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2230 pci_dev_put(p);
2231 }
2232 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2233 PCI_DEVICE_ID_TIGON3_5780,
2234 quirk_msi_intx_disable_bug);
2235 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2236 PCI_DEVICE_ID_TIGON3_5780S,
2237 quirk_msi_intx_disable_bug);
2238 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2239 PCI_DEVICE_ID_TIGON3_5714,
2240 quirk_msi_intx_disable_bug);
2241 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2242 PCI_DEVICE_ID_TIGON3_5714S,
2243 quirk_msi_intx_disable_bug);
2244 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2245 PCI_DEVICE_ID_TIGON3_5715,
2246 quirk_msi_intx_disable_bug);
2247 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2248 PCI_DEVICE_ID_TIGON3_5715S,
2249 quirk_msi_intx_disable_bug);
2250
2251 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
2252 quirk_msi_intx_disable_ati_bug);
2253 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
2254 quirk_msi_intx_disable_ati_bug);
2255 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
2256 quirk_msi_intx_disable_ati_bug);
2257 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
2258 quirk_msi_intx_disable_ati_bug);
2259 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
2260 quirk_msi_intx_disable_ati_bug);
2261
2262 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
2263 quirk_msi_intx_disable_bug);
2264 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
2265 quirk_msi_intx_disable_bug);
2266 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
2267 quirk_msi_intx_disable_bug);
2268
2269 #endif /* CONFIG_PCI_MSI */
2270
2271 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
2272 struct pci_fixup *end)
2273 {
2274 while (f < end) {
2275 if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) &&
2276 (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) {
2277 dev_dbg(&dev->dev, "calling %pF\n", f->hook);
2278 f->hook(dev);
2279 }
2280 f++;
2281 }
2282 }
2283
2284 extern struct pci_fixup __start_pci_fixups_early[];
2285 extern struct pci_fixup __end_pci_fixups_early[];
2286 extern struct pci_fixup __start_pci_fixups_header[];
2287 extern struct pci_fixup __end_pci_fixups_header[];
2288 extern struct pci_fixup __start_pci_fixups_final[];
2289 extern struct pci_fixup __end_pci_fixups_final[];
2290 extern struct pci_fixup __start_pci_fixups_enable[];
2291 extern struct pci_fixup __end_pci_fixups_enable[];
2292 extern struct pci_fixup __start_pci_fixups_resume[];
2293 extern struct pci_fixup __end_pci_fixups_resume[];
2294 extern struct pci_fixup __start_pci_fixups_resume_early[];
2295 extern struct pci_fixup __end_pci_fixups_resume_early[];
2296 extern struct pci_fixup __start_pci_fixups_suspend[];
2297 extern struct pci_fixup __end_pci_fixups_suspend[];
2298
2299
2300 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
2301 {
2302 struct pci_fixup *start, *end;
2303
2304 switch(pass) {
2305 case pci_fixup_early:
2306 start = __start_pci_fixups_early;
2307 end = __end_pci_fixups_early;
2308 break;
2309
2310 case pci_fixup_header:
2311 start = __start_pci_fixups_header;
2312 end = __end_pci_fixups_header;
2313 break;
2314
2315 case pci_fixup_final:
2316 start = __start_pci_fixups_final;
2317 end = __end_pci_fixups_final;
2318 break;
2319
2320 case pci_fixup_enable:
2321 start = __start_pci_fixups_enable;
2322 end = __end_pci_fixups_enable;
2323 break;
2324
2325 case pci_fixup_resume:
2326 start = __start_pci_fixups_resume;
2327 end = __end_pci_fixups_resume;
2328 break;
2329
2330 case pci_fixup_resume_early:
2331 start = __start_pci_fixups_resume_early;
2332 end = __end_pci_fixups_resume_early;
2333 break;
2334
2335 case pci_fixup_suspend:
2336 start = __start_pci_fixups_suspend;
2337 end = __end_pci_fixups_suspend;
2338 break;
2339
2340 default:
2341 /* stupid compiler warning, you would think with an enum... */
2342 return;
2343 }
2344 pci_do_fixups(dev, start, end);
2345 }
2346 #else
2347 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) {}
2348 #endif
2349 EXPORT_SYMBOL(pci_fixup_device);
Linus' kernel tree