2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/ratelimit.h>
21 #include <linux/pci.h>
22 #include <linux/pci-ats.h>
23 #include <linux/bitmap.h>
24 #include <linux/slab.h>
25 #include <linux/debugfs.h>
26 #include <linux/scatterlist.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/iommu-helper.h>
29 #include <linux/iommu.h>
30 #include <linux/delay.h>
31 #include <linux/amd-iommu.h>
32 #include <linux/notifier.h>
33 #include <linux/export.h>
34 #include <linux/irq.h>
35 #include <linux/msi.h>
36 #include <asm/irq_remapping.h>
37 #include <asm/io_apic.h>
39 #include <asm/hw_irq.h>
40 #include <asm/msidef.h>
41 #include <asm/proto.h>
42 #include <asm/iommu.h>
46 #include "amd_iommu_proto.h"
47 #include "amd_iommu_types.h"
48 #include "irq_remapping.h"
50 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
52 #define LOOP_TIMEOUT 100000
55 * This bitmap is used to advertise the page sizes our hardware support
56 * to the IOMMU core, which will then use this information to split
57 * physically contiguous memory regions it is mapping into page sizes
60 * 512GB Pages are not supported due to a hardware bug
62 #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
64 static DEFINE_RWLOCK(amd_iommu_devtable_lock
);
66 /* A list of preallocated protection domains */
67 static LIST_HEAD(iommu_pd_list
);
68 static DEFINE_SPINLOCK(iommu_pd_list_lock
);
70 /* List of all available dev_data structures */
71 static LIST_HEAD(dev_data_list
);
72 static DEFINE_SPINLOCK(dev_data_list_lock
);
74 LIST_HEAD(ioapic_map
);
78 * Domain for untranslated devices - only allocated
79 * if iommu=pt passed on kernel cmd line.
81 static struct protection_domain
*pt_domain
;
83 static struct iommu_ops amd_iommu_ops
;
85 static ATOMIC_NOTIFIER_HEAD(ppr_notifier
);
86 int amd_iommu_max_glx_val
= -1;
88 static struct dma_map_ops amd_iommu_dma_ops
;
91 * general struct to manage commands send to an IOMMU
97 struct kmem_cache
*amd_iommu_irq_cache
;
99 static void update_domain(struct protection_domain
*domain
);
100 static int __init
alloc_passthrough_domain(void);
102 /****************************************************************************
106 ****************************************************************************/
108 static struct iommu_dev_data
*alloc_dev_data(u16 devid
)
110 struct iommu_dev_data
*dev_data
;
113 dev_data
= kzalloc(sizeof(*dev_data
), GFP_KERNEL
);
117 dev_data
->devid
= devid
;
118 atomic_set(&dev_data
->bind
, 0);
120 spin_lock_irqsave(&dev_data_list_lock
, flags
);
121 list_add_tail(&dev_data
->dev_data_list
, &dev_data_list
);
122 spin_unlock_irqrestore(&dev_data_list_lock
, flags
);
127 static void free_dev_data(struct iommu_dev_data
*dev_data
)
131 spin_lock_irqsave(&dev_data_list_lock
, flags
);
132 list_del(&dev_data
->dev_data_list
);
133 spin_unlock_irqrestore(&dev_data_list_lock
, flags
);
136 iommu_group_put(dev_data
->group
);
141 static struct iommu_dev_data
*search_dev_data(u16 devid
)
143 struct iommu_dev_data
*dev_data
;
146 spin_lock_irqsave(&dev_data_list_lock
, flags
);
147 list_for_each_entry(dev_data
, &dev_data_list
, dev_data_list
) {
148 if (dev_data
->devid
== devid
)
155 spin_unlock_irqrestore(&dev_data_list_lock
, flags
);
160 static struct iommu_dev_data
*find_dev_data(u16 devid
)
162 struct iommu_dev_data
*dev_data
;
164 dev_data
= search_dev_data(devid
);
166 if (dev_data
== NULL
)
167 dev_data
= alloc_dev_data(devid
);
172 static inline u16
get_device_id(struct device
*dev
)
174 struct pci_dev
*pdev
= to_pci_dev(dev
);
176 return PCI_DEVID(pdev
->bus
->number
, pdev
->devfn
);
179 static struct iommu_dev_data
*get_dev_data(struct device
*dev
)
181 return dev
->archdata
.iommu
;
184 static bool pci_iommuv2_capable(struct pci_dev
*pdev
)
186 static const int caps
[] = {
189 PCI_EXT_CAP_ID_PASID
,
193 for (i
= 0; i
< 3; ++i
) {
194 pos
= pci_find_ext_capability(pdev
, caps
[i
]);
202 static bool pdev_pri_erratum(struct pci_dev
*pdev
, u32 erratum
)
204 struct iommu_dev_data
*dev_data
;
206 dev_data
= get_dev_data(&pdev
->dev
);
208 return dev_data
->errata
& (1 << erratum
) ? true : false;
212 * In this function the list of preallocated protection domains is traversed to
213 * find the domain for a specific device
215 static struct dma_ops_domain
*find_protection_domain(u16 devid
)
217 struct dma_ops_domain
*entry
, *ret
= NULL
;
219 u16 alias
= amd_iommu_alias_table
[devid
];
221 if (list_empty(&iommu_pd_list
))
224 spin_lock_irqsave(&iommu_pd_list_lock
, flags
);
226 list_for_each_entry(entry
, &iommu_pd_list
, list
) {
227 if (entry
->target_dev
== devid
||
228 entry
->target_dev
== alias
) {
234 spin_unlock_irqrestore(&iommu_pd_list_lock
, flags
);
240 * This function checks if the driver got a valid device from the caller to
241 * avoid dereferencing invalid pointers.
243 static bool check_device(struct device
*dev
)
247 if (!dev
|| !dev
->dma_mask
)
250 /* No device or no PCI device */
251 if (dev
->bus
!= &pci_bus_type
)
254 devid
= get_device_id(dev
);
256 /* Out of our scope? */
257 if (devid
> amd_iommu_last_bdf
)
260 if (amd_iommu_rlookup_table
[devid
] == NULL
)
266 static void swap_pci_ref(struct pci_dev
**from
, struct pci_dev
*to
)
272 static struct pci_bus
*find_hosted_bus(struct pci_bus
*bus
)
275 if (!pci_is_root_bus(bus
))
278 return ERR_PTR(-ENODEV
);
284 #define REQ_ACS_FLAGS (PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF)
286 static struct pci_dev
*get_isolation_root(struct pci_dev
*pdev
)
288 struct pci_dev
*dma_pdev
= pdev
;
290 /* Account for quirked devices */
291 swap_pci_ref(&dma_pdev
, pci_get_dma_source(dma_pdev
));
294 * If it's a multifunction device that does not support our
295 * required ACS flags, add to the same group as function 0.
297 if (dma_pdev
->multifunction
&&
298 !pci_acs_enabled(dma_pdev
, REQ_ACS_FLAGS
))
299 swap_pci_ref(&dma_pdev
,
300 pci_get_slot(dma_pdev
->bus
,
301 PCI_DEVFN(PCI_SLOT(dma_pdev
->devfn
),
305 * Devices on the root bus go through the iommu. If that's not us,
306 * find the next upstream device and test ACS up to the root bus.
307 * Finding the next device may require skipping virtual buses.
309 while (!pci_is_root_bus(dma_pdev
->bus
)) {
310 struct pci_bus
*bus
= find_hosted_bus(dma_pdev
->bus
);
314 if (pci_acs_path_enabled(bus
->self
, NULL
, REQ_ACS_FLAGS
))
317 swap_pci_ref(&dma_pdev
, pci_dev_get(bus
->self
));
323 static int use_pdev_iommu_group(struct pci_dev
*pdev
, struct device
*dev
)
325 struct iommu_group
*group
= iommu_group_get(&pdev
->dev
);
329 group
= iommu_group_alloc();
331 return PTR_ERR(group
);
333 WARN_ON(&pdev
->dev
!= dev
);
336 ret
= iommu_group_add_device(group
, dev
);
337 iommu_group_put(group
);
341 static int use_dev_data_iommu_group(struct iommu_dev_data
*dev_data
,
344 if (!dev_data
->group
) {
345 struct iommu_group
*group
= iommu_group_alloc();
347 return PTR_ERR(group
);
349 dev_data
->group
= group
;
352 return iommu_group_add_device(dev_data
->group
, dev
);
355 static int init_iommu_group(struct device
*dev
)
357 struct iommu_dev_data
*dev_data
;
358 struct iommu_group
*group
;
359 struct pci_dev
*dma_pdev
;
362 group
= iommu_group_get(dev
);
364 iommu_group_put(group
);
368 dev_data
= find_dev_data(get_device_id(dev
));
372 if (dev_data
->alias_data
) {
376 if (dev_data
->alias_data
->group
)
380 * If the alias device exists, it's effectively just a first
381 * level quirk for finding the DMA source.
383 alias
= amd_iommu_alias_table
[dev_data
->devid
];
384 dma_pdev
= pci_get_bus_and_slot(alias
>> 8, alias
& 0xff);
386 dma_pdev
= get_isolation_root(dma_pdev
);
391 * If the alias is virtual, try to find a parent device
392 * and test whether the IOMMU group is actualy rooted above
393 * the alias. Be careful to also test the parent device if
394 * we think the alias is the root of the group.
396 bus
= pci_find_bus(0, alias
>> 8);
400 bus
= find_hosted_bus(bus
);
401 if (IS_ERR(bus
) || !bus
->self
)
404 dma_pdev
= get_isolation_root(pci_dev_get(bus
->self
));
405 if (dma_pdev
!= bus
->self
|| (dma_pdev
->multifunction
&&
406 !pci_acs_enabled(dma_pdev
, REQ_ACS_FLAGS
)))
409 pci_dev_put(dma_pdev
);
413 dma_pdev
= get_isolation_root(pci_dev_get(to_pci_dev(dev
)));
415 ret
= use_pdev_iommu_group(dma_pdev
, dev
);
416 pci_dev_put(dma_pdev
);
419 return use_dev_data_iommu_group(dev_data
->alias_data
, dev
);
422 static int iommu_init_device(struct device
*dev
)
424 struct pci_dev
*pdev
= to_pci_dev(dev
);
425 struct iommu_dev_data
*dev_data
;
429 if (dev
->archdata
.iommu
)
432 dev_data
= find_dev_data(get_device_id(dev
));
436 alias
= amd_iommu_alias_table
[dev_data
->devid
];
437 if (alias
!= dev_data
->devid
) {
438 struct iommu_dev_data
*alias_data
;
440 alias_data
= find_dev_data(alias
);
441 if (alias_data
== NULL
) {
442 pr_err("AMD-Vi: Warning: Unhandled device %s\n",
444 free_dev_data(dev_data
);
447 dev_data
->alias_data
= alias_data
;
450 ret
= init_iommu_group(dev
);
454 if (pci_iommuv2_capable(pdev
)) {
455 struct amd_iommu
*iommu
;
457 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
458 dev_data
->iommu_v2
= iommu
->is_iommu_v2
;
461 dev
->archdata
.iommu
= dev_data
;
466 static void iommu_ignore_device(struct device
*dev
)
470 devid
= get_device_id(dev
);
471 alias
= amd_iommu_alias_table
[devid
];
473 memset(&amd_iommu_dev_table
[devid
], 0, sizeof(struct dev_table_entry
));
474 memset(&amd_iommu_dev_table
[alias
], 0, sizeof(struct dev_table_entry
));
476 amd_iommu_rlookup_table
[devid
] = NULL
;
477 amd_iommu_rlookup_table
[alias
] = NULL
;
480 static void iommu_uninit_device(struct device
*dev
)
482 iommu_group_remove_device(dev
);
485 * Nothing to do here - we keep dev_data around for unplugged devices
486 * and reuse it when the device is re-plugged - not doing so would
487 * introduce a ton of races.
491 void __init
amd_iommu_uninit_devices(void)
493 struct iommu_dev_data
*dev_data
, *n
;
494 struct pci_dev
*pdev
= NULL
;
496 for_each_pci_dev(pdev
) {
498 if (!check_device(&pdev
->dev
))
501 iommu_uninit_device(&pdev
->dev
);
504 /* Free all of our dev_data structures */
505 list_for_each_entry_safe(dev_data
, n
, &dev_data_list
, dev_data_list
)
506 free_dev_data(dev_data
);
509 int __init
amd_iommu_init_devices(void)
511 struct pci_dev
*pdev
= NULL
;
514 for_each_pci_dev(pdev
) {
516 if (!check_device(&pdev
->dev
))
519 ret
= iommu_init_device(&pdev
->dev
);
520 if (ret
== -ENOTSUPP
)
521 iommu_ignore_device(&pdev
->dev
);
530 amd_iommu_uninit_devices();
534 #ifdef CONFIG_AMD_IOMMU_STATS
537 * Initialization code for statistics collection
540 DECLARE_STATS_COUNTER(compl_wait
);
541 DECLARE_STATS_COUNTER(cnt_map_single
);
542 DECLARE_STATS_COUNTER(cnt_unmap_single
);
543 DECLARE_STATS_COUNTER(cnt_map_sg
);
544 DECLARE_STATS_COUNTER(cnt_unmap_sg
);
545 DECLARE_STATS_COUNTER(cnt_alloc_coherent
);
546 DECLARE_STATS_COUNTER(cnt_free_coherent
);
547 DECLARE_STATS_COUNTER(cross_page
);
548 DECLARE_STATS_COUNTER(domain_flush_single
);
549 DECLARE_STATS_COUNTER(domain_flush_all
);
550 DECLARE_STATS_COUNTER(alloced_io_mem
);
551 DECLARE_STATS_COUNTER(total_map_requests
);
552 DECLARE_STATS_COUNTER(complete_ppr
);
553 DECLARE_STATS_COUNTER(invalidate_iotlb
);
554 DECLARE_STATS_COUNTER(invalidate_iotlb_all
);
555 DECLARE_STATS_COUNTER(pri_requests
);
557 static struct dentry
*stats_dir
;
558 static struct dentry
*de_fflush
;
560 static void amd_iommu_stats_add(struct __iommu_counter
*cnt
)
562 if (stats_dir
== NULL
)
565 cnt
->dent
= debugfs_create_u64(cnt
->name
, 0444, stats_dir
,
569 static void amd_iommu_stats_init(void)
571 stats_dir
= debugfs_create_dir("amd-iommu", NULL
);
572 if (stats_dir
== NULL
)
575 de_fflush
= debugfs_create_bool("fullflush", 0444, stats_dir
,
576 &amd_iommu_unmap_flush
);
578 amd_iommu_stats_add(&compl_wait
);
579 amd_iommu_stats_add(&cnt_map_single
);
580 amd_iommu_stats_add(&cnt_unmap_single
);
581 amd_iommu_stats_add(&cnt_map_sg
);
582 amd_iommu_stats_add(&cnt_unmap_sg
);
583 amd_iommu_stats_add(&cnt_alloc_coherent
);
584 amd_iommu_stats_add(&cnt_free_coherent
);
585 amd_iommu_stats_add(&cross_page
);
586 amd_iommu_stats_add(&domain_flush_single
);
587 amd_iommu_stats_add(&domain_flush_all
);
588 amd_iommu_stats_add(&alloced_io_mem
);
589 amd_iommu_stats_add(&total_map_requests
);
590 amd_iommu_stats_add(&complete_ppr
);
591 amd_iommu_stats_add(&invalidate_iotlb
);
592 amd_iommu_stats_add(&invalidate_iotlb_all
);
593 amd_iommu_stats_add(&pri_requests
);
598 /****************************************************************************
600 * Interrupt handling functions
602 ****************************************************************************/
604 static void dump_dte_entry(u16 devid
)
608 for (i
= 0; i
< 4; ++i
)
609 pr_err("AMD-Vi: DTE[%d]: %016llx\n", i
,
610 amd_iommu_dev_table
[devid
].data
[i
]);
613 static void dump_command(unsigned long phys_addr
)
615 struct iommu_cmd
*cmd
= phys_to_virt(phys_addr
);
618 for (i
= 0; i
< 4; ++i
)
619 pr_err("AMD-Vi: CMD[%d]: %08x\n", i
, cmd
->data
[i
]);
622 static void iommu_print_event(struct amd_iommu
*iommu
, void *__evt
)
624 int type
, devid
, domid
, flags
;
625 volatile u32
*event
= __evt
;
630 type
= (event
[1] >> EVENT_TYPE_SHIFT
) & EVENT_TYPE_MASK
;
631 devid
= (event
[0] >> EVENT_DEVID_SHIFT
) & EVENT_DEVID_MASK
;
632 domid
= (event
[1] >> EVENT_DOMID_SHIFT
) & EVENT_DOMID_MASK
;
633 flags
= (event
[1] >> EVENT_FLAGS_SHIFT
) & EVENT_FLAGS_MASK
;
634 address
= (u64
)(((u64
)event
[3]) << 32) | event
[2];
637 /* Did we hit the erratum? */
638 if (++count
== LOOP_TIMEOUT
) {
639 pr_err("AMD-Vi: No event written to event log\n");
646 printk(KERN_ERR
"AMD-Vi: Event logged [");
649 case EVENT_TYPE_ILL_DEV
:
650 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
651 "address=0x%016llx flags=0x%04x]\n",
652 PCI_BUS_NUM(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
654 dump_dte_entry(devid
);
656 case EVENT_TYPE_IO_FAULT
:
657 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
658 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
659 PCI_BUS_NUM(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
660 domid
, address
, flags
);
662 case EVENT_TYPE_DEV_TAB_ERR
:
663 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
664 "address=0x%016llx flags=0x%04x]\n",
665 PCI_BUS_NUM(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
668 case EVENT_TYPE_PAGE_TAB_ERR
:
669 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
670 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
671 PCI_BUS_NUM(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
672 domid
, address
, flags
);
674 case EVENT_TYPE_ILL_CMD
:
675 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address
);
676 dump_command(address
);
678 case EVENT_TYPE_CMD_HARD_ERR
:
679 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
680 "flags=0x%04x]\n", address
, flags
);
682 case EVENT_TYPE_IOTLB_INV_TO
:
683 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
684 "address=0x%016llx]\n",
685 PCI_BUS_NUM(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
688 case EVENT_TYPE_INV_DEV_REQ
:
689 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
690 "address=0x%016llx flags=0x%04x]\n",
691 PCI_BUS_NUM(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
695 printk(KERN_ERR
"UNKNOWN type=0x%02x]\n", type
);
698 memset(__evt
, 0, 4 * sizeof(u32
));
701 static void iommu_poll_events(struct amd_iommu
*iommu
)
706 spin_lock_irqsave(&iommu
->lock
, flags
);
708 head
= readl(iommu
->mmio_base
+ MMIO_EVT_HEAD_OFFSET
);
709 tail
= readl(iommu
->mmio_base
+ MMIO_EVT_TAIL_OFFSET
);
711 while (head
!= tail
) {
712 iommu_print_event(iommu
, iommu
->evt_buf
+ head
);
713 head
= (head
+ EVENT_ENTRY_SIZE
) % iommu
->evt_buf_size
;
716 writel(head
, iommu
->mmio_base
+ MMIO_EVT_HEAD_OFFSET
);
718 spin_unlock_irqrestore(&iommu
->lock
, flags
);
721 static void iommu_handle_ppr_entry(struct amd_iommu
*iommu
, u64
*raw
)
723 struct amd_iommu_fault fault
;
725 INC_STATS_COUNTER(pri_requests
);
727 if (PPR_REQ_TYPE(raw
[0]) != PPR_REQ_FAULT
) {
728 pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n");
732 fault
.address
= raw
[1];
733 fault
.pasid
= PPR_PASID(raw
[0]);
734 fault
.device_id
= PPR_DEVID(raw
[0]);
735 fault
.tag
= PPR_TAG(raw
[0]);
736 fault
.flags
= PPR_FLAGS(raw
[0]);
738 atomic_notifier_call_chain(&ppr_notifier
, 0, &fault
);
741 static void iommu_poll_ppr_log(struct amd_iommu
*iommu
)
746 if (iommu
->ppr_log
== NULL
)
749 /* enable ppr interrupts again */
750 writel(MMIO_STATUS_PPR_INT_MASK
, iommu
->mmio_base
+ MMIO_STATUS_OFFSET
);
752 spin_lock_irqsave(&iommu
->lock
, flags
);
754 head
= readl(iommu
->mmio_base
+ MMIO_PPR_HEAD_OFFSET
);
755 tail
= readl(iommu
->mmio_base
+ MMIO_PPR_TAIL_OFFSET
);
757 while (head
!= tail
) {
762 raw
= (u64
*)(iommu
->ppr_log
+ head
);
765 * Hardware bug: Interrupt may arrive before the entry is
766 * written to memory. If this happens we need to wait for the
769 for (i
= 0; i
< LOOP_TIMEOUT
; ++i
) {
770 if (PPR_REQ_TYPE(raw
[0]) != 0)
775 /* Avoid memcpy function-call overhead */
780 * To detect the hardware bug we need to clear the entry
783 raw
[0] = raw
[1] = 0UL;
785 /* Update head pointer of hardware ring-buffer */
786 head
= (head
+ PPR_ENTRY_SIZE
) % PPR_LOG_SIZE
;
787 writel(head
, iommu
->mmio_base
+ MMIO_PPR_HEAD_OFFSET
);
790 * Release iommu->lock because ppr-handling might need to
793 spin_unlock_irqrestore(&iommu
->lock
, flags
);
795 /* Handle PPR entry */
796 iommu_handle_ppr_entry(iommu
, entry
);
798 spin_lock_irqsave(&iommu
->lock
, flags
);
800 /* Refresh ring-buffer information */
801 head
= readl(iommu
->mmio_base
+ MMIO_PPR_HEAD_OFFSET
);
802 tail
= readl(iommu
->mmio_base
+ MMIO_PPR_TAIL_OFFSET
);
805 spin_unlock_irqrestore(&iommu
->lock
, flags
);
808 irqreturn_t
amd_iommu_int_thread(int irq
, void *data
)
810 struct amd_iommu
*iommu
;
812 for_each_iommu(iommu
) {
813 iommu_poll_events(iommu
);
814 iommu_poll_ppr_log(iommu
);
820 irqreturn_t
amd_iommu_int_handler(int irq
, void *data
)
822 return IRQ_WAKE_THREAD
;
825 /****************************************************************************
827 * IOMMU command queuing functions
829 ****************************************************************************/
831 static int wait_on_sem(volatile u64
*sem
)
835 while (*sem
== 0 && i
< LOOP_TIMEOUT
) {
840 if (i
== LOOP_TIMEOUT
) {
841 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
848 static void copy_cmd_to_buffer(struct amd_iommu
*iommu
,
849 struct iommu_cmd
*cmd
,
854 target
= iommu
->cmd_buf
+ tail
;
855 tail
= (tail
+ sizeof(*cmd
)) % iommu
->cmd_buf_size
;
857 /* Copy command to buffer */
858 memcpy(target
, cmd
, sizeof(*cmd
));
860 /* Tell the IOMMU about it */
861 writel(tail
, iommu
->mmio_base
+ MMIO_CMD_TAIL_OFFSET
);
864 static void build_completion_wait(struct iommu_cmd
*cmd
, u64 address
)
866 WARN_ON(address
& 0x7ULL
);
868 memset(cmd
, 0, sizeof(*cmd
));
869 cmd
->data
[0] = lower_32_bits(__pa(address
)) | CMD_COMPL_WAIT_STORE_MASK
;
870 cmd
->data
[1] = upper_32_bits(__pa(address
));
872 CMD_SET_TYPE(cmd
, CMD_COMPL_WAIT
);
875 static void build_inv_dte(struct iommu_cmd
*cmd
, u16 devid
)
877 memset(cmd
, 0, sizeof(*cmd
));
878 cmd
->data
[0] = devid
;
879 CMD_SET_TYPE(cmd
, CMD_INV_DEV_ENTRY
);
882 static void build_inv_iommu_pages(struct iommu_cmd
*cmd
, u64 address
,
883 size_t size
, u16 domid
, int pde
)
888 pages
= iommu_num_pages(address
, size
, PAGE_SIZE
);
893 * If we have to flush more than one page, flush all
894 * TLB entries for this domain
896 address
= CMD_INV_IOMMU_ALL_PAGES_ADDRESS
;
900 address
&= PAGE_MASK
;
902 memset(cmd
, 0, sizeof(*cmd
));
903 cmd
->data
[1] |= domid
;
904 cmd
->data
[2] = lower_32_bits(address
);
905 cmd
->data
[3] = upper_32_bits(address
);
906 CMD_SET_TYPE(cmd
, CMD_INV_IOMMU_PAGES
);
907 if (s
) /* size bit - we flush more than one 4kb page */
908 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK
;
909 if (pde
) /* PDE bit - we want to flush everything, not only the PTEs */
910 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK
;
913 static void build_inv_iotlb_pages(struct iommu_cmd
*cmd
, u16 devid
, int qdep
,
914 u64 address
, size_t size
)
919 pages
= iommu_num_pages(address
, size
, PAGE_SIZE
);
924 * If we have to flush more than one page, flush all
925 * TLB entries for this domain
927 address
= CMD_INV_IOMMU_ALL_PAGES_ADDRESS
;
931 address
&= PAGE_MASK
;
933 memset(cmd
, 0, sizeof(*cmd
));
934 cmd
->data
[0] = devid
;
935 cmd
->data
[0] |= (qdep
& 0xff) << 24;
936 cmd
->data
[1] = devid
;
937 cmd
->data
[2] = lower_32_bits(address
);
938 cmd
->data
[3] = upper_32_bits(address
);
939 CMD_SET_TYPE(cmd
, CMD_INV_IOTLB_PAGES
);
941 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK
;
944 static void build_inv_iommu_pasid(struct iommu_cmd
*cmd
, u16 domid
, int pasid
,
945 u64 address
, bool size
)
947 memset(cmd
, 0, sizeof(*cmd
));
949 address
&= ~(0xfffULL
);
951 cmd
->data
[0] = pasid
& PASID_MASK
;
952 cmd
->data
[1] = domid
;
953 cmd
->data
[2] = lower_32_bits(address
);
954 cmd
->data
[3] = upper_32_bits(address
);
955 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK
;
956 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_GN_MASK
;
958 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK
;
959 CMD_SET_TYPE(cmd
, CMD_INV_IOMMU_PAGES
);
962 static void build_inv_iotlb_pasid(struct iommu_cmd
*cmd
, u16 devid
, int pasid
,
963 int qdep
, u64 address
, bool size
)
965 memset(cmd
, 0, sizeof(*cmd
));
967 address
&= ~(0xfffULL
);
969 cmd
->data
[0] = devid
;
970 cmd
->data
[0] |= (pasid
& 0xff) << 16;
971 cmd
->data
[0] |= (qdep
& 0xff) << 24;
972 cmd
->data
[1] = devid
;
973 cmd
->data
[1] |= ((pasid
>> 8) & 0xfff) << 16;
974 cmd
->data
[2] = lower_32_bits(address
);
975 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_GN_MASK
;
976 cmd
->data
[3] = upper_32_bits(address
);
978 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK
;
979 CMD_SET_TYPE(cmd
, CMD_INV_IOTLB_PAGES
);
982 static void build_complete_ppr(struct iommu_cmd
*cmd
, u16 devid
, int pasid
,
983 int status
, int tag
, bool gn
)
985 memset(cmd
, 0, sizeof(*cmd
));
987 cmd
->data
[0] = devid
;
989 cmd
->data
[1] = pasid
& PASID_MASK
;
990 cmd
->data
[2] = CMD_INV_IOMMU_PAGES_GN_MASK
;
992 cmd
->data
[3] = tag
& 0x1ff;
993 cmd
->data
[3] |= (status
& PPR_STATUS_MASK
) << PPR_STATUS_SHIFT
;
995 CMD_SET_TYPE(cmd
, CMD_COMPLETE_PPR
);
998 static void build_inv_all(struct iommu_cmd
*cmd
)
1000 memset(cmd
, 0, sizeof(*cmd
));
1001 CMD_SET_TYPE(cmd
, CMD_INV_ALL
);
1004 static void build_inv_irt(struct iommu_cmd
*cmd
, u16 devid
)
1006 memset(cmd
, 0, sizeof(*cmd
));
1007 cmd
->data
[0] = devid
;
1008 CMD_SET_TYPE(cmd
, CMD_INV_IRT
);
1012 * Writes the command to the IOMMUs command buffer and informs the
1013 * hardware about the new command.
1015 static int iommu_queue_command_sync(struct amd_iommu
*iommu
,
1016 struct iommu_cmd
*cmd
,
1019 u32 left
, tail
, head
, next_tail
;
1020 unsigned long flags
;
1022 WARN_ON(iommu
->cmd_buf_size
& CMD_BUFFER_UNINITIALIZED
);
1025 spin_lock_irqsave(&iommu
->lock
, flags
);
1027 head
= readl(iommu
->mmio_base
+ MMIO_CMD_HEAD_OFFSET
);
1028 tail
= readl(iommu
->mmio_base
+ MMIO_CMD_TAIL_OFFSET
);
1029 next_tail
= (tail
+ sizeof(*cmd
)) % iommu
->cmd_buf_size
;
1030 left
= (head
- next_tail
) % iommu
->cmd_buf_size
;
1033 struct iommu_cmd sync_cmd
;
1034 volatile u64 sem
= 0;
1037 build_completion_wait(&sync_cmd
, (u64
)&sem
);
1038 copy_cmd_to_buffer(iommu
, &sync_cmd
, tail
);
1040 spin_unlock_irqrestore(&iommu
->lock
, flags
);
1042 if ((ret
= wait_on_sem(&sem
)) != 0)
1048 copy_cmd_to_buffer(iommu
, cmd
, tail
);
1050 /* We need to sync now to make sure all commands are processed */
1051 iommu
->need_sync
= sync
;
1053 spin_unlock_irqrestore(&iommu
->lock
, flags
);
1058 static int iommu_queue_command(struct amd_iommu
*iommu
, struct iommu_cmd
*cmd
)
1060 return iommu_queue_command_sync(iommu
, cmd
, true);
1064 * This function queues a completion wait command into the command
1065 * buffer of an IOMMU
1067 static int iommu_completion_wait(struct amd_iommu
*iommu
)
1069 struct iommu_cmd cmd
;
1070 volatile u64 sem
= 0;
1073 if (!iommu
->need_sync
)
1076 build_completion_wait(&cmd
, (u64
)&sem
);
1078 ret
= iommu_queue_command_sync(iommu
, &cmd
, false);
1082 return wait_on_sem(&sem
);
1085 static int iommu_flush_dte(struct amd_iommu
*iommu
, u16 devid
)
1087 struct iommu_cmd cmd
;
1089 build_inv_dte(&cmd
, devid
);
1091 return iommu_queue_command(iommu
, &cmd
);
1094 static void iommu_flush_dte_all(struct amd_iommu
*iommu
)
1098 for (devid
= 0; devid
<= 0xffff; ++devid
)
1099 iommu_flush_dte(iommu
, devid
);
1101 iommu_completion_wait(iommu
);
1105 * This function uses heavy locking and may disable irqs for some time. But
1106 * this is no issue because it is only called during resume.
1108 static void iommu_flush_tlb_all(struct amd_iommu
*iommu
)
1112 for (dom_id
= 0; dom_id
<= 0xffff; ++dom_id
) {
1113 struct iommu_cmd cmd
;
1114 build_inv_iommu_pages(&cmd
, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS
,
1116 iommu_queue_command(iommu
, &cmd
);
1119 iommu_completion_wait(iommu
);
1122 static void iommu_flush_all(struct amd_iommu
*iommu
)
1124 struct iommu_cmd cmd
;
1126 build_inv_all(&cmd
);
1128 iommu_queue_command(iommu
, &cmd
);
1129 iommu_completion_wait(iommu
);
1132 static void iommu_flush_irt(struct amd_iommu
*iommu
, u16 devid
)
1134 struct iommu_cmd cmd
;
1136 build_inv_irt(&cmd
, devid
);
1138 iommu_queue_command(iommu
, &cmd
);
1141 static void iommu_flush_irt_all(struct amd_iommu
*iommu
)
1145 for (devid
= 0; devid
<= MAX_DEV_TABLE_ENTRIES
; devid
++)
1146 iommu_flush_irt(iommu
, devid
);
1148 iommu_completion_wait(iommu
);
1151 void iommu_flush_all_caches(struct amd_iommu
*iommu
)
1153 if (iommu_feature(iommu
, FEATURE_IA
)) {
1154 iommu_flush_all(iommu
);
1156 iommu_flush_dte_all(iommu
);
1157 iommu_flush_irt_all(iommu
);
1158 iommu_flush_tlb_all(iommu
);
1163 * Command send function for flushing on-device TLB
1165 static int device_flush_iotlb(struct iommu_dev_data
*dev_data
,
1166 u64 address
, size_t size
)
1168 struct amd_iommu
*iommu
;
1169 struct iommu_cmd cmd
;
1172 qdep
= dev_data
->ats
.qdep
;
1173 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
1175 build_inv_iotlb_pages(&cmd
, dev_data
->devid
, qdep
, address
, size
);
1177 return iommu_queue_command(iommu
, &cmd
);
1181 * Command send function for invalidating a device table entry
1183 static int device_flush_dte(struct iommu_dev_data
*dev_data
)
1185 struct amd_iommu
*iommu
;
1188 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
1190 ret
= iommu_flush_dte(iommu
, dev_data
->devid
);
1194 if (dev_data
->ats
.enabled
)
1195 ret
= device_flush_iotlb(dev_data
, 0, ~0UL);
1201 * TLB invalidation function which is called from the mapping functions.
1202 * It invalidates a single PTE if the range to flush is within a single
1203 * page. Otherwise it flushes the whole TLB of the IOMMU.
1205 static void __domain_flush_pages(struct protection_domain
*domain
,
1206 u64 address
, size_t size
, int pde
)
1208 struct iommu_dev_data
*dev_data
;
1209 struct iommu_cmd cmd
;
1212 build_inv_iommu_pages(&cmd
, address
, size
, domain
->id
, pde
);
1214 for (i
= 0; i
< amd_iommus_present
; ++i
) {
1215 if (!domain
->dev_iommu
[i
])
1219 * Devices of this domain are behind this IOMMU
1220 * We need a TLB flush
1222 ret
|= iommu_queue_command(amd_iommus
[i
], &cmd
);
1225 list_for_each_entry(dev_data
, &domain
->dev_list
, list
) {
1227 if (!dev_data
->ats
.enabled
)
1230 ret
|= device_flush_iotlb(dev_data
, address
, size
);
1236 static void domain_flush_pages(struct protection_domain
*domain
,
1237 u64 address
, size_t size
)
1239 __domain_flush_pages(domain
, address
, size
, 0);
1242 /* Flush the whole IO/TLB for a given protection domain */
1243 static void domain_flush_tlb(struct protection_domain
*domain
)
1245 __domain_flush_pages(domain
, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS
, 0);
1248 /* Flush the whole IO/TLB for a given protection domain - including PDE */
1249 static void domain_flush_tlb_pde(struct protection_domain
*domain
)
1251 __domain_flush_pages(domain
, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS
, 1);
1254 static void domain_flush_complete(struct protection_domain
*domain
)
1258 for (i
= 0; i
< amd_iommus_present
; ++i
) {
1259 if (!domain
->dev_iommu
[i
])
1263 * Devices of this domain are behind this IOMMU
1264 * We need to wait for completion of all commands.
1266 iommu_completion_wait(amd_iommus
[i
]);
1272 * This function flushes the DTEs for all devices in domain
1274 static void domain_flush_devices(struct protection_domain
*domain
)
1276 struct iommu_dev_data
*dev_data
;
1278 list_for_each_entry(dev_data
, &domain
->dev_list
, list
)
1279 device_flush_dte(dev_data
);
1282 /****************************************************************************
1284 * The functions below are used the create the page table mappings for
1285 * unity mapped regions.
1287 ****************************************************************************/
1290 * This function is used to add another level to an IO page table. Adding
1291 * another level increases the size of the address space by 9 bits to a size up
1294 static bool increase_address_space(struct protection_domain
*domain
,
1299 if (domain
->mode
== PAGE_MODE_6_LEVEL
)
1300 /* address space already 64 bit large */
1303 pte
= (void *)get_zeroed_page(gfp
);
1307 *pte
= PM_LEVEL_PDE(domain
->mode
,
1308 virt_to_phys(domain
->pt_root
));
1309 domain
->pt_root
= pte
;
1311 domain
->updated
= true;
1316 static u64
*alloc_pte(struct protection_domain
*domain
,
1317 unsigned long address
,
1318 unsigned long page_size
,
1325 BUG_ON(!is_power_of_2(page_size
));
1327 while (address
> PM_LEVEL_SIZE(domain
->mode
))
1328 increase_address_space(domain
, gfp
);
1330 level
= domain
->mode
- 1;
1331 pte
= &domain
->pt_root
[PM_LEVEL_INDEX(level
, address
)];
1332 address
= PAGE_SIZE_ALIGN(address
, page_size
);
1333 end_lvl
= PAGE_SIZE_LEVEL(page_size
);
1335 while (level
> end_lvl
) {
1336 if (!IOMMU_PTE_PRESENT(*pte
)) {
1337 page
= (u64
*)get_zeroed_page(gfp
);
1340 *pte
= PM_LEVEL_PDE(level
, virt_to_phys(page
));
1343 /* No level skipping support yet */
1344 if (PM_PTE_LEVEL(*pte
) != level
)
1349 pte
= IOMMU_PTE_PAGE(*pte
);
1351 if (pte_page
&& level
== end_lvl
)
1354 pte
= &pte
[PM_LEVEL_INDEX(level
, address
)];
1361 * This function checks if there is a PTE for a given dma address. If
1362 * there is one, it returns the pointer to it.
1364 static u64
*fetch_pte(struct protection_domain
*domain
, unsigned long address
)
1369 if (address
> PM_LEVEL_SIZE(domain
->mode
))
1372 level
= domain
->mode
- 1;
1373 pte
= &domain
->pt_root
[PM_LEVEL_INDEX(level
, address
)];
1378 if (!IOMMU_PTE_PRESENT(*pte
))
1382 if (PM_PTE_LEVEL(*pte
) == 0x07) {
1383 unsigned long pte_mask
, __pte
;
1386 * If we have a series of large PTEs, make
1387 * sure to return a pointer to the first one.
1389 pte_mask
= PTE_PAGE_SIZE(*pte
);
1390 pte_mask
= ~((PAGE_SIZE_PTE_COUNT(pte_mask
) << 3) - 1);
1391 __pte
= ((unsigned long)pte
) & pte_mask
;
1393 return (u64
*)__pte
;
1396 /* No level skipping support yet */
1397 if (PM_PTE_LEVEL(*pte
) != level
)
1402 /* Walk to the next level */
1403 pte
= IOMMU_PTE_PAGE(*pte
);
1404 pte
= &pte
[PM_LEVEL_INDEX(level
, address
)];
1411 * Generic mapping functions. It maps a physical address into a DMA
1412 * address space. It allocates the page table pages if necessary.
1413 * In the future it can be extended to a generic mapping function
1414 * supporting all features of AMD IOMMU page tables like level skipping
1415 * and full 64 bit address spaces.
1417 static int iommu_map_page(struct protection_domain
*dom
,
1418 unsigned long bus_addr
,
1419 unsigned long phys_addr
,
1421 unsigned long page_size
)
1426 if (!(prot
& IOMMU_PROT_MASK
))
1429 bus_addr
= PAGE_ALIGN(bus_addr
);
1430 phys_addr
= PAGE_ALIGN(phys_addr
);
1431 count
= PAGE_SIZE_PTE_COUNT(page_size
);
1432 pte
= alloc_pte(dom
, bus_addr
, page_size
, NULL
, GFP_KERNEL
);
1434 for (i
= 0; i
< count
; ++i
)
1435 if (IOMMU_PTE_PRESENT(pte
[i
]))
1438 if (page_size
> PAGE_SIZE
) {
1439 __pte
= PAGE_SIZE_PTE(phys_addr
, page_size
);
1440 __pte
|= PM_LEVEL_ENC(7) | IOMMU_PTE_P
| IOMMU_PTE_FC
;
1442 __pte
= phys_addr
| IOMMU_PTE_P
| IOMMU_PTE_FC
;
1444 if (prot
& IOMMU_PROT_IR
)
1445 __pte
|= IOMMU_PTE_IR
;
1446 if (prot
& IOMMU_PROT_IW
)
1447 __pte
|= IOMMU_PTE_IW
;
1449 for (i
= 0; i
< count
; ++i
)
1457 static unsigned long iommu_unmap_page(struct protection_domain
*dom
,
1458 unsigned long bus_addr
,
1459 unsigned long page_size
)
1461 unsigned long long unmap_size
, unmapped
;
1464 BUG_ON(!is_power_of_2(page_size
));
1468 while (unmapped
< page_size
) {
1470 pte
= fetch_pte(dom
, bus_addr
);
1474 * No PTE for this address
1475 * move forward in 4kb steps
1477 unmap_size
= PAGE_SIZE
;
1478 } else if (PM_PTE_LEVEL(*pte
) == 0) {
1479 /* 4kb PTE found for this address */
1480 unmap_size
= PAGE_SIZE
;
1485 /* Large PTE found which maps this address */
1486 unmap_size
= PTE_PAGE_SIZE(*pte
);
1487 count
= PAGE_SIZE_PTE_COUNT(unmap_size
);
1488 for (i
= 0; i
< count
; i
++)
1492 bus_addr
= (bus_addr
& ~(unmap_size
- 1)) + unmap_size
;
1493 unmapped
+= unmap_size
;
1496 BUG_ON(!is_power_of_2(unmapped
));
1502 * This function checks if a specific unity mapping entry is needed for
1503 * this specific IOMMU.
1505 static int iommu_for_unity_map(struct amd_iommu
*iommu
,
1506 struct unity_map_entry
*entry
)
1510 for (i
= entry
->devid_start
; i
<= entry
->devid_end
; ++i
) {
1511 bdf
= amd_iommu_alias_table
[i
];
1512 if (amd_iommu_rlookup_table
[bdf
] == iommu
)
1520 * This function actually applies the mapping to the page table of the
1523 static int dma_ops_unity_map(struct dma_ops_domain
*dma_dom
,
1524 struct unity_map_entry
*e
)
1529 for (addr
= e
->address_start
; addr
< e
->address_end
;
1530 addr
+= PAGE_SIZE
) {
1531 ret
= iommu_map_page(&dma_dom
->domain
, addr
, addr
, e
->prot
,
1536 * if unity mapping is in aperture range mark the page
1537 * as allocated in the aperture
1539 if (addr
< dma_dom
->aperture_size
)
1540 __set_bit(addr
>> PAGE_SHIFT
,
1541 dma_dom
->aperture
[0]->bitmap
);
1548 * Init the unity mappings for a specific IOMMU in the system
1550 * Basically iterates over all unity mapping entries and applies them to
1551 * the default domain DMA of that IOMMU if necessary.
1553 static int iommu_init_unity_mappings(struct amd_iommu
*iommu
)
1555 struct unity_map_entry
*entry
;
1558 list_for_each_entry(entry
, &amd_iommu_unity_map
, list
) {
1559 if (!iommu_for_unity_map(iommu
, entry
))
1561 ret
= dma_ops_unity_map(iommu
->default_dom
, entry
);
1570 * Inits the unity mappings required for a specific device
1572 static int init_unity_mappings_for_device(struct dma_ops_domain
*dma_dom
,
1575 struct unity_map_entry
*e
;
1578 list_for_each_entry(e
, &amd_iommu_unity_map
, list
) {
1579 if (!(devid
>= e
->devid_start
&& devid
<= e
->devid_end
))
1581 ret
= dma_ops_unity_map(dma_dom
, e
);
1589 /****************************************************************************
1591 * The next functions belong to the address allocator for the dma_ops
1592 * interface functions. They work like the allocators in the other IOMMU
1593 * drivers. Its basically a bitmap which marks the allocated pages in
1594 * the aperture. Maybe it could be enhanced in the future to a more
1595 * efficient allocator.
1597 ****************************************************************************/
1600 * The address allocator core functions.
1602 * called with domain->lock held
1606 * Used to reserve address ranges in the aperture (e.g. for exclusion
1609 static void dma_ops_reserve_addresses(struct dma_ops_domain
*dom
,
1610 unsigned long start_page
,
1613 unsigned int i
, last_page
= dom
->aperture_size
>> PAGE_SHIFT
;
1615 if (start_page
+ pages
> last_page
)
1616 pages
= last_page
- start_page
;
1618 for (i
= start_page
; i
< start_page
+ pages
; ++i
) {
1619 int index
= i
/ APERTURE_RANGE_PAGES
;
1620 int page
= i
% APERTURE_RANGE_PAGES
;
1621 __set_bit(page
, dom
->aperture
[index
]->bitmap
);
1626 * This function is used to add a new aperture range to an existing
1627 * aperture in case of dma_ops domain allocation or address allocation
1630 static int alloc_new_range(struct dma_ops_domain
*dma_dom
,
1631 bool populate
, gfp_t gfp
)
1633 int index
= dma_dom
->aperture_size
>> APERTURE_RANGE_SHIFT
;
1634 struct amd_iommu
*iommu
;
1635 unsigned long i
, old_size
;
1637 #ifdef CONFIG_IOMMU_STRESS
1641 if (index
>= APERTURE_MAX_RANGES
)
1644 dma_dom
->aperture
[index
] = kzalloc(sizeof(struct aperture_range
), gfp
);
1645 if (!dma_dom
->aperture
[index
])
1648 dma_dom
->aperture
[index
]->bitmap
= (void *)get_zeroed_page(gfp
);
1649 if (!dma_dom
->aperture
[index
]->bitmap
)
1652 dma_dom
->aperture
[index
]->offset
= dma_dom
->aperture_size
;
1655 unsigned long address
= dma_dom
->aperture_size
;
1656 int i
, num_ptes
= APERTURE_RANGE_PAGES
/ 512;
1657 u64
*pte
, *pte_page
;
1659 for (i
= 0; i
< num_ptes
; ++i
) {
1660 pte
= alloc_pte(&dma_dom
->domain
, address
, PAGE_SIZE
,
1665 dma_dom
->aperture
[index
]->pte_pages
[i
] = pte_page
;
1667 address
+= APERTURE_RANGE_SIZE
/ 64;
1671 old_size
= dma_dom
->aperture_size
;
1672 dma_dom
->aperture_size
+= APERTURE_RANGE_SIZE
;
1674 /* Reserve address range used for MSI messages */
1675 if (old_size
< MSI_ADDR_BASE_LO
&&
1676 dma_dom
->aperture_size
> MSI_ADDR_BASE_LO
) {
1677 unsigned long spage
;
1680 pages
= iommu_num_pages(MSI_ADDR_BASE_LO
, 0x10000, PAGE_SIZE
);
1681 spage
= MSI_ADDR_BASE_LO
>> PAGE_SHIFT
;
1683 dma_ops_reserve_addresses(dma_dom
, spage
, pages
);
1686 /* Initialize the exclusion range if necessary */
1687 for_each_iommu(iommu
) {
1688 if (iommu
->exclusion_start
&&
1689 iommu
->exclusion_start
>= dma_dom
->aperture
[index
]->offset
1690 && iommu
->exclusion_start
< dma_dom
->aperture_size
) {
1691 unsigned long startpage
;
1692 int pages
= iommu_num_pages(iommu
->exclusion_start
,
1693 iommu
->exclusion_length
,
1695 startpage
= iommu
->exclusion_start
>> PAGE_SHIFT
;
1696 dma_ops_reserve_addresses(dma_dom
, startpage
, pages
);
1701 * Check for areas already mapped as present in the new aperture
1702 * range and mark those pages as reserved in the allocator. Such
1703 * mappings may already exist as a result of requested unity
1704 * mappings for devices.
1706 for (i
= dma_dom
->aperture
[index
]->offset
;
1707 i
< dma_dom
->aperture_size
;
1709 u64
*pte
= fetch_pte(&dma_dom
->domain
, i
);
1710 if (!pte
|| !IOMMU_PTE_PRESENT(*pte
))
1713 dma_ops_reserve_addresses(dma_dom
, i
>> PAGE_SHIFT
, 1);
1716 update_domain(&dma_dom
->domain
);
1721 update_domain(&dma_dom
->domain
);
1723 free_page((unsigned long)dma_dom
->aperture
[index
]->bitmap
);
1725 kfree(dma_dom
->aperture
[index
]);
1726 dma_dom
->aperture
[index
] = NULL
;
1731 static unsigned long dma_ops_area_alloc(struct device
*dev
,
1732 struct dma_ops_domain
*dom
,
1734 unsigned long align_mask
,
1736 unsigned long start
)
1738 unsigned long next_bit
= dom
->next_address
% APERTURE_RANGE_SIZE
;
1739 int max_index
= dom
->aperture_size
>> APERTURE_RANGE_SHIFT
;
1740 int i
= start
>> APERTURE_RANGE_SHIFT
;
1741 unsigned long boundary_size
;
1742 unsigned long address
= -1;
1743 unsigned long limit
;
1745 next_bit
>>= PAGE_SHIFT
;
1747 boundary_size
= ALIGN(dma_get_seg_boundary(dev
) + 1,
1748 PAGE_SIZE
) >> PAGE_SHIFT
;
1750 for (;i
< max_index
; ++i
) {
1751 unsigned long offset
= dom
->aperture
[i
]->offset
>> PAGE_SHIFT
;
1753 if (dom
->aperture
[i
]->offset
>= dma_mask
)
1756 limit
= iommu_device_max_index(APERTURE_RANGE_PAGES
, offset
,
1757 dma_mask
>> PAGE_SHIFT
);
1759 address
= iommu_area_alloc(dom
->aperture
[i
]->bitmap
,
1760 limit
, next_bit
, pages
, 0,
1761 boundary_size
, align_mask
);
1762 if (address
!= -1) {
1763 address
= dom
->aperture
[i
]->offset
+
1764 (address
<< PAGE_SHIFT
);
1765 dom
->next_address
= address
+ (pages
<< PAGE_SHIFT
);
1775 static unsigned long dma_ops_alloc_addresses(struct device
*dev
,
1776 struct dma_ops_domain
*dom
,
1778 unsigned long align_mask
,
1781 unsigned long address
;
1783 #ifdef CONFIG_IOMMU_STRESS
1784 dom
->next_address
= 0;
1785 dom
->need_flush
= true;
1788 address
= dma_ops_area_alloc(dev
, dom
, pages
, align_mask
,
1789 dma_mask
, dom
->next_address
);
1791 if (address
== -1) {
1792 dom
->next_address
= 0;
1793 address
= dma_ops_area_alloc(dev
, dom
, pages
, align_mask
,
1795 dom
->need_flush
= true;
1798 if (unlikely(address
== -1))
1799 address
= DMA_ERROR_CODE
;
1801 WARN_ON((address
+ (PAGE_SIZE
*pages
)) > dom
->aperture_size
);
1807 * The address free function.
1809 * called with domain->lock held
1811 static void dma_ops_free_addresses(struct dma_ops_domain
*dom
,
1812 unsigned long address
,
1815 unsigned i
= address
>> APERTURE_RANGE_SHIFT
;
1816 struct aperture_range
*range
= dom
->aperture
[i
];
1818 BUG_ON(i
>= APERTURE_MAX_RANGES
|| range
== NULL
);
1820 #ifdef CONFIG_IOMMU_STRESS
1825 if (address
>= dom
->next_address
)
1826 dom
->need_flush
= true;
1828 address
= (address
% APERTURE_RANGE_SIZE
) >> PAGE_SHIFT
;
1830 bitmap_clear(range
->bitmap
, address
, pages
);
1834 /****************************************************************************
1836 * The next functions belong to the domain allocation. A domain is
1837 * allocated for every IOMMU as the default domain. If device isolation
1838 * is enabled, every device get its own domain. The most important thing
1839 * about domains is the page table mapping the DMA address space they
1842 ****************************************************************************/
1845 * This function adds a protection domain to the global protection domain list
1847 static void add_domain_to_list(struct protection_domain
*domain
)
1849 unsigned long flags
;
1851 spin_lock_irqsave(&amd_iommu_pd_lock
, flags
);
1852 list_add(&domain
->list
, &amd_iommu_pd_list
);
1853 spin_unlock_irqrestore(&amd_iommu_pd_lock
, flags
);
1857 * This function removes a protection domain to the global
1858 * protection domain list
1860 static void del_domain_from_list(struct protection_domain
*domain
)
1862 unsigned long flags
;
1864 spin_lock_irqsave(&amd_iommu_pd_lock
, flags
);
1865 list_del(&domain
->list
);
1866 spin_unlock_irqrestore(&amd_iommu_pd_lock
, flags
);
1869 static u16
domain_id_alloc(void)
1871 unsigned long flags
;
1874 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
1875 id
= find_first_zero_bit(amd_iommu_pd_alloc_bitmap
, MAX_DOMAIN_ID
);
1877 if (id
> 0 && id
< MAX_DOMAIN_ID
)
1878 __set_bit(id
, amd_iommu_pd_alloc_bitmap
);
1881 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
1886 static void domain_id_free(int id
)
1888 unsigned long flags
;
1890 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
1891 if (id
> 0 && id
< MAX_DOMAIN_ID
)
1892 __clear_bit(id
, amd_iommu_pd_alloc_bitmap
);
1893 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
1896 static void free_pagetable(struct protection_domain
*domain
)
1901 p1
= domain
->pt_root
;
1906 for (i
= 0; i
< 512; ++i
) {
1907 if (!IOMMU_PTE_PRESENT(p1
[i
]))
1910 p2
= IOMMU_PTE_PAGE(p1
[i
]);
1911 for (j
= 0; j
< 512; ++j
) {
1912 if (!IOMMU_PTE_PRESENT(p2
[j
]))
1914 p3
= IOMMU_PTE_PAGE(p2
[j
]);
1915 free_page((unsigned long)p3
);
1918 free_page((unsigned long)p2
);
1921 free_page((unsigned long)p1
);
1923 domain
->pt_root
= NULL
;
1926 static void free_gcr3_tbl_level1(u64
*tbl
)
1931 for (i
= 0; i
< 512; ++i
) {
1932 if (!(tbl
[i
] & GCR3_VALID
))
1935 ptr
= __va(tbl
[i
] & PAGE_MASK
);
1937 free_page((unsigned long)ptr
);
1941 static void free_gcr3_tbl_level2(u64
*tbl
)
1946 for (i
= 0; i
< 512; ++i
) {
1947 if (!(tbl
[i
] & GCR3_VALID
))
1950 ptr
= __va(tbl
[i
] & PAGE_MASK
);
1952 free_gcr3_tbl_level1(ptr
);
1956 static void free_gcr3_table(struct protection_domain
*domain
)
1958 if (domain
->glx
== 2)
1959 free_gcr3_tbl_level2(domain
->gcr3_tbl
);
1960 else if (domain
->glx
== 1)
1961 free_gcr3_tbl_level1(domain
->gcr3_tbl
);
1962 else if (domain
->glx
!= 0)
1965 free_page((unsigned long)domain
->gcr3_tbl
);
1969 * Free a domain, only used if something went wrong in the
1970 * allocation path and we need to free an already allocated page table
1972 static void dma_ops_domain_free(struct dma_ops_domain
*dom
)
1979 del_domain_from_list(&dom
->domain
);
1981 free_pagetable(&dom
->domain
);
1983 for (i
= 0; i
< APERTURE_MAX_RANGES
; ++i
) {
1984 if (!dom
->aperture
[i
])
1986 free_page((unsigned long)dom
->aperture
[i
]->bitmap
);
1987 kfree(dom
->aperture
[i
]);
1994 * Allocates a new protection domain usable for the dma_ops functions.
1995 * It also initializes the page table and the address allocator data
1996 * structures required for the dma_ops interface
1998 static struct dma_ops_domain
*dma_ops_domain_alloc(void)
2000 struct dma_ops_domain
*dma_dom
;
2002 dma_dom
= kzalloc(sizeof(struct dma_ops_domain
), GFP_KERNEL
);
2006 spin_lock_init(&dma_dom
->domain
.lock
);
2008 dma_dom
->domain
.id
= domain_id_alloc();
2009 if (dma_dom
->domain
.id
== 0)
2011 INIT_LIST_HEAD(&dma_dom
->domain
.dev_list
);
2012 dma_dom
->domain
.mode
= PAGE_MODE_2_LEVEL
;
2013 dma_dom
->domain
.pt_root
= (void *)get_zeroed_page(GFP_KERNEL
);
2014 dma_dom
->domain
.flags
= PD_DMA_OPS_MASK
;
2015 dma_dom
->domain
.priv
= dma_dom
;
2016 if (!dma_dom
->domain
.pt_root
)
2019 dma_dom
->need_flush
= false;
2020 dma_dom
->target_dev
= 0xffff;
2022 add_domain_to_list(&dma_dom
->domain
);
2024 if (alloc_new_range(dma_dom
, true, GFP_KERNEL
))
2028 * mark the first page as allocated so we never return 0 as
2029 * a valid dma-address. So we can use 0 as error value
2031 dma_dom
->aperture
[0]->bitmap
[0] = 1;
2032 dma_dom
->next_address
= 0;
2038 dma_ops_domain_free(dma_dom
);
2044 * little helper function to check whether a given protection domain is a
2047 static bool dma_ops_domain(struct protection_domain
*domain
)
2049 return domain
->flags
& PD_DMA_OPS_MASK
;
2052 static void set_dte_entry(u16 devid
, struct protection_domain
*domain
, bool ats
)
2057 if (domain
->mode
!= PAGE_MODE_NONE
)
2058 pte_root
= virt_to_phys(domain
->pt_root
);
2060 pte_root
|= (domain
->mode
& DEV_ENTRY_MODE_MASK
)
2061 << DEV_ENTRY_MODE_SHIFT
;
2062 pte_root
|= IOMMU_PTE_IR
| IOMMU_PTE_IW
| IOMMU_PTE_P
| IOMMU_PTE_TV
;
2064 flags
= amd_iommu_dev_table
[devid
].data
[1];
2067 flags
|= DTE_FLAG_IOTLB
;
2069 if (domain
->flags
& PD_IOMMUV2_MASK
) {
2070 u64 gcr3
= __pa(domain
->gcr3_tbl
);
2071 u64 glx
= domain
->glx
;
2074 pte_root
|= DTE_FLAG_GV
;
2075 pte_root
|= (glx
& DTE_GLX_MASK
) << DTE_GLX_SHIFT
;
2077 /* First mask out possible old values for GCR3 table */
2078 tmp
= DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B
;
2081 tmp
= DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C
;
2084 /* Encode GCR3 table into DTE */
2085 tmp
= DTE_GCR3_VAL_A(gcr3
) << DTE_GCR3_SHIFT_A
;
2088 tmp
= DTE_GCR3_VAL_B(gcr3
) << DTE_GCR3_SHIFT_B
;
2091 tmp
= DTE_GCR3_VAL_C(gcr3
) << DTE_GCR3_SHIFT_C
;
2095 flags
&= ~(0xffffUL
);
2096 flags
|= domain
->id
;
2098 amd_iommu_dev_table
[devid
].data
[1] = flags
;
2099 amd_iommu_dev_table
[devid
].data
[0] = pte_root
;
2102 static void clear_dte_entry(u16 devid
)
2104 /* remove entry from the device table seen by the hardware */
2105 amd_iommu_dev_table
[devid
].data
[0] = IOMMU_PTE_P
| IOMMU_PTE_TV
;
2106 amd_iommu_dev_table
[devid
].data
[1] = 0;
2108 amd_iommu_apply_erratum_63(devid
);
2111 static void do_attach(struct iommu_dev_data
*dev_data
,
2112 struct protection_domain
*domain
)
2114 struct amd_iommu
*iommu
;
2117 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
2118 ats
= dev_data
->ats
.enabled
;
2120 /* Update data structures */
2121 dev_data
->domain
= domain
;
2122 list_add(&dev_data
->list
, &domain
->dev_list
);
2123 set_dte_entry(dev_data
->devid
, domain
, ats
);
2125 /* Do reference counting */
2126 domain
->dev_iommu
[iommu
->index
] += 1;
2127 domain
->dev_cnt
+= 1;
2129 /* Flush the DTE entry */
2130 device_flush_dte(dev_data
);
2133 static void do_detach(struct iommu_dev_data
*dev_data
)
2135 struct amd_iommu
*iommu
;
2137 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
2139 /* decrease reference counters */
2140 dev_data
->domain
->dev_iommu
[iommu
->index
] -= 1;
2141 dev_data
->domain
->dev_cnt
-= 1;
2143 /* Update data structures */
2144 dev_data
->domain
= NULL
;
2145 list_del(&dev_data
->list
);
2146 clear_dte_entry(dev_data
->devid
);
2148 /* Flush the DTE entry */
2149 device_flush_dte(dev_data
);
2153 * If a device is not yet associated with a domain, this function does
2154 * assigns it visible for the hardware
2156 static int __attach_device(struct iommu_dev_data
*dev_data
,
2157 struct protection_domain
*domain
)
2162 spin_lock(&domain
->lock
);
2164 if (dev_data
->alias_data
!= NULL
) {
2165 struct iommu_dev_data
*alias_data
= dev_data
->alias_data
;
2167 /* Some sanity checks */
2169 if (alias_data
->domain
!= NULL
&&
2170 alias_data
->domain
!= domain
)
2173 if (dev_data
->domain
!= NULL
&&
2174 dev_data
->domain
!= domain
)
2177 /* Do real assignment */
2178 if (alias_data
->domain
== NULL
)
2179 do_attach(alias_data
, domain
);
2181 atomic_inc(&alias_data
->bind
);
2184 if (dev_data
->domain
== NULL
)
2185 do_attach(dev_data
, domain
);
2187 atomic_inc(&dev_data
->bind
);
2194 spin_unlock(&domain
->lock
);
2200 static void pdev_iommuv2_disable(struct pci_dev
*pdev
)
2202 pci_disable_ats(pdev
);
2203 pci_disable_pri(pdev
);
2204 pci_disable_pasid(pdev
);
2207 /* FIXME: Change generic reset-function to do the same */
2208 static int pri_reset_while_enabled(struct pci_dev
*pdev
)
2213 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_PRI
);
2217 pci_read_config_word(pdev
, pos
+ PCI_PRI_CTRL
, &control
);
2218 control
|= PCI_PRI_CTRL_RESET
;
2219 pci_write_config_word(pdev
, pos
+ PCI_PRI_CTRL
, control
);
2224 static int pdev_iommuv2_enable(struct pci_dev
*pdev
)
2229 /* FIXME: Hardcode number of outstanding requests for now */
2231 if (pdev_pri_erratum(pdev
, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE
))
2233 reset_enable
= pdev_pri_erratum(pdev
, AMD_PRI_DEV_ERRATUM_ENABLE_RESET
);
2235 /* Only allow access to user-accessible pages */
2236 ret
= pci_enable_pasid(pdev
, 0);
2240 /* First reset the PRI state of the device */
2241 ret
= pci_reset_pri(pdev
);
2246 ret
= pci_enable_pri(pdev
, reqs
);
2251 ret
= pri_reset_while_enabled(pdev
);
2256 ret
= pci_enable_ats(pdev
, PAGE_SHIFT
);
2263 pci_disable_pri(pdev
);
2264 pci_disable_pasid(pdev
);
2269 /* FIXME: Move this to PCI code */
2270 #define PCI_PRI_TLP_OFF (1 << 15)
2272 static bool pci_pri_tlp_required(struct pci_dev
*pdev
)
2277 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_PRI
);
2281 pci_read_config_word(pdev
, pos
+ PCI_PRI_STATUS
, &status
);
2283 return (status
& PCI_PRI_TLP_OFF
) ? true : false;
2287 * If a device is not yet associated with a domain, this function
2288 * assigns it visible for the hardware
2290 static int attach_device(struct device
*dev
,
2291 struct protection_domain
*domain
)
2293 struct pci_dev
*pdev
= to_pci_dev(dev
);
2294 struct iommu_dev_data
*dev_data
;
2295 unsigned long flags
;
2298 dev_data
= get_dev_data(dev
);
2300 if (domain
->flags
& PD_IOMMUV2_MASK
) {
2301 if (!dev_data
->iommu_v2
|| !dev_data
->passthrough
)
2304 if (pdev_iommuv2_enable(pdev
) != 0)
2307 dev_data
->ats
.enabled
= true;
2308 dev_data
->ats
.qdep
= pci_ats_queue_depth(pdev
);
2309 dev_data
->pri_tlp
= pci_pri_tlp_required(pdev
);
2310 } else if (amd_iommu_iotlb_sup
&&
2311 pci_enable_ats(pdev
, PAGE_SHIFT
) == 0) {
2312 dev_data
->ats
.enabled
= true;
2313 dev_data
->ats
.qdep
= pci_ats_queue_depth(pdev
);
2316 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
2317 ret
= __attach_device(dev_data
, domain
);
2318 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
2321 * We might boot into a crash-kernel here. The crashed kernel
2322 * left the caches in the IOMMU dirty. So we have to flush
2323 * here to evict all dirty stuff.
2325 domain_flush_tlb_pde(domain
);
2331 * Removes a device from a protection domain (unlocked)
2333 static void __detach_device(struct iommu_dev_data
*dev_data
)
2335 struct protection_domain
*domain
;
2336 unsigned long flags
;
2338 BUG_ON(!dev_data
->domain
);
2340 domain
= dev_data
->domain
;
2342 spin_lock_irqsave(&domain
->lock
, flags
);
2344 if (dev_data
->alias_data
!= NULL
) {
2345 struct iommu_dev_data
*alias_data
= dev_data
->alias_data
;
2347 if (atomic_dec_and_test(&alias_data
->bind
))
2348 do_detach(alias_data
);
2351 if (atomic_dec_and_test(&dev_data
->bind
))
2352 do_detach(dev_data
);
2354 spin_unlock_irqrestore(&domain
->lock
, flags
);
2357 * If we run in passthrough mode the device must be assigned to the
2358 * passthrough domain if it is detached from any other domain.
2359 * Make sure we can deassign from the pt_domain itself.
2361 if (dev_data
->passthrough
&&
2362 (dev_data
->domain
== NULL
&& domain
!= pt_domain
))
2363 __attach_device(dev_data
, pt_domain
);
2367 * Removes a device from a protection domain (with devtable_lock held)
2369 static void detach_device(struct device
*dev
)
2371 struct protection_domain
*domain
;
2372 struct iommu_dev_data
*dev_data
;
2373 unsigned long flags
;
2375 dev_data
= get_dev_data(dev
);
2376 domain
= dev_data
->domain
;
2378 /* lock device table */
2379 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
2380 __detach_device(dev_data
);
2381 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
2383 if (domain
->flags
& PD_IOMMUV2_MASK
)
2384 pdev_iommuv2_disable(to_pci_dev(dev
));
2385 else if (dev_data
->ats
.enabled
)
2386 pci_disable_ats(to_pci_dev(dev
));
2388 dev_data
->ats
.enabled
= false;
2392 * Find out the protection domain structure for a given PCI device. This
2393 * will give us the pointer to the page table root for example.
2395 static struct protection_domain
*domain_for_device(struct device
*dev
)
2397 struct iommu_dev_data
*dev_data
;
2398 struct protection_domain
*dom
= NULL
;
2399 unsigned long flags
;
2401 dev_data
= get_dev_data(dev
);
2403 if (dev_data
->domain
)
2404 return dev_data
->domain
;
2406 if (dev_data
->alias_data
!= NULL
) {
2407 struct iommu_dev_data
*alias_data
= dev_data
->alias_data
;
2409 read_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
2410 if (alias_data
->domain
!= NULL
) {
2411 __attach_device(dev_data
, alias_data
->domain
);
2412 dom
= alias_data
->domain
;
2414 read_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
2420 static int device_change_notifier(struct notifier_block
*nb
,
2421 unsigned long action
, void *data
)
2423 struct dma_ops_domain
*dma_domain
;
2424 struct protection_domain
*domain
;
2425 struct iommu_dev_data
*dev_data
;
2426 struct device
*dev
= data
;
2427 struct amd_iommu
*iommu
;
2428 unsigned long flags
;
2431 if (!check_device(dev
))
2434 devid
= get_device_id(dev
);
2435 iommu
= amd_iommu_rlookup_table
[devid
];
2436 dev_data
= get_dev_data(dev
);
2439 case BUS_NOTIFY_UNBOUND_DRIVER
:
2441 domain
= domain_for_device(dev
);
2445 if (dev_data
->passthrough
)
2449 case BUS_NOTIFY_ADD_DEVICE
:
2451 iommu_init_device(dev
);
2454 * dev_data is still NULL and
2455 * got initialized in iommu_init_device
2457 dev_data
= get_dev_data(dev
);
2459 if (iommu_pass_through
|| dev_data
->iommu_v2
) {
2460 dev_data
->passthrough
= true;
2461 attach_device(dev
, pt_domain
);
2465 domain
= domain_for_device(dev
);
2467 /* allocate a protection domain if a device is added */
2468 dma_domain
= find_protection_domain(devid
);
2471 dma_domain
= dma_ops_domain_alloc();
2474 dma_domain
->target_dev
= devid
;
2476 spin_lock_irqsave(&iommu_pd_list_lock
, flags
);
2477 list_add_tail(&dma_domain
->list
, &iommu_pd_list
);
2478 spin_unlock_irqrestore(&iommu_pd_list_lock
, flags
);
2480 dev_data
= get_dev_data(dev
);
2482 dev
->archdata
.dma_ops
= &amd_iommu_dma_ops
;
2485 case BUS_NOTIFY_DEL_DEVICE
:
2487 iommu_uninit_device(dev
);
2493 iommu_completion_wait(iommu
);
2499 static struct notifier_block device_nb
= {
2500 .notifier_call
= device_change_notifier
,
2503 void amd_iommu_init_notifier(void)
2505 bus_register_notifier(&pci_bus_type
, &device_nb
);
2508 /*****************************************************************************
2510 * The next functions belong to the dma_ops mapping/unmapping code.
2512 *****************************************************************************/
2515 * In the dma_ops path we only have the struct device. This function
2516 * finds the corresponding IOMMU, the protection domain and the
2517 * requestor id for a given device.
2518 * If the device is not yet associated with a domain this is also done
2521 static struct protection_domain
*get_domain(struct device
*dev
)
2523 struct protection_domain
*domain
;
2524 struct dma_ops_domain
*dma_dom
;
2525 u16 devid
= get_device_id(dev
);
2527 if (!check_device(dev
))
2528 return ERR_PTR(-EINVAL
);
2530 domain
= domain_for_device(dev
);
2531 if (domain
!= NULL
&& !dma_ops_domain(domain
))
2532 return ERR_PTR(-EBUSY
);
2537 /* Device not bound yet - bind it */
2538 dma_dom
= find_protection_domain(devid
);
2540 dma_dom
= amd_iommu_rlookup_table
[devid
]->default_dom
;
2541 attach_device(dev
, &dma_dom
->domain
);
2542 DUMP_printk("Using protection domain %d for device %s\n",
2543 dma_dom
->domain
.id
, dev_name(dev
));
2545 return &dma_dom
->domain
;
2548 static void update_device_table(struct protection_domain
*domain
)
2550 struct iommu_dev_data
*dev_data
;
2552 list_for_each_entry(dev_data
, &domain
->dev_list
, list
)
2553 set_dte_entry(dev_data
->devid
, domain
, dev_data
->ats
.enabled
);
2556 static void update_domain(struct protection_domain
*domain
)
2558 if (!domain
->updated
)
2561 update_device_table(domain
);
2563 domain_flush_devices(domain
);
2564 domain_flush_tlb_pde(domain
);
2566 domain
->updated
= false;
2570 * This function fetches the PTE for a given address in the aperture
2572 static u64
* dma_ops_get_pte(struct dma_ops_domain
*dom
,
2573 unsigned long address
)
2575 struct aperture_range
*aperture
;
2576 u64
*pte
, *pte_page
;
2578 aperture
= dom
->aperture
[APERTURE_RANGE_INDEX(address
)];
2582 pte
= aperture
->pte_pages
[APERTURE_PAGE_INDEX(address
)];
2584 pte
= alloc_pte(&dom
->domain
, address
, PAGE_SIZE
, &pte_page
,
2586 aperture
->pte_pages
[APERTURE_PAGE_INDEX(address
)] = pte_page
;
2588 pte
+= PM_LEVEL_INDEX(0, address
);
2590 update_domain(&dom
->domain
);
2596 * This is the generic map function. It maps one 4kb page at paddr to
2597 * the given address in the DMA address space for the domain.
2599 static dma_addr_t
dma_ops_domain_map(struct dma_ops_domain
*dom
,
2600 unsigned long address
,
2606 WARN_ON(address
> dom
->aperture_size
);
2610 pte
= dma_ops_get_pte(dom
, address
);
2612 return DMA_ERROR_CODE
;
2614 __pte
= paddr
| IOMMU_PTE_P
| IOMMU_PTE_FC
;
2616 if (direction
== DMA_TO_DEVICE
)
2617 __pte
|= IOMMU_PTE_IR
;
2618 else if (direction
== DMA_FROM_DEVICE
)
2619 __pte
|= IOMMU_PTE_IW
;
2620 else if (direction
== DMA_BIDIRECTIONAL
)
2621 __pte
|= IOMMU_PTE_IR
| IOMMU_PTE_IW
;
2627 return (dma_addr_t
)address
;
2631 * The generic unmapping function for on page in the DMA address space.
2633 static void dma_ops_domain_unmap(struct dma_ops_domain
*dom
,
2634 unsigned long address
)
2636 struct aperture_range
*aperture
;
2639 if (address
>= dom
->aperture_size
)
2642 aperture
= dom
->aperture
[APERTURE_RANGE_INDEX(address
)];
2646 pte
= aperture
->pte_pages
[APERTURE_PAGE_INDEX(address
)];
2650 pte
+= PM_LEVEL_INDEX(0, address
);
2658 * This function contains common code for mapping of a physically
2659 * contiguous memory region into DMA address space. It is used by all
2660 * mapping functions provided with this IOMMU driver.
2661 * Must be called with the domain lock held.
2663 static dma_addr_t
__map_single(struct device
*dev
,
2664 struct dma_ops_domain
*dma_dom
,
2671 dma_addr_t offset
= paddr
& ~PAGE_MASK
;
2672 dma_addr_t address
, start
, ret
;
2674 unsigned long align_mask
= 0;
2677 pages
= iommu_num_pages(paddr
, size
, PAGE_SIZE
);
2680 INC_STATS_COUNTER(total_map_requests
);
2683 INC_STATS_COUNTER(cross_page
);
2686 align_mask
= (1UL << get_order(size
)) - 1;
2689 address
= dma_ops_alloc_addresses(dev
, dma_dom
, pages
, align_mask
,
2691 if (unlikely(address
== DMA_ERROR_CODE
)) {
2693 * setting next_address here will let the address
2694 * allocator only scan the new allocated range in the
2695 * first run. This is a small optimization.
2697 dma_dom
->next_address
= dma_dom
->aperture_size
;
2699 if (alloc_new_range(dma_dom
, false, GFP_ATOMIC
))
2703 * aperture was successfully enlarged by 128 MB, try
2710 for (i
= 0; i
< pages
; ++i
) {
2711 ret
= dma_ops_domain_map(dma_dom
, start
, paddr
, dir
);
2712 if (ret
== DMA_ERROR_CODE
)
2720 ADD_STATS_COUNTER(alloced_io_mem
, size
);
2722 if (unlikely(dma_dom
->need_flush
&& !amd_iommu_unmap_flush
)) {
2723 domain_flush_tlb(&dma_dom
->domain
);
2724 dma_dom
->need_flush
= false;
2725 } else if (unlikely(amd_iommu_np_cache
))
2726 domain_flush_pages(&dma_dom
->domain
, address
, size
);
2733 for (--i
; i
>= 0; --i
) {
2735 dma_ops_domain_unmap(dma_dom
, start
);
2738 dma_ops_free_addresses(dma_dom
, address
, pages
);
2740 return DMA_ERROR_CODE
;
2744 * Does the reverse of the __map_single function. Must be called with
2745 * the domain lock held too
2747 static void __unmap_single(struct dma_ops_domain
*dma_dom
,
2748 dma_addr_t dma_addr
,
2752 dma_addr_t flush_addr
;
2753 dma_addr_t i
, start
;
2756 if ((dma_addr
== DMA_ERROR_CODE
) ||
2757 (dma_addr
+ size
> dma_dom
->aperture_size
))
2760 flush_addr
= dma_addr
;
2761 pages
= iommu_num_pages(dma_addr
, size
, PAGE_SIZE
);
2762 dma_addr
&= PAGE_MASK
;
2765 for (i
= 0; i
< pages
; ++i
) {
2766 dma_ops_domain_unmap(dma_dom
, start
);
2770 SUB_STATS_COUNTER(alloced_io_mem
, size
);
2772 dma_ops_free_addresses(dma_dom
, dma_addr
, pages
);
2774 if (amd_iommu_unmap_flush
|| dma_dom
->need_flush
) {
2775 domain_flush_pages(&dma_dom
->domain
, flush_addr
, size
);
2776 dma_dom
->need_flush
= false;
2781 * The exported map_single function for dma_ops.
2783 static dma_addr_t
map_page(struct device
*dev
, struct page
*page
,
2784 unsigned long offset
, size_t size
,
2785 enum dma_data_direction dir
,
2786 struct dma_attrs
*attrs
)
2788 unsigned long flags
;
2789 struct protection_domain
*domain
;
2792 phys_addr_t paddr
= page_to_phys(page
) + offset
;
2794 INC_STATS_COUNTER(cnt_map_single
);
2796 domain
= get_domain(dev
);
2797 if (PTR_ERR(domain
) == -EINVAL
)
2798 return (dma_addr_t
)paddr
;
2799 else if (IS_ERR(domain
))
2800 return DMA_ERROR_CODE
;
2802 dma_mask
= *dev
->dma_mask
;
2804 spin_lock_irqsave(&domain
->lock
, flags
);
2806 addr
= __map_single(dev
, domain
->priv
, paddr
, size
, dir
, false,
2808 if (addr
== DMA_ERROR_CODE
)
2811 domain_flush_complete(domain
);
2814 spin_unlock_irqrestore(&domain
->lock
, flags
);
2820 * The exported unmap_single function for dma_ops.
2822 static void unmap_page(struct device
*dev
, dma_addr_t dma_addr
, size_t size
,
2823 enum dma_data_direction dir
, struct dma_attrs
*attrs
)
2825 unsigned long flags
;
2826 struct protection_domain
*domain
;
2828 INC_STATS_COUNTER(cnt_unmap_single
);
2830 domain
= get_domain(dev
);
2834 spin_lock_irqsave(&domain
->lock
, flags
);
2836 __unmap_single(domain
->priv
, dma_addr
, size
, dir
);
2838 domain_flush_complete(domain
);
2840 spin_unlock_irqrestore(&domain
->lock
, flags
);
2844 * This is a special map_sg function which is used if we should map a
2845 * device which is not handled by an AMD IOMMU in the system.
2847 static int map_sg_no_iommu(struct device
*dev
, struct scatterlist
*sglist
,
2848 int nelems
, int dir
)
2850 struct scatterlist
*s
;
2853 for_each_sg(sglist
, s
, nelems
, i
) {
2854 s
->dma_address
= (dma_addr_t
)sg_phys(s
);
2855 s
->dma_length
= s
->length
;
2862 * The exported map_sg function for dma_ops (handles scatter-gather
2865 static int map_sg(struct device
*dev
, struct scatterlist
*sglist
,
2866 int nelems
, enum dma_data_direction dir
,
2867 struct dma_attrs
*attrs
)
2869 unsigned long flags
;
2870 struct protection_domain
*domain
;
2872 struct scatterlist
*s
;
2874 int mapped_elems
= 0;
2877 INC_STATS_COUNTER(cnt_map_sg
);
2879 domain
= get_domain(dev
);
2880 if (PTR_ERR(domain
) == -EINVAL
)
2881 return map_sg_no_iommu(dev
, sglist
, nelems
, dir
);
2882 else if (IS_ERR(domain
))
2885 dma_mask
= *dev
->dma_mask
;
2887 spin_lock_irqsave(&domain
->lock
, flags
);
2889 for_each_sg(sglist
, s
, nelems
, i
) {
2892 s
->dma_address
= __map_single(dev
, domain
->priv
,
2893 paddr
, s
->length
, dir
, false,
2896 if (s
->dma_address
) {
2897 s
->dma_length
= s
->length
;
2903 domain_flush_complete(domain
);
2906 spin_unlock_irqrestore(&domain
->lock
, flags
);
2908 return mapped_elems
;
2910 for_each_sg(sglist
, s
, mapped_elems
, i
) {
2912 __unmap_single(domain
->priv
, s
->dma_address
,
2913 s
->dma_length
, dir
);
2914 s
->dma_address
= s
->dma_length
= 0;
2923 * The exported map_sg function for dma_ops (handles scatter-gather
2926 static void unmap_sg(struct device
*dev
, struct scatterlist
*sglist
,
2927 int nelems
, enum dma_data_direction dir
,
2928 struct dma_attrs
*attrs
)
2930 unsigned long flags
;
2931 struct protection_domain
*domain
;
2932 struct scatterlist
*s
;
2935 INC_STATS_COUNTER(cnt_unmap_sg
);
2937 domain
= get_domain(dev
);
2941 spin_lock_irqsave(&domain
->lock
, flags
);
2943 for_each_sg(sglist
, s
, nelems
, i
) {
2944 __unmap_single(domain
->priv
, s
->dma_address
,
2945 s
->dma_length
, dir
);
2946 s
->dma_address
= s
->dma_length
= 0;
2949 domain_flush_complete(domain
);
2951 spin_unlock_irqrestore(&domain
->lock
, flags
);
2955 * The exported alloc_coherent function for dma_ops.
2957 static void *alloc_coherent(struct device
*dev
, size_t size
,
2958 dma_addr_t
*dma_addr
, gfp_t flag
,
2959 struct dma_attrs
*attrs
)
2961 unsigned long flags
;
2963 struct protection_domain
*domain
;
2965 u64 dma_mask
= dev
->coherent_dma_mask
;
2967 INC_STATS_COUNTER(cnt_alloc_coherent
);
2969 domain
= get_domain(dev
);
2970 if (PTR_ERR(domain
) == -EINVAL
) {
2971 virt_addr
= (void *)__get_free_pages(flag
, get_order(size
));
2972 *dma_addr
= __pa(virt_addr
);
2974 } else if (IS_ERR(domain
))
2977 dma_mask
= dev
->coherent_dma_mask
;
2978 flag
&= ~(__GFP_DMA
| __GFP_HIGHMEM
| __GFP_DMA32
);
2981 virt_addr
= (void *)__get_free_pages(flag
, get_order(size
));
2985 paddr
= virt_to_phys(virt_addr
);
2988 dma_mask
= *dev
->dma_mask
;
2990 spin_lock_irqsave(&domain
->lock
, flags
);
2992 *dma_addr
= __map_single(dev
, domain
->priv
, paddr
,
2993 size
, DMA_BIDIRECTIONAL
, true, dma_mask
);
2995 if (*dma_addr
== DMA_ERROR_CODE
) {
2996 spin_unlock_irqrestore(&domain
->lock
, flags
);
3000 domain_flush_complete(domain
);
3002 spin_unlock_irqrestore(&domain
->lock
, flags
);
3008 free_pages((unsigned long)virt_addr
, get_order(size
));
3014 * The exported free_coherent function for dma_ops.
3016 static void free_coherent(struct device
*dev
, size_t size
,
3017 void *virt_addr
, dma_addr_t dma_addr
,
3018 struct dma_attrs
*attrs
)
3020 unsigned long flags
;
3021 struct protection_domain
*domain
;
3023 INC_STATS_COUNTER(cnt_free_coherent
);
3025 domain
= get_domain(dev
);
3029 spin_lock_irqsave(&domain
->lock
, flags
);
3031 __unmap_single(domain
->priv
, dma_addr
, size
, DMA_BIDIRECTIONAL
);
3033 domain_flush_complete(domain
);
3035 spin_unlock_irqrestore(&domain
->lock
, flags
);
3038 free_pages((unsigned long)virt_addr
, get_order(size
));
3042 * This function is called by the DMA layer to find out if we can handle a
3043 * particular device. It is part of the dma_ops.
3045 static int amd_iommu_dma_supported(struct device
*dev
, u64 mask
)
3047 return check_device(dev
);
3051 * The function for pre-allocating protection domains.
3053 * If the driver core informs the DMA layer if a driver grabs a device
3054 * we don't need to preallocate the protection domains anymore.
3055 * For now we have to.
3057 static void __init
prealloc_protection_domains(void)
3059 struct iommu_dev_data
*dev_data
;
3060 struct dma_ops_domain
*dma_dom
;
3061 struct pci_dev
*dev
= NULL
;
3064 for_each_pci_dev(dev
) {
3066 /* Do we handle this device? */
3067 if (!check_device(&dev
->dev
))
3070 dev_data
= get_dev_data(&dev
->dev
);
3071 if (!amd_iommu_force_isolation
&& dev_data
->iommu_v2
) {
3072 /* Make sure passthrough domain is allocated */
3073 alloc_passthrough_domain();
3074 dev_data
->passthrough
= true;
3075 attach_device(&dev
->dev
, pt_domain
);
3076 pr_info("AMD-Vi: Using passthrough domain for device %s\n",
3077 dev_name(&dev
->dev
));
3080 /* Is there already any domain for it? */
3081 if (domain_for_device(&dev
->dev
))
3084 devid
= get_device_id(&dev
->dev
);
3086 dma_dom
= dma_ops_domain_alloc();
3089 init_unity_mappings_for_device(dma_dom
, devid
);
3090 dma_dom
->target_dev
= devid
;
3092 attach_device(&dev
->dev
, &dma_dom
->domain
);
3094 list_add_tail(&dma_dom
->list
, &iommu_pd_list
);
3098 static struct dma_map_ops amd_iommu_dma_ops
= {
3099 .alloc
= alloc_coherent
,
3100 .free
= free_coherent
,
3101 .map_page
= map_page
,
3102 .unmap_page
= unmap_page
,
3104 .unmap_sg
= unmap_sg
,
3105 .dma_supported
= amd_iommu_dma_supported
,
3108 static unsigned device_dma_ops_init(void)
3110 struct iommu_dev_data
*dev_data
;
3111 struct pci_dev
*pdev
= NULL
;
3112 unsigned unhandled
= 0;
3114 for_each_pci_dev(pdev
) {
3115 if (!check_device(&pdev
->dev
)) {
3117 iommu_ignore_device(&pdev
->dev
);
3123 dev_data
= get_dev_data(&pdev
->dev
);
3125 if (!dev_data
->passthrough
)
3126 pdev
->dev
.archdata
.dma_ops
= &amd_iommu_dma_ops
;
3128 pdev
->dev
.archdata
.dma_ops
= &nommu_dma_ops
;
3135 * The function which clues the AMD IOMMU driver into dma_ops.
3138 void __init
amd_iommu_init_api(void)
3140 bus_set_iommu(&pci_bus_type
, &amd_iommu_ops
);
3143 int __init
amd_iommu_init_dma_ops(void)
3145 struct amd_iommu
*iommu
;
3149 * first allocate a default protection domain for every IOMMU we
3150 * found in the system. Devices not assigned to any other
3151 * protection domain will be assigned to the default one.
3153 for_each_iommu(iommu
) {
3154 iommu
->default_dom
= dma_ops_domain_alloc();
3155 if (iommu
->default_dom
== NULL
)
3157 iommu
->default_dom
->domain
.flags
|= PD_DEFAULT_MASK
;
3158 ret
= iommu_init_unity_mappings(iommu
);
3164 * Pre-allocate the protection domains for each device.
3166 prealloc_protection_domains();
3171 /* Make the driver finally visible to the drivers */
3172 unhandled
= device_dma_ops_init();
3173 if (unhandled
&& max_pfn
> MAX_DMA32_PFN
) {
3174 /* There are unhandled devices - initialize swiotlb for them */
3178 amd_iommu_stats_init();
3180 if (amd_iommu_unmap_flush
)
3181 pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n");
3183 pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n");
3189 for_each_iommu(iommu
) {
3190 dma_ops_domain_free(iommu
->default_dom
);
3196 /*****************************************************************************
3198 * The following functions belong to the exported interface of AMD IOMMU
3200 * This interface allows access to lower level functions of the IOMMU
3201 * like protection domain handling and assignement of devices to domains
3202 * which is not possible with the dma_ops interface.
3204 *****************************************************************************/
3206 static void cleanup_domain(struct protection_domain
*domain
)
3208 struct iommu_dev_data
*dev_data
, *next
;
3209 unsigned long flags
;
3211 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
3213 list_for_each_entry_safe(dev_data
, next
, &domain
->dev_list
, list
) {
3214 __detach_device(dev_data
);
3215 atomic_set(&dev_data
->bind
, 0);
3218 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
3221 static void protection_domain_free(struct protection_domain
*domain
)
3226 del_domain_from_list(domain
);
3229 domain_id_free(domain
->id
);
3234 static struct protection_domain
*protection_domain_alloc(void)
3236 struct protection_domain
*domain
;
3238 domain
= kzalloc(sizeof(*domain
), GFP_KERNEL
);
3242 spin_lock_init(&domain
->lock
);
3243 mutex_init(&domain
->api_lock
);
3244 domain
->id
= domain_id_alloc();
3247 INIT_LIST_HEAD(&domain
->dev_list
);
3249 add_domain_to_list(domain
);
3259 static int __init
alloc_passthrough_domain(void)
3261 if (pt_domain
!= NULL
)
3264 /* allocate passthrough domain */
3265 pt_domain
= protection_domain_alloc();
3269 pt_domain
->mode
= PAGE_MODE_NONE
;
3273 static int amd_iommu_domain_init(struct iommu_domain
*dom
)
3275 struct protection_domain
*domain
;
3277 domain
= protection_domain_alloc();
3281 domain
->mode
= PAGE_MODE_3_LEVEL
;
3282 domain
->pt_root
= (void *)get_zeroed_page(GFP_KERNEL
);
3283 if (!domain
->pt_root
)
3286 domain
->iommu_domain
= dom
;
3290 dom
->geometry
.aperture_start
= 0;
3291 dom
->geometry
.aperture_end
= ~0ULL;
3292 dom
->geometry
.force_aperture
= true;
3297 protection_domain_free(domain
);
3302 static void amd_iommu_domain_destroy(struct iommu_domain
*dom
)
3304 struct protection_domain
*domain
= dom
->priv
;
3309 if (domain
->dev_cnt
> 0)
3310 cleanup_domain(domain
);
3312 BUG_ON(domain
->dev_cnt
!= 0);
3314 if (domain
->mode
!= PAGE_MODE_NONE
)
3315 free_pagetable(domain
);
3317 if (domain
->flags
& PD_IOMMUV2_MASK
)
3318 free_gcr3_table(domain
);
3320 protection_domain_free(domain
);
3325 static void amd_iommu_detach_device(struct iommu_domain
*dom
,
3328 struct iommu_dev_data
*dev_data
= dev
->archdata
.iommu
;
3329 struct amd_iommu
*iommu
;
3332 if (!check_device(dev
))
3335 devid
= get_device_id(dev
);
3337 if (dev_data
->domain
!= NULL
)
3340 iommu
= amd_iommu_rlookup_table
[devid
];
3344 iommu_completion_wait(iommu
);
3347 static int amd_iommu_attach_device(struct iommu_domain
*dom
,
3350 struct protection_domain
*domain
= dom
->priv
;
3351 struct iommu_dev_data
*dev_data
;
3352 struct amd_iommu
*iommu
;
3355 if (!check_device(dev
))
3358 dev_data
= dev
->archdata
.iommu
;
3360 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
3364 if (dev_data
->domain
)
3367 ret
= attach_device(dev
, domain
);
3369 iommu_completion_wait(iommu
);
3374 static int amd_iommu_map(struct iommu_domain
*dom
, unsigned long iova
,
3375 phys_addr_t paddr
, size_t page_size
, int iommu_prot
)
3377 struct protection_domain
*domain
= dom
->priv
;
3381 if (domain
->mode
== PAGE_MODE_NONE
)
3384 if (iommu_prot
& IOMMU_READ
)
3385 prot
|= IOMMU_PROT_IR
;
3386 if (iommu_prot
& IOMMU_WRITE
)
3387 prot
|= IOMMU_PROT_IW
;
3389 mutex_lock(&domain
->api_lock
);
3390 ret
= iommu_map_page(domain
, iova
, paddr
, prot
, page_size
);
3391 mutex_unlock(&domain
->api_lock
);
3396 static size_t amd_iommu_unmap(struct iommu_domain
*dom
, unsigned long iova
,
3399 struct protection_domain
*domain
= dom
->priv
;
3402 if (domain
->mode
== PAGE_MODE_NONE
)
3405 mutex_lock(&domain
->api_lock
);
3406 unmap_size
= iommu_unmap_page(domain
, iova
, page_size
);
3407 mutex_unlock(&domain
->api_lock
);
3409 domain_flush_tlb_pde(domain
);
3414 static phys_addr_t
amd_iommu_iova_to_phys(struct iommu_domain
*dom
,
3417 struct protection_domain
*domain
= dom
->priv
;
3418 unsigned long offset_mask
;
3422 if (domain
->mode
== PAGE_MODE_NONE
)
3425 pte
= fetch_pte(domain
, iova
);
3427 if (!pte
|| !IOMMU_PTE_PRESENT(*pte
))
3430 if (PM_PTE_LEVEL(*pte
) == 0)
3431 offset_mask
= PAGE_SIZE
- 1;
3433 offset_mask
= PTE_PAGE_SIZE(*pte
) - 1;
3435 __pte
= *pte
& PM_ADDR_MASK
;
3436 paddr
= (__pte
& ~offset_mask
) | (iova
& offset_mask
);
3441 static int amd_iommu_domain_has_cap(struct iommu_domain
*domain
,
3445 case IOMMU_CAP_CACHE_COHERENCY
:
3447 case IOMMU_CAP_INTR_REMAP
:
3448 return irq_remapping_enabled
;
3454 static struct iommu_ops amd_iommu_ops
= {
3455 .domain_init
= amd_iommu_domain_init
,
3456 .domain_destroy
= amd_iommu_domain_destroy
,
3457 .attach_dev
= amd_iommu_attach_device
,
3458 .detach_dev
= amd_iommu_detach_device
,
3459 .map
= amd_iommu_map
,
3460 .unmap
= amd_iommu_unmap
,
3461 .iova_to_phys
= amd_iommu_iova_to_phys
,
3462 .domain_has_cap
= amd_iommu_domain_has_cap
,
3463 .pgsize_bitmap
= AMD_IOMMU_PGSIZES
,
3466 /*****************************************************************************
3468 * The next functions do a basic initialization of IOMMU for pass through
3471 * In passthrough mode the IOMMU is initialized and enabled but not used for
3472 * DMA-API translation.
3474 *****************************************************************************/
3476 int __init
amd_iommu_init_passthrough(void)
3478 struct iommu_dev_data
*dev_data
;
3479 struct pci_dev
*dev
= NULL
;
3480 struct amd_iommu
*iommu
;
3484 ret
= alloc_passthrough_domain();
3488 for_each_pci_dev(dev
) {
3489 if (!check_device(&dev
->dev
))
3492 dev_data
= get_dev_data(&dev
->dev
);
3493 dev_data
->passthrough
= true;
3495 devid
= get_device_id(&dev
->dev
);
3497 iommu
= amd_iommu_rlookup_table
[devid
];
3501 attach_device(&dev
->dev
, pt_domain
);
3504 amd_iommu_stats_init();
3506 pr_info("AMD-Vi: Initialized for Passthrough Mode\n");
3511 /* IOMMUv2 specific functions */
3512 int amd_iommu_register_ppr_notifier(struct notifier_block
*nb
)
3514 return atomic_notifier_chain_register(&ppr_notifier
, nb
);
3516 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier
);
3518 int amd_iommu_unregister_ppr_notifier(struct notifier_block
*nb
)
3520 return atomic_notifier_chain_unregister(&ppr_notifier
, nb
);
3522 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier
);
3524 void amd_iommu_domain_direct_map(struct iommu_domain
*dom
)
3526 struct protection_domain
*domain
= dom
->priv
;
3527 unsigned long flags
;
3529 spin_lock_irqsave(&domain
->lock
, flags
);
3531 /* Update data structure */
3532 domain
->mode
= PAGE_MODE_NONE
;
3533 domain
->updated
= true;
3535 /* Make changes visible to IOMMUs */
3536 update_domain(domain
);
3538 /* Page-table is not visible to IOMMU anymore, so free it */
3539 free_pagetable(domain
);
3541 spin_unlock_irqrestore(&domain
->lock
, flags
);
3543 EXPORT_SYMBOL(amd_iommu_domain_direct_map
);
3545 int amd_iommu_domain_enable_v2(struct iommu_domain
*dom
, int pasids
)
3547 struct protection_domain
*domain
= dom
->priv
;
3548 unsigned long flags
;
3551 if (pasids
<= 0 || pasids
> (PASID_MASK
+ 1))
3554 /* Number of GCR3 table levels required */
3555 for (levels
= 0; (pasids
- 1) & ~0x1ff; pasids
>>= 9)
3558 if (levels
> amd_iommu_max_glx_val
)
3561 spin_lock_irqsave(&domain
->lock
, flags
);
3564 * Save us all sanity checks whether devices already in the
3565 * domain support IOMMUv2. Just force that the domain has no
3566 * devices attached when it is switched into IOMMUv2 mode.
3569 if (domain
->dev_cnt
> 0 || domain
->flags
& PD_IOMMUV2_MASK
)
3573 domain
->gcr3_tbl
= (void *)get_zeroed_page(GFP_ATOMIC
);
3574 if (domain
->gcr3_tbl
== NULL
)
3577 domain
->glx
= levels
;
3578 domain
->flags
|= PD_IOMMUV2_MASK
;
3579 domain
->updated
= true;
3581 update_domain(domain
);
3586 spin_unlock_irqrestore(&domain
->lock
, flags
);
3590 EXPORT_SYMBOL(amd_iommu_domain_enable_v2
);
3592 static int __flush_pasid(struct protection_domain
*domain
, int pasid
,
3593 u64 address
, bool size
)
3595 struct iommu_dev_data
*dev_data
;
3596 struct iommu_cmd cmd
;
3599 if (!(domain
->flags
& PD_IOMMUV2_MASK
))
3602 build_inv_iommu_pasid(&cmd
, domain
->id
, pasid
, address
, size
);
3605 * IOMMU TLB needs to be flushed before Device TLB to
3606 * prevent device TLB refill from IOMMU TLB
3608 for (i
= 0; i
< amd_iommus_present
; ++i
) {
3609 if (domain
->dev_iommu
[i
] == 0)
3612 ret
= iommu_queue_command(amd_iommus
[i
], &cmd
);
3617 /* Wait until IOMMU TLB flushes are complete */
3618 domain_flush_complete(domain
);
3620 /* Now flush device TLBs */
3621 list_for_each_entry(dev_data
, &domain
->dev_list
, list
) {
3622 struct amd_iommu
*iommu
;
3625 BUG_ON(!dev_data
->ats
.enabled
);
3627 qdep
= dev_data
->ats
.qdep
;
3628 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
3630 build_inv_iotlb_pasid(&cmd
, dev_data
->devid
, pasid
,
3631 qdep
, address
, size
);
3633 ret
= iommu_queue_command(iommu
, &cmd
);
3638 /* Wait until all device TLBs are flushed */
3639 domain_flush_complete(domain
);
3648 static int __amd_iommu_flush_page(struct protection_domain
*domain
, int pasid
,
3651 INC_STATS_COUNTER(invalidate_iotlb
);
3653 return __flush_pasid(domain
, pasid
, address
, false);
3656 int amd_iommu_flush_page(struct iommu_domain
*dom
, int pasid
,
3659 struct protection_domain
*domain
= dom
->priv
;
3660 unsigned long flags
;
3663 spin_lock_irqsave(&domain
->lock
, flags
);
3664 ret
= __amd_iommu_flush_page(domain
, pasid
, address
);
3665 spin_unlock_irqrestore(&domain
->lock
, flags
);
3669 EXPORT_SYMBOL(amd_iommu_flush_page
);
3671 static int __amd_iommu_flush_tlb(struct protection_domain
*domain
, int pasid
)
3673 INC_STATS_COUNTER(invalidate_iotlb_all
);
3675 return __flush_pasid(domain
, pasid
, CMD_INV_IOMMU_ALL_PAGES_ADDRESS
,
3679 int amd_iommu_flush_tlb(struct iommu_domain
*dom
, int pasid
)
3681 struct protection_domain
*domain
= dom
->priv
;
3682 unsigned long flags
;
3685 spin_lock_irqsave(&domain
->lock
, flags
);
3686 ret
= __amd_iommu_flush_tlb(domain
, pasid
);
3687 spin_unlock_irqrestore(&domain
->lock
, flags
);
3691 EXPORT_SYMBOL(amd_iommu_flush_tlb
);
3693 static u64
*__get_gcr3_pte(u64
*root
, int level
, int pasid
, bool alloc
)
3700 index
= (pasid
>> (9 * level
)) & 0x1ff;
3706 if (!(*pte
& GCR3_VALID
)) {
3710 root
= (void *)get_zeroed_page(GFP_ATOMIC
);
3714 *pte
= __pa(root
) | GCR3_VALID
;
3717 root
= __va(*pte
& PAGE_MASK
);
3725 static int __set_gcr3(struct protection_domain
*domain
, int pasid
,
3730 if (domain
->mode
!= PAGE_MODE_NONE
)
3733 pte
= __get_gcr3_pte(domain
->gcr3_tbl
, domain
->glx
, pasid
, true);
3737 *pte
= (cr3
& PAGE_MASK
) | GCR3_VALID
;
3739 return __amd_iommu_flush_tlb(domain
, pasid
);
3742 static int __clear_gcr3(struct protection_domain
*domain
, int pasid
)
3746 if (domain
->mode
!= PAGE_MODE_NONE
)
3749 pte
= __get_gcr3_pte(domain
->gcr3_tbl
, domain
->glx
, pasid
, false);
3755 return __amd_iommu_flush_tlb(domain
, pasid
);
3758 int amd_iommu_domain_set_gcr3(struct iommu_domain
*dom
, int pasid
,
3761 struct protection_domain
*domain
= dom
->priv
;
3762 unsigned long flags
;
3765 spin_lock_irqsave(&domain
->lock
, flags
);
3766 ret
= __set_gcr3(domain
, pasid
, cr3
);
3767 spin_unlock_irqrestore(&domain
->lock
, flags
);
3771 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3
);
3773 int amd_iommu_domain_clear_gcr3(struct iommu_domain
*dom
, int pasid
)
3775 struct protection_domain
*domain
= dom
->priv
;
3776 unsigned long flags
;
3779 spin_lock_irqsave(&domain
->lock
, flags
);
3780 ret
= __clear_gcr3(domain
, pasid
);
3781 spin_unlock_irqrestore(&domain
->lock
, flags
);
3785 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3
);
3787 int amd_iommu_complete_ppr(struct pci_dev
*pdev
, int pasid
,
3788 int status
, int tag
)
3790 struct iommu_dev_data
*dev_data
;
3791 struct amd_iommu
*iommu
;
3792 struct iommu_cmd cmd
;
3794 INC_STATS_COUNTER(complete_ppr
);
3796 dev_data
= get_dev_data(&pdev
->dev
);
3797 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
3799 build_complete_ppr(&cmd
, dev_data
->devid
, pasid
, status
,
3800 tag
, dev_data
->pri_tlp
);
3802 return iommu_queue_command(iommu
, &cmd
);
3804 EXPORT_SYMBOL(amd_iommu_complete_ppr
);
3806 struct iommu_domain
*amd_iommu_get_v2_domain(struct pci_dev
*pdev
)
3808 struct protection_domain
*domain
;
3810 domain
= get_domain(&pdev
->dev
);
3814 /* Only return IOMMUv2 domains */
3815 if (!(domain
->flags
& PD_IOMMUV2_MASK
))
3818 return domain
->iommu_domain
;
3820 EXPORT_SYMBOL(amd_iommu_get_v2_domain
);
3822 void amd_iommu_enable_device_erratum(struct pci_dev
*pdev
, u32 erratum
)
3824 struct iommu_dev_data
*dev_data
;
3826 if (!amd_iommu_v2_supported())
3829 dev_data
= get_dev_data(&pdev
->dev
);
3830 dev_data
->errata
|= (1 << erratum
);
3832 EXPORT_SYMBOL(amd_iommu_enable_device_erratum
);
3834 int amd_iommu_device_info(struct pci_dev
*pdev
,
3835 struct amd_iommu_device_info
*info
)
3840 if (pdev
== NULL
|| info
== NULL
)
3843 if (!amd_iommu_v2_supported())
3846 memset(info
, 0, sizeof(*info
));
3848 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_ATS
);
3850 info
->flags
|= AMD_IOMMU_DEVICE_FLAG_ATS_SUP
;
3852 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_PRI
);
3854 info
->flags
|= AMD_IOMMU_DEVICE_FLAG_PRI_SUP
;
3856 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_PASID
);
3860 max_pasids
= 1 << (9 * (amd_iommu_max_glx_val
+ 1));
3861 max_pasids
= min(max_pasids
, (1 << 20));
3863 info
->flags
|= AMD_IOMMU_DEVICE_FLAG_PASID_SUP
;
3864 info
->max_pasids
= min(pci_max_pasids(pdev
), max_pasids
);
3866 features
= pci_pasid_features(pdev
);
3867 if (features
& PCI_PASID_CAP_EXEC
)
3868 info
->flags
|= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP
;
3869 if (features
& PCI_PASID_CAP_PRIV
)
3870 info
->flags
|= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP
;
3875 EXPORT_SYMBOL(amd_iommu_device_info
);
3877 #ifdef CONFIG_IRQ_REMAP
3879 /*****************************************************************************
3881 * Interrupt Remapping Implementation
3883 *****************************************************************************/
3900 #define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6)
3901 #define DTE_IRQ_REMAP_INTCTL (2ULL << 60)
3902 #define DTE_IRQ_TABLE_LEN (8ULL << 1)
3903 #define DTE_IRQ_REMAP_ENABLE 1ULL
3905 static void set_dte_irq_entry(u16 devid
, struct irq_remap_table
*table
)
3909 dte
= amd_iommu_dev_table
[devid
].data
[2];
3910 dte
&= ~DTE_IRQ_PHYS_ADDR_MASK
;
3911 dte
|= virt_to_phys(table
->table
);
3912 dte
|= DTE_IRQ_REMAP_INTCTL
;
3913 dte
|= DTE_IRQ_TABLE_LEN
;
3914 dte
|= DTE_IRQ_REMAP_ENABLE
;
3916 amd_iommu_dev_table
[devid
].data
[2] = dte
;
3919 #define IRTE_ALLOCATED (~1U)
3921 static struct irq_remap_table
*get_irq_table(u16 devid
, bool ioapic
)
3923 struct irq_remap_table
*table
= NULL
;
3924 struct amd_iommu
*iommu
;
3925 unsigned long flags
;
3928 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
3930 iommu
= amd_iommu_rlookup_table
[devid
];
3934 table
= irq_lookup_table
[devid
];
3938 alias
= amd_iommu_alias_table
[devid
];
3939 table
= irq_lookup_table
[alias
];
3941 irq_lookup_table
[devid
] = table
;
3942 set_dte_irq_entry(devid
, table
);
3943 iommu_flush_dte(iommu
, devid
);
3947 /* Nothing there yet, allocate new irq remapping table */
3948 table
= kzalloc(sizeof(*table
), GFP_ATOMIC
);
3953 /* Keep the first 32 indexes free for IOAPIC interrupts */
3954 table
->min_index
= 32;
3956 table
->table
= kmem_cache_alloc(amd_iommu_irq_cache
, GFP_ATOMIC
);
3957 if (!table
->table
) {
3963 memset(table
->table
, 0, MAX_IRQS_PER_TABLE
* sizeof(u32
));
3968 for (i
= 0; i
< 32; ++i
)
3969 table
->table
[i
] = IRTE_ALLOCATED
;
3972 irq_lookup_table
[devid
] = table
;
3973 set_dte_irq_entry(devid
, table
);
3974 iommu_flush_dte(iommu
, devid
);
3975 if (devid
!= alias
) {
3976 irq_lookup_table
[alias
] = table
;
3977 set_dte_irq_entry(devid
, table
);
3978 iommu_flush_dte(iommu
, alias
);
3982 iommu_completion_wait(iommu
);
3985 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
3990 static int alloc_irq_index(struct irq_cfg
*cfg
, u16 devid
, int count
)
3992 struct irq_remap_table
*table
;
3993 unsigned long flags
;
3996 table
= get_irq_table(devid
, false);
4000 spin_lock_irqsave(&table
->lock
, flags
);
4002 /* Scan table for free entries */
4003 for (c
= 0, index
= table
->min_index
;
4004 index
< MAX_IRQS_PER_TABLE
;
4006 if (table
->table
[index
] == 0)
4012 struct irq_2_iommu
*irte_info
;
4015 table
->table
[index
- c
+ 1] = IRTE_ALLOCATED
;
4020 irte_info
= &cfg
->irq_2_iommu
;
4021 irte_info
->sub_handle
= devid
;
4022 irte_info
->irte_index
= index
;
4031 spin_unlock_irqrestore(&table
->lock
, flags
);
4036 static int get_irte(u16 devid
, int index
, union irte
*irte
)
4038 struct irq_remap_table
*table
;
4039 unsigned long flags
;
4041 table
= get_irq_table(devid
, false);
4045 spin_lock_irqsave(&table
->lock
, flags
);
4046 irte
->val
= table
->table
[index
];
4047 spin_unlock_irqrestore(&table
->lock
, flags
);
4052 static int modify_irte(u16 devid
, int index
, union irte irte
)
4054 struct irq_remap_table
*table
;
4055 struct amd_iommu
*iommu
;
4056 unsigned long flags
;
4058 iommu
= amd_iommu_rlookup_table
[devid
];
4062 table
= get_irq_table(devid
, false);
4066 spin_lock_irqsave(&table
->lock
, flags
);
4067 table
->table
[index
] = irte
.val
;
4068 spin_unlock_irqrestore(&table
->lock
, flags
);
4070 iommu_flush_irt(iommu
, devid
);
4071 iommu_completion_wait(iommu
);
4076 static void free_irte(u16 devid
, int index
)
4078 struct irq_remap_table
*table
;
4079 struct amd_iommu
*iommu
;
4080 unsigned long flags
;
4082 iommu
= amd_iommu_rlookup_table
[devid
];
4086 table
= get_irq_table(devid
, false);
4090 spin_lock_irqsave(&table
->lock
, flags
);
4091 table
->table
[index
] = 0;
4092 spin_unlock_irqrestore(&table
->lock
, flags
);
4094 iommu_flush_irt(iommu
, devid
);
4095 iommu_completion_wait(iommu
);
4098 static int setup_ioapic_entry(int irq
, struct IO_APIC_route_entry
*entry
,
4099 unsigned int destination
, int vector
,
4100 struct io_apic_irq_attr
*attr
)
4102 struct irq_remap_table
*table
;
4103 struct irq_2_iommu
*irte_info
;
4104 struct irq_cfg
*cfg
;
4111 cfg
= irq_get_chip_data(irq
);
4115 irte_info
= &cfg
->irq_2_iommu
;
4116 ioapic_id
= mpc_ioapic_id(attr
->ioapic
);
4117 devid
= get_ioapic_devid(ioapic_id
);
4122 table
= get_irq_table(devid
, true);
4126 index
= attr
->ioapic_pin
;
4128 /* Setup IRQ remapping info */
4130 irte_info
->sub_handle
= devid
;
4131 irte_info
->irte_index
= index
;
4133 /* Setup IRTE for IOMMU */
4135 irte
.fields
.vector
= vector
;
4136 irte
.fields
.int_type
= apic
->irq_delivery_mode
;
4137 irte
.fields
.destination
= destination
;
4138 irte
.fields
.dm
= apic
->irq_dest_mode
;
4139 irte
.fields
.valid
= 1;
4141 ret
= modify_irte(devid
, index
, irte
);
4145 /* Setup IOAPIC entry */
4146 memset(entry
, 0, sizeof(*entry
));
4148 entry
->vector
= index
;
4150 entry
->trigger
= attr
->trigger
;
4151 entry
->polarity
= attr
->polarity
;
4154 * Mask level triggered irqs.
4162 static int set_affinity(struct irq_data
*data
, const struct cpumask
*mask
,
4165 struct irq_2_iommu
*irte_info
;
4166 unsigned int dest
, irq
;
4167 struct irq_cfg
*cfg
;
4171 if (!config_enabled(CONFIG_SMP
))
4174 cfg
= data
->chip_data
;
4176 irte_info
= &cfg
->irq_2_iommu
;
4178 if (!cpumask_intersects(mask
, cpu_online_mask
))
4181 if (get_irte(irte_info
->sub_handle
, irte_info
->irte_index
, &irte
))
4184 if (assign_irq_vector(irq
, cfg
, mask
))
4187 err
= apic
->cpu_mask_to_apicid_and(cfg
->domain
, mask
, &dest
);
4189 if (assign_irq_vector(irq
, cfg
, data
->affinity
))
4190 pr_err("AMD-Vi: Failed to recover vector for irq %d\n", irq
);
4194 irte
.fields
.vector
= cfg
->vector
;
4195 irte
.fields
.destination
= dest
;
4197 modify_irte(irte_info
->sub_handle
, irte_info
->irte_index
, irte
);
4199 if (cfg
->move_in_progress
)
4200 send_cleanup_vector(cfg
);
4202 cpumask_copy(data
->affinity
, mask
);
4207 static int free_irq(int irq
)
4209 struct irq_2_iommu
*irte_info
;
4210 struct irq_cfg
*cfg
;
4212 cfg
= irq_get_chip_data(irq
);
4216 irte_info
= &cfg
->irq_2_iommu
;
4218 free_irte(irte_info
->sub_handle
, irte_info
->irte_index
);
4223 static void compose_msi_msg(struct pci_dev
*pdev
,
4224 unsigned int irq
, unsigned int dest
,
4225 struct msi_msg
*msg
, u8 hpet_id
)
4227 struct irq_2_iommu
*irte_info
;
4228 struct irq_cfg
*cfg
;
4231 cfg
= irq_get_chip_data(irq
);
4235 irte_info
= &cfg
->irq_2_iommu
;
4238 irte
.fields
.vector
= cfg
->vector
;
4239 irte
.fields
.int_type
= apic
->irq_delivery_mode
;
4240 irte
.fields
.destination
= dest
;
4241 irte
.fields
.dm
= apic
->irq_dest_mode
;
4242 irte
.fields
.valid
= 1;
4244 modify_irte(irte_info
->sub_handle
, irte_info
->irte_index
, irte
);
4246 msg
->address_hi
= MSI_ADDR_BASE_HI
;
4247 msg
->address_lo
= MSI_ADDR_BASE_LO
;
4248 msg
->data
= irte_info
->irte_index
;
4251 static int msi_alloc_irq(struct pci_dev
*pdev
, int irq
, int nvec
)
4253 struct irq_cfg
*cfg
;
4260 cfg
= irq_get_chip_data(irq
);
4264 devid
= get_device_id(&pdev
->dev
);
4265 index
= alloc_irq_index(cfg
, devid
, nvec
);
4267 return index
< 0 ? MAX_IRQS_PER_TABLE
: index
;
4270 static int msi_setup_irq(struct pci_dev
*pdev
, unsigned int irq
,
4271 int index
, int offset
)
4273 struct irq_2_iommu
*irte_info
;
4274 struct irq_cfg
*cfg
;
4280 cfg
= irq_get_chip_data(irq
);
4284 if (index
>= MAX_IRQS_PER_TABLE
)
4287 devid
= get_device_id(&pdev
->dev
);
4288 irte_info
= &cfg
->irq_2_iommu
;
4291 irte_info
->sub_handle
= devid
;
4292 irte_info
->irte_index
= index
+ offset
;
4297 static int setup_hpet_msi(unsigned int irq
, unsigned int id
)
4299 struct irq_2_iommu
*irte_info
;
4300 struct irq_cfg
*cfg
;
4303 cfg
= irq_get_chip_data(irq
);
4307 irte_info
= &cfg
->irq_2_iommu
;
4308 devid
= get_hpet_devid(id
);
4312 index
= alloc_irq_index(cfg
, devid
, 1);
4317 irte_info
->sub_handle
= devid
;
4318 irte_info
->irte_index
= index
;
4323 struct irq_remap_ops amd_iommu_irq_ops
= {
4324 .supported
= amd_iommu_supported
,
4325 .prepare
= amd_iommu_prepare
,
4326 .enable
= amd_iommu_enable
,
4327 .disable
= amd_iommu_disable
,
4328 .reenable
= amd_iommu_reenable
,
4329 .enable_faulting
= amd_iommu_enable_faulting
,
4330 .setup_ioapic_entry
= setup_ioapic_entry
,
4331 .set_affinity
= set_affinity
,
4332 .free_irq
= free_irq
,
4333 .compose_msi_msg
= compose_msi_msg
,
4334 .msi_alloc_irq
= msi_alloc_irq
,
4335 .msi_setup_irq
= msi_setup_irq
,
4336 .setup_hpet_msi
= setup_hpet_msi
,