1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
30 * 82562G 10/100 Network Connection
31 * 82562G-2 10/100 Network Connection
32 * 82562GT 10/100 Network Connection
33 * 82562GT-2 10/100 Network Connection
34 * 82562V 10/100 Network Connection
35 * 82562V-2 10/100 Network Connection
36 * 82566DC-2 Gigabit Network Connection
37 * 82566DC Gigabit Network Connection
38 * 82566DM-2 Gigabit Network Connection
39 * 82566DM Gigabit Network Connection
40 * 82566MC Gigabit Network Connection
41 * 82566MM Gigabit Network Connection
42 * 82567LM Gigabit Network Connection
43 * 82567LF Gigabit Network Connection
44 * 82567V Gigabit Network Connection
45 * 82567LM-2 Gigabit Network Connection
46 * 82567LF-2 Gigabit Network Connection
47 * 82567V-2 Gigabit Network Connection
48 * 82567LF-3 Gigabit Network Connection
49 * 82567LM-3 Gigabit Network Connection
50 * 82567LM-4 Gigabit Network Connection
51 * 82577LM Gigabit Network Connection
52 * 82577LC Gigabit Network Connection
53 * 82578DM Gigabit Network Connection
54 * 82578DC Gigabit Network Connection
55 * 82579LM Gigabit Network Connection
56 * 82579V Gigabit Network Connection
61 #define ICH_FLASH_GFPREG 0x0000
62 #define ICH_FLASH_HSFSTS 0x0004
63 #define ICH_FLASH_HSFCTL 0x0006
64 #define ICH_FLASH_FADDR 0x0008
65 #define ICH_FLASH_FDATA0 0x0010
66 #define ICH_FLASH_PR0 0x0074
68 #define ICH_FLASH_READ_COMMAND_TIMEOUT 500
69 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
70 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
71 #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
72 #define ICH_FLASH_CYCLE_REPEAT_COUNT 10
74 #define ICH_CYCLE_READ 0
75 #define ICH_CYCLE_WRITE 2
76 #define ICH_CYCLE_ERASE 3
78 #define FLASH_GFPREG_BASE_MASK 0x1FFF
79 #define FLASH_SECTOR_ADDR_SHIFT 12
81 #define ICH_FLASH_SEG_SIZE_256 256
82 #define ICH_FLASH_SEG_SIZE_4K 4096
83 #define ICH_FLASH_SEG_SIZE_8K 8192
84 #define ICH_FLASH_SEG_SIZE_64K 65536
87 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
88 /* FW established a valid mode */
89 #define E1000_ICH_FWSM_FW_VALID 0x00008000
91 #define E1000_ICH_MNG_IAMT_MODE 0x2
93 #define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
94 (ID_LED_DEF1_OFF2 << 8) | \
95 (ID_LED_DEF1_ON2 << 4) | \
98 #define E1000_ICH_NVM_SIG_WORD 0x13
99 #define E1000_ICH_NVM_SIG_MASK 0xC000
100 #define E1000_ICH_NVM_VALID_SIG_MASK 0xC0
101 #define E1000_ICH_NVM_SIG_VALUE 0x80
103 #define E1000_ICH8_LAN_INIT_TIMEOUT 1500
105 #define E1000_FEXTNVM_SW_CONFIG 1
106 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
108 #define E1000_FEXTNVM4_BEACON_DURATION_MASK 0x7
109 #define E1000_FEXTNVM4_BEACON_DURATION_8USEC 0x7
110 #define E1000_FEXTNVM4_BEACON_DURATION_16USEC 0x3
112 #define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
114 #define E1000_ICH_RAR_ENTRIES 7
116 #define PHY_PAGE_SHIFT 5
117 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
118 ((reg) & MAX_PHY_REG_ADDRESS))
119 #define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */
120 #define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */
122 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002
123 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
124 #define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200
126 #define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */
128 #define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in milliseconds */
130 /* SMBus Address Phy Register */
131 #define HV_SMB_ADDR PHY_REG(768, 26)
132 #define HV_SMB_ADDR_MASK 0x007F
133 #define HV_SMB_ADDR_PEC_EN 0x0200
134 #define HV_SMB_ADDR_VALID 0x0080
136 /* PHY Power Management Control */
137 #define HV_PM_CTRL PHY_REG(770, 17)
139 /* PHY Low Power Idle Control */
140 #define I82579_LPI_CTRL PHY_REG(772, 20)
141 #define I82579_LPI_CTRL_ENABLE_MASK 0x6000
142 #define I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT 0x80
145 #define I82579_EMI_ADDR 0x10
146 #define I82579_EMI_DATA 0x11
147 #define I82579_LPI_UPDATE_TIMER 0x4805 /* in 40ns units + 40 ns base value */
148 #define I82579_MSE_THRESHOLD 0x084F /* Mean Square Error Threshold */
149 #define I82579_MSE_LINK_DOWN 0x2411 /* MSE count before dropping link */
151 /* Strapping Option Register - RO */
152 #define E1000_STRAP 0x0000C
153 #define E1000_STRAP_SMBUS_ADDRESS_MASK 0x00FE0000
154 #define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
156 /* OEM Bits Phy Register */
157 #define HV_OEM_BITS PHY_REG(768, 25)
158 #define HV_OEM_BITS_LPLU 0x0004 /* Low Power Link Up */
159 #define HV_OEM_BITS_GBE_DIS 0x0040 /* Gigabit Disable */
160 #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
162 #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
163 #define E1000_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */
165 /* KMRN Mode Control */
166 #define HV_KMRN_MODE_CTRL PHY_REG(769, 16)
167 #define HV_KMRN_MDIO_SLOW 0x0400
169 /* KMRN FIFO Control and Status */
170 #define HV_KMRN_FIFO_CTRLSTA PHY_REG(770, 16)
171 #define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK 0x7000
172 #define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT 12
174 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
175 /* Offset 04h HSFSTS */
176 union ich8_hws_flash_status
{
178 u16 flcdone
:1; /* bit 0 Flash Cycle Done */
179 u16 flcerr
:1; /* bit 1 Flash Cycle Error */
180 u16 dael
:1; /* bit 2 Direct Access error Log */
181 u16 berasesz
:2; /* bit 4:3 Sector Erase Size */
182 u16 flcinprog
:1; /* bit 5 flash cycle in Progress */
183 u16 reserved1
:2; /* bit 13:6 Reserved */
184 u16 reserved2
:6; /* bit 13:6 Reserved */
185 u16 fldesvalid
:1; /* bit 14 Flash Descriptor Valid */
186 u16 flockdn
:1; /* bit 15 Flash Config Lock-Down */
191 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
192 /* Offset 06h FLCTL */
193 union ich8_hws_flash_ctrl
{
194 struct ich8_hsflctl
{
195 u16 flcgo
:1; /* 0 Flash Cycle Go */
196 u16 flcycle
:2; /* 2:1 Flash Cycle */
197 u16 reserved
:5; /* 7:3 Reserved */
198 u16 fldbcount
:2; /* 9:8 Flash Data Byte Count */
199 u16 flockdn
:6; /* 15:10 Reserved */
204 /* ICH Flash Region Access Permissions */
205 union ich8_hws_flash_regacc
{
207 u32 grra
:8; /* 0:7 GbE region Read Access */
208 u32 grwa
:8; /* 8:15 GbE region Write Access */
209 u32 gmrag
:8; /* 23:16 GbE Master Read Access Grant */
210 u32 gmwag
:8; /* 31:24 GbE Master Write Access Grant */
215 /* ICH Flash Protected Region */
216 union ich8_flash_protected_range
{
218 u32 base
:13; /* 0:12 Protected Range Base */
219 u32 reserved1
:2; /* 13:14 Reserved */
220 u32 rpe
:1; /* 15 Read Protection Enable */
221 u32 limit
:13; /* 16:28 Protected Range Limit */
222 u32 reserved2
:2; /* 29:30 Reserved */
223 u32 wpe
:1; /* 31 Write Protection Enable */
228 static s32
e1000_setup_link_ich8lan(struct e1000_hw
*hw
);
229 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw
*hw
);
230 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw
*hw
);
231 static s32
e1000_erase_flash_bank_ich8lan(struct e1000_hw
*hw
, u32 bank
);
232 static s32
e1000_retry_write_flash_byte_ich8lan(struct e1000_hw
*hw
,
233 u32 offset
, u8 byte
);
234 static s32
e1000_read_flash_byte_ich8lan(struct e1000_hw
*hw
, u32 offset
,
236 static s32
e1000_read_flash_word_ich8lan(struct e1000_hw
*hw
, u32 offset
,
238 static s32
e1000_read_flash_data_ich8lan(struct e1000_hw
*hw
, u32 offset
,
240 static s32
e1000_setup_copper_link_ich8lan(struct e1000_hw
*hw
);
241 static s32
e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw
*hw
);
242 static s32
e1000_get_cfg_done_ich8lan(struct e1000_hw
*hw
);
243 static s32
e1000_cleanup_led_ich8lan(struct e1000_hw
*hw
);
244 static s32
e1000_led_on_ich8lan(struct e1000_hw
*hw
);
245 static s32
e1000_led_off_ich8lan(struct e1000_hw
*hw
);
246 static s32
e1000_id_led_init_pchlan(struct e1000_hw
*hw
);
247 static s32
e1000_setup_led_pchlan(struct e1000_hw
*hw
);
248 static s32
e1000_cleanup_led_pchlan(struct e1000_hw
*hw
);
249 static s32
e1000_led_on_pchlan(struct e1000_hw
*hw
);
250 static s32
e1000_led_off_pchlan(struct e1000_hw
*hw
);
251 static s32
e1000_set_lplu_state_pchlan(struct e1000_hw
*hw
, bool active
);
252 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw
*hw
);
253 static void e1000_lan_init_done_ich8lan(struct e1000_hw
*hw
);
254 static s32
e1000_k1_gig_workaround_hv(struct e1000_hw
*hw
, bool link
);
255 static s32
e1000_set_mdio_slow_mode_hv(struct e1000_hw
*hw
);
256 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw
*hw
);
257 static bool e1000_check_mng_mode_pchlan(struct e1000_hw
*hw
);
258 static s32
e1000_k1_workaround_lv(struct e1000_hw
*hw
);
259 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw
*hw
, bool gate
);
261 static inline u16
__er16flash(struct e1000_hw
*hw
, unsigned long reg
)
263 return readw(hw
->flash_address
+ reg
);
266 static inline u32
__er32flash(struct e1000_hw
*hw
, unsigned long reg
)
268 return readl(hw
->flash_address
+ reg
);
271 static inline void __ew16flash(struct e1000_hw
*hw
, unsigned long reg
, u16 val
)
273 writew(val
, hw
->flash_address
+ reg
);
276 static inline void __ew32flash(struct e1000_hw
*hw
, unsigned long reg
, u32 val
)
278 writel(val
, hw
->flash_address
+ reg
);
281 #define er16flash(reg) __er16flash(hw, (reg))
282 #define er32flash(reg) __er32flash(hw, (reg))
283 #define ew16flash(reg, val) __ew16flash(hw, (reg), (val))
284 #define ew32flash(reg, val) __ew32flash(hw, (reg), (val))
286 static void e1000_toggle_lanphypc_value_ich8lan(struct e1000_hw
*hw
)
291 ctrl
|= E1000_CTRL_LANPHYPC_OVERRIDE
;
292 ctrl
&= ~E1000_CTRL_LANPHYPC_VALUE
;
296 ctrl
&= ~E1000_CTRL_LANPHYPC_OVERRIDE
;
301 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
302 * @hw: pointer to the HW structure
304 * Initialize family-specific PHY parameters and function pointers.
306 static s32
e1000_init_phy_params_pchlan(struct e1000_hw
*hw
)
308 struct e1000_phy_info
*phy
= &hw
->phy
;
312 phy
->reset_delay_us
= 100;
314 phy
->ops
.set_page
= e1000_set_page_igp
;
315 phy
->ops
.read_reg
= e1000_read_phy_reg_hv
;
316 phy
->ops
.read_reg_locked
= e1000_read_phy_reg_hv_locked
;
317 phy
->ops
.read_reg_page
= e1000_read_phy_reg_page_hv
;
318 phy
->ops
.set_d0_lplu_state
= e1000_set_lplu_state_pchlan
;
319 phy
->ops
.set_d3_lplu_state
= e1000_set_lplu_state_pchlan
;
320 phy
->ops
.write_reg
= e1000_write_phy_reg_hv
;
321 phy
->ops
.write_reg_locked
= e1000_write_phy_reg_hv_locked
;
322 phy
->ops
.write_reg_page
= e1000_write_phy_reg_page_hv
;
323 phy
->ops
.power_up
= e1000_power_up_phy_copper
;
324 phy
->ops
.power_down
= e1000_power_down_phy_copper_ich8lan
;
325 phy
->autoneg_mask
= AUTONEG_ADVERTISE_SPEED_DEFAULT
;
327 if (!hw
->phy
.ops
.check_reset_block(hw
)) {
328 u32 fwsm
= er32(FWSM
);
331 * The MAC-PHY interconnect may still be in SMBus mode after
332 * Sx->S0. If resetting the PHY is not blocked, toggle the
333 * LANPHYPC Value bit to force the interconnect to PCIe mode.
335 e1000_toggle_lanphypc_value_ich8lan(hw
);
339 * Gate automatic PHY configuration by hardware on
342 if ((hw
->mac
.type
== e1000_pch2lan
) &&
343 !(fwsm
& E1000_ICH_FWSM_FW_VALID
))
344 e1000_gate_hw_phy_config_ich8lan(hw
, true);
347 * Reset the PHY before any access to it. Doing so, ensures
348 * that the PHY is in a known good state before we read/write
349 * PHY registers. The generic reset is sufficient here,
350 * because we haven't determined the PHY type yet.
352 ret_val
= e1000e_phy_hw_reset_generic(hw
);
356 /* Ungate automatic PHY configuration on non-managed 82579 */
357 if ((hw
->mac
.type
== e1000_pch2lan
) &&
358 !(fwsm
& E1000_ICH_FWSM_FW_VALID
)) {
359 usleep_range(10000, 20000);
360 e1000_gate_hw_phy_config_ich8lan(hw
, false);
364 phy
->id
= e1000_phy_unknown
;
365 switch (hw
->mac
.type
) {
367 ret_val
= e1000e_get_phy_id(hw
);
370 if ((phy
->id
!= 0) && (phy
->id
!= PHY_REVISION_MASK
))
375 * In case the PHY needs to be in mdio slow mode,
376 * set slow mode and try to get the PHY id again.
378 ret_val
= e1000_set_mdio_slow_mode_hv(hw
);
381 ret_val
= e1000e_get_phy_id(hw
);
386 phy
->type
= e1000e_get_phy_type_from_id(phy
->id
);
389 case e1000_phy_82577
:
390 case e1000_phy_82579
:
391 phy
->ops
.check_polarity
= e1000_check_polarity_82577
;
392 phy
->ops
.force_speed_duplex
=
393 e1000_phy_force_speed_duplex_82577
;
394 phy
->ops
.get_cable_length
= e1000_get_cable_length_82577
;
395 phy
->ops
.get_info
= e1000_get_phy_info_82577
;
396 phy
->ops
.commit
= e1000e_phy_sw_reset
;
398 case e1000_phy_82578
:
399 phy
->ops
.check_polarity
= e1000_check_polarity_m88
;
400 phy
->ops
.force_speed_duplex
= e1000e_phy_force_speed_duplex_m88
;
401 phy
->ops
.get_cable_length
= e1000e_get_cable_length_m88
;
402 phy
->ops
.get_info
= e1000e_get_phy_info_m88
;
405 ret_val
= -E1000_ERR_PHY
;
413 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
414 * @hw: pointer to the HW structure
416 * Initialize family-specific PHY parameters and function pointers.
418 static s32
e1000_init_phy_params_ich8lan(struct e1000_hw
*hw
)
420 struct e1000_phy_info
*phy
= &hw
->phy
;
425 phy
->reset_delay_us
= 100;
427 phy
->ops
.power_up
= e1000_power_up_phy_copper
;
428 phy
->ops
.power_down
= e1000_power_down_phy_copper_ich8lan
;
431 * We may need to do this twice - once for IGP and if that fails,
432 * we'll set BM func pointers and try again
434 ret_val
= e1000e_determine_phy_address(hw
);
436 phy
->ops
.write_reg
= e1000e_write_phy_reg_bm
;
437 phy
->ops
.read_reg
= e1000e_read_phy_reg_bm
;
438 ret_val
= e1000e_determine_phy_address(hw
);
440 e_dbg("Cannot determine PHY addr. Erroring out\n");
446 while ((e1000_phy_unknown
== e1000e_get_phy_type_from_id(phy
->id
)) &&
448 usleep_range(1000, 2000);
449 ret_val
= e1000e_get_phy_id(hw
);
456 case IGP03E1000_E_PHY_ID
:
457 phy
->type
= e1000_phy_igp_3
;
458 phy
->autoneg_mask
= AUTONEG_ADVERTISE_SPEED_DEFAULT
;
459 phy
->ops
.read_reg_locked
= e1000e_read_phy_reg_igp_locked
;
460 phy
->ops
.write_reg_locked
= e1000e_write_phy_reg_igp_locked
;
461 phy
->ops
.get_info
= e1000e_get_phy_info_igp
;
462 phy
->ops
.check_polarity
= e1000_check_polarity_igp
;
463 phy
->ops
.force_speed_duplex
= e1000e_phy_force_speed_duplex_igp
;
466 case IFE_PLUS_E_PHY_ID
:
468 phy
->type
= e1000_phy_ife
;
469 phy
->autoneg_mask
= E1000_ALL_NOT_GIG
;
470 phy
->ops
.get_info
= e1000_get_phy_info_ife
;
471 phy
->ops
.check_polarity
= e1000_check_polarity_ife
;
472 phy
->ops
.force_speed_duplex
= e1000_phy_force_speed_duplex_ife
;
474 case BME1000_E_PHY_ID
:
475 phy
->type
= e1000_phy_bm
;
476 phy
->autoneg_mask
= AUTONEG_ADVERTISE_SPEED_DEFAULT
;
477 phy
->ops
.read_reg
= e1000e_read_phy_reg_bm
;
478 phy
->ops
.write_reg
= e1000e_write_phy_reg_bm
;
479 phy
->ops
.commit
= e1000e_phy_sw_reset
;
480 phy
->ops
.get_info
= e1000e_get_phy_info_m88
;
481 phy
->ops
.check_polarity
= e1000_check_polarity_m88
;
482 phy
->ops
.force_speed_duplex
= e1000e_phy_force_speed_duplex_m88
;
485 return -E1000_ERR_PHY
;
493 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
494 * @hw: pointer to the HW structure
496 * Initialize family-specific NVM parameters and function
499 static s32
e1000_init_nvm_params_ich8lan(struct e1000_hw
*hw
)
501 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
502 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
503 u32 gfpreg
, sector_base_addr
, sector_end_addr
;
506 /* Can't read flash registers if the register set isn't mapped. */
507 if (!hw
->flash_address
) {
508 e_dbg("ERROR: Flash registers not mapped\n");
509 return -E1000_ERR_CONFIG
;
512 nvm
->type
= e1000_nvm_flash_sw
;
514 gfpreg
= er32flash(ICH_FLASH_GFPREG
);
517 * sector_X_addr is a "sector"-aligned address (4096 bytes)
518 * Add 1 to sector_end_addr since this sector is included in
521 sector_base_addr
= gfpreg
& FLASH_GFPREG_BASE_MASK
;
522 sector_end_addr
= ((gfpreg
>> 16) & FLASH_GFPREG_BASE_MASK
) + 1;
524 /* flash_base_addr is byte-aligned */
525 nvm
->flash_base_addr
= sector_base_addr
<< FLASH_SECTOR_ADDR_SHIFT
;
528 * find total size of the NVM, then cut in half since the total
529 * size represents two separate NVM banks.
531 nvm
->flash_bank_size
= (sector_end_addr
- sector_base_addr
)
532 << FLASH_SECTOR_ADDR_SHIFT
;
533 nvm
->flash_bank_size
/= 2;
534 /* Adjust to word count */
535 nvm
->flash_bank_size
/= sizeof(u16
);
537 nvm
->word_size
= E1000_ICH8_SHADOW_RAM_WORDS
;
539 /* Clear shadow ram */
540 for (i
= 0; i
< nvm
->word_size
; i
++) {
541 dev_spec
->shadow_ram
[i
].modified
= false;
542 dev_spec
->shadow_ram
[i
].value
= 0xFFFF;
549 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
550 * @hw: pointer to the HW structure
552 * Initialize family-specific MAC parameters and function
555 static s32
e1000_init_mac_params_ich8lan(struct e1000_hw
*hw
)
557 struct e1000_mac_info
*mac
= &hw
->mac
;
559 /* Set media type function pointer */
560 hw
->phy
.media_type
= e1000_media_type_copper
;
562 /* Set mta register count */
563 mac
->mta_reg_count
= 32;
564 /* Set rar entry count */
565 mac
->rar_entry_count
= E1000_ICH_RAR_ENTRIES
;
566 if (mac
->type
== e1000_ich8lan
)
567 mac
->rar_entry_count
--;
569 mac
->has_fwsm
= true;
570 /* ARC subsystem not supported */
571 mac
->arc_subsystem_valid
= false;
572 /* Adaptive IFS supported */
573 mac
->adaptive_ifs
= true;
580 /* check management mode */
581 mac
->ops
.check_mng_mode
= e1000_check_mng_mode_ich8lan
;
583 mac
->ops
.id_led_init
= e1000e_id_led_init_generic
;
585 mac
->ops
.blink_led
= e1000e_blink_led_generic
;
587 mac
->ops
.setup_led
= e1000e_setup_led_generic
;
589 mac
->ops
.cleanup_led
= e1000_cleanup_led_ich8lan
;
590 /* turn on/off LED */
591 mac
->ops
.led_on
= e1000_led_on_ich8lan
;
592 mac
->ops
.led_off
= e1000_led_off_ich8lan
;
596 /* check management mode */
597 mac
->ops
.check_mng_mode
= e1000_check_mng_mode_pchlan
;
599 mac
->ops
.id_led_init
= e1000_id_led_init_pchlan
;
601 mac
->ops
.setup_led
= e1000_setup_led_pchlan
;
603 mac
->ops
.cleanup_led
= e1000_cleanup_led_pchlan
;
604 /* turn on/off LED */
605 mac
->ops
.led_on
= e1000_led_on_pchlan
;
606 mac
->ops
.led_off
= e1000_led_off_pchlan
;
612 /* Enable PCS Lock-loss workaround for ICH8 */
613 if (mac
->type
== e1000_ich8lan
)
614 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw
, true);
616 /* Gate automatic PHY configuration by hardware on managed 82579 */
617 if ((mac
->type
== e1000_pch2lan
) &&
618 (er32(FWSM
) & E1000_ICH_FWSM_FW_VALID
))
619 e1000_gate_hw_phy_config_ich8lan(hw
, true);
625 * e1000_set_eee_pchlan - Enable/disable EEE support
626 * @hw: pointer to the HW structure
628 * Enable/disable EEE based on setting in dev_spec structure. The bits in
629 * the LPI Control register will remain set only if/when link is up.
631 static s32
e1000_set_eee_pchlan(struct e1000_hw
*hw
)
636 if (hw
->phy
.type
!= e1000_phy_82579
)
639 ret_val
= e1e_rphy(hw
, I82579_LPI_CTRL
, &phy_reg
);
643 if (hw
->dev_spec
.ich8lan
.eee_disable
)
644 phy_reg
&= ~I82579_LPI_CTRL_ENABLE_MASK
;
646 phy_reg
|= I82579_LPI_CTRL_ENABLE_MASK
;
648 return e1e_wphy(hw
, I82579_LPI_CTRL
, phy_reg
);
652 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
653 * @hw: pointer to the HW structure
655 * Checks to see of the link status of the hardware has changed. If a
656 * change in link status has been detected, then we read the PHY registers
657 * to get the current speed/duplex if link exists.
659 static s32
e1000_check_for_copper_link_ich8lan(struct e1000_hw
*hw
)
661 struct e1000_mac_info
*mac
= &hw
->mac
;
667 * We only want to go out to the PHY registers to see if Auto-Neg
668 * has completed and/or if our link status has changed. The
669 * get_link_status flag is set upon receiving a Link Status
670 * Change or Rx Sequence Error interrupt.
672 if (!mac
->get_link_status
)
676 * First we want to see if the MII Status Register reports
677 * link. If so, then we want to get the current speed/duplex
680 ret_val
= e1000e_phy_has_link_generic(hw
, 1, 0, &link
);
684 if (hw
->mac
.type
== e1000_pchlan
) {
685 ret_val
= e1000_k1_gig_workaround_hv(hw
, link
);
691 return 0; /* No link detected */
693 mac
->get_link_status
= false;
695 switch (hw
->mac
.type
) {
697 ret_val
= e1000_k1_workaround_lv(hw
);
702 if (hw
->phy
.type
== e1000_phy_82578
) {
703 ret_val
= e1000_link_stall_workaround_hv(hw
);
709 * Workaround for PCHx parts in half-duplex:
710 * Set the number of preambles removed from the packet
711 * when it is passed from the PHY to the MAC to prevent
712 * the MAC from misinterpreting the packet type.
714 e1e_rphy(hw
, HV_KMRN_FIFO_CTRLSTA
, &phy_reg
);
715 phy_reg
&= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK
;
717 if ((er32(STATUS
) & E1000_STATUS_FD
) != E1000_STATUS_FD
)
718 phy_reg
|= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT
);
720 e1e_wphy(hw
, HV_KMRN_FIFO_CTRLSTA
, phy_reg
);
727 * Check if there was DownShift, must be checked
728 * immediately after link-up
730 e1000e_check_downshift(hw
);
732 /* Enable/Disable EEE after link up */
733 ret_val
= e1000_set_eee_pchlan(hw
);
738 * If we are forcing speed/duplex, then we simply return since
739 * we have already determined whether we have link or not.
742 return -E1000_ERR_CONFIG
;
745 * Auto-Neg is enabled. Auto Speed Detection takes care
746 * of MAC speed/duplex configuration. So we only need to
747 * configure Collision Distance in the MAC.
749 e1000e_config_collision_dist(hw
);
752 * Configure Flow Control now that Auto-Neg has completed.
753 * First, we need to restore the desired flow control
754 * settings because we may have had to re-autoneg with a
755 * different link partner.
757 ret_val
= e1000e_config_fc_after_link_up(hw
);
759 e_dbg("Error configuring flow control\n");
764 static s32
e1000_get_variants_ich8lan(struct e1000_adapter
*adapter
)
766 struct e1000_hw
*hw
= &adapter
->hw
;
769 rc
= e1000_init_mac_params_ich8lan(hw
);
773 rc
= e1000_init_nvm_params_ich8lan(hw
);
777 switch (hw
->mac
.type
) {
781 rc
= e1000_init_phy_params_ich8lan(hw
);
785 rc
= e1000_init_phy_params_pchlan(hw
);
794 * Disable Jumbo Frame support on parts with Intel 10/100 PHY or
795 * on parts with MACsec enabled in NVM (reflected in CTRL_EXT).
797 if ((adapter
->hw
.phy
.type
== e1000_phy_ife
) ||
798 ((adapter
->hw
.mac
.type
>= e1000_pch2lan
) &&
799 (!(er32(CTRL_EXT
) & E1000_CTRL_EXT_LSECCK
)))) {
800 adapter
->flags
&= ~FLAG_HAS_JUMBO_FRAMES
;
801 adapter
->max_hw_frame_size
= ETH_FRAME_LEN
+ ETH_FCS_LEN
;
803 hw
->mac
.ops
.blink_led
= NULL
;
806 if ((adapter
->hw
.mac
.type
== e1000_ich8lan
) &&
807 (adapter
->hw
.phy
.type
!= e1000_phy_ife
))
808 adapter
->flags
|= FLAG_LSC_GIG_SPEED_DROP
;
810 /* Enable workaround for 82579 w/ ME enabled */
811 if ((adapter
->hw
.mac
.type
== e1000_pch2lan
) &&
812 (er32(FWSM
) & E1000_ICH_FWSM_FW_VALID
))
813 adapter
->flags2
|= FLAG2_PCIM2PCI_ARBITER_WA
;
815 /* Disable EEE by default until IEEE802.3az spec is finalized */
816 if (adapter
->flags2
& FLAG2_HAS_EEE
)
817 adapter
->hw
.dev_spec
.ich8lan
.eee_disable
= true;
822 static DEFINE_MUTEX(nvm_mutex
);
825 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
826 * @hw: pointer to the HW structure
828 * Acquires the mutex for performing NVM operations.
830 static s32
e1000_acquire_nvm_ich8lan(struct e1000_hw
*hw
)
832 mutex_lock(&nvm_mutex
);
838 * e1000_release_nvm_ich8lan - Release NVM mutex
839 * @hw: pointer to the HW structure
841 * Releases the mutex used while performing NVM operations.
843 static void e1000_release_nvm_ich8lan(struct e1000_hw
*hw
)
845 mutex_unlock(&nvm_mutex
);
849 * e1000_acquire_swflag_ich8lan - Acquire software control flag
850 * @hw: pointer to the HW structure
852 * Acquires the software control flag for performing PHY and select
855 static s32
e1000_acquire_swflag_ich8lan(struct e1000_hw
*hw
)
857 u32 extcnf_ctrl
, timeout
= PHY_CFG_TIMEOUT
;
860 if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE
,
861 &hw
->adapter
->state
)) {
862 e_dbg("contention for Phy access\n");
863 return -E1000_ERR_PHY
;
867 extcnf_ctrl
= er32(EXTCNF_CTRL
);
868 if (!(extcnf_ctrl
& E1000_EXTCNF_CTRL_SWFLAG
))
876 e_dbg("SW has already locked the resource.\n");
877 ret_val
= -E1000_ERR_CONFIG
;
881 timeout
= SW_FLAG_TIMEOUT
;
883 extcnf_ctrl
|= E1000_EXTCNF_CTRL_SWFLAG
;
884 ew32(EXTCNF_CTRL
, extcnf_ctrl
);
887 extcnf_ctrl
= er32(EXTCNF_CTRL
);
888 if (extcnf_ctrl
& E1000_EXTCNF_CTRL_SWFLAG
)
896 e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
897 er32(FWSM
), extcnf_ctrl
);
898 extcnf_ctrl
&= ~E1000_EXTCNF_CTRL_SWFLAG
;
899 ew32(EXTCNF_CTRL
, extcnf_ctrl
);
900 ret_val
= -E1000_ERR_CONFIG
;
906 clear_bit(__E1000_ACCESS_SHARED_RESOURCE
, &hw
->adapter
->state
);
912 * e1000_release_swflag_ich8lan - Release software control flag
913 * @hw: pointer to the HW structure
915 * Releases the software control flag for performing PHY and select
918 static void e1000_release_swflag_ich8lan(struct e1000_hw
*hw
)
922 extcnf_ctrl
= er32(EXTCNF_CTRL
);
924 if (extcnf_ctrl
& E1000_EXTCNF_CTRL_SWFLAG
) {
925 extcnf_ctrl
&= ~E1000_EXTCNF_CTRL_SWFLAG
;
926 ew32(EXTCNF_CTRL
, extcnf_ctrl
);
928 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n");
931 clear_bit(__E1000_ACCESS_SHARED_RESOURCE
, &hw
->adapter
->state
);
935 * e1000_check_mng_mode_ich8lan - Checks management mode
936 * @hw: pointer to the HW structure
938 * This checks if the adapter has any manageability enabled.
939 * This is a function pointer entry point only called by read/write
940 * routines for the PHY and NVM parts.
942 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw
*hw
)
947 return (fwsm
& E1000_ICH_FWSM_FW_VALID
) &&
948 ((fwsm
& E1000_FWSM_MODE_MASK
) ==
949 (E1000_ICH_MNG_IAMT_MODE
<< E1000_FWSM_MODE_SHIFT
));
953 * e1000_check_mng_mode_pchlan - Checks management mode
954 * @hw: pointer to the HW structure
956 * This checks if the adapter has iAMT enabled.
957 * This is a function pointer entry point only called by read/write
958 * routines for the PHY and NVM parts.
960 static bool e1000_check_mng_mode_pchlan(struct e1000_hw
*hw
)
965 return (fwsm
& E1000_ICH_FWSM_FW_VALID
) &&
966 (fwsm
& (E1000_ICH_MNG_IAMT_MODE
<< E1000_FWSM_MODE_SHIFT
));
970 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
971 * @hw: pointer to the HW structure
973 * Checks if firmware is blocking the reset of the PHY.
974 * This is a function pointer entry point only called by
977 static s32
e1000_check_reset_block_ich8lan(struct e1000_hw
*hw
)
983 return (fwsm
& E1000_ICH_FWSM_RSPCIPHY
) ? 0 : E1000_BLK_PHY_RESET
;
987 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
988 * @hw: pointer to the HW structure
990 * Assumes semaphore already acquired.
993 static s32
e1000_write_smbus_addr(struct e1000_hw
*hw
)
996 u32 strap
= er32(STRAP
);
999 strap
&= E1000_STRAP_SMBUS_ADDRESS_MASK
;
1001 ret_val
= e1000_read_phy_reg_hv_locked(hw
, HV_SMB_ADDR
, &phy_data
);
1005 phy_data
&= ~HV_SMB_ADDR_MASK
;
1006 phy_data
|= (strap
>> E1000_STRAP_SMBUS_ADDRESS_SHIFT
);
1007 phy_data
|= HV_SMB_ADDR_PEC_EN
| HV_SMB_ADDR_VALID
;
1009 return e1000_write_phy_reg_hv_locked(hw
, HV_SMB_ADDR
, phy_data
);
1013 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
1014 * @hw: pointer to the HW structure
1016 * SW should configure the LCD from the NVM extended configuration region
1017 * as a workaround for certain parts.
1019 static s32
e1000_sw_lcd_config_ich8lan(struct e1000_hw
*hw
)
1021 struct e1000_phy_info
*phy
= &hw
->phy
;
1022 u32 i
, data
, cnf_size
, cnf_base_addr
, sw_cfg_mask
;
1024 u16 word_addr
, reg_data
, reg_addr
, phy_page
= 0;
1027 * Initialize the PHY from the NVM on ICH platforms. This
1028 * is needed due to an issue where the NVM configuration is
1029 * not properly autoloaded after power transitions.
1030 * Therefore, after each PHY reset, we will load the
1031 * configuration data out of the NVM manually.
1033 switch (hw
->mac
.type
) {
1035 if (phy
->type
!= e1000_phy_igp_3
)
1038 if ((hw
->adapter
->pdev
->device
== E1000_DEV_ID_ICH8_IGP_AMT
) ||
1039 (hw
->adapter
->pdev
->device
== E1000_DEV_ID_ICH8_IGP_C
)) {
1040 sw_cfg_mask
= E1000_FEXTNVM_SW_CONFIG
;
1046 sw_cfg_mask
= E1000_FEXTNVM_SW_CONFIG_ICH8M
;
1052 ret_val
= hw
->phy
.ops
.acquire(hw
);
1056 data
= er32(FEXTNVM
);
1057 if (!(data
& sw_cfg_mask
))
1061 * Make sure HW does not configure LCD from PHY
1062 * extended configuration before SW configuration
1064 data
= er32(EXTCNF_CTRL
);
1065 if (!(hw
->mac
.type
== e1000_pch2lan
)) {
1066 if (data
& E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE
)
1070 cnf_size
= er32(EXTCNF_SIZE
);
1071 cnf_size
&= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK
;
1072 cnf_size
>>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT
;
1076 cnf_base_addr
= data
& E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK
;
1077 cnf_base_addr
>>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT
;
1079 if ((!(data
& E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE
) &&
1080 (hw
->mac
.type
== e1000_pchlan
)) ||
1081 (hw
->mac
.type
== e1000_pch2lan
)) {
1083 * HW configures the SMBus address and LEDs when the
1084 * OEM and LCD Write Enable bits are set in the NVM.
1085 * When both NVM bits are cleared, SW will configure
1088 ret_val
= e1000_write_smbus_addr(hw
);
1092 data
= er32(LEDCTL
);
1093 ret_val
= e1000_write_phy_reg_hv_locked(hw
, HV_LED_CONFIG
,
1099 /* Configure LCD from extended configuration region. */
1101 /* cnf_base_addr is in DWORD */
1102 word_addr
= (u16
)(cnf_base_addr
<< 1);
1104 for (i
= 0; i
< cnf_size
; i
++) {
1105 ret_val
= e1000_read_nvm(hw
, (word_addr
+ i
* 2), 1,
1110 ret_val
= e1000_read_nvm(hw
, (word_addr
+ i
* 2 + 1),
1115 /* Save off the PHY page for future writes. */
1116 if (reg_addr
== IGP01E1000_PHY_PAGE_SELECT
) {
1117 phy_page
= reg_data
;
1121 reg_addr
&= PHY_REG_MASK
;
1122 reg_addr
|= phy_page
;
1124 ret_val
= phy
->ops
.write_reg_locked(hw
, (u32
)reg_addr
,
1131 hw
->phy
.ops
.release(hw
);
1136 * e1000_k1_gig_workaround_hv - K1 Si workaround
1137 * @hw: pointer to the HW structure
1138 * @link: link up bool flag
1140 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning
1141 * from a lower speed. This workaround disables K1 whenever link is at 1Gig
1142 * If link is down, the function will restore the default K1 setting located
1145 static s32
e1000_k1_gig_workaround_hv(struct e1000_hw
*hw
, bool link
)
1149 bool k1_enable
= hw
->dev_spec
.ich8lan
.nvm_k1_enabled
;
1151 if (hw
->mac
.type
!= e1000_pchlan
)
1154 /* Wrap the whole flow with the sw flag */
1155 ret_val
= hw
->phy
.ops
.acquire(hw
);
1159 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
1161 if (hw
->phy
.type
== e1000_phy_82578
) {
1162 ret_val
= hw
->phy
.ops
.read_reg_locked(hw
, BM_CS_STATUS
,
1167 status_reg
&= BM_CS_STATUS_LINK_UP
|
1168 BM_CS_STATUS_RESOLVED
|
1169 BM_CS_STATUS_SPEED_MASK
;
1171 if (status_reg
== (BM_CS_STATUS_LINK_UP
|
1172 BM_CS_STATUS_RESOLVED
|
1173 BM_CS_STATUS_SPEED_1000
))
1177 if (hw
->phy
.type
== e1000_phy_82577
) {
1178 ret_val
= hw
->phy
.ops
.read_reg_locked(hw
, HV_M_STATUS
,
1183 status_reg
&= HV_M_STATUS_LINK_UP
|
1184 HV_M_STATUS_AUTONEG_COMPLETE
|
1185 HV_M_STATUS_SPEED_MASK
;
1187 if (status_reg
== (HV_M_STATUS_LINK_UP
|
1188 HV_M_STATUS_AUTONEG_COMPLETE
|
1189 HV_M_STATUS_SPEED_1000
))
1193 /* Link stall fix for link up */
1194 ret_val
= hw
->phy
.ops
.write_reg_locked(hw
, PHY_REG(770, 19),
1200 /* Link stall fix for link down */
1201 ret_val
= hw
->phy
.ops
.write_reg_locked(hw
, PHY_REG(770, 19),
1207 ret_val
= e1000_configure_k1_ich8lan(hw
, k1_enable
);
1210 hw
->phy
.ops
.release(hw
);
1216 * e1000_configure_k1_ich8lan - Configure K1 power state
1217 * @hw: pointer to the HW structure
1218 * @enable: K1 state to configure
1220 * Configure the K1 power state based on the provided parameter.
1221 * Assumes semaphore already acquired.
1223 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1225 s32
e1000_configure_k1_ich8lan(struct e1000_hw
*hw
, bool k1_enable
)
1233 ret_val
= e1000e_read_kmrn_reg_locked(hw
,
1234 E1000_KMRNCTRLSTA_K1_CONFIG
,
1240 kmrn_reg
|= E1000_KMRNCTRLSTA_K1_ENABLE
;
1242 kmrn_reg
&= ~E1000_KMRNCTRLSTA_K1_ENABLE
;
1244 ret_val
= e1000e_write_kmrn_reg_locked(hw
,
1245 E1000_KMRNCTRLSTA_K1_CONFIG
,
1251 ctrl_ext
= er32(CTRL_EXT
);
1252 ctrl_reg
= er32(CTRL
);
1254 reg
= ctrl_reg
& ~(E1000_CTRL_SPD_1000
| E1000_CTRL_SPD_100
);
1255 reg
|= E1000_CTRL_FRCSPD
;
1258 ew32(CTRL_EXT
, ctrl_ext
| E1000_CTRL_EXT_SPD_BYPS
);
1261 ew32(CTRL
, ctrl_reg
);
1262 ew32(CTRL_EXT
, ctrl_ext
);
1270 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
1271 * @hw: pointer to the HW structure
1272 * @d0_state: boolean if entering d0 or d3 device state
1274 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
1275 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit
1276 * in NVM determines whether HW should configure LPLU and Gbe Disable.
1278 static s32
e1000_oem_bits_config_ich8lan(struct e1000_hw
*hw
, bool d0_state
)
1284 if ((hw
->mac
.type
!= e1000_pch2lan
) && (hw
->mac
.type
!= e1000_pchlan
))
1287 ret_val
= hw
->phy
.ops
.acquire(hw
);
1291 if (!(hw
->mac
.type
== e1000_pch2lan
)) {
1292 mac_reg
= er32(EXTCNF_CTRL
);
1293 if (mac_reg
& E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE
)
1297 mac_reg
= er32(FEXTNVM
);
1298 if (!(mac_reg
& E1000_FEXTNVM_SW_CONFIG_ICH8M
))
1301 mac_reg
= er32(PHY_CTRL
);
1303 ret_val
= hw
->phy
.ops
.read_reg_locked(hw
, HV_OEM_BITS
, &oem_reg
);
1307 oem_reg
&= ~(HV_OEM_BITS_GBE_DIS
| HV_OEM_BITS_LPLU
);
1310 if (mac_reg
& E1000_PHY_CTRL_GBE_DISABLE
)
1311 oem_reg
|= HV_OEM_BITS_GBE_DIS
;
1313 if (mac_reg
& E1000_PHY_CTRL_D0A_LPLU
)
1314 oem_reg
|= HV_OEM_BITS_LPLU
;
1316 /* Set Restart auto-neg to activate the bits */
1317 if (!hw
->phy
.ops
.check_reset_block(hw
))
1318 oem_reg
|= HV_OEM_BITS_RESTART_AN
;
1320 if (mac_reg
& (E1000_PHY_CTRL_GBE_DISABLE
|
1321 E1000_PHY_CTRL_NOND0A_GBE_DISABLE
))
1322 oem_reg
|= HV_OEM_BITS_GBE_DIS
;
1324 if (mac_reg
& (E1000_PHY_CTRL_D0A_LPLU
|
1325 E1000_PHY_CTRL_NOND0A_LPLU
))
1326 oem_reg
|= HV_OEM_BITS_LPLU
;
1329 ret_val
= hw
->phy
.ops
.write_reg_locked(hw
, HV_OEM_BITS
, oem_reg
);
1332 hw
->phy
.ops
.release(hw
);
1339 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
1340 * @hw: pointer to the HW structure
1342 static s32
e1000_set_mdio_slow_mode_hv(struct e1000_hw
*hw
)
1347 ret_val
= e1e_rphy(hw
, HV_KMRN_MODE_CTRL
, &data
);
1351 data
|= HV_KMRN_MDIO_SLOW
;
1353 ret_val
= e1e_wphy(hw
, HV_KMRN_MODE_CTRL
, data
);
1359 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1360 * done after every PHY reset.
1362 static s32
e1000_hv_phy_workarounds_ich8lan(struct e1000_hw
*hw
)
1367 if (hw
->mac
.type
!= e1000_pchlan
)
1370 /* Set MDIO slow mode before any other MDIO access */
1371 if (hw
->phy
.type
== e1000_phy_82577
) {
1372 ret_val
= e1000_set_mdio_slow_mode_hv(hw
);
1377 if (((hw
->phy
.type
== e1000_phy_82577
) &&
1378 ((hw
->phy
.revision
== 1) || (hw
->phy
.revision
== 2))) ||
1379 ((hw
->phy
.type
== e1000_phy_82578
) && (hw
->phy
.revision
== 1))) {
1380 /* Disable generation of early preamble */
1381 ret_val
= e1e_wphy(hw
, PHY_REG(769, 25), 0x4431);
1385 /* Preamble tuning for SSC */
1386 ret_val
= e1e_wphy(hw
, HV_KMRN_FIFO_CTRLSTA
, 0xA204);
1391 if (hw
->phy
.type
== e1000_phy_82578
) {
1393 * Return registers to default by doing a soft reset then
1394 * writing 0x3140 to the control register.
1396 if (hw
->phy
.revision
< 2) {
1397 e1000e_phy_sw_reset(hw
);
1398 ret_val
= e1e_wphy(hw
, PHY_CONTROL
, 0x3140);
1403 ret_val
= hw
->phy
.ops
.acquire(hw
);
1408 ret_val
= e1000e_write_phy_reg_mdic(hw
, IGP01E1000_PHY_PAGE_SELECT
, 0);
1409 hw
->phy
.ops
.release(hw
);
1414 * Configure the K1 Si workaround during phy reset assuming there is
1415 * link so that it disables K1 if link is in 1Gbps.
1417 ret_val
= e1000_k1_gig_workaround_hv(hw
, true);
1421 /* Workaround for link disconnects on a busy hub in half duplex */
1422 ret_val
= hw
->phy
.ops
.acquire(hw
);
1425 ret_val
= hw
->phy
.ops
.read_reg_locked(hw
, BM_PORT_GEN_CFG
, &phy_data
);
1428 ret_val
= hw
->phy
.ops
.write_reg_locked(hw
, BM_PORT_GEN_CFG
,
1431 hw
->phy
.ops
.release(hw
);
1437 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
1438 * @hw: pointer to the HW structure
1440 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw
*hw
)
1446 ret_val
= hw
->phy
.ops
.acquire(hw
);
1449 ret_val
= e1000_enable_phy_wakeup_reg_access_bm(hw
, &phy_reg
);
1453 /* Copy both RAL/H (rar_entry_count) and SHRAL/H (+4) to PHY */
1454 for (i
= 0; i
< (hw
->mac
.rar_entry_count
+ 4); i
++) {
1455 mac_reg
= er32(RAL(i
));
1456 hw
->phy
.ops
.write_reg_page(hw
, BM_RAR_L(i
),
1457 (u16
)(mac_reg
& 0xFFFF));
1458 hw
->phy
.ops
.write_reg_page(hw
, BM_RAR_M(i
),
1459 (u16
)((mac_reg
>> 16) & 0xFFFF));
1461 mac_reg
= er32(RAH(i
));
1462 hw
->phy
.ops
.write_reg_page(hw
, BM_RAR_H(i
),
1463 (u16
)(mac_reg
& 0xFFFF));
1464 hw
->phy
.ops
.write_reg_page(hw
, BM_RAR_CTRL(i
),
1465 (u16
)((mac_reg
& E1000_RAH_AV
)
1469 e1000_disable_phy_wakeup_reg_access_bm(hw
, &phy_reg
);
1472 hw
->phy
.ops
.release(hw
);
1476 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
1478 * @hw: pointer to the HW structure
1479 * @enable: flag to enable/disable workaround when enabling/disabling jumbos
1481 s32
e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw
*hw
, bool enable
)
1488 if (hw
->mac
.type
!= e1000_pch2lan
)
1491 /* disable Rx path while enabling/disabling workaround */
1492 e1e_rphy(hw
, PHY_REG(769, 20), &phy_reg
);
1493 ret_val
= e1e_wphy(hw
, PHY_REG(769, 20), phy_reg
| (1 << 14));
1499 * Write Rx addresses (rar_entry_count for RAL/H, +4 for
1500 * SHRAL/H) and initial CRC values to the MAC
1502 for (i
= 0; i
< (hw
->mac
.rar_entry_count
+ 4); i
++) {
1503 u8 mac_addr
[ETH_ALEN
] = {0};
1504 u32 addr_high
, addr_low
;
1506 addr_high
= er32(RAH(i
));
1507 if (!(addr_high
& E1000_RAH_AV
))
1509 addr_low
= er32(RAL(i
));
1510 mac_addr
[0] = (addr_low
& 0xFF);
1511 mac_addr
[1] = ((addr_low
>> 8) & 0xFF);
1512 mac_addr
[2] = ((addr_low
>> 16) & 0xFF);
1513 mac_addr
[3] = ((addr_low
>> 24) & 0xFF);
1514 mac_addr
[4] = (addr_high
& 0xFF);
1515 mac_addr
[5] = ((addr_high
>> 8) & 0xFF);
1517 ew32(PCH_RAICC(i
), ~ether_crc_le(ETH_ALEN
, mac_addr
));
1520 /* Write Rx addresses to the PHY */
1521 e1000_copy_rx_addrs_to_phy_ich8lan(hw
);
1523 /* Enable jumbo frame workaround in the MAC */
1524 mac_reg
= er32(FFLT_DBG
);
1525 mac_reg
&= ~(1 << 14);
1526 mac_reg
|= (7 << 15);
1527 ew32(FFLT_DBG
, mac_reg
);
1529 mac_reg
= er32(RCTL
);
1530 mac_reg
|= E1000_RCTL_SECRC
;
1531 ew32(RCTL
, mac_reg
);
1533 ret_val
= e1000e_read_kmrn_reg(hw
,
1534 E1000_KMRNCTRLSTA_CTRL_OFFSET
,
1538 ret_val
= e1000e_write_kmrn_reg(hw
,
1539 E1000_KMRNCTRLSTA_CTRL_OFFSET
,
1543 ret_val
= e1000e_read_kmrn_reg(hw
,
1544 E1000_KMRNCTRLSTA_HD_CTRL
,
1548 data
&= ~(0xF << 8);
1550 ret_val
= e1000e_write_kmrn_reg(hw
,
1551 E1000_KMRNCTRLSTA_HD_CTRL
,
1556 /* Enable jumbo frame workaround in the PHY */
1557 e1e_rphy(hw
, PHY_REG(769, 23), &data
);
1558 data
&= ~(0x7F << 5);
1559 data
|= (0x37 << 5);
1560 ret_val
= e1e_wphy(hw
, PHY_REG(769, 23), data
);
1563 e1e_rphy(hw
, PHY_REG(769, 16), &data
);
1565 ret_val
= e1e_wphy(hw
, PHY_REG(769, 16), data
);
1568 e1e_rphy(hw
, PHY_REG(776, 20), &data
);
1569 data
&= ~(0x3FF << 2);
1570 data
|= (0x1A << 2);
1571 ret_val
= e1e_wphy(hw
, PHY_REG(776, 20), data
);
1574 ret_val
= e1e_wphy(hw
, PHY_REG(776, 23), 0xF100);
1577 e1e_rphy(hw
, HV_PM_CTRL
, &data
);
1578 ret_val
= e1e_wphy(hw
, HV_PM_CTRL
, data
| (1 << 10));
1582 /* Write MAC register values back to h/w defaults */
1583 mac_reg
= er32(FFLT_DBG
);
1584 mac_reg
&= ~(0xF << 14);
1585 ew32(FFLT_DBG
, mac_reg
);
1587 mac_reg
= er32(RCTL
);
1588 mac_reg
&= ~E1000_RCTL_SECRC
;
1589 ew32(RCTL
, mac_reg
);
1591 ret_val
= e1000e_read_kmrn_reg(hw
,
1592 E1000_KMRNCTRLSTA_CTRL_OFFSET
,
1596 ret_val
= e1000e_write_kmrn_reg(hw
,
1597 E1000_KMRNCTRLSTA_CTRL_OFFSET
,
1601 ret_val
= e1000e_read_kmrn_reg(hw
,
1602 E1000_KMRNCTRLSTA_HD_CTRL
,
1606 data
&= ~(0xF << 8);
1608 ret_val
= e1000e_write_kmrn_reg(hw
,
1609 E1000_KMRNCTRLSTA_HD_CTRL
,
1614 /* Write PHY register values back to h/w defaults */
1615 e1e_rphy(hw
, PHY_REG(769, 23), &data
);
1616 data
&= ~(0x7F << 5);
1617 ret_val
= e1e_wphy(hw
, PHY_REG(769, 23), data
);
1620 e1e_rphy(hw
, PHY_REG(769, 16), &data
);
1622 ret_val
= e1e_wphy(hw
, PHY_REG(769, 16), data
);
1625 e1e_rphy(hw
, PHY_REG(776, 20), &data
);
1626 data
&= ~(0x3FF << 2);
1628 ret_val
= e1e_wphy(hw
, PHY_REG(776, 20), data
);
1631 ret_val
= e1e_wphy(hw
, PHY_REG(776, 23), 0x7E00);
1634 e1e_rphy(hw
, HV_PM_CTRL
, &data
);
1635 ret_val
= e1e_wphy(hw
, HV_PM_CTRL
, data
& ~(1 << 10));
1640 /* re-enable Rx path after enabling/disabling workaround */
1641 return e1e_wphy(hw
, PHY_REG(769, 20), phy_reg
& ~(1 << 14));
1645 * e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1646 * done after every PHY reset.
1648 static s32
e1000_lv_phy_workarounds_ich8lan(struct e1000_hw
*hw
)
1652 if (hw
->mac
.type
!= e1000_pch2lan
)
1655 /* Set MDIO slow mode before any other MDIO access */
1656 ret_val
= e1000_set_mdio_slow_mode_hv(hw
);
1658 ret_val
= hw
->phy
.ops
.acquire(hw
);
1661 ret_val
= hw
->phy
.ops
.write_reg_locked(hw
, I82579_EMI_ADDR
,
1662 I82579_MSE_THRESHOLD
);
1665 /* set MSE higher to enable link to stay up when noise is high */
1666 ret_val
= hw
->phy
.ops
.write_reg_locked(hw
, I82579_EMI_DATA
, 0x0034);
1669 ret_val
= hw
->phy
.ops
.write_reg_locked(hw
, I82579_EMI_ADDR
,
1670 I82579_MSE_LINK_DOWN
);
1673 /* drop link after 5 times MSE threshold was reached */
1674 ret_val
= hw
->phy
.ops
.write_reg_locked(hw
, I82579_EMI_DATA
, 0x0005);
1676 hw
->phy
.ops
.release(hw
);
1682 * e1000_k1_gig_workaround_lv - K1 Si workaround
1683 * @hw: pointer to the HW structure
1685 * Workaround to set the K1 beacon duration for 82579 parts
1687 static s32
e1000_k1_workaround_lv(struct e1000_hw
*hw
)
1694 if (hw
->mac
.type
!= e1000_pch2lan
)
1697 /* Set K1 beacon duration based on 1Gbps speed or otherwise */
1698 ret_val
= e1e_rphy(hw
, HV_M_STATUS
, &status_reg
);
1702 if ((status_reg
& (HV_M_STATUS_LINK_UP
| HV_M_STATUS_AUTONEG_COMPLETE
))
1703 == (HV_M_STATUS_LINK_UP
| HV_M_STATUS_AUTONEG_COMPLETE
)) {
1704 mac_reg
= er32(FEXTNVM4
);
1705 mac_reg
&= ~E1000_FEXTNVM4_BEACON_DURATION_MASK
;
1707 ret_val
= e1e_rphy(hw
, I82579_LPI_CTRL
, &phy_reg
);
1711 if (status_reg
& HV_M_STATUS_SPEED_1000
) {
1712 mac_reg
|= E1000_FEXTNVM4_BEACON_DURATION_8USEC
;
1713 phy_reg
&= ~I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT
;
1715 mac_reg
|= E1000_FEXTNVM4_BEACON_DURATION_16USEC
;
1716 phy_reg
|= I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT
;
1718 ew32(FEXTNVM4
, mac_reg
);
1719 ret_val
= e1e_wphy(hw
, I82579_LPI_CTRL
, phy_reg
);
1726 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
1727 * @hw: pointer to the HW structure
1728 * @gate: boolean set to true to gate, false to ungate
1730 * Gate/ungate the automatic PHY configuration via hardware; perform
1731 * the configuration via software instead.
1733 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw
*hw
, bool gate
)
1737 if (hw
->mac
.type
!= e1000_pch2lan
)
1740 extcnf_ctrl
= er32(EXTCNF_CTRL
);
1743 extcnf_ctrl
|= E1000_EXTCNF_CTRL_GATE_PHY_CFG
;
1745 extcnf_ctrl
&= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG
;
1747 ew32(EXTCNF_CTRL
, extcnf_ctrl
);
1751 * e1000_lan_init_done_ich8lan - Check for PHY config completion
1752 * @hw: pointer to the HW structure
1754 * Check the appropriate indication the MAC has finished configuring the
1755 * PHY after a software reset.
1757 static void e1000_lan_init_done_ich8lan(struct e1000_hw
*hw
)
1759 u32 data
, loop
= E1000_ICH8_LAN_INIT_TIMEOUT
;
1761 /* Wait for basic configuration completes before proceeding */
1763 data
= er32(STATUS
);
1764 data
&= E1000_STATUS_LAN_INIT_DONE
;
1766 } while ((!data
) && --loop
);
1769 * If basic configuration is incomplete before the above loop
1770 * count reaches 0, loading the configuration from NVM will
1771 * leave the PHY in a bad state possibly resulting in no link.
1774 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
1776 /* Clear the Init Done bit for the next init event */
1777 data
= er32(STATUS
);
1778 data
&= ~E1000_STATUS_LAN_INIT_DONE
;
1783 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
1784 * @hw: pointer to the HW structure
1786 static s32
e1000_post_phy_reset_ich8lan(struct e1000_hw
*hw
)
1791 if (hw
->phy
.ops
.check_reset_block(hw
))
1794 /* Allow time for h/w to get to quiescent state after reset */
1795 usleep_range(10000, 20000);
1797 /* Perform any necessary post-reset workarounds */
1798 switch (hw
->mac
.type
) {
1800 ret_val
= e1000_hv_phy_workarounds_ich8lan(hw
);
1805 ret_val
= e1000_lv_phy_workarounds_ich8lan(hw
);
1813 /* Clear the host wakeup bit after lcd reset */
1814 if (hw
->mac
.type
>= e1000_pchlan
) {
1815 e1e_rphy(hw
, BM_PORT_GEN_CFG
, ®
);
1816 reg
&= ~BM_WUC_HOST_WU_BIT
;
1817 e1e_wphy(hw
, BM_PORT_GEN_CFG
, reg
);
1820 /* Configure the LCD with the extended configuration region in NVM */
1821 ret_val
= e1000_sw_lcd_config_ich8lan(hw
);
1825 /* Configure the LCD with the OEM bits in NVM */
1826 ret_val
= e1000_oem_bits_config_ich8lan(hw
, true);
1828 if (hw
->mac
.type
== e1000_pch2lan
) {
1829 /* Ungate automatic PHY configuration on non-managed 82579 */
1830 if (!(er32(FWSM
) & E1000_ICH_FWSM_FW_VALID
)) {
1831 usleep_range(10000, 20000);
1832 e1000_gate_hw_phy_config_ich8lan(hw
, false);
1835 /* Set EEE LPI Update Timer to 200usec */
1836 ret_val
= hw
->phy
.ops
.acquire(hw
);
1839 ret_val
= hw
->phy
.ops
.write_reg_locked(hw
, I82579_EMI_ADDR
,
1840 I82579_LPI_UPDATE_TIMER
);
1842 ret_val
= hw
->phy
.ops
.write_reg_locked(hw
,
1845 hw
->phy
.ops
.release(hw
);
1852 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
1853 * @hw: pointer to the HW structure
1856 * This is a function pointer entry point called by drivers
1857 * or other shared routines.
1859 static s32
e1000_phy_hw_reset_ich8lan(struct e1000_hw
*hw
)
1863 /* Gate automatic PHY configuration by hardware on non-managed 82579 */
1864 if ((hw
->mac
.type
== e1000_pch2lan
) &&
1865 !(er32(FWSM
) & E1000_ICH_FWSM_FW_VALID
))
1866 e1000_gate_hw_phy_config_ich8lan(hw
, true);
1868 ret_val
= e1000e_phy_hw_reset_generic(hw
);
1872 return e1000_post_phy_reset_ich8lan(hw
);
1876 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
1877 * @hw: pointer to the HW structure
1878 * @active: true to enable LPLU, false to disable
1880 * Sets the LPLU state according to the active flag. For PCH, if OEM write
1881 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
1882 * the phy speed. This function will manually set the LPLU bit and restart
1883 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
1884 * since it configures the same bit.
1886 static s32
e1000_set_lplu_state_pchlan(struct e1000_hw
*hw
, bool active
)
1891 ret_val
= e1e_rphy(hw
, HV_OEM_BITS
, &oem_reg
);
1896 oem_reg
|= HV_OEM_BITS_LPLU
;
1898 oem_reg
&= ~HV_OEM_BITS_LPLU
;
1900 if (!hw
->phy
.ops
.check_reset_block(hw
))
1901 oem_reg
|= HV_OEM_BITS_RESTART_AN
;
1903 return e1e_wphy(hw
, HV_OEM_BITS
, oem_reg
);
1907 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
1908 * @hw: pointer to the HW structure
1909 * @active: true to enable LPLU, false to disable
1911 * Sets the LPLU D0 state according to the active flag. When
1912 * activating LPLU this function also disables smart speed
1913 * and vice versa. LPLU will not be activated unless the
1914 * device autonegotiation advertisement meets standards of
1915 * either 10 or 10/100 or 10/100/1000 at all duplexes.
1916 * This is a function pointer entry point only called by
1917 * PHY setup routines.
1919 static s32
e1000_set_d0_lplu_state_ich8lan(struct e1000_hw
*hw
, bool active
)
1921 struct e1000_phy_info
*phy
= &hw
->phy
;
1926 if (phy
->type
== e1000_phy_ife
)
1929 phy_ctrl
= er32(PHY_CTRL
);
1932 phy_ctrl
|= E1000_PHY_CTRL_D0A_LPLU
;
1933 ew32(PHY_CTRL
, phy_ctrl
);
1935 if (phy
->type
!= e1000_phy_igp_3
)
1939 * Call gig speed drop workaround on LPLU before accessing
1942 if (hw
->mac
.type
== e1000_ich8lan
)
1943 e1000e_gig_downshift_workaround_ich8lan(hw
);
1945 /* When LPLU is enabled, we should disable SmartSpeed */
1946 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, &data
);
1947 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
1948 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, data
);
1952 phy_ctrl
&= ~E1000_PHY_CTRL_D0A_LPLU
;
1953 ew32(PHY_CTRL
, phy_ctrl
);
1955 if (phy
->type
!= e1000_phy_igp_3
)
1959 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1960 * during Dx states where the power conservation is most
1961 * important. During driver activity we should enable
1962 * SmartSpeed, so performance is maintained.
1964 if (phy
->smart_speed
== e1000_smart_speed_on
) {
1965 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
1970 data
|= IGP01E1000_PSCFR_SMART_SPEED
;
1971 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
1975 } else if (phy
->smart_speed
== e1000_smart_speed_off
) {
1976 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
1981 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
1982 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
1993 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
1994 * @hw: pointer to the HW structure
1995 * @active: true to enable LPLU, false to disable
1997 * Sets the LPLU D3 state according to the active flag. When
1998 * activating LPLU this function also disables smart speed
1999 * and vice versa. LPLU will not be activated unless the
2000 * device autonegotiation advertisement meets standards of
2001 * either 10 or 10/100 or 10/100/1000 at all duplexes.
2002 * This is a function pointer entry point only called by
2003 * PHY setup routines.
2005 static s32
e1000_set_d3_lplu_state_ich8lan(struct e1000_hw
*hw
, bool active
)
2007 struct e1000_phy_info
*phy
= &hw
->phy
;
2012 phy_ctrl
= er32(PHY_CTRL
);
2015 phy_ctrl
&= ~E1000_PHY_CTRL_NOND0A_LPLU
;
2016 ew32(PHY_CTRL
, phy_ctrl
);
2018 if (phy
->type
!= e1000_phy_igp_3
)
2022 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
2023 * during Dx states where the power conservation is most
2024 * important. During driver activity we should enable
2025 * SmartSpeed, so performance is maintained.
2027 if (phy
->smart_speed
== e1000_smart_speed_on
) {
2028 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
2033 data
|= IGP01E1000_PSCFR_SMART_SPEED
;
2034 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
2038 } else if (phy
->smart_speed
== e1000_smart_speed_off
) {
2039 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
2044 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
2045 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
2050 } else if ((phy
->autoneg_advertised
== E1000_ALL_SPEED_DUPLEX
) ||
2051 (phy
->autoneg_advertised
== E1000_ALL_NOT_GIG
) ||
2052 (phy
->autoneg_advertised
== E1000_ALL_10_SPEED
)) {
2053 phy_ctrl
|= E1000_PHY_CTRL_NOND0A_LPLU
;
2054 ew32(PHY_CTRL
, phy_ctrl
);
2056 if (phy
->type
!= e1000_phy_igp_3
)
2060 * Call gig speed drop workaround on LPLU before accessing
2063 if (hw
->mac
.type
== e1000_ich8lan
)
2064 e1000e_gig_downshift_workaround_ich8lan(hw
);
2066 /* When LPLU is enabled, we should disable SmartSpeed */
2067 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, &data
);
2071 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
2072 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, data
);
2079 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
2080 * @hw: pointer to the HW structure
2081 * @bank: pointer to the variable that returns the active bank
2083 * Reads signature byte from the NVM using the flash access registers.
2084 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
2086 static s32
e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw
*hw
, u32
*bank
)
2089 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
2090 u32 bank1_offset
= nvm
->flash_bank_size
* sizeof(u16
);
2091 u32 act_offset
= E1000_ICH_NVM_SIG_WORD
* 2 + 1;
2095 switch (hw
->mac
.type
) {
2099 if ((eecd
& E1000_EECD_SEC1VAL_VALID_MASK
) ==
2100 E1000_EECD_SEC1VAL_VALID_MASK
) {
2101 if (eecd
& E1000_EECD_SEC1VAL
)
2108 e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n");
2111 /* set bank to 0 in case flash read fails */
2115 ret_val
= e1000_read_flash_byte_ich8lan(hw
, act_offset
,
2119 if ((sig_byte
& E1000_ICH_NVM_VALID_SIG_MASK
) ==
2120 E1000_ICH_NVM_SIG_VALUE
) {
2126 ret_val
= e1000_read_flash_byte_ich8lan(hw
, act_offset
+
2131 if ((sig_byte
& E1000_ICH_NVM_VALID_SIG_MASK
) ==
2132 E1000_ICH_NVM_SIG_VALUE
) {
2137 e_dbg("ERROR: No valid NVM bank present\n");
2138 return -E1000_ERR_NVM
;
2143 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
2144 * @hw: pointer to the HW structure
2145 * @offset: The offset (in bytes) of the word(s) to read.
2146 * @words: Size of data to read in words
2147 * @data: Pointer to the word(s) to read at offset.
2149 * Reads a word(s) from the NVM using the flash access registers.
2151 static s32
e1000_read_nvm_ich8lan(struct e1000_hw
*hw
, u16 offset
, u16 words
,
2154 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
2155 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
2161 if ((offset
>= nvm
->word_size
) || (words
> nvm
->word_size
- offset
) ||
2163 e_dbg("nvm parameter(s) out of bounds\n");
2164 ret_val
= -E1000_ERR_NVM
;
2168 nvm
->ops
.acquire(hw
);
2170 ret_val
= e1000_valid_nvm_bank_detect_ich8lan(hw
, &bank
);
2172 e_dbg("Could not detect valid bank, assuming bank 0\n");
2176 act_offset
= (bank
) ? nvm
->flash_bank_size
: 0;
2177 act_offset
+= offset
;
2180 for (i
= 0; i
< words
; i
++) {
2181 if (dev_spec
->shadow_ram
[offset
+i
].modified
) {
2182 data
[i
] = dev_spec
->shadow_ram
[offset
+i
].value
;
2184 ret_val
= e1000_read_flash_word_ich8lan(hw
,
2193 nvm
->ops
.release(hw
);
2197 e_dbg("NVM read error: %d\n", ret_val
);
2203 * e1000_flash_cycle_init_ich8lan - Initialize flash
2204 * @hw: pointer to the HW structure
2206 * This function does initial flash setup so that a new read/write/erase cycle
2209 static s32
e1000_flash_cycle_init_ich8lan(struct e1000_hw
*hw
)
2211 union ich8_hws_flash_status hsfsts
;
2212 s32 ret_val
= -E1000_ERR_NVM
;
2214 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
2216 /* Check if the flash descriptor is valid */
2217 if (hsfsts
.hsf_status
.fldesvalid
== 0) {
2218 e_dbg("Flash descriptor invalid. SW Sequencing must be used.\n");
2219 return -E1000_ERR_NVM
;
2222 /* Clear FCERR and DAEL in hw status by writing 1 */
2223 hsfsts
.hsf_status
.flcerr
= 1;
2224 hsfsts
.hsf_status
.dael
= 1;
2226 ew16flash(ICH_FLASH_HSFSTS
, hsfsts
.regval
);
2229 * Either we should have a hardware SPI cycle in progress
2230 * bit to check against, in order to start a new cycle or
2231 * FDONE bit should be changed in the hardware so that it
2232 * is 1 after hardware reset, which can then be used as an
2233 * indication whether a cycle is in progress or has been
2237 if (hsfsts
.hsf_status
.flcinprog
== 0) {
2239 * There is no cycle running at present,
2240 * so we can start a cycle.
2241 * Begin by setting Flash Cycle Done.
2243 hsfsts
.hsf_status
.flcdone
= 1;
2244 ew16flash(ICH_FLASH_HSFSTS
, hsfsts
.regval
);
2250 * Otherwise poll for sometime so the current
2251 * cycle has a chance to end before giving up.
2253 for (i
= 0; i
< ICH_FLASH_READ_COMMAND_TIMEOUT
; i
++) {
2254 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
2255 if (hsfsts
.hsf_status
.flcinprog
== 0) {
2263 * Successful in waiting for previous cycle to timeout,
2264 * now set the Flash Cycle Done.
2266 hsfsts
.hsf_status
.flcdone
= 1;
2267 ew16flash(ICH_FLASH_HSFSTS
, hsfsts
.regval
);
2269 e_dbg("Flash controller busy, cannot get access\n");
2277 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
2278 * @hw: pointer to the HW structure
2279 * @timeout: maximum time to wait for completion
2281 * This function starts a flash cycle and waits for its completion.
2283 static s32
e1000_flash_cycle_ich8lan(struct e1000_hw
*hw
, u32 timeout
)
2285 union ich8_hws_flash_ctrl hsflctl
;
2286 union ich8_hws_flash_status hsfsts
;
2289 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
2290 hsflctl
.regval
= er16flash(ICH_FLASH_HSFCTL
);
2291 hsflctl
.hsf_ctrl
.flcgo
= 1;
2292 ew16flash(ICH_FLASH_HSFCTL
, hsflctl
.regval
);
2294 /* wait till FDONE bit is set to 1 */
2296 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
2297 if (hsfsts
.hsf_status
.flcdone
== 1)
2300 } while (i
++ < timeout
);
2302 if (hsfsts
.hsf_status
.flcdone
== 1 && hsfsts
.hsf_status
.flcerr
== 0)
2305 return -E1000_ERR_NVM
;
2309 * e1000_read_flash_word_ich8lan - Read word from flash
2310 * @hw: pointer to the HW structure
2311 * @offset: offset to data location
2312 * @data: pointer to the location for storing the data
2314 * Reads the flash word at offset into data. Offset is converted
2315 * to bytes before read.
2317 static s32
e1000_read_flash_word_ich8lan(struct e1000_hw
*hw
, u32 offset
,
2320 /* Must convert offset into bytes. */
2323 return e1000_read_flash_data_ich8lan(hw
, offset
, 2, data
);
2327 * e1000_read_flash_byte_ich8lan - Read byte from flash
2328 * @hw: pointer to the HW structure
2329 * @offset: The offset of the byte to read.
2330 * @data: Pointer to a byte to store the value read.
2332 * Reads a single byte from the NVM using the flash access registers.
2334 static s32
e1000_read_flash_byte_ich8lan(struct e1000_hw
*hw
, u32 offset
,
2340 ret_val
= e1000_read_flash_data_ich8lan(hw
, offset
, 1, &word
);
2350 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
2351 * @hw: pointer to the HW structure
2352 * @offset: The offset (in bytes) of the byte or word to read.
2353 * @size: Size of data to read, 1=byte 2=word
2354 * @data: Pointer to the word to store the value read.
2356 * Reads a byte or word from the NVM using the flash access registers.
2358 static s32
e1000_read_flash_data_ich8lan(struct e1000_hw
*hw
, u32 offset
,
2361 union ich8_hws_flash_status hsfsts
;
2362 union ich8_hws_flash_ctrl hsflctl
;
2363 u32 flash_linear_addr
;
2365 s32 ret_val
= -E1000_ERR_NVM
;
2368 if (size
< 1 || size
> 2 || offset
> ICH_FLASH_LINEAR_ADDR_MASK
)
2369 return -E1000_ERR_NVM
;
2371 flash_linear_addr
= (ICH_FLASH_LINEAR_ADDR_MASK
& offset
) +
2372 hw
->nvm
.flash_base_addr
;
2377 ret_val
= e1000_flash_cycle_init_ich8lan(hw
);
2381 hsflctl
.regval
= er16flash(ICH_FLASH_HSFCTL
);
2382 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2383 hsflctl
.hsf_ctrl
.fldbcount
= size
- 1;
2384 hsflctl
.hsf_ctrl
.flcycle
= ICH_CYCLE_READ
;
2385 ew16flash(ICH_FLASH_HSFCTL
, hsflctl
.regval
);
2387 ew32flash(ICH_FLASH_FADDR
, flash_linear_addr
);
2389 ret_val
= e1000_flash_cycle_ich8lan(hw
,
2390 ICH_FLASH_READ_COMMAND_TIMEOUT
);
2393 * Check if FCERR is set to 1, if set to 1, clear it
2394 * and try the whole sequence a few more times, else
2395 * read in (shift in) the Flash Data0, the order is
2396 * least significant byte first msb to lsb
2399 flash_data
= er32flash(ICH_FLASH_FDATA0
);
2401 *data
= (u8
)(flash_data
& 0x000000FF);
2403 *data
= (u16
)(flash_data
& 0x0000FFFF);
2407 * If we've gotten here, then things are probably
2408 * completely hosed, but if the error condition is
2409 * detected, it won't hurt to give it another try...
2410 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
2412 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
2413 if (hsfsts
.hsf_status
.flcerr
== 1) {
2414 /* Repeat for some time before giving up. */
2416 } else if (hsfsts
.hsf_status
.flcdone
== 0) {
2417 e_dbg("Timeout error - flash cycle did not complete.\n");
2421 } while (count
++ < ICH_FLASH_CYCLE_REPEAT_COUNT
);
2427 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
2428 * @hw: pointer to the HW structure
2429 * @offset: The offset (in bytes) of the word(s) to write.
2430 * @words: Size of data to write in words
2431 * @data: Pointer to the word(s) to write at offset.
2433 * Writes a byte or word to the NVM using the flash access registers.
2435 static s32
e1000_write_nvm_ich8lan(struct e1000_hw
*hw
, u16 offset
, u16 words
,
2438 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
2439 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
2442 if ((offset
>= nvm
->word_size
) || (words
> nvm
->word_size
- offset
) ||
2444 e_dbg("nvm parameter(s) out of bounds\n");
2445 return -E1000_ERR_NVM
;
2448 nvm
->ops
.acquire(hw
);
2450 for (i
= 0; i
< words
; i
++) {
2451 dev_spec
->shadow_ram
[offset
+i
].modified
= true;
2452 dev_spec
->shadow_ram
[offset
+i
].value
= data
[i
];
2455 nvm
->ops
.release(hw
);
2461 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
2462 * @hw: pointer to the HW structure
2464 * The NVM checksum is updated by calling the generic update_nvm_checksum,
2465 * which writes the checksum to the shadow ram. The changes in the shadow
2466 * ram are then committed to the EEPROM by processing each bank at a time
2467 * checking for the modified bit and writing only the pending changes.
2468 * After a successful commit, the shadow ram is cleared and is ready for
2471 static s32
e1000_update_nvm_checksum_ich8lan(struct e1000_hw
*hw
)
2473 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
2474 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
2475 u32 i
, act_offset
, new_bank_offset
, old_bank_offset
, bank
;
2479 ret_val
= e1000e_update_nvm_checksum_generic(hw
);
2483 if (nvm
->type
!= e1000_nvm_flash_sw
)
2486 nvm
->ops
.acquire(hw
);
2489 * We're writing to the opposite bank so if we're on bank 1,
2490 * write to bank 0 etc. We also need to erase the segment that
2491 * is going to be written
2493 ret_val
= e1000_valid_nvm_bank_detect_ich8lan(hw
, &bank
);
2495 e_dbg("Could not detect valid bank, assuming bank 0\n");
2500 new_bank_offset
= nvm
->flash_bank_size
;
2501 old_bank_offset
= 0;
2502 ret_val
= e1000_erase_flash_bank_ich8lan(hw
, 1);
2506 old_bank_offset
= nvm
->flash_bank_size
;
2507 new_bank_offset
= 0;
2508 ret_val
= e1000_erase_flash_bank_ich8lan(hw
, 0);
2513 for (i
= 0; i
< E1000_ICH8_SHADOW_RAM_WORDS
; i
++) {
2515 * Determine whether to write the value stored
2516 * in the other NVM bank or a modified value stored
2519 if (dev_spec
->shadow_ram
[i
].modified
) {
2520 data
= dev_spec
->shadow_ram
[i
].value
;
2522 ret_val
= e1000_read_flash_word_ich8lan(hw
, i
+
2530 * If the word is 0x13, then make sure the signature bits
2531 * (15:14) are 11b until the commit has completed.
2532 * This will allow us to write 10b which indicates the
2533 * signature is valid. We want to do this after the write
2534 * has completed so that we don't mark the segment valid
2535 * while the write is still in progress
2537 if (i
== E1000_ICH_NVM_SIG_WORD
)
2538 data
|= E1000_ICH_NVM_SIG_MASK
;
2540 /* Convert offset to bytes. */
2541 act_offset
= (i
+ new_bank_offset
) << 1;
2544 /* Write the bytes to the new bank. */
2545 ret_val
= e1000_retry_write_flash_byte_ich8lan(hw
,
2552 ret_val
= e1000_retry_write_flash_byte_ich8lan(hw
,
2560 * Don't bother writing the segment valid bits if sector
2561 * programming failed.
2564 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
2565 e_dbg("Flash commit failed.\n");
2570 * Finally validate the new segment by setting bit 15:14
2571 * to 10b in word 0x13 , this can be done without an
2572 * erase as well since these bits are 11 to start with
2573 * and we need to change bit 14 to 0b
2575 act_offset
= new_bank_offset
+ E1000_ICH_NVM_SIG_WORD
;
2576 ret_val
= e1000_read_flash_word_ich8lan(hw
, act_offset
, &data
);
2581 ret_val
= e1000_retry_write_flash_byte_ich8lan(hw
,
2588 * And invalidate the previously valid segment by setting
2589 * its signature word (0x13) high_byte to 0b. This can be
2590 * done without an erase because flash erase sets all bits
2591 * to 1's. We can write 1's to 0's without an erase
2593 act_offset
= (old_bank_offset
+ E1000_ICH_NVM_SIG_WORD
) * 2 + 1;
2594 ret_val
= e1000_retry_write_flash_byte_ich8lan(hw
, act_offset
, 0);
2598 /* Great! Everything worked, we can now clear the cached entries. */
2599 for (i
= 0; i
< E1000_ICH8_SHADOW_RAM_WORDS
; i
++) {
2600 dev_spec
->shadow_ram
[i
].modified
= false;
2601 dev_spec
->shadow_ram
[i
].value
= 0xFFFF;
2605 nvm
->ops
.release(hw
);
2608 * Reload the EEPROM, or else modifications will not appear
2609 * until after the next adapter reset.
2612 e1000e_reload_nvm(hw
);
2613 usleep_range(10000, 20000);
2618 e_dbg("NVM update error: %d\n", ret_val
);
2624 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
2625 * @hw: pointer to the HW structure
2627 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
2628 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
2629 * calculated, in which case we need to calculate the checksum and set bit 6.
2631 static s32
e1000_validate_nvm_checksum_ich8lan(struct e1000_hw
*hw
)
2637 * Read 0x19 and check bit 6. If this bit is 0, the checksum
2638 * needs to be fixed. This bit is an indication that the NVM
2639 * was prepared by OEM software and did not calculate the
2640 * checksum...a likely scenario.
2642 ret_val
= e1000_read_nvm(hw
, 0x19, 1, &data
);
2646 if ((data
& 0x40) == 0) {
2648 ret_val
= e1000_write_nvm(hw
, 0x19, 1, &data
);
2651 ret_val
= e1000e_update_nvm_checksum(hw
);
2656 return e1000e_validate_nvm_checksum_generic(hw
);
2660 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
2661 * @hw: pointer to the HW structure
2663 * To prevent malicious write/erase of the NVM, set it to be read-only
2664 * so that the hardware ignores all write/erase cycles of the NVM via
2665 * the flash control registers. The shadow-ram copy of the NVM will
2666 * still be updated, however any updates to this copy will not stick
2667 * across driver reloads.
2669 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw
*hw
)
2671 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
2672 union ich8_flash_protected_range pr0
;
2673 union ich8_hws_flash_status hsfsts
;
2676 nvm
->ops
.acquire(hw
);
2678 gfpreg
= er32flash(ICH_FLASH_GFPREG
);
2680 /* Write-protect GbE Sector of NVM */
2681 pr0
.regval
= er32flash(ICH_FLASH_PR0
);
2682 pr0
.range
.base
= gfpreg
& FLASH_GFPREG_BASE_MASK
;
2683 pr0
.range
.limit
= ((gfpreg
>> 16) & FLASH_GFPREG_BASE_MASK
);
2684 pr0
.range
.wpe
= true;
2685 ew32flash(ICH_FLASH_PR0
, pr0
.regval
);
2688 * Lock down a subset of GbE Flash Control Registers, e.g.
2689 * PR0 to prevent the write-protection from being lifted.
2690 * Once FLOCKDN is set, the registers protected by it cannot
2691 * be written until FLOCKDN is cleared by a hardware reset.
2693 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
2694 hsfsts
.hsf_status
.flockdn
= true;
2695 ew32flash(ICH_FLASH_HSFSTS
, hsfsts
.regval
);
2697 nvm
->ops
.release(hw
);
2701 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
2702 * @hw: pointer to the HW structure
2703 * @offset: The offset (in bytes) of the byte/word to read.
2704 * @size: Size of data to read, 1=byte 2=word
2705 * @data: The byte(s) to write to the NVM.
2707 * Writes one/two bytes to the NVM using the flash access registers.
2709 static s32
e1000_write_flash_data_ich8lan(struct e1000_hw
*hw
, u32 offset
,
2712 union ich8_hws_flash_status hsfsts
;
2713 union ich8_hws_flash_ctrl hsflctl
;
2714 u32 flash_linear_addr
;
2719 if (size
< 1 || size
> 2 || data
> size
* 0xff ||
2720 offset
> ICH_FLASH_LINEAR_ADDR_MASK
)
2721 return -E1000_ERR_NVM
;
2723 flash_linear_addr
= (ICH_FLASH_LINEAR_ADDR_MASK
& offset
) +
2724 hw
->nvm
.flash_base_addr
;
2729 ret_val
= e1000_flash_cycle_init_ich8lan(hw
);
2733 hsflctl
.regval
= er16flash(ICH_FLASH_HSFCTL
);
2734 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2735 hsflctl
.hsf_ctrl
.fldbcount
= size
-1;
2736 hsflctl
.hsf_ctrl
.flcycle
= ICH_CYCLE_WRITE
;
2737 ew16flash(ICH_FLASH_HSFCTL
, hsflctl
.regval
);
2739 ew32flash(ICH_FLASH_FADDR
, flash_linear_addr
);
2742 flash_data
= (u32
)data
& 0x00FF;
2744 flash_data
= (u32
)data
;
2746 ew32flash(ICH_FLASH_FDATA0
, flash_data
);
2749 * check if FCERR is set to 1 , if set to 1, clear it
2750 * and try the whole sequence a few more times else done
2752 ret_val
= e1000_flash_cycle_ich8lan(hw
,
2753 ICH_FLASH_WRITE_COMMAND_TIMEOUT
);
2758 * If we're here, then things are most likely
2759 * completely hosed, but if the error condition
2760 * is detected, it won't hurt to give it another
2761 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
2763 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
2764 if (hsfsts
.hsf_status
.flcerr
== 1)
2765 /* Repeat for some time before giving up. */
2767 if (hsfsts
.hsf_status
.flcdone
== 0) {
2768 e_dbg("Timeout error - flash cycle did not complete.\n");
2771 } while (count
++ < ICH_FLASH_CYCLE_REPEAT_COUNT
);
2777 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
2778 * @hw: pointer to the HW structure
2779 * @offset: The index of the byte to read.
2780 * @data: The byte to write to the NVM.
2782 * Writes a single byte to the NVM using the flash access registers.
2784 static s32
e1000_write_flash_byte_ich8lan(struct e1000_hw
*hw
, u32 offset
,
2787 u16 word
= (u16
)data
;
2789 return e1000_write_flash_data_ich8lan(hw
, offset
, 1, word
);
2793 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
2794 * @hw: pointer to the HW structure
2795 * @offset: The offset of the byte to write.
2796 * @byte: The byte to write to the NVM.
2798 * Writes a single byte to the NVM using the flash access registers.
2799 * Goes through a retry algorithm before giving up.
2801 static s32
e1000_retry_write_flash_byte_ich8lan(struct e1000_hw
*hw
,
2802 u32 offset
, u8 byte
)
2805 u16 program_retries
;
2807 ret_val
= e1000_write_flash_byte_ich8lan(hw
, offset
, byte
);
2811 for (program_retries
= 0; program_retries
< 100; program_retries
++) {
2812 e_dbg("Retrying Byte %2.2X at offset %u\n", byte
, offset
);
2814 ret_val
= e1000_write_flash_byte_ich8lan(hw
, offset
, byte
);
2818 if (program_retries
== 100)
2819 return -E1000_ERR_NVM
;
2825 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
2826 * @hw: pointer to the HW structure
2827 * @bank: 0 for first bank, 1 for second bank, etc.
2829 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
2830 * bank N is 4096 * N + flash_reg_addr.
2832 static s32
e1000_erase_flash_bank_ich8lan(struct e1000_hw
*hw
, u32 bank
)
2834 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
2835 union ich8_hws_flash_status hsfsts
;
2836 union ich8_hws_flash_ctrl hsflctl
;
2837 u32 flash_linear_addr
;
2838 /* bank size is in 16bit words - adjust to bytes */
2839 u32 flash_bank_size
= nvm
->flash_bank_size
* 2;
2842 s32 j
, iteration
, sector_size
;
2844 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
2847 * Determine HW Sector size: Read BERASE bits of hw flash status
2849 * 00: The Hw sector is 256 bytes, hence we need to erase 16
2850 * consecutive sectors. The start index for the nth Hw sector
2851 * can be calculated as = bank * 4096 + n * 256
2852 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
2853 * The start index for the nth Hw sector can be calculated
2855 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
2856 * (ich9 only, otherwise error condition)
2857 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
2859 switch (hsfsts
.hsf_status
.berasesz
) {
2861 /* Hw sector size 256 */
2862 sector_size
= ICH_FLASH_SEG_SIZE_256
;
2863 iteration
= flash_bank_size
/ ICH_FLASH_SEG_SIZE_256
;
2866 sector_size
= ICH_FLASH_SEG_SIZE_4K
;
2870 sector_size
= ICH_FLASH_SEG_SIZE_8K
;
2874 sector_size
= ICH_FLASH_SEG_SIZE_64K
;
2878 return -E1000_ERR_NVM
;
2881 /* Start with the base address, then add the sector offset. */
2882 flash_linear_addr
= hw
->nvm
.flash_base_addr
;
2883 flash_linear_addr
+= (bank
) ? flash_bank_size
: 0;
2885 for (j
= 0; j
< iteration
; j
++) {
2888 ret_val
= e1000_flash_cycle_init_ich8lan(hw
);
2893 * Write a value 11 (block Erase) in Flash
2894 * Cycle field in hw flash control
2896 hsflctl
.regval
= er16flash(ICH_FLASH_HSFCTL
);
2897 hsflctl
.hsf_ctrl
.flcycle
= ICH_CYCLE_ERASE
;
2898 ew16flash(ICH_FLASH_HSFCTL
, hsflctl
.regval
);
2901 * Write the last 24 bits of an index within the
2902 * block into Flash Linear address field in Flash
2905 flash_linear_addr
+= (j
* sector_size
);
2906 ew32flash(ICH_FLASH_FADDR
, flash_linear_addr
);
2908 ret_val
= e1000_flash_cycle_ich8lan(hw
,
2909 ICH_FLASH_ERASE_COMMAND_TIMEOUT
);
2914 * Check if FCERR is set to 1. If 1,
2915 * clear it and try the whole sequence
2916 * a few more times else Done
2918 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
2919 if (hsfsts
.hsf_status
.flcerr
== 1)
2920 /* repeat for some time before giving up */
2922 else if (hsfsts
.hsf_status
.flcdone
== 0)
2924 } while (++count
< ICH_FLASH_CYCLE_REPEAT_COUNT
);
2931 * e1000_valid_led_default_ich8lan - Set the default LED settings
2932 * @hw: pointer to the HW structure
2933 * @data: Pointer to the LED settings
2935 * Reads the LED default settings from the NVM to data. If the NVM LED
2936 * settings is all 0's or F's, set the LED default to a valid LED default
2939 static s32
e1000_valid_led_default_ich8lan(struct e1000_hw
*hw
, u16
*data
)
2943 ret_val
= e1000_read_nvm(hw
, NVM_ID_LED_SETTINGS
, 1, data
);
2945 e_dbg("NVM Read Error\n");
2949 if (*data
== ID_LED_RESERVED_0000
||
2950 *data
== ID_LED_RESERVED_FFFF
)
2951 *data
= ID_LED_DEFAULT_ICH8LAN
;
2957 * e1000_id_led_init_pchlan - store LED configurations
2958 * @hw: pointer to the HW structure
2960 * PCH does not control LEDs via the LEDCTL register, rather it uses
2961 * the PHY LED configuration register.
2963 * PCH also does not have an "always on" or "always off" mode which
2964 * complicates the ID feature. Instead of using the "on" mode to indicate
2965 * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init_generic()),
2966 * use "link_up" mode. The LEDs will still ID on request if there is no
2967 * link based on logic in e1000_led_[on|off]_pchlan().
2969 static s32
e1000_id_led_init_pchlan(struct e1000_hw
*hw
)
2971 struct e1000_mac_info
*mac
= &hw
->mac
;
2973 const u32 ledctl_on
= E1000_LEDCTL_MODE_LINK_UP
;
2974 const u32 ledctl_off
= E1000_LEDCTL_MODE_LINK_UP
| E1000_PHY_LED0_IVRT
;
2975 u16 data
, i
, temp
, shift
;
2977 /* Get default ID LED modes */
2978 ret_val
= hw
->nvm
.ops
.valid_led_default(hw
, &data
);
2982 mac
->ledctl_default
= er32(LEDCTL
);
2983 mac
->ledctl_mode1
= mac
->ledctl_default
;
2984 mac
->ledctl_mode2
= mac
->ledctl_default
;
2986 for (i
= 0; i
< 4; i
++) {
2987 temp
= (data
>> (i
<< 2)) & E1000_LEDCTL_LED0_MODE_MASK
;
2990 case ID_LED_ON1_DEF2
:
2991 case ID_LED_ON1_ON2
:
2992 case ID_LED_ON1_OFF2
:
2993 mac
->ledctl_mode1
&= ~(E1000_PHY_LED0_MASK
<< shift
);
2994 mac
->ledctl_mode1
|= (ledctl_on
<< shift
);
2996 case ID_LED_OFF1_DEF2
:
2997 case ID_LED_OFF1_ON2
:
2998 case ID_LED_OFF1_OFF2
:
2999 mac
->ledctl_mode1
&= ~(E1000_PHY_LED0_MASK
<< shift
);
3000 mac
->ledctl_mode1
|= (ledctl_off
<< shift
);
3007 case ID_LED_DEF1_ON2
:
3008 case ID_LED_ON1_ON2
:
3009 case ID_LED_OFF1_ON2
:
3010 mac
->ledctl_mode2
&= ~(E1000_PHY_LED0_MASK
<< shift
);
3011 mac
->ledctl_mode2
|= (ledctl_on
<< shift
);
3013 case ID_LED_DEF1_OFF2
:
3014 case ID_LED_ON1_OFF2
:
3015 case ID_LED_OFF1_OFF2
:
3016 mac
->ledctl_mode2
&= ~(E1000_PHY_LED0_MASK
<< shift
);
3017 mac
->ledctl_mode2
|= (ledctl_off
<< shift
);
3029 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
3030 * @hw: pointer to the HW structure
3032 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
3033 * register, so the the bus width is hard coded.
3035 static s32
e1000_get_bus_info_ich8lan(struct e1000_hw
*hw
)
3037 struct e1000_bus_info
*bus
= &hw
->bus
;
3040 ret_val
= e1000e_get_bus_info_pcie(hw
);
3043 * ICH devices are "PCI Express"-ish. They have
3044 * a configuration space, but do not contain
3045 * PCI Express Capability registers, so bus width
3046 * must be hardcoded.
3048 if (bus
->width
== e1000_bus_width_unknown
)
3049 bus
->width
= e1000_bus_width_pcie_x1
;
3055 * e1000_reset_hw_ich8lan - Reset the hardware
3056 * @hw: pointer to the HW structure
3058 * Does a full reset of the hardware which includes a reset of the PHY and
3061 static s32
e1000_reset_hw_ich8lan(struct e1000_hw
*hw
)
3063 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
3069 * Prevent the PCI-E bus from sticking if there is no TLP connection
3070 * on the last TLP read/write transaction when MAC is reset.
3072 ret_val
= e1000e_disable_pcie_master(hw
);
3074 e_dbg("PCI-E Master disable polling has failed.\n");
3076 e_dbg("Masking off all interrupts\n");
3077 ew32(IMC
, 0xffffffff);
3080 * Disable the Transmit and Receive units. Then delay to allow
3081 * any pending transactions to complete before we hit the MAC
3082 * with the global reset.
3085 ew32(TCTL
, E1000_TCTL_PSP
);
3088 usleep_range(10000, 20000);
3090 /* Workaround for ICH8 bit corruption issue in FIFO memory */
3091 if (hw
->mac
.type
== e1000_ich8lan
) {
3092 /* Set Tx and Rx buffer allocation to 8k apiece. */
3093 ew32(PBA
, E1000_PBA_8K
);
3094 /* Set Packet Buffer Size to 16k. */
3095 ew32(PBS
, E1000_PBS_16K
);
3098 if (hw
->mac
.type
== e1000_pchlan
) {
3099 /* Save the NVM K1 bit setting*/
3100 ret_val
= e1000_read_nvm(hw
, E1000_NVM_K1_CONFIG
, 1, ®
);
3104 if (reg
& E1000_NVM_K1_ENABLE
)
3105 dev_spec
->nvm_k1_enabled
= true;
3107 dev_spec
->nvm_k1_enabled
= false;
3112 if (!hw
->phy
.ops
.check_reset_block(hw
)) {
3114 * Full-chip reset requires MAC and PHY reset at the same
3115 * time to make sure the interface between MAC and the
3116 * external PHY is reset.
3118 ctrl
|= E1000_CTRL_PHY_RST
;
3121 * Gate automatic PHY configuration by hardware on
3124 if ((hw
->mac
.type
== e1000_pch2lan
) &&
3125 !(er32(FWSM
) & E1000_ICH_FWSM_FW_VALID
))
3126 e1000_gate_hw_phy_config_ich8lan(hw
, true);
3128 ret_val
= e1000_acquire_swflag_ich8lan(hw
);
3129 e_dbg("Issuing a global reset to ich8lan\n");
3130 ew32(CTRL
, (ctrl
| E1000_CTRL_RST
));
3131 /* cannot issue a flush here because it hangs the hardware */
3135 clear_bit(__E1000_ACCESS_SHARED_RESOURCE
, &hw
->adapter
->state
);
3137 if (ctrl
& E1000_CTRL_PHY_RST
) {
3138 ret_val
= hw
->phy
.ops
.get_cfg_done(hw
);
3142 ret_val
= e1000_post_phy_reset_ich8lan(hw
);
3148 * For PCH, this write will make sure that any noise
3149 * will be detected as a CRC error and be dropped rather than show up
3150 * as a bad packet to the DMA engine.
3152 if (hw
->mac
.type
== e1000_pchlan
)
3153 ew32(CRC_OFFSET
, 0x65656565);
3155 ew32(IMC
, 0xffffffff);
3158 kab
= er32(KABGTXD
);
3159 kab
|= E1000_KABGTXD_BGSQLBIAS
;
3166 * e1000_init_hw_ich8lan - Initialize the hardware
3167 * @hw: pointer to the HW structure
3169 * Prepares the hardware for transmit and receive by doing the following:
3170 * - initialize hardware bits
3171 * - initialize LED identification
3172 * - setup receive address registers
3173 * - setup flow control
3174 * - setup transmit descriptors
3175 * - clear statistics
3177 static s32
e1000_init_hw_ich8lan(struct e1000_hw
*hw
)
3179 struct e1000_mac_info
*mac
= &hw
->mac
;
3180 u32 ctrl_ext
, txdctl
, snoop
;
3184 e1000_initialize_hw_bits_ich8lan(hw
);
3186 /* Initialize identification LED */
3187 ret_val
= mac
->ops
.id_led_init(hw
);
3189 e_dbg("Error initializing identification LED\n");
3190 /* This is not fatal and we should not stop init due to this */
3192 /* Setup the receive address. */
3193 e1000e_init_rx_addrs(hw
, mac
->rar_entry_count
);
3195 /* Zero out the Multicast HASH table */
3196 e_dbg("Zeroing the MTA\n");
3197 for (i
= 0; i
< mac
->mta_reg_count
; i
++)
3198 E1000_WRITE_REG_ARRAY(hw
, E1000_MTA
, i
, 0);
3201 * The 82578 Rx buffer will stall if wakeup is enabled in host and
3202 * the ME. Disable wakeup by clearing the host wakeup bit.
3203 * Reset the phy after disabling host wakeup to reset the Rx buffer.
3205 if (hw
->phy
.type
== e1000_phy_82578
) {
3206 e1e_rphy(hw
, BM_PORT_GEN_CFG
, &i
);
3207 i
&= ~BM_WUC_HOST_WU_BIT
;
3208 e1e_wphy(hw
, BM_PORT_GEN_CFG
, i
);
3209 ret_val
= e1000_phy_hw_reset_ich8lan(hw
);
3214 /* Setup link and flow control */
3215 ret_val
= mac
->ops
.setup_link(hw
);
3217 /* Set the transmit descriptor write-back policy for both queues */
3218 txdctl
= er32(TXDCTL(0));
3219 txdctl
= (txdctl
& ~E1000_TXDCTL_WTHRESH
) |
3220 E1000_TXDCTL_FULL_TX_DESC_WB
;
3221 txdctl
= (txdctl
& ~E1000_TXDCTL_PTHRESH
) |
3222 E1000_TXDCTL_MAX_TX_DESC_PREFETCH
;
3223 ew32(TXDCTL(0), txdctl
);
3224 txdctl
= er32(TXDCTL(1));
3225 txdctl
= (txdctl
& ~E1000_TXDCTL_WTHRESH
) |
3226 E1000_TXDCTL_FULL_TX_DESC_WB
;
3227 txdctl
= (txdctl
& ~E1000_TXDCTL_PTHRESH
) |
3228 E1000_TXDCTL_MAX_TX_DESC_PREFETCH
;
3229 ew32(TXDCTL(1), txdctl
);
3232 * ICH8 has opposite polarity of no_snoop bits.
3233 * By default, we should use snoop behavior.
3235 if (mac
->type
== e1000_ich8lan
)
3236 snoop
= PCIE_ICH8_SNOOP_ALL
;
3238 snoop
= (u32
) ~(PCIE_NO_SNOOP_ALL
);
3239 e1000e_set_pcie_no_snoop(hw
, snoop
);
3241 ctrl_ext
= er32(CTRL_EXT
);
3242 ctrl_ext
|= E1000_CTRL_EXT_RO_DIS
;
3243 ew32(CTRL_EXT
, ctrl_ext
);
3246 * Clear all of the statistics registers (clear on read). It is
3247 * important that we do this after we have tried to establish link
3248 * because the symbol error count will increment wildly if there
3251 e1000_clear_hw_cntrs_ich8lan(hw
);
3256 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
3257 * @hw: pointer to the HW structure
3259 * Sets/Clears required hardware bits necessary for correctly setting up the
3260 * hardware for transmit and receive.
3262 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw
*hw
)
3266 /* Extended Device Control */
3267 reg
= er32(CTRL_EXT
);
3269 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
3270 if (hw
->mac
.type
>= e1000_pchlan
)
3271 reg
|= E1000_CTRL_EXT_PHYPDEN
;
3272 ew32(CTRL_EXT
, reg
);
3274 /* Transmit Descriptor Control 0 */
3275 reg
= er32(TXDCTL(0));
3277 ew32(TXDCTL(0), reg
);
3279 /* Transmit Descriptor Control 1 */
3280 reg
= er32(TXDCTL(1));
3282 ew32(TXDCTL(1), reg
);
3284 /* Transmit Arbitration Control 0 */
3285 reg
= er32(TARC(0));
3286 if (hw
->mac
.type
== e1000_ich8lan
)
3287 reg
|= (1 << 28) | (1 << 29);
3288 reg
|= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
3291 /* Transmit Arbitration Control 1 */
3292 reg
= er32(TARC(1));
3293 if (er32(TCTL
) & E1000_TCTL_MULR
)
3297 reg
|= (1 << 24) | (1 << 26) | (1 << 30);
3301 if (hw
->mac
.type
== e1000_ich8lan
) {
3308 * work-around descriptor data corruption issue during nfs v2 udp
3309 * traffic, just disable the nfs filtering capability
3312 reg
|= (E1000_RFCTL_NFSW_DIS
| E1000_RFCTL_NFSR_DIS
);
3317 * e1000_setup_link_ich8lan - Setup flow control and link settings
3318 * @hw: pointer to the HW structure
3320 * Determines which flow control settings to use, then configures flow
3321 * control. Calls the appropriate media-specific link configuration
3322 * function. Assuming the adapter has a valid link partner, a valid link
3323 * should be established. Assumes the hardware has previously been reset
3324 * and the transmitter and receiver are not enabled.
3326 static s32
e1000_setup_link_ich8lan(struct e1000_hw
*hw
)
3330 if (hw
->phy
.ops
.check_reset_block(hw
))
3334 * ICH parts do not have a word in the NVM to determine
3335 * the default flow control setting, so we explicitly
3338 if (hw
->fc
.requested_mode
== e1000_fc_default
) {
3339 /* Workaround h/w hang when Tx flow control enabled */
3340 if (hw
->mac
.type
== e1000_pchlan
)
3341 hw
->fc
.requested_mode
= e1000_fc_rx_pause
;
3343 hw
->fc
.requested_mode
= e1000_fc_full
;
3347 * Save off the requested flow control mode for use later. Depending
3348 * on the link partner's capabilities, we may or may not use this mode.
3350 hw
->fc
.current_mode
= hw
->fc
.requested_mode
;
3352 e_dbg("After fix-ups FlowControl is now = %x\n",
3353 hw
->fc
.current_mode
);
3355 /* Continue to configure the copper link. */
3356 ret_val
= hw
->mac
.ops
.setup_physical_interface(hw
);
3360 ew32(FCTTV
, hw
->fc
.pause_time
);
3361 if ((hw
->phy
.type
== e1000_phy_82578
) ||
3362 (hw
->phy
.type
== e1000_phy_82579
) ||
3363 (hw
->phy
.type
== e1000_phy_82577
)) {
3364 ew32(FCRTV_PCH
, hw
->fc
.refresh_time
);
3366 ret_val
= e1e_wphy(hw
, PHY_REG(BM_PORT_CTRL_PAGE
, 27),
3372 return e1000e_set_fc_watermarks(hw
);
3376 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
3377 * @hw: pointer to the HW structure
3379 * Configures the kumeran interface to the PHY to wait the appropriate time
3380 * when polling the PHY, then call the generic setup_copper_link to finish
3381 * configuring the copper link.
3383 static s32
e1000_setup_copper_link_ich8lan(struct e1000_hw
*hw
)
3390 ctrl
|= E1000_CTRL_SLU
;
3391 ctrl
&= ~(E1000_CTRL_FRCSPD
| E1000_CTRL_FRCDPX
);
3395 * Set the mac to wait the maximum time between each iteration
3396 * and increase the max iterations when polling the phy;
3397 * this fixes erroneous timeouts at 10Mbps.
3399 ret_val
= e1000e_write_kmrn_reg(hw
, E1000_KMRNCTRLSTA_TIMEOUTS
, 0xFFFF);
3402 ret_val
= e1000e_read_kmrn_reg(hw
, E1000_KMRNCTRLSTA_INBAND_PARAM
,
3407 ret_val
= e1000e_write_kmrn_reg(hw
, E1000_KMRNCTRLSTA_INBAND_PARAM
,
3412 switch (hw
->phy
.type
) {
3413 case e1000_phy_igp_3
:
3414 ret_val
= e1000e_copper_link_setup_igp(hw
);
3419 case e1000_phy_82578
:
3420 ret_val
= e1000e_copper_link_setup_m88(hw
);
3424 case e1000_phy_82577
:
3425 case e1000_phy_82579
:
3426 ret_val
= e1000_copper_link_setup_82577(hw
);
3431 ret_val
= e1e_rphy(hw
, IFE_PHY_MDIX_CONTROL
, ®_data
);
3435 reg_data
&= ~IFE_PMC_AUTO_MDIX
;
3437 switch (hw
->phy
.mdix
) {
3439 reg_data
&= ~IFE_PMC_FORCE_MDIX
;
3442 reg_data
|= IFE_PMC_FORCE_MDIX
;
3446 reg_data
|= IFE_PMC_AUTO_MDIX
;
3449 ret_val
= e1e_wphy(hw
, IFE_PHY_MDIX_CONTROL
, reg_data
);
3457 return e1000e_setup_copper_link(hw
);
3461 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
3462 * @hw: pointer to the HW structure
3463 * @speed: pointer to store current link speed
3464 * @duplex: pointer to store the current link duplex
3466 * Calls the generic get_speed_and_duplex to retrieve the current link
3467 * information and then calls the Kumeran lock loss workaround for links at
3470 static s32
e1000_get_link_up_info_ich8lan(struct e1000_hw
*hw
, u16
*speed
,
3475 ret_val
= e1000e_get_speed_and_duplex_copper(hw
, speed
, duplex
);
3479 if ((hw
->mac
.type
== e1000_ich8lan
) &&
3480 (hw
->phy
.type
== e1000_phy_igp_3
) &&
3481 (*speed
== SPEED_1000
)) {
3482 ret_val
= e1000_kmrn_lock_loss_workaround_ich8lan(hw
);
3489 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
3490 * @hw: pointer to the HW structure
3492 * Work-around for 82566 Kumeran PCS lock loss:
3493 * On link status change (i.e. PCI reset, speed change) and link is up and
3495 * 0) if workaround is optionally disabled do nothing
3496 * 1) wait 1ms for Kumeran link to come up
3497 * 2) check Kumeran Diagnostic register PCS lock loss bit
3498 * 3) if not set the link is locked (all is good), otherwise...
3500 * 5) repeat up to 10 times
3501 * Note: this is only called for IGP3 copper when speed is 1gb.
3503 static s32
e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw
*hw
)
3505 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
3511 if (!dev_spec
->kmrn_lock_loss_workaround_enabled
)
3515 * Make sure link is up before proceeding. If not just return.
3516 * Attempting this while link is negotiating fouled up link
3519 ret_val
= e1000e_phy_has_link_generic(hw
, 1, 0, &link
);
3523 for (i
= 0; i
< 10; i
++) {
3524 /* read once to clear */
3525 ret_val
= e1e_rphy(hw
, IGP3_KMRN_DIAG
, &data
);
3528 /* and again to get new status */
3529 ret_val
= e1e_rphy(hw
, IGP3_KMRN_DIAG
, &data
);
3533 /* check for PCS lock */
3534 if (!(data
& IGP3_KMRN_DIAG_PCS_LOCK_LOSS
))
3537 /* Issue PHY reset */
3538 e1000_phy_hw_reset(hw
);
3541 /* Disable GigE link negotiation */
3542 phy_ctrl
= er32(PHY_CTRL
);
3543 phy_ctrl
|= (E1000_PHY_CTRL_GBE_DISABLE
|
3544 E1000_PHY_CTRL_NOND0A_GBE_DISABLE
);
3545 ew32(PHY_CTRL
, phy_ctrl
);
3548 * Call gig speed drop workaround on Gig disable before accessing
3551 e1000e_gig_downshift_workaround_ich8lan(hw
);
3553 /* unable to acquire PCS lock */
3554 return -E1000_ERR_PHY
;
3558 * e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
3559 * @hw: pointer to the HW structure
3560 * @state: boolean value used to set the current Kumeran workaround state
3562 * If ICH8, set the current Kumeran workaround state (enabled - true
3563 * /disabled - false).
3565 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw
*hw
,
3568 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
3570 if (hw
->mac
.type
!= e1000_ich8lan
) {
3571 e_dbg("Workaround applies to ICH8 only.\n");
3575 dev_spec
->kmrn_lock_loss_workaround_enabled
= state
;
3579 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
3580 * @hw: pointer to the HW structure
3582 * Workaround for 82566 power-down on D3 entry:
3583 * 1) disable gigabit link
3584 * 2) write VR power-down enable
3586 * Continue if successful, else issue LCD reset and repeat
3588 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw
*hw
)
3594 if (hw
->phy
.type
!= e1000_phy_igp_3
)
3597 /* Try the workaround twice (if needed) */
3600 reg
= er32(PHY_CTRL
);
3601 reg
|= (E1000_PHY_CTRL_GBE_DISABLE
|
3602 E1000_PHY_CTRL_NOND0A_GBE_DISABLE
);
3603 ew32(PHY_CTRL
, reg
);
3606 * Call gig speed drop workaround on Gig disable before
3607 * accessing any PHY registers
3609 if (hw
->mac
.type
== e1000_ich8lan
)
3610 e1000e_gig_downshift_workaround_ich8lan(hw
);
3612 /* Write VR power-down enable */
3613 e1e_rphy(hw
, IGP3_VR_CTRL
, &data
);
3614 data
&= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK
;
3615 e1e_wphy(hw
, IGP3_VR_CTRL
, data
| IGP3_VR_CTRL_MODE_SHUTDOWN
);
3617 /* Read it back and test */
3618 e1e_rphy(hw
, IGP3_VR_CTRL
, &data
);
3619 data
&= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK
;
3620 if ((data
== IGP3_VR_CTRL_MODE_SHUTDOWN
) || retry
)
3623 /* Issue PHY reset and repeat at most one more time */
3625 ew32(CTRL
, reg
| E1000_CTRL_PHY_RST
);
3631 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
3632 * @hw: pointer to the HW structure
3634 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
3635 * LPLU, Gig disable, MDIC PHY reset):
3636 * 1) Set Kumeran Near-end loopback
3637 * 2) Clear Kumeran Near-end loopback
3638 * Should only be called for ICH8[m] devices with any 1G Phy.
3640 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw
*hw
)
3645 if ((hw
->mac
.type
!= e1000_ich8lan
) || (hw
->phy
.type
== e1000_phy_ife
))
3648 ret_val
= e1000e_read_kmrn_reg(hw
, E1000_KMRNCTRLSTA_DIAG_OFFSET
,
3652 reg_data
|= E1000_KMRNCTRLSTA_DIAG_NELPBK
;
3653 ret_val
= e1000e_write_kmrn_reg(hw
, E1000_KMRNCTRLSTA_DIAG_OFFSET
,
3657 reg_data
&= ~E1000_KMRNCTRLSTA_DIAG_NELPBK
;
3658 ret_val
= e1000e_write_kmrn_reg(hw
, E1000_KMRNCTRLSTA_DIAG_OFFSET
,
3663 * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
3664 * @hw: pointer to the HW structure
3666 * During S0 to Sx transition, it is possible the link remains at gig
3667 * instead of negotiating to a lower speed. Before going to Sx, set
3668 * 'Gig Disable' to force link speed negotiation to a lower speed based on
3669 * the LPLU setting in the NVM or custom setting. For PCH and newer parts,
3670 * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
3671 * needs to be written.
3673 void e1000_suspend_workarounds_ich8lan(struct e1000_hw
*hw
)
3678 phy_ctrl
= er32(PHY_CTRL
);
3679 phy_ctrl
|= E1000_PHY_CTRL_GBE_DISABLE
;
3680 ew32(PHY_CTRL
, phy_ctrl
);
3682 if (hw
->mac
.type
== e1000_ich8lan
)
3683 e1000e_gig_downshift_workaround_ich8lan(hw
);
3685 if (hw
->mac
.type
>= e1000_pchlan
) {
3686 e1000_oem_bits_config_ich8lan(hw
, false);
3687 e1000_phy_hw_reset_ich8lan(hw
);
3688 ret_val
= hw
->phy
.ops
.acquire(hw
);
3691 e1000_write_smbus_addr(hw
);
3692 hw
->phy
.ops
.release(hw
);
3697 * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
3698 * @hw: pointer to the HW structure
3700 * During Sx to S0 transitions on non-managed devices or managed devices
3701 * on which PHY resets are not blocked, if the PHY registers cannot be
3702 * accessed properly by the s/w toggle the LANPHYPC value to power cycle
3705 void e1000_resume_workarounds_pchlan(struct e1000_hw
*hw
)
3707 u16 phy_id1
, phy_id2
;
3710 if ((hw
->mac
.type
!= e1000_pch2lan
) ||
3711 hw
->phy
.ops
.check_reset_block(hw
))
3714 ret_val
= hw
->phy
.ops
.acquire(hw
);
3716 e_dbg("Failed to acquire PHY semaphore in resume\n");
3720 /* Test access to the PHY registers by reading the ID regs */
3721 ret_val
= hw
->phy
.ops
.read_reg_locked(hw
, PHY_ID1
, &phy_id1
);
3724 ret_val
= hw
->phy
.ops
.read_reg_locked(hw
, PHY_ID2
, &phy_id2
);
3728 if (hw
->phy
.id
== ((u32
)(phy_id1
<< 16) |
3729 (u32
)(phy_id2
& PHY_REVISION_MASK
)))
3732 e1000_toggle_lanphypc_value_ich8lan(hw
);
3734 hw
->phy
.ops
.release(hw
);
3736 e1000_phy_hw_reset(hw
);
3741 hw
->phy
.ops
.release(hw
);
3745 * e1000_cleanup_led_ich8lan - Restore the default LED operation
3746 * @hw: pointer to the HW structure
3748 * Return the LED back to the default configuration.
3750 static s32
e1000_cleanup_led_ich8lan(struct e1000_hw
*hw
)
3752 if (hw
->phy
.type
== e1000_phy_ife
)
3753 return e1e_wphy(hw
, IFE_PHY_SPECIAL_CONTROL_LED
, 0);
3755 ew32(LEDCTL
, hw
->mac
.ledctl_default
);
3760 * e1000_led_on_ich8lan - Turn LEDs on
3761 * @hw: pointer to the HW structure
3765 static s32
e1000_led_on_ich8lan(struct e1000_hw
*hw
)
3767 if (hw
->phy
.type
== e1000_phy_ife
)
3768 return e1e_wphy(hw
, IFE_PHY_SPECIAL_CONTROL_LED
,
3769 (IFE_PSCL_PROBE_MODE
| IFE_PSCL_PROBE_LEDS_ON
));
3771 ew32(LEDCTL
, hw
->mac
.ledctl_mode2
);
3776 * e1000_led_off_ich8lan - Turn LEDs off
3777 * @hw: pointer to the HW structure
3779 * Turn off the LEDs.
3781 static s32
e1000_led_off_ich8lan(struct e1000_hw
*hw
)
3783 if (hw
->phy
.type
== e1000_phy_ife
)
3784 return e1e_wphy(hw
, IFE_PHY_SPECIAL_CONTROL_LED
,
3785 (IFE_PSCL_PROBE_MODE
|
3786 IFE_PSCL_PROBE_LEDS_OFF
));
3788 ew32(LEDCTL
, hw
->mac
.ledctl_mode1
);
3793 * e1000_setup_led_pchlan - Configures SW controllable LED
3794 * @hw: pointer to the HW structure
3796 * This prepares the SW controllable LED for use.
3798 static s32
e1000_setup_led_pchlan(struct e1000_hw
*hw
)
3800 return e1e_wphy(hw
, HV_LED_CONFIG
, (u16
)hw
->mac
.ledctl_mode1
);
3804 * e1000_cleanup_led_pchlan - Restore the default LED operation
3805 * @hw: pointer to the HW structure
3807 * Return the LED back to the default configuration.
3809 static s32
e1000_cleanup_led_pchlan(struct e1000_hw
*hw
)
3811 return e1e_wphy(hw
, HV_LED_CONFIG
, (u16
)hw
->mac
.ledctl_default
);
3815 * e1000_led_on_pchlan - Turn LEDs on
3816 * @hw: pointer to the HW structure
3820 static s32
e1000_led_on_pchlan(struct e1000_hw
*hw
)
3822 u16 data
= (u16
)hw
->mac
.ledctl_mode2
;
3826 * If no link, then turn LED on by setting the invert bit
3827 * for each LED that's mode is "link_up" in ledctl_mode2.
3829 if (!(er32(STATUS
) & E1000_STATUS_LU
)) {
3830 for (i
= 0; i
< 3; i
++) {
3831 led
= (data
>> (i
* 5)) & E1000_PHY_LED0_MASK
;
3832 if ((led
& E1000_PHY_LED0_MODE_MASK
) !=
3833 E1000_LEDCTL_MODE_LINK_UP
)
3835 if (led
& E1000_PHY_LED0_IVRT
)
3836 data
&= ~(E1000_PHY_LED0_IVRT
<< (i
* 5));
3838 data
|= (E1000_PHY_LED0_IVRT
<< (i
* 5));
3842 return e1e_wphy(hw
, HV_LED_CONFIG
, data
);
3846 * e1000_led_off_pchlan - Turn LEDs off
3847 * @hw: pointer to the HW structure
3849 * Turn off the LEDs.
3851 static s32
e1000_led_off_pchlan(struct e1000_hw
*hw
)
3853 u16 data
= (u16
)hw
->mac
.ledctl_mode1
;
3857 * If no link, then turn LED off by clearing the invert bit
3858 * for each LED that's mode is "link_up" in ledctl_mode1.
3860 if (!(er32(STATUS
) & E1000_STATUS_LU
)) {
3861 for (i
= 0; i
< 3; i
++) {
3862 led
= (data
>> (i
* 5)) & E1000_PHY_LED0_MASK
;
3863 if ((led
& E1000_PHY_LED0_MODE_MASK
) !=
3864 E1000_LEDCTL_MODE_LINK_UP
)
3866 if (led
& E1000_PHY_LED0_IVRT
)
3867 data
&= ~(E1000_PHY_LED0_IVRT
<< (i
* 5));
3869 data
|= (E1000_PHY_LED0_IVRT
<< (i
* 5));
3873 return e1e_wphy(hw
, HV_LED_CONFIG
, data
);
3877 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
3878 * @hw: pointer to the HW structure
3880 * Read appropriate register for the config done bit for completion status
3881 * and configure the PHY through s/w for EEPROM-less parts.
3883 * NOTE: some silicon which is EEPROM-less will fail trying to read the
3884 * config done bit, so only an error is logged and continues. If we were
3885 * to return with error, EEPROM-less silicon would not be able to be reset
3888 static s32
e1000_get_cfg_done_ich8lan(struct e1000_hw
*hw
)
3894 e1000e_get_cfg_done(hw
);
3896 /* Wait for indication from h/w that it has completed basic config */
3897 if (hw
->mac
.type
>= e1000_ich10lan
) {
3898 e1000_lan_init_done_ich8lan(hw
);
3900 ret_val
= e1000e_get_auto_rd_done(hw
);
3903 * When auto config read does not complete, do not
3904 * return with an error. This can happen in situations
3905 * where there is no eeprom and prevents getting link.
3907 e_dbg("Auto Read Done did not complete\n");
3912 /* Clear PHY Reset Asserted bit */
3913 status
= er32(STATUS
);
3914 if (status
& E1000_STATUS_PHYRA
)
3915 ew32(STATUS
, status
& ~E1000_STATUS_PHYRA
);
3917 e_dbg("PHY Reset Asserted not set - needs delay\n");
3919 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
3920 if (hw
->mac
.type
<= e1000_ich9lan
) {
3921 if (((er32(EECD
) & E1000_EECD_PRES
) == 0) &&
3922 (hw
->phy
.type
== e1000_phy_igp_3
)) {
3923 e1000e_phy_init_script_igp3(hw
);
3926 if (e1000_valid_nvm_bank_detect_ich8lan(hw
, &bank
)) {
3927 /* Maybe we should do a basic PHY config */
3928 e_dbg("EEPROM not present\n");
3929 ret_val
= -E1000_ERR_CONFIG
;
3937 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
3938 * @hw: pointer to the HW structure
3940 * In the case of a PHY power down to save power, or to turn off link during a
3941 * driver unload, or wake on lan is not enabled, remove the link.
3943 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw
*hw
)
3945 /* If the management interface is not enabled, then power down */
3946 if (!(hw
->mac
.ops
.check_mng_mode(hw
) ||
3947 hw
->phy
.ops
.check_reset_block(hw
)))
3948 e1000_power_down_phy_copper(hw
);
3952 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
3953 * @hw: pointer to the HW structure
3955 * Clears hardware counters specific to the silicon family and calls
3956 * clear_hw_cntrs_generic to clear all general purpose counters.
3958 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw
*hw
)
3963 e1000e_clear_hw_cntrs_base(hw
);
3979 /* Clear PHY statistics registers */
3980 if ((hw
->phy
.type
== e1000_phy_82578
) ||
3981 (hw
->phy
.type
== e1000_phy_82579
) ||
3982 (hw
->phy
.type
== e1000_phy_82577
)) {
3983 ret_val
= hw
->phy
.ops
.acquire(hw
);
3986 ret_val
= hw
->phy
.ops
.set_page(hw
,
3987 HV_STATS_PAGE
<< IGP_PAGE_SHIFT
);
3990 hw
->phy
.ops
.read_reg_page(hw
, HV_SCC_UPPER
, &phy_data
);
3991 hw
->phy
.ops
.read_reg_page(hw
, HV_SCC_LOWER
, &phy_data
);
3992 hw
->phy
.ops
.read_reg_page(hw
, HV_ECOL_UPPER
, &phy_data
);
3993 hw
->phy
.ops
.read_reg_page(hw
, HV_ECOL_LOWER
, &phy_data
);
3994 hw
->phy
.ops
.read_reg_page(hw
, HV_MCC_UPPER
, &phy_data
);
3995 hw
->phy
.ops
.read_reg_page(hw
, HV_MCC_LOWER
, &phy_data
);
3996 hw
->phy
.ops
.read_reg_page(hw
, HV_LATECOL_UPPER
, &phy_data
);
3997 hw
->phy
.ops
.read_reg_page(hw
, HV_LATECOL_LOWER
, &phy_data
);
3998 hw
->phy
.ops
.read_reg_page(hw
, HV_COLC_UPPER
, &phy_data
);
3999 hw
->phy
.ops
.read_reg_page(hw
, HV_COLC_LOWER
, &phy_data
);
4000 hw
->phy
.ops
.read_reg_page(hw
, HV_DC_UPPER
, &phy_data
);
4001 hw
->phy
.ops
.read_reg_page(hw
, HV_DC_LOWER
, &phy_data
);
4002 hw
->phy
.ops
.read_reg_page(hw
, HV_TNCRS_UPPER
, &phy_data
);
4003 hw
->phy
.ops
.read_reg_page(hw
, HV_TNCRS_LOWER
, &phy_data
);
4005 hw
->phy
.ops
.release(hw
);
4009 static const struct e1000_mac_operations ich8_mac_ops
= {
4010 /* check_mng_mode dependent on mac type */
4011 .check_for_link
= e1000_check_for_copper_link_ich8lan
,
4012 /* cleanup_led dependent on mac type */
4013 .clear_hw_cntrs
= e1000_clear_hw_cntrs_ich8lan
,
4014 .get_bus_info
= e1000_get_bus_info_ich8lan
,
4015 .set_lan_id
= e1000_set_lan_id_single_port
,
4016 .get_link_up_info
= e1000_get_link_up_info_ich8lan
,
4017 /* led_on dependent on mac type */
4018 /* led_off dependent on mac type */
4019 .update_mc_addr_list
= e1000e_update_mc_addr_list_generic
,
4020 .reset_hw
= e1000_reset_hw_ich8lan
,
4021 .init_hw
= e1000_init_hw_ich8lan
,
4022 .setup_link
= e1000_setup_link_ich8lan
,
4023 .setup_physical_interface
= e1000_setup_copper_link_ich8lan
,
4024 /* id_led_init dependent on mac type */
4027 static const struct e1000_phy_operations ich8_phy_ops
= {
4028 .acquire
= e1000_acquire_swflag_ich8lan
,
4029 .check_reset_block
= e1000_check_reset_block_ich8lan
,
4031 .get_cfg_done
= e1000_get_cfg_done_ich8lan
,
4032 .get_cable_length
= e1000e_get_cable_length_igp_2
,
4033 .read_reg
= e1000e_read_phy_reg_igp
,
4034 .release
= e1000_release_swflag_ich8lan
,
4035 .reset
= e1000_phy_hw_reset_ich8lan
,
4036 .set_d0_lplu_state
= e1000_set_d0_lplu_state_ich8lan
,
4037 .set_d3_lplu_state
= e1000_set_d3_lplu_state_ich8lan
,
4038 .write_reg
= e1000e_write_phy_reg_igp
,
4041 static const struct e1000_nvm_operations ich8_nvm_ops
= {
4042 .acquire
= e1000_acquire_nvm_ich8lan
,
4043 .read
= e1000_read_nvm_ich8lan
,
4044 .release
= e1000_release_nvm_ich8lan
,
4045 .update
= e1000_update_nvm_checksum_ich8lan
,
4046 .valid_led_default
= e1000_valid_led_default_ich8lan
,
4047 .validate
= e1000_validate_nvm_checksum_ich8lan
,
4048 .write
= e1000_write_nvm_ich8lan
,
4051 const struct e1000_info e1000_ich8_info
= {
4052 .mac
= e1000_ich8lan
,
4053 .flags
= FLAG_HAS_WOL
4055 | FLAG_HAS_CTRLEXT_ON_LOAD
4060 .max_hw_frame_size
= ETH_FRAME_LEN
+ ETH_FCS_LEN
,
4061 .get_variants
= e1000_get_variants_ich8lan
,
4062 .mac_ops
= &ich8_mac_ops
,
4063 .phy_ops
= &ich8_phy_ops
,
4064 .nvm_ops
= &ich8_nvm_ops
,
4067 const struct e1000_info e1000_ich9_info
= {
4068 .mac
= e1000_ich9lan
,
4069 .flags
= FLAG_HAS_JUMBO_FRAMES
4072 | FLAG_HAS_CTRLEXT_ON_LOAD
4077 .max_hw_frame_size
= DEFAULT_JUMBO
,
4078 .get_variants
= e1000_get_variants_ich8lan
,
4079 .mac_ops
= &ich8_mac_ops
,
4080 .phy_ops
= &ich8_phy_ops
,
4081 .nvm_ops
= &ich8_nvm_ops
,
4084 const struct e1000_info e1000_ich10_info
= {
4085 .mac
= e1000_ich10lan
,
4086 .flags
= FLAG_HAS_JUMBO_FRAMES
4089 | FLAG_HAS_CTRLEXT_ON_LOAD
4094 .max_hw_frame_size
= DEFAULT_JUMBO
,
4095 .get_variants
= e1000_get_variants_ich8lan
,
4096 .mac_ops
= &ich8_mac_ops
,
4097 .phy_ops
= &ich8_phy_ops
,
4098 .nvm_ops
= &ich8_nvm_ops
,
4101 const struct e1000_info e1000_pch_info
= {
4102 .mac
= e1000_pchlan
,
4103 .flags
= FLAG_IS_ICH
4105 | FLAG_HAS_CTRLEXT_ON_LOAD
4108 | FLAG_HAS_JUMBO_FRAMES
4109 | FLAG_DISABLE_FC_PAUSE_TIME
/* errata */
4111 .flags2
= FLAG2_HAS_PHY_STATS
,
4113 .max_hw_frame_size
= 4096,
4114 .get_variants
= e1000_get_variants_ich8lan
,
4115 .mac_ops
= &ich8_mac_ops
,
4116 .phy_ops
= &ich8_phy_ops
,
4117 .nvm_ops
= &ich8_nvm_ops
,
4120 const struct e1000_info e1000_pch2_info
= {
4121 .mac
= e1000_pch2lan
,
4122 .flags
= FLAG_IS_ICH
4124 | FLAG_HAS_CTRLEXT_ON_LOAD
4127 | FLAG_HAS_JUMBO_FRAMES
4129 .flags2
= FLAG2_HAS_PHY_STATS
4132 .max_hw_frame_size
= DEFAULT_JUMBO
,
4133 .get_variants
= e1000_get_variants_ich8lan
,
4134 .mac_ops
= &ich8_mac_ops
,
4135 .phy_ops
= &ich8_phy_ops
,
4136 .nvm_ops
= &ich8_nvm_ops
,