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mtd: fsmc_nand: pass the ale and cmd resource via resource
[linux-2.6.git] / drivers / mtd / nand / fsmc_nand.c
blobcb86450871517143977abfc618d083d13ddcbaee
1 /*
2 * drivers/mtd/nand/fsmc_nand.c
3 *
4 * ST Microelectronics
5 * Flexible Static Memory Controller (FSMC)
6 * Driver for NAND portions
7 *
8 * Copyright © 2010 ST Microelectronics
9 * Vipin Kumar <vipin.kumar@st.com>
10 * Ashish Priyadarshi
11 *
12 * Based on drivers/mtd/nand/nomadik_nand.c
13 *
14 * This file is licensed under the terms of the GNU General Public
15 * License version 2. This program is licensed "as is" without any
16 * warranty of any kind, whether express or implied.
17 */
18
19 #include <linux/clk.h>
20 #include <linux/completion.h>
21 #include <linux/dmaengine.h>
22 #include <linux/dma-direction.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/err.h>
25 #include <linux/init.h>
26 #include <linux/module.h>
27 #include <linux/resource.h>
28 #include <linux/sched.h>
29 #include <linux/types.h>
30 #include <linux/mtd/mtd.h>
31 #include <linux/mtd/nand.h>
32 #include <linux/mtd/nand_ecc.h>
33 #include <linux/platform_device.h>
34 #include <linux/of.h>
35 #include <linux/mtd/partitions.h>
36 #include <linux/io.h>
37 #include <linux/slab.h>
38 #include <linux/mtd/fsmc.h>
39 #include <linux/amba/bus.h>
40 #include <mtd/mtd-abi.h>
41
42 static struct nand_ecclayout fsmc_ecc1_128_layout = {
43 .eccbytes = 24,
44 .eccpos = {2, 3, 4, 18, 19, 20, 34, 35, 36, 50, 51, 52,
45 66, 67, 68, 82, 83, 84, 98, 99, 100, 114, 115, 116},
46 .oobfree = {
47 {.offset = 8, .length = 8},
48 {.offset = 24, .length = 8},
49 {.offset = 40, .length = 8},
50 {.offset = 56, .length = 8},
51 {.offset = 72, .length = 8},
52 {.offset = 88, .length = 8},
53 {.offset = 104, .length = 8},
54 {.offset = 120, .length = 8}
55 }
56 };
57
58 static struct nand_ecclayout fsmc_ecc1_64_layout = {
59 .eccbytes = 12,
60 .eccpos = {2, 3, 4, 18, 19, 20, 34, 35, 36, 50, 51, 52},
61 .oobfree = {
62 {.offset = 8, .length = 8},
63 {.offset = 24, .length = 8},
64 {.offset = 40, .length = 8},
65 {.offset = 56, .length = 8},
66 }
67 };
68
69 static struct nand_ecclayout fsmc_ecc1_16_layout = {
70 .eccbytes = 3,
71 .eccpos = {2, 3, 4},
72 .oobfree = {
73 {.offset = 8, .length = 8},
74 }
75 };
76
77 /*
78 * ECC4 layout for NAND of pagesize 8192 bytes & OOBsize 256 bytes. 13*16 bytes
79 * of OB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block and 46
80 * bytes are free for use.
81 */
82 static struct nand_ecclayout fsmc_ecc4_256_layout = {
83 .eccbytes = 208,
84 .eccpos = { 2, 3, 4, 5, 6, 7, 8,
85 9, 10, 11, 12, 13, 14,
86 18, 19, 20, 21, 22, 23, 24,
87 25, 26, 27, 28, 29, 30,
88 34, 35, 36, 37, 38, 39, 40,
89 41, 42, 43, 44, 45, 46,
90 50, 51, 52, 53, 54, 55, 56,
91 57, 58, 59, 60, 61, 62,
92 66, 67, 68, 69, 70, 71, 72,
93 73, 74, 75, 76, 77, 78,
94 82, 83, 84, 85, 86, 87, 88,
95 89, 90, 91, 92, 93, 94,
96 98, 99, 100, 101, 102, 103, 104,
97 105, 106, 107, 108, 109, 110,
98 114, 115, 116, 117, 118, 119, 120,
99 121, 122, 123, 124, 125, 126,
100 130, 131, 132, 133, 134, 135, 136,
101 137, 138, 139, 140, 141, 142,
102 146, 147, 148, 149, 150, 151, 152,
103 153, 154, 155, 156, 157, 158,
104 162, 163, 164, 165, 166, 167, 168,
105 169, 170, 171, 172, 173, 174,
106 178, 179, 180, 181, 182, 183, 184,
107 185, 186, 187, 188, 189, 190,
108 194, 195, 196, 197, 198, 199, 200,
109 201, 202, 203, 204, 205, 206,
110 210, 211, 212, 213, 214, 215, 216,
111 217, 218, 219, 220, 221, 222,
112 226, 227, 228, 229, 230, 231, 232,
113 233, 234, 235, 236, 237, 238,
114 242, 243, 244, 245, 246, 247, 248,
115 249, 250, 251, 252, 253, 254
116 },
117 .oobfree = {
118 {.offset = 15, .length = 3},
119 {.offset = 31, .length = 3},
120 {.offset = 47, .length = 3},
121 {.offset = 63, .length = 3},
122 {.offset = 79, .length = 3},
123 {.offset = 95, .length = 3},
124 {.offset = 111, .length = 3},
125 {.offset = 127, .length = 3},
126 {.offset = 143, .length = 3},
127 {.offset = 159, .length = 3},
128 {.offset = 175, .length = 3},
129 {.offset = 191, .length = 3},
130 {.offset = 207, .length = 3},
131 {.offset = 223, .length = 3},
132 {.offset = 239, .length = 3},
133 {.offset = 255, .length = 1}
134 }
135 };
136
137 /*
138 * ECC4 layout for NAND of pagesize 4096 bytes & OOBsize 224 bytes. 13*8 bytes
139 * of OOB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block & 118
140 * bytes are free for use.
141 */
142 static struct nand_ecclayout fsmc_ecc4_224_layout = {
143 .eccbytes = 104,
144 .eccpos = { 2, 3, 4, 5, 6, 7, 8,
145 9, 10, 11, 12, 13, 14,
146 18, 19, 20, 21, 22, 23, 24,
147 25, 26, 27, 28, 29, 30,
148 34, 35, 36, 37, 38, 39, 40,
149 41, 42, 43, 44, 45, 46,
150 50, 51, 52, 53, 54, 55, 56,
151 57, 58, 59, 60, 61, 62,
152 66, 67, 68, 69, 70, 71, 72,
153 73, 74, 75, 76, 77, 78,
154 82, 83, 84, 85, 86, 87, 88,
155 89, 90, 91, 92, 93, 94,
156 98, 99, 100, 101, 102, 103, 104,
157 105, 106, 107, 108, 109, 110,
158 114, 115, 116, 117, 118, 119, 120,
159 121, 122, 123, 124, 125, 126
160 },
161 .oobfree = {
162 {.offset = 15, .length = 3},
163 {.offset = 31, .length = 3},
164 {.offset = 47, .length = 3},
165 {.offset = 63, .length = 3},
166 {.offset = 79, .length = 3},
167 {.offset = 95, .length = 3},
168 {.offset = 111, .length = 3},
169 {.offset = 127, .length = 97}
170 }
171 };
172
173 /*
174 * ECC4 layout for NAND of pagesize 4096 bytes & OOBsize 128 bytes. 13*8 bytes
175 * of OOB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block & 22
176 * bytes are free for use.
177 */
178 static struct nand_ecclayout fsmc_ecc4_128_layout = {
179 .eccbytes = 104,
180 .eccpos = { 2, 3, 4, 5, 6, 7, 8,
181 9, 10, 11, 12, 13, 14,
182 18, 19, 20, 21, 22, 23, 24,
183 25, 26, 27, 28, 29, 30,
184 34, 35, 36, 37, 38, 39, 40,
185 41, 42, 43, 44, 45, 46,
186 50, 51, 52, 53, 54, 55, 56,
187 57, 58, 59, 60, 61, 62,
188 66, 67, 68, 69, 70, 71, 72,
189 73, 74, 75, 76, 77, 78,
190 82, 83, 84, 85, 86, 87, 88,
191 89, 90, 91, 92, 93, 94,
192 98, 99, 100, 101, 102, 103, 104,
193 105, 106, 107, 108, 109, 110,
194 114, 115, 116, 117, 118, 119, 120,
195 121, 122, 123, 124, 125, 126
196 },
197 .oobfree = {
198 {.offset = 15, .length = 3},
199 {.offset = 31, .length = 3},
200 {.offset = 47, .length = 3},
201 {.offset = 63, .length = 3},
202 {.offset = 79, .length = 3},
203 {.offset = 95, .length = 3},
204 {.offset = 111, .length = 3},
205 {.offset = 127, .length = 1}
206 }
207 };
208
209 /*
210 * ECC4 layout for NAND of pagesize 2048 bytes & OOBsize 64 bytes. 13*4 bytes of
211 * OOB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block and 10
212 * bytes are free for use.
213 */
214 static struct nand_ecclayout fsmc_ecc4_64_layout = {
215 .eccbytes = 52,
216 .eccpos = { 2, 3, 4, 5, 6, 7, 8,
217 9, 10, 11, 12, 13, 14,
218 18, 19, 20, 21, 22, 23, 24,
219 25, 26, 27, 28, 29, 30,
220 34, 35, 36, 37, 38, 39, 40,
221 41, 42, 43, 44, 45, 46,
222 50, 51, 52, 53, 54, 55, 56,
223 57, 58, 59, 60, 61, 62,
224 },
225 .oobfree = {
226 {.offset = 15, .length = 3},
227 {.offset = 31, .length = 3},
228 {.offset = 47, .length = 3},
229 {.offset = 63, .length = 1},
230 }
231 };
232
233 /*
234 * ECC4 layout for NAND of pagesize 512 bytes & OOBsize 16 bytes. 13 bytes of
235 * OOB size is reserved for ECC, Byte no. 4 & 5 reserved for bad block and One
236 * byte is free for use.
237 */
238 static struct nand_ecclayout fsmc_ecc4_16_layout = {
239 .eccbytes = 13,
240 .eccpos = { 0, 1, 2, 3, 6, 7, 8,
241 9, 10, 11, 12, 13, 14
242 },
243 .oobfree = {
244 {.offset = 15, .length = 1},
245 }
246 };
247
248 /*
249 * ECC placement definitions in oobfree type format.
250 * There are 13 bytes of ecc for every 512 byte block and it has to be read
251 * consecutively and immediately after the 512 byte data block for hardware to
252 * generate the error bit offsets in 512 byte data.
253 * Managing the ecc bytes in the following way makes it easier for software to
254 * read ecc bytes consecutive to data bytes. This way is similar to
255 * oobfree structure maintained already in generic nand driver
256 */
257 static struct fsmc_eccplace fsmc_ecc4_lp_place = {
258 .eccplace = {
259 {.offset = 2, .length = 13},
260 {.offset = 18, .length = 13},
261 {.offset = 34, .length = 13},
262 {.offset = 50, .length = 13},
263 {.offset = 66, .length = 13},
264 {.offset = 82, .length = 13},
265 {.offset = 98, .length = 13},
266 {.offset = 114, .length = 13}
267 }
268 };
269
270 static struct fsmc_eccplace fsmc_ecc4_sp_place = {
271 .eccplace = {
272 {.offset = 0, .length = 4},
273 {.offset = 6, .length = 9}
274 }
275 };
276
277 /**
278 * struct fsmc_nand_data - structure for FSMC NAND device state
279 *
280 * @pid: Part ID on the AMBA PrimeCell format
281 * @mtd: MTD info for a NAND flash.
282 * @nand: Chip related info for a NAND flash.
283 * @partitions: Partition info for a NAND Flash.
284 * @nr_partitions: Total number of partition of a NAND flash.
285 *
286 * @ecc_place: ECC placing locations in oobfree type format.
287 * @bank: Bank number for probed device.
288 * @clk: Clock structure for FSMC.
289 *
290 * @read_dma_chan: DMA channel for read access
291 * @write_dma_chan: DMA channel for write access to NAND
292 * @dma_access_complete: Completion structure
293 *
294 * @data_pa: NAND Physical port for Data.
295 * @data_va: NAND port for Data.
296 * @cmd_va: NAND port for Command.
297 * @addr_va: NAND port for Address.
298 * @regs_va: FSMC regs base address.
299 */
300 struct fsmc_nand_data {
301 u32 pid;
302 struct mtd_info mtd;
303 struct nand_chip nand;
304 struct mtd_partition *partitions;
305 unsigned int nr_partitions;
306
307 struct fsmc_eccplace *ecc_place;
308 unsigned int bank;
309 struct device *dev;
310 enum access_mode mode;
311 struct clk *clk;
312
313 /* DMA related objects */
314 struct dma_chan *read_dma_chan;
315 struct dma_chan *write_dma_chan;
316 struct completion dma_access_complete;
317
318 struct fsmc_nand_timings *dev_timings;
319
320 dma_addr_t data_pa;
321 void __iomem *data_va;
322 void __iomem *cmd_va;
323 void __iomem *addr_va;
324 void __iomem *regs_va;
325
326 void (*select_chip)(uint32_t bank, uint32_t busw);
327 };
328
329 /* Assert CS signal based on chipnr */
330 static void fsmc_select_chip(struct mtd_info *mtd, int chipnr)
331 {
332 struct nand_chip *chip = mtd->priv;
333 struct fsmc_nand_data *host;
334
335 host = container_of(mtd, struct fsmc_nand_data, mtd);
336
337 switch (chipnr) {
338 case -1:
339 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
340 break;
341 case 0:
342 case 1:
343 case 2:
344 case 3:
345 if (host->select_chip)
346 host->select_chip(chipnr,
347 chip->options & NAND_BUSWIDTH_16);
348 break;
349
350 default:
351 BUG();
352 }
353 }
354
355 /*
356 * fsmc_cmd_ctrl - For facilitaing Hardware access
357 * This routine allows hardware specific access to control-lines(ALE,CLE)
358 */
359 static void fsmc_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
360 {
361 struct nand_chip *this = mtd->priv;
362 struct fsmc_nand_data *host = container_of(mtd,
363 struct fsmc_nand_data, mtd);
364 void *__iomem *regs = host->regs_va;
365 unsigned int bank = host->bank;
366
367 if (ctrl & NAND_CTRL_CHANGE) {
368 u32 pc;
369
370 if (ctrl & NAND_CLE) {
371 this->IO_ADDR_R = host->cmd_va;
372 this->IO_ADDR_W = host->cmd_va;
373 } else if (ctrl & NAND_ALE) {
374 this->IO_ADDR_R = host->addr_va;
375 this->IO_ADDR_W = host->addr_va;
376 } else {
377 this->IO_ADDR_R = host->data_va;
378 this->IO_ADDR_W = host->data_va;
379 }
380
381 pc = readl(FSMC_NAND_REG(regs, bank, PC));
382 if (ctrl & NAND_NCE)
383 pc |= FSMC_ENABLE;
384 else
385 pc &= ~FSMC_ENABLE;
386 writel(pc, FSMC_NAND_REG(regs, bank, PC));
387 }
388
389 mb();
390
391 if (cmd != NAND_CMD_NONE)
392 writeb(cmd, this->IO_ADDR_W);
393 }
394
395 /*
396 * fsmc_nand_setup - FSMC (Flexible Static Memory Controller) init routine
397 *
398 * This routine initializes timing parameters related to NAND memory access in
399 * FSMC registers
400 */
401 static void fsmc_nand_setup(void __iomem *regs, uint32_t bank,
402 uint32_t busw, struct fsmc_nand_timings *timings)
403 {
404 uint32_t value = FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON;
405 uint32_t tclr, tar, thiz, thold, twait, tset;
406 struct fsmc_nand_timings *tims;
407 struct fsmc_nand_timings default_timings = {
408 .tclr = FSMC_TCLR_1,
409 .tar = FSMC_TAR_1,
410 .thiz = FSMC_THIZ_1,
411 .thold = FSMC_THOLD_4,
412 .twait = FSMC_TWAIT_6,
413 .tset = FSMC_TSET_0,
414 };
415
416 if (timings)
417 tims = timings;
418 else
419 tims = &default_timings;
420
421 tclr = (tims->tclr & FSMC_TCLR_MASK) << FSMC_TCLR_SHIFT;
422 tar = (tims->tar & FSMC_TAR_MASK) << FSMC_TAR_SHIFT;
423 thiz = (tims->thiz & FSMC_THIZ_MASK) << FSMC_THIZ_SHIFT;
424 thold = (tims->thold & FSMC_THOLD_MASK) << FSMC_THOLD_SHIFT;
425 twait = (tims->twait & FSMC_TWAIT_MASK) << FSMC_TWAIT_SHIFT;
426 tset = (tims->tset & FSMC_TSET_MASK) << FSMC_TSET_SHIFT;
427
428 if (busw)
429 writel(value | FSMC_DEVWID_16, FSMC_NAND_REG(regs, bank, PC));
430 else
431 writel(value | FSMC_DEVWID_8, FSMC_NAND_REG(regs, bank, PC));
432
433 writel(readl(FSMC_NAND_REG(regs, bank, PC)) | tclr | tar,
434 FSMC_NAND_REG(regs, bank, PC));
435 writel(thiz | thold | twait | tset, FSMC_NAND_REG(regs, bank, COMM));
436 writel(thiz | thold | twait | tset, FSMC_NAND_REG(regs, bank, ATTRIB));
437 }
438
439 /*
440 * fsmc_enable_hwecc - Enables Hardware ECC through FSMC registers
441 */
442 static void fsmc_enable_hwecc(struct mtd_info *mtd, int mode)
443 {
444 struct fsmc_nand_data *host = container_of(mtd,
445 struct fsmc_nand_data, mtd);
446 void __iomem *regs = host->regs_va;
447 uint32_t bank = host->bank;
448
449 writel(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCPLEN_256,
450 FSMC_NAND_REG(regs, bank, PC));
451 writel(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCEN,
452 FSMC_NAND_REG(regs, bank, PC));
453 writel(readl(FSMC_NAND_REG(regs, bank, PC)) | FSMC_ECCEN,
454 FSMC_NAND_REG(regs, bank, PC));
455 }
456
457 /*
458 * fsmc_read_hwecc_ecc4 - Hardware ECC calculator for ecc4 option supported by
459 * FSMC. ECC is 13 bytes for 512 bytes of data (supports error correction up to
460 * max of 8-bits)
461 */
462 static int fsmc_read_hwecc_ecc4(struct mtd_info *mtd, const uint8_t *data,
463 uint8_t *ecc)
464 {
465 struct fsmc_nand_data *host = container_of(mtd,
466 struct fsmc_nand_data, mtd);
467 void __iomem *regs = host->regs_va;
468 uint32_t bank = host->bank;
469 uint32_t ecc_tmp;
470 unsigned long deadline = jiffies + FSMC_BUSY_WAIT_TIMEOUT;
471
472 do {
473 if (readl(FSMC_NAND_REG(regs, bank, STS)) & FSMC_CODE_RDY)
474 break;
475 else
476 cond_resched();
477 } while (!time_after_eq(jiffies, deadline));
478
479 if (time_after_eq(jiffies, deadline)) {
480 dev_err(host->dev, "calculate ecc timed out\n");
481 return -ETIMEDOUT;
482 }
483
484 ecc_tmp = readl(FSMC_NAND_REG(regs, bank, ECC1));
485 ecc[0] = (uint8_t) (ecc_tmp >> 0);
486 ecc[1] = (uint8_t) (ecc_tmp >> 8);
487 ecc[2] = (uint8_t) (ecc_tmp >> 16);
488 ecc[3] = (uint8_t) (ecc_tmp >> 24);
489
490 ecc_tmp = readl(FSMC_NAND_REG(regs, bank, ECC2));
491 ecc[4] = (uint8_t) (ecc_tmp >> 0);
492 ecc[5] = (uint8_t) (ecc_tmp >> 8);
493 ecc[6] = (uint8_t) (ecc_tmp >> 16);
494 ecc[7] = (uint8_t) (ecc_tmp >> 24);
495
496 ecc_tmp = readl(FSMC_NAND_REG(regs, bank, ECC3));
497 ecc[8] = (uint8_t) (ecc_tmp >> 0);
498 ecc[9] = (uint8_t) (ecc_tmp >> 8);
499 ecc[10] = (uint8_t) (ecc_tmp >> 16);
500 ecc[11] = (uint8_t) (ecc_tmp >> 24);
501
502 ecc_tmp = readl(FSMC_NAND_REG(regs, bank, STS));
503 ecc[12] = (uint8_t) (ecc_tmp >> 16);
504
505 return 0;
506 }
507
508 /*
509 * fsmc_read_hwecc_ecc1 - Hardware ECC calculator for ecc1 option supported by
510 * FSMC. ECC is 3 bytes for 512 bytes of data (supports error correction up to
511 * max of 1-bit)
512 */
513 static int fsmc_read_hwecc_ecc1(struct mtd_info *mtd, const uint8_t *data,
514 uint8_t *ecc)
515 {
516 struct fsmc_nand_data *host = container_of(mtd,
517 struct fsmc_nand_data, mtd);
518 void __iomem *regs = host->regs_va;
519 uint32_t bank = host->bank;
520 uint32_t ecc_tmp;
521
522 ecc_tmp = readl(FSMC_NAND_REG(regs, bank, ECC1));
523 ecc[0] = (uint8_t) (ecc_tmp >> 0);
524 ecc[1] = (uint8_t) (ecc_tmp >> 8);
525 ecc[2] = (uint8_t) (ecc_tmp >> 16);
526
527 return 0;
528 }
529
530 /* Count the number of 0's in buff upto a max of max_bits */
531 static int count_written_bits(uint8_t *buff, int size, int max_bits)
532 {
533 int k, written_bits = 0;
534
535 for (k = 0; k < size; k++) {
536 written_bits += hweight8(~buff[k]);
537 if (written_bits > max_bits)
538 break;
539 }
540
541 return written_bits;
542 }
543
544 static void dma_complete(void *param)
545 {
546 struct fsmc_nand_data *host = param;
547
548 complete(&host->dma_access_complete);
549 }
550
551 static int dma_xfer(struct fsmc_nand_data *host, void *buffer, int len,
552 enum dma_data_direction direction)
553 {
554 struct dma_chan *chan;
555 struct dma_device *dma_dev;
556 struct dma_async_tx_descriptor *tx;
557 dma_addr_t dma_dst, dma_src, dma_addr;
558 dma_cookie_t cookie;
559 unsigned long flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
560 int ret;
561
562 if (direction == DMA_TO_DEVICE)
563 chan = host->write_dma_chan;
564 else if (direction == DMA_FROM_DEVICE)
565 chan = host->read_dma_chan;
566 else
567 return -EINVAL;
568
569 dma_dev = chan->device;
570 dma_addr = dma_map_single(dma_dev->dev, buffer, len, direction);
571
572 if (direction == DMA_TO_DEVICE) {
573 dma_src = dma_addr;
574 dma_dst = host->data_pa;
575 flags |= DMA_COMPL_SRC_UNMAP_SINGLE | DMA_COMPL_SKIP_DEST_UNMAP;
576 } else {
577 dma_src = host->data_pa;
578 dma_dst = dma_addr;
579 flags |= DMA_COMPL_DEST_UNMAP_SINGLE | DMA_COMPL_SKIP_SRC_UNMAP;
580 }
581
582 tx = dma_dev->device_prep_dma_memcpy(chan, dma_dst, dma_src,
583 len, flags);
584
585 if (!tx) {
586 dev_err(host->dev, "device_prep_dma_memcpy error\n");
587 dma_unmap_single(dma_dev->dev, dma_addr, len, direction);
588 return -EIO;
589 }
590
591 tx->callback = dma_complete;
592 tx->callback_param = host;
593 cookie = tx->tx_submit(tx);
594
595 ret = dma_submit_error(cookie);
596 if (ret) {
597 dev_err(host->dev, "dma_submit_error %d\n", cookie);
598 return ret;
599 }
600
601 dma_async_issue_pending(chan);
602
603 ret =
604 wait_for_completion_interruptible_timeout(&host->dma_access_complete,
605 msecs_to_jiffies(3000));
606 if (ret <= 0) {
607 chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
608 dev_err(host->dev, "wait_for_completion_timeout\n");
609 return ret ? ret : -ETIMEDOUT;
610 }
611
612 return 0;
613 }
614
615 /*
616 * fsmc_write_buf - write buffer to chip
617 * @mtd: MTD device structure
618 * @buf: data buffer
619 * @len: number of bytes to write
620 */
621 static void fsmc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
622 {
623 int i;
624 struct nand_chip *chip = mtd->priv;
625
626 if (IS_ALIGNED((uint32_t)buf, sizeof(uint32_t)) &&
627 IS_ALIGNED(len, sizeof(uint32_t))) {
628 uint32_t *p = (uint32_t *)buf;
629 len = len >> 2;
630 for (i = 0; i < len; i++)
631 writel(p[i], chip->IO_ADDR_W);
632 } else {
633 for (i = 0; i < len; i++)
634 writeb(buf[i], chip->IO_ADDR_W);
635 }
636 }
637
638 /*
639 * fsmc_read_buf - read chip data into buffer
640 * @mtd: MTD device structure
641 * @buf: buffer to store date
642 * @len: number of bytes to read
643 */
644 static void fsmc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
645 {
646 int i;
647 struct nand_chip *chip = mtd->priv;
648
649 if (IS_ALIGNED((uint32_t)buf, sizeof(uint32_t)) &&
650 IS_ALIGNED(len, sizeof(uint32_t))) {
651 uint32_t *p = (uint32_t *)buf;
652 len = len >> 2;
653 for (i = 0; i < len; i++)
654 p[i] = readl(chip->IO_ADDR_R);
655 } else {
656 for (i = 0; i < len; i++)
657 buf[i] = readb(chip->IO_ADDR_R);
658 }
659 }
660
661 /*
662 * fsmc_read_buf_dma - read chip data into buffer
663 * @mtd: MTD device structure
664 * @buf: buffer to store date
665 * @len: number of bytes to read
666 */
667 static void fsmc_read_buf_dma(struct mtd_info *mtd, uint8_t *buf, int len)
668 {
669 struct fsmc_nand_data *host;
670
671 host = container_of(mtd, struct fsmc_nand_data, mtd);
672 dma_xfer(host, buf, len, DMA_FROM_DEVICE);
673 }
674
675 /*
676 * fsmc_write_buf_dma - write buffer to chip
677 * @mtd: MTD device structure
678 * @buf: data buffer
679 * @len: number of bytes to write
680 */
681 static void fsmc_write_buf_dma(struct mtd_info *mtd, const uint8_t *buf,
682 int len)
683 {
684 struct fsmc_nand_data *host;
685
686 host = container_of(mtd, struct fsmc_nand_data, mtd);
687 dma_xfer(host, (void *)buf, len, DMA_TO_DEVICE);
688 }
689
690 /*
691 * fsmc_read_page_hwecc
692 * @mtd: mtd info structure
693 * @chip: nand chip info structure
694 * @buf: buffer to store read data
695 * @oob_required: caller expects OOB data read to chip->oob_poi
696 * @page: page number to read
697 *
698 * This routine is needed for fsmc version 8 as reading from NAND chip has to be
699 * performed in a strict sequence as follows:
700 * data(512 byte) -> ecc(13 byte)
701 * After this read, fsmc hardware generates and reports error data bits(up to a
702 * max of 8 bits)
703 */
704 static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
705 uint8_t *buf, int oob_required, int page)
706 {
707 struct fsmc_nand_data *host = container_of(mtd,
708 struct fsmc_nand_data, mtd);
709 struct fsmc_eccplace *ecc_place = host->ecc_place;
710 int i, j, s, stat, eccsize = chip->ecc.size;
711 int eccbytes = chip->ecc.bytes;
712 int eccsteps = chip->ecc.steps;
713 uint8_t *p = buf;
714 uint8_t *ecc_calc = chip->buffers->ecccalc;
715 uint8_t *ecc_code = chip->buffers->ecccode;
716 int off, len, group = 0;
717 /*
718 * ecc_oob is intentionally taken as uint16_t. In 16bit devices, we
719 * end up reading 14 bytes (7 words) from oob. The local array is
720 * to maintain word alignment
721 */
722 uint16_t ecc_oob[7];
723 uint8_t *oob = (uint8_t *)&ecc_oob[0];
724 unsigned int max_bitflips = 0;
725
726 for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, p += eccsize) {
727 chip->cmdfunc(mtd, NAND_CMD_READ0, s * eccsize, page);
728 chip->ecc.hwctl(mtd, NAND_ECC_READ);
729 chip->read_buf(mtd, p, eccsize);
730
731 for (j = 0; j < eccbytes;) {
732 off = ecc_place->eccplace[group].offset;
733 len = ecc_place->eccplace[group].length;
734 group++;
735
736 /*
737 * length is intentionally kept a higher multiple of 2
738 * to read at least 13 bytes even in case of 16 bit NAND
739 * devices
740 */
741 if (chip->options & NAND_BUSWIDTH_16)
742 len = roundup(len, 2);
743
744 chip->cmdfunc(mtd, NAND_CMD_READOOB, off, page);
745 chip->read_buf(mtd, oob + j, len);
746 j += len;
747 }
748
749 memcpy(&ecc_code[i], oob, chip->ecc.bytes);
750 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
751
752 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
753 if (stat < 0) {
754 mtd->ecc_stats.failed++;
755 } else {
756 mtd->ecc_stats.corrected += stat;
757 max_bitflips = max_t(unsigned int, max_bitflips, stat);
758 }
759 }
760
761 return max_bitflips;
762 }
763
764 /*
765 * fsmc_bch8_correct_data
766 * @mtd: mtd info structure
767 * @dat: buffer of read data
768 * @read_ecc: ecc read from device spare area
769 * @calc_ecc: ecc calculated from read data
770 *
771 * calc_ecc is a 104 bit information containing maximum of 8 error
772 * offset informations of 13 bits each in 512 bytes of read data.
773 */
774 static int fsmc_bch8_correct_data(struct mtd_info *mtd, uint8_t *dat,
775 uint8_t *read_ecc, uint8_t *calc_ecc)
776 {
777 struct fsmc_nand_data *host = container_of(mtd,
778 struct fsmc_nand_data, mtd);
779 struct nand_chip *chip = mtd->priv;
780 void __iomem *regs = host->regs_va;
781 unsigned int bank = host->bank;
782 uint32_t err_idx[8];
783 uint32_t num_err, i;
784 uint32_t ecc1, ecc2, ecc3, ecc4;
785
786 num_err = (readl(FSMC_NAND_REG(regs, bank, STS)) >> 10) & 0xF;
787
788 /* no bit flipping */
789 if (likely(num_err == 0))
790 return 0;
791
792 /* too many errors */
793 if (unlikely(num_err > 8)) {
794 /*
795 * This is a temporary erase check. A newly erased page read
796 * would result in an ecc error because the oob data is also
797 * erased to FF and the calculated ecc for an FF data is not
798 * FF..FF.
799 * This is a workaround to skip performing correction in case
800 * data is FF..FF
801 *
802 * Logic:
803 * For every page, each bit written as 0 is counted until these
804 * number of bits are greater than 8 (the maximum correction
805 * capability of FSMC for each 512 + 13 bytes)
806 */
807
808 int bits_ecc = count_written_bits(read_ecc, chip->ecc.bytes, 8);
809 int bits_data = count_written_bits(dat, chip->ecc.size, 8);
810
811 if ((bits_ecc + bits_data) <= 8) {
812 if (bits_data)
813 memset(dat, 0xff, chip->ecc.size);
814 return bits_data;
815 }
816
817 return -EBADMSG;
818 }
819
820 /*
821 * ------------------- calc_ecc[] bit wise -----------|--13 bits--|
822 * |---idx[7]--|--.....-----|---idx[2]--||---idx[1]--||---idx[0]--|
823 *
824 * calc_ecc is a 104 bit information containing maximum of 8 error
825 * offset informations of 13 bits each. calc_ecc is copied into a
826 * uint64_t array and error offset indexes are populated in err_idx
827 * array
828 */
829 ecc1 = readl(FSMC_NAND_REG(regs, bank, ECC1));
830 ecc2 = readl(FSMC_NAND_REG(regs, bank, ECC2));
831 ecc3 = readl(FSMC_NAND_REG(regs, bank, ECC3));
832 ecc4 = readl(FSMC_NAND_REG(regs, bank, STS));
833
834 err_idx[0] = (ecc1 >> 0) & 0x1FFF;
835 err_idx[1] = (ecc1 >> 13) & 0x1FFF;
836 err_idx[2] = (((ecc2 >> 0) & 0x7F) << 6) | ((ecc1 >> 26) & 0x3F);
837 err_idx[3] = (ecc2 >> 7) & 0x1FFF;
838 err_idx[4] = (((ecc3 >> 0) & 0x1) << 12) | ((ecc2 >> 20) & 0xFFF);
839 err_idx[5] = (ecc3 >> 1) & 0x1FFF;
840 err_idx[6] = (ecc3 >> 14) & 0x1FFF;
841 err_idx[7] = (((ecc4 >> 16) & 0xFF) << 5) | ((ecc3 >> 27) & 0x1F);
842
843 i = 0;
844 while (num_err--) {
845 change_bit(0, (unsigned long *)&err_idx[i]);
846 change_bit(1, (unsigned long *)&err_idx[i]);
847
848 if (err_idx[i] < chip->ecc.size * 8) {
849 change_bit(err_idx[i], (unsigned long *)dat);
850 i++;
851 }
852 }
853 return i;
854 }
855
856 static bool filter(struct dma_chan *chan, void *slave)
857 {
858 chan->private = slave;
859 return true;
860 }
861
862 #ifdef CONFIG_OF
863 static int __devinit fsmc_nand_probe_config_dt(struct platform_device *pdev,
864 struct device_node *np)
865 {
866 struct fsmc_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
867 u32 val;
868
869 /* Set default NAND width to 8 bits */
870 pdata->width = 8;
871 if (!of_property_read_u32(np, "bank-width", &val)) {
872 if (val == 2) {
873 pdata->width = 16;
874 } else if (val != 1) {
875 dev_err(&pdev->dev, "invalid bank-width %u\n", val);
876 return -EINVAL;
877 }
878 }
879 if (of_get_property(np, "nand-skip-bbtscan", NULL))
880 pdata->options = NAND_SKIP_BBTSCAN;
881
882 return 0;
883 }
884 #else
885 static int __devinit fsmc_nand_probe_config_dt(struct platform_device *pdev,
886 struct device_node *np)
887 {
888 return -ENOSYS;
889 }
890 #endif
891
892 /*
893 * fsmc_nand_probe - Probe function
894 * @pdev: platform device structure
895 */
896 static int __init fsmc_nand_probe(struct platform_device *pdev)
897 {
898 struct fsmc_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
899 struct device_node __maybe_unused *np = pdev->dev.of_node;
900 struct mtd_part_parser_data ppdata = {};
901 struct fsmc_nand_data *host;
902 struct mtd_info *mtd;
903 struct nand_chip *nand;
904 struct resource *res;
905 dma_cap_mask_t mask;
906 int ret = 0;
907 u32 pid;
908 int i;
909
910 if (np) {
911 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
912 pdev->dev.platform_data = pdata;
913 ret = fsmc_nand_probe_config_dt(pdev, np);
914 if (ret) {
915 dev_err(&pdev->dev, "no platform data\n");
916 return -ENODEV;
917 }
918 }
919
920 if (!pdata) {
921 dev_err(&pdev->dev, "platform data is NULL\n");
922 return -EINVAL;
923 }
924
925 /* Allocate memory for the device structure (and zero it) */
926 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
927 if (!host) {
928 dev_err(&pdev->dev, "failed to allocate device structure\n");
929 return -ENOMEM;
930 }
931
932 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_data");
933 if (!res)
934 return -EINVAL;
935
936 host->data_va = devm_request_and_ioremap(&pdev->dev, res);
937 if (!host->data_va) {
938 dev_err(&pdev->dev, "data ioremap failed\n");
939 return -ENOMEM;
940 }
941 host->data_pa = (dma_addr_t)res->start;
942
943 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_addr");
944 if (!res)
945 return -EINVAL;
946
947 host->addr_va = devm_request_and_ioremap(&pdev->dev, res);
948 if (!host->addr_va) {
949 dev_err(&pdev->dev, "ale ioremap failed\n");
950 return -ENOMEM;
951 }
952
953 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_cmd");
954 if (!res)
955 return -EINVAL;
956
957 host->cmd_va = devm_request_and_ioremap(&pdev->dev, res);
958 if (!host->cmd_va) {
959 dev_err(&pdev->dev, "ale ioremap failed\n");
960 return -ENOMEM;
961 }
962
963 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fsmc_regs");
964 if (!res)
965 return -EINVAL;
966
967 host->regs_va = devm_request_and_ioremap(&pdev->dev, res);
968 if (!host->regs_va) {
969 dev_err(&pdev->dev, "regs ioremap failed\n");
970 return -ENOMEM;
971 }
972
973 host->clk = clk_get(&pdev->dev, NULL);
974 if (IS_ERR(host->clk)) {
975 dev_err(&pdev->dev, "failed to fetch block clock\n");
976 return PTR_ERR(host->clk);
977 }
978
979 ret = clk_prepare_enable(host->clk);
980 if (ret)
981 goto err_clk_prepare_enable;
982
983 /*
984 * This device ID is actually a common AMBA ID as used on the
985 * AMBA PrimeCell bus. However it is not a PrimeCell.
986 */
987 for (pid = 0, i = 0; i < 4; i++)
988 pid |= (readl(host->regs_va + resource_size(res) - 0x20 + 4 * i) & 255) << (i * 8);
989 host->pid = pid;
990 dev_info(&pdev->dev, "FSMC device partno %03x, manufacturer %02x, "
991 "revision %02x, config %02x\n",
992 AMBA_PART_BITS(pid), AMBA_MANF_BITS(pid),
993 AMBA_REV_BITS(pid), AMBA_CONFIG_BITS(pid));
994
995 host->bank = pdata->bank;
996 host->select_chip = pdata->select_bank;
997 host->partitions = pdata->partitions;
998 host->nr_partitions = pdata->nr_partitions;
999 host->dev = &pdev->dev;
1000 host->dev_timings = pdata->nand_timings;
1001 host->mode = pdata->mode;
1002
1003 if (host->mode == USE_DMA_ACCESS)
1004 init_completion(&host->dma_access_complete);
1005
1006 /* Link all private pointers */
1007 mtd = &host->mtd;
1008 nand = &host->nand;
1009 mtd->priv = nand;
1010 nand->priv = host;
1011
1012 host->mtd.owner = THIS_MODULE;
1013 nand->IO_ADDR_R = host->data_va;
1014 nand->IO_ADDR_W = host->data_va;
1015 nand->cmd_ctrl = fsmc_cmd_ctrl;
1016 nand->chip_delay = 30;
1017
1018 nand->ecc.mode = NAND_ECC_HW;
1019 nand->ecc.hwctl = fsmc_enable_hwecc;
1020 nand->ecc.size = 512;
1021 nand->options = pdata->options;
1022 nand->select_chip = fsmc_select_chip;
1023 nand->badblockbits = 7;
1024
1025 if (pdata->width == FSMC_NAND_BW16)
1026 nand->options |= NAND_BUSWIDTH_16;
1027
1028 switch (host->mode) {
1029 case USE_DMA_ACCESS:
1030 dma_cap_zero(mask);
1031 dma_cap_set(DMA_MEMCPY, mask);
1032 host->read_dma_chan = dma_request_channel(mask, filter,
1033 pdata->read_dma_priv);
1034 if (!host->read_dma_chan) {
1035 dev_err(&pdev->dev, "Unable to get read dma channel\n");
1036 goto err_req_read_chnl;
1037 }
1038 host->write_dma_chan = dma_request_channel(mask, filter,
1039 pdata->write_dma_priv);
1040 if (!host->write_dma_chan) {
1041 dev_err(&pdev->dev, "Unable to get write dma channel\n");
1042 goto err_req_write_chnl;
1043 }
1044 nand->read_buf = fsmc_read_buf_dma;
1045 nand->write_buf = fsmc_write_buf_dma;
1046 break;
1047
1048 default:
1049 case USE_WORD_ACCESS:
1050 nand->read_buf = fsmc_read_buf;
1051 nand->write_buf = fsmc_write_buf;
1052 break;
1053 }
1054
1055 fsmc_nand_setup(host->regs_va, host->bank,
1056 nand->options & NAND_BUSWIDTH_16,
1057 host->dev_timings);
1058
1059 if (AMBA_REV_BITS(host->pid) >= 8) {
1060 nand->ecc.read_page = fsmc_read_page_hwecc;
1061 nand->ecc.calculate = fsmc_read_hwecc_ecc4;
1062 nand->ecc.correct = fsmc_bch8_correct_data;
1063 nand->ecc.bytes = 13;
1064 nand->ecc.strength = 8;
1065 } else {
1066 nand->ecc.calculate = fsmc_read_hwecc_ecc1;
1067 nand->ecc.correct = nand_correct_data;
1068 nand->ecc.bytes = 3;
1069 nand->ecc.strength = 1;
1070 }
1071
1072 /*
1073 * Scan to find existence of the device
1074 */
1075 if (nand_scan_ident(&host->mtd, 1, NULL)) {
1076 ret = -ENXIO;
1077 dev_err(&pdev->dev, "No NAND Device found!\n");
1078 goto err_scan_ident;
1079 }
1080
1081 if (AMBA_REV_BITS(host->pid) >= 8) {
1082 switch (host->mtd.oobsize) {
1083 case 16:
1084 nand->ecc.layout = &fsmc_ecc4_16_layout;
1085 host->ecc_place = &fsmc_ecc4_sp_place;
1086 break;
1087 case 64:
1088 nand->ecc.layout = &fsmc_ecc4_64_layout;
1089 host->ecc_place = &fsmc_ecc4_lp_place;
1090 break;
1091 case 128:
1092 nand->ecc.layout = &fsmc_ecc4_128_layout;
1093 host->ecc_place = &fsmc_ecc4_lp_place;
1094 break;
1095 case 224:
1096 nand->ecc.layout = &fsmc_ecc4_224_layout;
1097 host->ecc_place = &fsmc_ecc4_lp_place;
1098 break;
1099 case 256:
1100 nand->ecc.layout = &fsmc_ecc4_256_layout;
1101 host->ecc_place = &fsmc_ecc4_lp_place;
1102 break;
1103 default:
1104 printk(KERN_WARNING "No oob scheme defined for "
1105 "oobsize %d\n", mtd->oobsize);
1106 BUG();
1107 }
1108 } else {
1109 switch (host->mtd.oobsize) {
1110 case 16:
1111 nand->ecc.layout = &fsmc_ecc1_16_layout;
1112 break;
1113 case 64:
1114 nand->ecc.layout = &fsmc_ecc1_64_layout;
1115 break;
1116 case 128:
1117 nand->ecc.layout = &fsmc_ecc1_128_layout;
1118 break;
1119 default:
1120 printk(KERN_WARNING "No oob scheme defined for "
1121 "oobsize %d\n", mtd->oobsize);
1122 BUG();
1123 }
1124 }
1125
1126 /* Second stage of scan to fill MTD data-structures */
1127 if (nand_scan_tail(&host->mtd)) {
1128 ret = -ENXIO;
1129 goto err_probe;
1130 }
1131
1132 /*
1133 * The partition information can is accessed by (in the same precedence)
1134 *
1135 * command line through Bootloader,
1136 * platform data,
1137 * default partition information present in driver.
1138 */
1139 /*
1140 * Check for partition info passed
1141 */
1142 host->mtd.name = "nand";
1143 ppdata.of_node = np;
1144 ret = mtd_device_parse_register(&host->mtd, NULL, &ppdata,
1145 host->partitions, host->nr_partitions);
1146 if (ret)
1147 goto err_probe;
1148
1149 platform_set_drvdata(pdev, host);
1150 dev_info(&pdev->dev, "FSMC NAND driver registration successful\n");
1151 return 0;
1152
1153 err_probe:
1154 err_scan_ident:
1155 if (host->mode == USE_DMA_ACCESS)
1156 dma_release_channel(host->write_dma_chan);
1157 err_req_write_chnl:
1158 if (host->mode == USE_DMA_ACCESS)
1159 dma_release_channel(host->read_dma_chan);
1160 err_req_read_chnl:
1161 clk_disable_unprepare(host->clk);
1162 err_clk_prepare_enable:
1163 clk_put(host->clk);
1164 return ret;
1165 }
1166
1167 /*
1168 * Clean up routine
1169 */
1170 static int fsmc_nand_remove(struct platform_device *pdev)
1171 {
1172 struct fsmc_nand_data *host = platform_get_drvdata(pdev);
1173
1174 platform_set_drvdata(pdev, NULL);
1175
1176 if (host) {
1177 nand_release(&host->mtd);
1178
1179 if (host->mode == USE_DMA_ACCESS) {
1180 dma_release_channel(host->write_dma_chan);
1181 dma_release_channel(host->read_dma_chan);
1182 }
1183 clk_disable_unprepare(host->clk);
1184 clk_put(host->clk);
1185 }
1186
1187 return 0;
1188 }
1189
1190 #ifdef CONFIG_PM
1191 static int fsmc_nand_suspend(struct device *dev)
1192 {
1193 struct fsmc_nand_data *host = dev_get_drvdata(dev);
1194 if (host)
1195 clk_disable_unprepare(host->clk);
1196 return 0;
1197 }
1198
1199 static int fsmc_nand_resume(struct device *dev)
1200 {
1201 struct fsmc_nand_data *host = dev_get_drvdata(dev);
1202 if (host) {
1203 clk_prepare_enable(host->clk);
1204 fsmc_nand_setup(host->regs_va, host->bank,
1205 host->nand.options & NAND_BUSWIDTH_16,
1206 host->dev_timings);
1207 }
1208 return 0;
1209 }
1210
1211 static SIMPLE_DEV_PM_OPS(fsmc_nand_pm_ops, fsmc_nand_suspend, fsmc_nand_resume);
1212 #endif
1213
1214 #ifdef CONFIG_OF
1215 static const struct of_device_id fsmc_nand_id_table[] = {
1216 { .compatible = "st,spear600-fsmc-nand" },
1217 {}
1218 };
1219 MODULE_DEVICE_TABLE(of, fsmc_nand_id_table);
1220 #endif
1221
1222 static struct platform_driver fsmc_nand_driver = {
1223 .remove = fsmc_nand_remove,
1224 .driver = {
1225 .owner = THIS_MODULE,
1226 .name = "fsmc-nand",
1227 .of_match_table = of_match_ptr(fsmc_nand_id_table),
1228 #ifdef CONFIG_PM
1229 .pm = &fsmc_nand_pm_ops,
1230 #endif
1231 },
1232 };
1233
1234 static int __init fsmc_nand_init(void)
1235 {
1236 return platform_driver_probe(&fsmc_nand_driver,
1237 fsmc_nand_probe);
1238 }
1239 module_init(fsmc_nand_init);
1240
1241 static void __exit fsmc_nand_exit(void)
1242 {
1243 platform_driver_unregister(&fsmc_nand_driver);
1244 }
1245 module_exit(fsmc_nand_exit);
1246
1247 MODULE_LICENSE("GPL");
1248 MODULE_AUTHOR("Vipin Kumar <vipin.kumar@st.com>, Ashish Priyadarshi");
1249 MODULE_DESCRIPTION("NAND driver for SPEAr Platforms");
Linus' kernel tree