arch/arm/boot/dts/spear320.dtsi

   1 /*
   2  * DTS file for SPEAr320 SoC
   3  *
   4  * Copyright 2012 Viresh Kumar <viresh.linux@gmail.com>
   5  *
   6  * The code contained herein is licensed under the GNU General Public
   7  * License. You may obtain a copy of the GNU General Public License
   8  * Version 2 or later at the following locations:
   9  *
  10  * http://www.opensource.org/licenses/gpl-license.html
  11  * http://www.gnu.org/copyleft/gpl.html
  12  */
  13
  14 /include/ "spear3xx.dtsi"
  15
  16 / {
  17         ahb {
  18                 #address-cells = <1>;
  19                 #size-cells = <1>;
  20                 compatible = "simple-bus";
  21                 ranges = <0x40000000 0x40000000 0x80000000
  22                           0xd0000000 0xd0000000 0x30000000>;
  23
  24                 pinmux@b3000000 {
  25                         compatible = "st,spear320-pinmux";
  26                         reg = <0xb3000000 0x1000>;
  27                 };
  28
  29                 clcd@90000000 {
  30                         compatible = "arm,clcd-pl110", "arm,primecell";
  31                         reg = <0x90000000 0x1000>;
  32                         interrupts = <33>;
  33                         status = "disabled";
  34                 };
  35
  36                 fsmc: flash@4c000000 {
  37                         compatible = "st,spear600-fsmc-nand";
  38                         #address-cells = <1>;
  39                         #size-cells = <1>;
  40                         reg = <0x4c000000 0x1000        /* FSMC Register */
  41                                0x50000000 0x0010        /* NAND Base DATA */
  42                                0x50020000 0x0010        /* NAND Base ADDR */
  43                                0x50010000 0x0010>;      /* NAND Base CMD */
  44                         reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
  45                         status = "disabled";
  46                 };
  47
  48                 sdhci@70000000 {
  49                         compatible = "st,sdhci-spear";
  50                         reg = <0x70000000 0x100>;
  51                         interrupts = <29>;
  52                         status = "disabled";
  53                 };
  54
  55                 spi1: spi@a5000000 {
  56                         compatible = "arm,pl022", "arm,primecell";
  57                         reg = <0xa5000000 0x1000>;
  58                         status = "disabled";
  59                 };
  60
  61                 spi2: spi@a6000000 {
  62                         compatible = "arm,pl022", "arm,primecell";
  63                         reg = <0xa6000000 0x1000>;
  64                         status = "disabled";
  65                 };
  66
  67                 apb {
  68                         #address-cells = <1>;
  69                         #size-cells = <1>;
  70                         compatible = "simple-bus";
  71                         ranges = <0xa0000000 0xa0000000 0x10000000
  72                                   0xd0000000 0xd0000000 0x30000000>;
  73
  74                         i2c1: i2c@a7000000 {
  75                                 #address-cells = <1>;
  76                                 #size-cells = <0>;
  77                                 compatible = "snps,designware-i2c";
  78                                 reg = <0xa7000000 0x1000>;
  79                                 status = "disabled";
  80                         };
  81
  82                         serial@a3000000 {
  83                                 compatible = "arm,pl011", "arm,primecell";
  84                                 reg = <0xa3000000 0x1000>;
  85                                 status = "disabled";
  86                         };
  87
  88                         serial@a4000000 {
  89                                 compatible = "arm,pl011", "arm,primecell";
  90                                 reg = <0xa4000000 0x1000>;
  91                                 status = "disabled";
  92                         };
  93                 };
  94         };
  95 };