2 * Copyright (C) 1994 Linus Torvalds
4 * Pentium III FXSR, SSE support
5 * General FPU state handling cleanups
6 * Gareth Hughes <gareth@valinux.com>, May 2000
7 * x86-64 work by Andi Kleen 2002
10 #ifndef _ASM_X86_I387_H
11 #define _ASM_X86_I387_H
15 #include <linux/sched.h>
16 #include <linux/kernel_stat.h>
17 #include <linux/regset.h>
18 #include <linux/hardirq.h>
19 #include <linux/slab.h>
21 #include <asm/cpufeature.h>
22 #include <asm/processor.h>
23 #include <asm/sigcontext.h>
25 #include <asm/uaccess.h>
26 #include <asm/xsave.h>
28 extern unsigned int sig_xstate_size
;
29 extern void fpu_init(void);
30 extern void mxcsr_feature_mask_init(void);
31 extern int init_fpu(struct task_struct
*child
);
32 extern void math_state_restore(void);
33 extern void __math_state_restore(void);
34 extern int dump_fpu(struct pt_regs
*, struct user_i387_struct
*);
36 extern user_regset_active_fn fpregs_active
, xfpregs_active
;
37 extern user_regset_get_fn fpregs_get
, xfpregs_get
, fpregs_soft_get
,
39 extern user_regset_set_fn fpregs_set
, xfpregs_set
, fpregs_soft_set
,
43 * xstateregs_active == fpregs_active. Please refer to the comment
44 * at the definition of fpregs_active.
46 #define xstateregs_active fpregs_active
48 extern struct _fpx_sw_bytes fx_sw_reserved
;
49 #ifdef CONFIG_IA32_EMULATION
50 extern unsigned int sig_xstate_ia32_size
;
51 extern struct _fpx_sw_bytes fx_sw_reserved_ia32
;
54 extern int save_i387_xstate_ia32(void __user
*buf
);
55 extern int restore_i387_xstate_ia32(void __user
*buf
);
58 #ifdef CONFIG_MATH_EMULATION
59 extern void finit_soft_fpu(struct i387_soft_struct
*soft
);
61 static inline void finit_soft_fpu(struct i387_soft_struct
*soft
) {}
64 #define X87_FSW_ES (1 << 7) /* Exception Summary */
66 static __always_inline __pure
bool use_xsaveopt(void)
68 return static_cpu_has(X86_FEATURE_XSAVEOPT
);
71 static __always_inline __pure
bool use_xsave(void)
73 return static_cpu_has(X86_FEATURE_XSAVE
);
76 static __always_inline __pure
bool use_fxsr(void)
78 return static_cpu_has(X86_FEATURE_FXSR
);
81 extern void __sanitize_i387_state(struct task_struct
*);
83 static inline void sanitize_i387_state(struct task_struct
*tsk
)
87 __sanitize_i387_state(tsk
);
91 static inline int fxrstor_checking(struct i387_fxsave_struct
*fx
)
95 /* See comment in fxsave() below. */
96 #ifdef CONFIG_AS_FXSAVEQ
97 asm volatile("1: fxrstorq %[fx]\n\t"
99 ".section .fixup,\"ax\"\n"
100 "3: movl $-1,%[err]\n"
105 : [fx
] "m" (*fx
), "0" (0));
107 asm volatile("1: rex64/fxrstor (%[fx])\n\t"
109 ".section .fixup,\"ax\"\n"
110 "3: movl $-1,%[err]\n"
115 : [fx
] "R" (fx
), "m" (*fx
), "0" (0));
120 static inline int fxsave_user(struct i387_fxsave_struct __user
*fx
)
125 * Clear the bytes not touched by the fxsave and reserved
128 err
= __clear_user(&fx
->sw_reserved
,
129 sizeof(struct _fpx_sw_bytes
));
133 /* See comment in fxsave() below. */
134 #ifdef CONFIG_AS_FXSAVEQ
135 asm volatile("1: fxsaveq %[fx]\n\t"
137 ".section .fixup,\"ax\"\n"
138 "3: movl $-1,%[err]\n"
142 : [err
] "=r" (err
), [fx
] "=m" (*fx
)
145 asm volatile("1: rex64/fxsave (%[fx])\n\t"
147 ".section .fixup,\"ax\"\n"
148 "3: movl $-1,%[err]\n"
152 : [err
] "=r" (err
), "=m" (*fx
)
153 : [fx
] "R" (fx
), "0" (0));
156 __clear_user(fx
, sizeof(struct i387_fxsave_struct
)))
158 /* No need to clear here because the caller clears USED_MATH */
162 static inline void fpu_fxsave(struct fpu
*fpu
)
164 /* Using "rex64; fxsave %0" is broken because, if the memory operand
165 uses any extended registers for addressing, a second REX prefix
166 will be generated (to the assembler, rex64 followed by semicolon
167 is a separate instruction), and hence the 64-bitness is lost. */
169 #ifdef CONFIG_AS_FXSAVEQ
170 /* Using "fxsaveq %0" would be the ideal choice, but is only supported
171 starting with gas 2.16. */
172 __asm__
__volatile__("fxsaveq %0"
173 : "=m" (fpu
->state
->fxsave
));
175 /* Using, as a workaround, the properly prefixed form below isn't
176 accepted by any binutils version so far released, complaining that
177 the same type of prefix is used twice if an extended register is
178 needed for addressing (fix submitted to mainline 2005-11-21).
179 asm volatile("rex64/fxsave %0"
180 : "=m" (fpu->state->fxsave));
181 This, however, we can work around by forcing the compiler to select
182 an addressing mode that doesn't require extended registers. */
183 asm volatile("rex64/fxsave (%[fx])"
184 : "=m" (fpu
->state
->fxsave
)
185 : [fx
] "R" (&fpu
->state
->fxsave
));
189 #else /* CONFIG_X86_32 */
191 /* perform fxrstor iff the processor has extended states, otherwise frstor */
192 static inline int fxrstor_checking(struct i387_fxsave_struct
*fx
)
195 * The "nop" is needed to make the instructions the same
207 static inline void fpu_fxsave(struct fpu
*fpu
)
209 asm volatile("fxsave %[fx]"
210 : [fx
] "=m" (fpu
->state
->fxsave
));
213 #endif /* CONFIG_X86_64 */
215 /* We need a safe address that is cheap to find and that is already
216 in L1 during context switch. The best choices are unfortunately
217 different for UP and SMP */
219 #define safe_address (__per_cpu_offset[0])
221 #define safe_address (__get_cpu_var(kernel_cpustat).cpustat[CPUTIME_USER])
225 * These must be called with preempt disabled
227 static inline void fpu_save_init(struct fpu
*fpu
)
233 * xsave header may indicate the init state of the FP.
235 if (!(fpu
->state
->xsave
.xsave_hdr
.xstate_bv
& XSTATE_FP
))
237 } else if (use_fxsr()) {
240 asm volatile("fnsave %[fx]; fwait"
241 : [fx
] "=m" (fpu
->state
->fsave
));
245 if (unlikely(fpu
->state
->fxsave
.swd
& X87_FSW_ES
))
246 asm volatile("fnclex");
248 /* AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception
249 is pending. Clear the x87 state here by setting it to fixed
250 values. safe_address is a random variable that should be in L1 */
253 "emms\n\t" /* clear stack tags */
254 "fildl %P[addr]", /* set F?P to defined value */
255 X86_FEATURE_FXSAVE_LEAK
,
256 [addr
] "m" (safe_address
));
259 static inline void __save_init_fpu(struct task_struct
*tsk
)
261 fpu_save_init(&tsk
->thread
.fpu
);
264 static inline int fpu_fxrstor_checking(struct fpu
*fpu
)
266 return fxrstor_checking(&fpu
->state
->fxsave
);
269 static inline int fpu_restore_checking(struct fpu
*fpu
)
272 return fpu_xrstor_checking(fpu
);
274 return fpu_fxrstor_checking(fpu
);
277 static inline int restore_fpu_checking(struct task_struct
*tsk
)
279 return fpu_restore_checking(&tsk
->thread
.fpu
);
283 * Software FPU state helpers. Careful: these need to
284 * be preemption protection *and* they need to be
285 * properly paired with the CR0.TS changes!
287 static inline int __thread_has_fpu(struct thread_info
*ti
)
289 return ti
->status
& TS_USEDFPU
;
292 /* Must be paired with an 'stts' after! */
293 static inline void __thread_clear_has_fpu(struct thread_info
*ti
)
295 ti
->status
&= ~TS_USEDFPU
;
298 /* Must be paired with a 'clts' before! */
299 static inline void __thread_set_has_fpu(struct thread_info
*ti
)
301 ti
->status
|= TS_USEDFPU
;
305 * Encapsulate the CR0.TS handling together with the
308 * These generally need preemption protection to work,
309 * do try to avoid using these on their own.
311 static inline void __thread_fpu_end(struct thread_info
*ti
)
313 __thread_clear_has_fpu(ti
);
317 static inline void __thread_fpu_begin(struct thread_info
*ti
)
320 __thread_set_has_fpu(ti
);
324 * Signal frame handlers...
326 extern int save_i387_xstate(void __user
*buf
);
327 extern int restore_i387_xstate(void __user
*buf
);
329 static inline void __unlazy_fpu(struct task_struct
*tsk
)
331 if (__thread_has_fpu(task_thread_info(tsk
))) {
332 __save_init_fpu(tsk
);
333 __thread_fpu_end(task_thread_info(tsk
));
335 tsk
->fpu_counter
= 0;
338 static inline void __clear_fpu(struct task_struct
*tsk
)
340 if (__thread_has_fpu(task_thread_info(tsk
))) {
341 /* Ignore delayed exceptions from user space */
342 asm volatile("1: fwait\n"
344 _ASM_EXTABLE(1b
, 2b
));
345 __thread_fpu_end(task_thread_info(tsk
));
350 * Were we in an interrupt that interrupted kernel mode?
352 * We can do a kernel_fpu_begin/end() pair *ONLY* if that
353 * pair does nothing at all: the thread must not have fpu (so
354 * that we don't try to save the FPU state), and TS must
355 * be set (so that the clts/stts pair does nothing that is
356 * visible in the interrupted kernel thread).
358 static inline bool interrupted_kernel_fpu_idle(void)
360 return !__thread_has_fpu(current_thread_info()) &&
361 (read_cr0() & X86_CR0_TS
);
365 * Were we in user mode (or vm86 mode) when we were
368 * Doing kernel_fpu_begin/end() is ok if we are running
369 * in an interrupt context from user mode - we'll just
370 * save the FPU state as required.
372 static inline bool interrupted_user_mode(void)
374 struct pt_regs
*regs
= get_irq_regs();
375 return regs
&& user_mode_vm(regs
);
379 * Can we use the FPU in kernel mode with the
380 * whole "kernel_fpu_begin/end()" sequence?
382 * It's always ok in process context (ie "not interrupt")
383 * but it is sometimes ok even from an irq.
385 static inline bool irq_fpu_usable(void)
387 return !in_interrupt() ||
388 interrupted_user_mode() ||
389 interrupted_kernel_fpu_idle();
392 static inline void kernel_fpu_begin(void)
394 struct thread_info
*me
= current_thread_info();
396 WARN_ON_ONCE(!irq_fpu_usable());
398 if (__thread_has_fpu(me
)) {
399 __save_init_fpu(me
->task
);
400 __thread_clear_has_fpu(me
);
401 /* We do 'stts()' in kernel_fpu_end() */
406 static inline void kernel_fpu_end(void)
413 * Some instructions like VIA's padlock instructions generate a spurious
414 * DNA fault but don't modify SSE registers. And these instructions
415 * get used from interrupt context as well. To prevent these kernel instructions
416 * in interrupt context interacting wrongly with other user/kernel fpu usage, we
417 * should use them only in the context of irq_ts_save/restore()
419 static inline int irq_ts_save(void)
422 * If in process context and not atomic, we can take a spurious DNA fault.
423 * Otherwise, doing clts() in process context requires disabling preemption
424 * or some heavy lifting like kernel_fpu_begin()
429 if (read_cr0() & X86_CR0_TS
) {
437 static inline void irq_ts_restore(int TS_state
)
444 * The question "does this thread have fpu access?"
445 * is slightly racy, since preemption could come in
446 * and revoke it immediately after the test.
448 * However, even in that very unlikely scenario,
449 * we can just assume we have FPU access - typically
450 * to save the FP state - we'll just take a #NM
451 * fault and get the FPU access back.
453 * The actual user_fpu_begin/end() functions
454 * need to be preemption-safe, though.
456 * NOTE! user_fpu_end() must be used only after you
457 * have saved the FP state, and user_fpu_begin() must
458 * be used only immediately before restoring it.
459 * These functions do not do any save/restore on
462 static inline int user_has_fpu(void)
464 return __thread_has_fpu(current_thread_info());
467 static inline void user_fpu_end(void)
470 __thread_fpu_end(current_thread_info());
474 static inline void user_fpu_begin(void)
478 __thread_fpu_begin(current_thread_info());
483 * These disable preemption on their own and are safe
485 static inline void save_init_fpu(struct task_struct
*tsk
)
487 WARN_ON_ONCE(!__thread_has_fpu(task_thread_info(tsk
)));
489 __save_init_fpu(tsk
);
490 __thread_fpu_end(task_thread_info(tsk
));
494 static inline void unlazy_fpu(struct task_struct
*tsk
)
501 static inline void clear_fpu(struct task_struct
*tsk
)
509 * i387 state interaction
511 static inline unsigned short get_fpu_cwd(struct task_struct
*tsk
)
514 return tsk
->thread
.fpu
.state
->fxsave
.cwd
;
516 return (unsigned short)tsk
->thread
.fpu
.state
->fsave
.cwd
;
520 static inline unsigned short get_fpu_swd(struct task_struct
*tsk
)
523 return tsk
->thread
.fpu
.state
->fxsave
.swd
;
525 return (unsigned short)tsk
->thread
.fpu
.state
->fsave
.swd
;
529 static inline unsigned short get_fpu_mxcsr(struct task_struct
*tsk
)
532 return tsk
->thread
.fpu
.state
->fxsave
.mxcsr
;
534 return MXCSR_DEFAULT
;
538 static bool fpu_allocated(struct fpu
*fpu
)
540 return fpu
->state
!= NULL
;
543 static inline int fpu_alloc(struct fpu
*fpu
)
545 if (fpu_allocated(fpu
))
547 fpu
->state
= kmem_cache_alloc(task_xstate_cachep
, GFP_KERNEL
);
550 WARN_ON((unsigned long)fpu
->state
& 15);
554 static inline void fpu_free(struct fpu
*fpu
)
557 kmem_cache_free(task_xstate_cachep
, fpu
->state
);
562 static inline void fpu_copy(struct fpu
*dst
, struct fpu
*src
)
564 memcpy(dst
->state
, src
->state
, xstate_size
);
567 extern void fpu_finit(struct fpu
*fpu
);
569 #endif /* __ASSEMBLY__ */
571 #endif /* _ASM_X86_I387_H */