1 /* linux/drivers/usb/gadget/s3c-hsotg.c
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
8 * S3C USB2.0 High-speed / OtG driver
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/spinlock.h>
20 #include <linux/interrupt.h>
21 #include <linux/platform_device.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/debugfs.h>
24 #include <linux/seq_file.h>
25 #include <linux/delay.h>
27 #include <linux/slab.h>
29 #include <linux/usb/ch9.h>
30 #include <linux/usb/gadget.h>
34 #include <plat/regs-usb-hsotg-phy.h>
35 #include <plat/regs-usb-hsotg.h>
36 #include <mach/regs-sys.h>
37 #include <plat/udc-hs.h>
39 #define DMA_ADDR_INVALID (~((dma_addr_t)0))
43 * Unfortunately there seems to be a limit of the amount of data that can
44 * be transfered by IN transactions on EP0. This is either 127 bytes or 3
45 * packets (which practially means 1 packet and 63 bytes of data) when the
48 * This means if we are wanting to move >127 bytes of data, we need to
49 * split the transactions up, but just doing one packet at a time does
50 * not work (this may be an implicit DATA0 PID on first packet of the
51 * transaction) and doing 2 packets is outside the controller's limits.
53 * If we try to lower the MPS size for EP0, then no transfers work properly
54 * for EP0, and the system will fail basic enumeration. As no cause for this
55 * has currently been found, we cannot support any large IN transfers for
58 #define EP0_MPS_LIMIT 64
64 * struct s3c_hsotg_ep - driver endpoint definition.
65 * @ep: The gadget layer representation of the endpoint.
66 * @name: The driver generated name for the endpoint.
67 * @queue: Queue of requests for this endpoint.
68 * @parent: Reference back to the parent device structure.
69 * @req: The current request that the endpoint is processing. This is
70 * used to indicate an request has been loaded onto the endpoint
71 * and has yet to be completed (maybe due to data move, or simply
72 * awaiting an ack from the core all the data has been completed).
73 * @debugfs: File entry for debugfs file for this endpoint.
74 * @lock: State lock to protect contents of endpoint.
75 * @dir_in: Set to true if this endpoint is of the IN direction, which
76 * means that it is sending data to the Host.
77 * @index: The index for the endpoint registers.
78 * @name: The name array passed to the USB core.
79 * @halted: Set if the endpoint has been halted.
80 * @periodic: Set if this is a periodic ep, such as Interrupt
81 * @sent_zlp: Set if we've sent a zero-length packet.
82 * @total_data: The total number of data bytes done.
83 * @fifo_size: The size of the FIFO (for periodic IN endpoints)
84 * @fifo_load: The amount of data loaded into the FIFO (periodic IN)
85 * @last_load: The offset of data for the last start of request.
86 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN
88 * This is the driver's state for each registered enpoint, allowing it
89 * to keep track of transactions that need doing. Each endpoint has a
90 * lock to protect the state, to try and avoid using an overall lock
91 * for the host controller as much as possible.
93 * For periodic IN endpoints, we have fifo_size and fifo_load to try
94 * and keep track of the amount of data in the periodic FIFO for each
95 * of these as we don't have a status register that tells us how much
96 * is in each of them. (note, this may actually be useless information
97 * as in shared-fifo mode periodic in acts like a single-frame packet
100 struct s3c_hsotg_ep
{
102 struct list_head queue
;
103 struct s3c_hsotg
*parent
;
104 struct s3c_hsotg_req
*req
;
105 struct dentry
*debugfs
;
109 unsigned long total_data
;
110 unsigned int size_loaded
;
111 unsigned int last_load
;
112 unsigned int fifo_load
;
113 unsigned short fifo_size
;
115 unsigned char dir_in
;
118 unsigned int halted
:1;
119 unsigned int periodic
:1;
120 unsigned int sent_zlp
:1;
125 #define S3C_HSOTG_EPS (8+1) /* limit to 9 for the moment */
128 * struct s3c_hsotg - driver state.
129 * @dev: The parent device supplied to the probe function
130 * @driver: USB gadget driver
131 * @plat: The platform specific configuration data.
132 * @regs: The memory area mapped for accessing registers.
133 * @regs_res: The resource that was allocated when claiming register space.
134 * @irq: The IRQ number we are using
135 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos.
136 * @debug_root: root directrory for debugfs.
137 * @debug_file: main status file for debugfs.
138 * @debug_fifo: FIFO status file for debugfs.
139 * @ep0_reply: Request used for ep0 reply.
140 * @ep0_buff: Buffer for EP0 reply data, if needed.
141 * @ctrl_buff: Buffer for EP0 control requests.
142 * @ctrl_req: Request for EP0 control packets.
143 * @eps: The endpoints being supplied to the gadget framework
147 struct usb_gadget_driver
*driver
;
148 struct s3c_hsotg_plat
*plat
;
151 struct resource
*regs_res
;
154 unsigned int dedicated_fifos
:1;
156 struct dentry
*debug_root
;
157 struct dentry
*debug_file
;
158 struct dentry
*debug_fifo
;
160 struct usb_request
*ep0_reply
;
161 struct usb_request
*ctrl_req
;
165 struct usb_gadget gadget
;
166 struct s3c_hsotg_ep eps
[];
170 * struct s3c_hsotg_req - data transfer request
171 * @req: The USB gadget request
172 * @queue: The list of requests for the endpoint this is queued for.
173 * @in_progress: Has already had size/packets written to core
174 * @mapped: DMA buffer for this request has been mapped via dma_map_single().
176 struct s3c_hsotg_req
{
177 struct usb_request req
;
178 struct list_head queue
;
179 unsigned char in_progress
;
180 unsigned char mapped
;
183 /* conversion functions */
184 static inline struct s3c_hsotg_req
*our_req(struct usb_request
*req
)
186 return container_of(req
, struct s3c_hsotg_req
, req
);
189 static inline struct s3c_hsotg_ep
*our_ep(struct usb_ep
*ep
)
191 return container_of(ep
, struct s3c_hsotg_ep
, ep
);
194 static inline struct s3c_hsotg
*to_hsotg(struct usb_gadget
*gadget
)
196 return container_of(gadget
, struct s3c_hsotg
, gadget
);
199 static inline void __orr32(void __iomem
*ptr
, u32 val
)
201 writel(readl(ptr
) | val
, ptr
);
204 static inline void __bic32(void __iomem
*ptr
, u32 val
)
206 writel(readl(ptr
) & ~val
, ptr
);
209 /* forward decleration of functions */
210 static void s3c_hsotg_dump(struct s3c_hsotg
*hsotg
);
213 * using_dma - return the DMA status of the driver.
214 * @hsotg: The driver state.
216 * Return true if we're using DMA.
218 * Currently, we have the DMA support code worked into everywhere
219 * that needs it, but the AMBA DMA implementation in the hardware can
220 * only DMA from 32bit aligned addresses. This means that gadgets such
221 * as the CDC Ethernet cannot work as they often pass packets which are
224 * Unfortunately the choice to use DMA or not is global to the controller
225 * and seems to be only settable when the controller is being put through
226 * a core reset. This means we either need to fix the gadgets to take
227 * account of DMA alignment, or add bounce buffers (yuerk).
229 * Until this issue is sorted out, we always return 'false'.
231 static inline bool using_dma(struct s3c_hsotg
*hsotg
)
233 return false; /* support is not complete */
237 * s3c_hsotg_en_gsint - enable one or more of the general interrupt
238 * @hsotg: The device state
239 * @ints: A bitmask of the interrupts to enable
241 static void s3c_hsotg_en_gsint(struct s3c_hsotg
*hsotg
, u32 ints
)
243 u32 gsintmsk
= readl(hsotg
->regs
+ S3C_GINTMSK
);
246 new_gsintmsk
= gsintmsk
| ints
;
248 if (new_gsintmsk
!= gsintmsk
) {
249 dev_dbg(hsotg
->dev
, "gsintmsk now 0x%08x\n", new_gsintmsk
);
250 writel(new_gsintmsk
, hsotg
->regs
+ S3C_GINTMSK
);
255 * s3c_hsotg_disable_gsint - disable one or more of the general interrupt
256 * @hsotg: The device state
257 * @ints: A bitmask of the interrupts to enable
259 static void s3c_hsotg_disable_gsint(struct s3c_hsotg
*hsotg
, u32 ints
)
261 u32 gsintmsk
= readl(hsotg
->regs
+ S3C_GINTMSK
);
264 new_gsintmsk
= gsintmsk
& ~ints
;
266 if (new_gsintmsk
!= gsintmsk
)
267 writel(new_gsintmsk
, hsotg
->regs
+ S3C_GINTMSK
);
271 * s3c_hsotg_ctrl_epint - enable/disable an endpoint irq
272 * @hsotg: The device state
273 * @ep: The endpoint index
274 * @dir_in: True if direction is in.
275 * @en: The enable value, true to enable
277 * Set or clear the mask for an individual endpoint's interrupt
280 static void s3c_hsotg_ctrl_epint(struct s3c_hsotg
*hsotg
,
281 unsigned int ep
, unsigned int dir_in
,
291 local_irq_save(flags
);
292 daint
= readl(hsotg
->regs
+ S3C_DAINTMSK
);
297 writel(daint
, hsotg
->regs
+ S3C_DAINTMSK
);
298 local_irq_restore(flags
);
302 * s3c_hsotg_init_fifo - initialise non-periodic FIFOs
303 * @hsotg: The device instance.
305 static void s3c_hsotg_init_fifo(struct s3c_hsotg
*hsotg
)
313 /* the ryu 2.6.24 release ahs
314 writel(0x1C0, hsotg->regs + S3C_GRXFSIZ);
315 writel(S3C_GNPTXFSIZ_NPTxFStAddr(0x200) |
316 S3C_GNPTXFSIZ_NPTxFDep(0x1C0),
317 hsotg->regs + S3C_GNPTXFSIZ);
320 /* set FIFO sizes to 2048/1024 */
322 writel(2048, hsotg
->regs
+ S3C_GRXFSIZ
);
323 writel(S3C_GNPTXFSIZ_NPTxFStAddr(2048) |
324 S3C_GNPTXFSIZ_NPTxFDep(1024),
325 hsotg
->regs
+ S3C_GNPTXFSIZ
);
327 /* arange all the rest of the TX FIFOs, as some versions of this
328 * block have overlapping default addresses. This also ensures
329 * that if the settings have been changed, then they are set to
332 /* start at the end of the GNPTXFSIZ, rounded up */
336 /* currently we allocate TX FIFOs for all possible endpoints,
337 * and assume that they are all the same size. */
339 for (ep
= 0; ep
<= 15; ep
++) {
341 val
|= size
<< S3C_DPTXFSIZn_DPTxFSize_SHIFT
;
344 writel(val
, hsotg
->regs
+ S3C_DPTXFSIZn(ep
));
347 /* according to p428 of the design guide, we need to ensure that
348 * all fifos are flushed before continuing */
350 writel(S3C_GRSTCTL_TxFNum(0x10) | S3C_GRSTCTL_TxFFlsh
|
351 S3C_GRSTCTL_RxFFlsh
, hsotg
->regs
+ S3C_GRSTCTL
);
353 /* wait until the fifos are both flushed */
356 val
= readl(hsotg
->regs
+ S3C_GRSTCTL
);
358 if ((val
& (S3C_GRSTCTL_TxFFlsh
| S3C_GRSTCTL_RxFFlsh
)) == 0)
361 if (--timeout
== 0) {
363 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
370 dev_dbg(hsotg
->dev
, "FIFOs reset, timeout at %d\n", timeout
);
374 * @ep: USB endpoint to allocate request for.
375 * @flags: Allocation flags
377 * Allocate a new USB request structure appropriate for the specified endpoint
379 static struct usb_request
*s3c_hsotg_ep_alloc_request(struct usb_ep
*ep
,
382 struct s3c_hsotg_req
*req
;
384 req
= kzalloc(sizeof(struct s3c_hsotg_req
), flags
);
388 INIT_LIST_HEAD(&req
->queue
);
390 req
->req
.dma
= DMA_ADDR_INVALID
;
395 * is_ep_periodic - return true if the endpoint is in periodic mode.
396 * @hs_ep: The endpoint to query.
398 * Returns true if the endpoint is in periodic mode, meaning it is being
399 * used for an Interrupt or ISO transfer.
401 static inline int is_ep_periodic(struct s3c_hsotg_ep
*hs_ep
)
403 return hs_ep
->periodic
;
407 * s3c_hsotg_unmap_dma - unmap the DMA memory being used for the request
408 * @hsotg: The device state.
409 * @hs_ep: The endpoint for the request
410 * @hs_req: The request being processed.
412 * This is the reverse of s3c_hsotg_map_dma(), called for the completion
413 * of a request to ensure the buffer is ready for access by the caller.
415 static void s3c_hsotg_unmap_dma(struct s3c_hsotg
*hsotg
,
416 struct s3c_hsotg_ep
*hs_ep
,
417 struct s3c_hsotg_req
*hs_req
)
419 struct usb_request
*req
= &hs_req
->req
;
420 enum dma_data_direction dir
;
422 dir
= hs_ep
->dir_in
? DMA_TO_DEVICE
: DMA_FROM_DEVICE
;
424 /* ignore this if we're not moving any data */
425 if (hs_req
->req
.length
== 0)
428 if (hs_req
->mapped
) {
429 /* we mapped this, so unmap and remove the dma */
431 dma_unmap_single(hsotg
->dev
, req
->dma
, req
->length
, dir
);
433 req
->dma
= DMA_ADDR_INVALID
;
436 dma_sync_single_for_cpu(hsotg
->dev
, req
->dma
, req
->length
, dir
);
441 * s3c_hsotg_write_fifo - write packet Data to the TxFIFO
442 * @hsotg: The controller state.
443 * @hs_ep: The endpoint we're going to write for.
444 * @hs_req: The request to write data for.
446 * This is called when the TxFIFO has some space in it to hold a new
447 * transmission and we have something to give it. The actual setup of
448 * the data size is done elsewhere, so all we have to do is to actually
451 * The return value is zero if there is more space (or nothing was done)
452 * otherwise -ENOSPC is returned if the FIFO space was used up.
454 * This routine is only needed for PIO
456 static int s3c_hsotg_write_fifo(struct s3c_hsotg
*hsotg
,
457 struct s3c_hsotg_ep
*hs_ep
,
458 struct s3c_hsotg_req
*hs_req
)
460 bool periodic
= is_ep_periodic(hs_ep
);
461 u32 gnptxsts
= readl(hsotg
->regs
+ S3C_GNPTXSTS
);
462 int buf_pos
= hs_req
->req
.actual
;
463 int to_write
= hs_ep
->size_loaded
;
468 to_write
-= (buf_pos
- hs_ep
->last_load
);
470 /* if there's nothing to write, get out early */
474 if (periodic
&& !hsotg
->dedicated_fifos
) {
475 u32 epsize
= readl(hsotg
->regs
+ S3C_DIEPTSIZ(hs_ep
->index
));
479 /* work out how much data was loaded so we can calculate
480 * how much data is left in the fifo. */
482 size_left
= S3C_DxEPTSIZ_XferSize_GET(epsize
);
484 /* if shared fifo, we cannot write anything until the
485 * previous data has been completely sent.
487 if (hs_ep
->fifo_load
!= 0) {
488 s3c_hsotg_en_gsint(hsotg
, S3C_GINTSTS_PTxFEmp
);
492 dev_dbg(hsotg
->dev
, "%s: left=%d, load=%d, fifo=%d, size %d\n",
494 hs_ep
->size_loaded
, hs_ep
->fifo_load
, hs_ep
->fifo_size
);
496 /* how much of the data has moved */
497 size_done
= hs_ep
->size_loaded
- size_left
;
499 /* how much data is left in the fifo */
500 can_write
= hs_ep
->fifo_load
- size_done
;
501 dev_dbg(hsotg
->dev
, "%s: => can_write1=%d\n",
502 __func__
, can_write
);
504 can_write
= hs_ep
->fifo_size
- can_write
;
505 dev_dbg(hsotg
->dev
, "%s: => can_write2=%d\n",
506 __func__
, can_write
);
508 if (can_write
<= 0) {
509 s3c_hsotg_en_gsint(hsotg
, S3C_GINTSTS_PTxFEmp
);
512 } else if (hsotg
->dedicated_fifos
&& hs_ep
->index
!= 0) {
513 can_write
= readl(hsotg
->regs
+ S3C_DTXFSTS(hs_ep
->index
));
518 if (S3C_GNPTXSTS_NPTxQSpcAvail_GET(gnptxsts
) == 0) {
520 "%s: no queue slots available (0x%08x)\n",
523 s3c_hsotg_en_gsint(hsotg
, S3C_GINTSTS_NPTxFEmp
);
527 can_write
= S3C_GNPTXSTS_NPTxFSpcAvail_GET(gnptxsts
);
528 can_write
*= 4; /* fifo size is in 32bit quantities. */
531 dev_dbg(hsotg
->dev
, "%s: GNPTXSTS=%08x, can=%d, to=%d, mps %d\n",
532 __func__
, gnptxsts
, can_write
, to_write
, hs_ep
->ep
.maxpacket
);
534 /* limit to 512 bytes of data, it seems at least on the non-periodic
535 * FIFO, requests of >512 cause the endpoint to get stuck with a
536 * fragment of the end of the transfer in it.
541 /* limit the write to one max-packet size worth of data, but allow
542 * the transfer to return that it did not run out of fifo space
544 if (to_write
> hs_ep
->ep
.maxpacket
) {
545 to_write
= hs_ep
->ep
.maxpacket
;
547 s3c_hsotg_en_gsint(hsotg
,
548 periodic
? S3C_GINTSTS_PTxFEmp
:
549 S3C_GINTSTS_NPTxFEmp
);
552 /* see if we can write data */
554 if (to_write
> can_write
) {
555 to_write
= can_write
;
556 pkt_round
= to_write
% hs_ep
->ep
.maxpacket
;
558 /* Not sure, but we probably shouldn't be writing partial
559 * packets into the FIFO, so round the write down to an
560 * exact number of packets.
562 * Note, we do not currently check to see if we can ever
563 * write a full packet or not to the FIFO.
567 to_write
-= pkt_round
;
569 /* enable correct FIFO interrupt to alert us when there
570 * is more room left. */
572 s3c_hsotg_en_gsint(hsotg
,
573 periodic
? S3C_GINTSTS_PTxFEmp
:
574 S3C_GINTSTS_NPTxFEmp
);
577 dev_dbg(hsotg
->dev
, "write %d/%d, can_write %d, done %d\n",
578 to_write
, hs_req
->req
.length
, can_write
, buf_pos
);
583 hs_req
->req
.actual
= buf_pos
+ to_write
;
584 hs_ep
->total_data
+= to_write
;
587 hs_ep
->fifo_load
+= to_write
;
589 to_write
= DIV_ROUND_UP(to_write
, 4);
590 data
= hs_req
->req
.buf
+ buf_pos
;
592 writesl(hsotg
->regs
+ S3C_EPFIFO(hs_ep
->index
), data
, to_write
);
594 return (to_write
>= can_write
) ? -ENOSPC
: 0;
598 * get_ep_limit - get the maximum data legnth for this endpoint
599 * @hs_ep: The endpoint
601 * Return the maximum data that can be queued in one go on a given endpoint
602 * so that transfers that are too long can be split.
604 static unsigned get_ep_limit(struct s3c_hsotg_ep
*hs_ep
)
606 int index
= hs_ep
->index
;
611 maxsize
= S3C_DxEPTSIZ_XferSize_LIMIT
+ 1;
612 maxpkt
= S3C_DxEPTSIZ_PktCnt_LIMIT
+ 1;
616 maxpkt
= S3C_DIEPTSIZ0_PktCnt_LIMIT
+ 1;
623 /* we made the constant loading easier above by using +1 */
627 /* constrain by packet count if maxpkts*pktsize is greater
628 * than the length register size. */
630 if ((maxpkt
* hs_ep
->ep
.maxpacket
) < maxsize
)
631 maxsize
= maxpkt
* hs_ep
->ep
.maxpacket
;
637 * s3c_hsotg_start_req - start a USB request from an endpoint's queue
638 * @hsotg: The controller state.
639 * @hs_ep: The endpoint to process a request for
640 * @hs_req: The request to start.
641 * @continuing: True if we are doing more for the current request.
643 * Start the given request running by setting the endpoint registers
644 * appropriately, and writing any data to the FIFOs.
646 static void s3c_hsotg_start_req(struct s3c_hsotg
*hsotg
,
647 struct s3c_hsotg_ep
*hs_ep
,
648 struct s3c_hsotg_req
*hs_req
,
651 struct usb_request
*ureq
= &hs_req
->req
;
652 int index
= hs_ep
->index
;
653 int dir_in
= hs_ep
->dir_in
;
663 if (hs_ep
->req
&& !continuing
) {
664 dev_err(hsotg
->dev
, "%s: active request\n", __func__
);
667 } else if (hs_ep
->req
!= hs_req
&& continuing
) {
669 "%s: continue different req\n", __func__
);
675 epctrl_reg
= dir_in
? S3C_DIEPCTL(index
) : S3C_DOEPCTL(index
);
676 epsize_reg
= dir_in
? S3C_DIEPTSIZ(index
) : S3C_DOEPTSIZ(index
);
678 dev_dbg(hsotg
->dev
, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
679 __func__
, readl(hsotg
->regs
+ epctrl_reg
), index
,
680 hs_ep
->dir_in
? "in" : "out");
682 length
= ureq
->length
- ureq
->actual
;
686 "REQ buf %p len %d dma 0x%08x noi=%d zp=%d snok=%d\n",
687 ureq
->buf
, length
, ureq
->dma
,
688 ureq
->no_interrupt
, ureq
->zero
, ureq
->short_not_ok
);
690 maxreq
= get_ep_limit(hs_ep
);
691 if (length
> maxreq
) {
692 int round
= maxreq
% hs_ep
->ep
.maxpacket
;
694 dev_dbg(hsotg
->dev
, "%s: length %d, max-req %d, r %d\n",
695 __func__
, length
, maxreq
, round
);
697 /* round down to multiple of packets */
705 packets
= DIV_ROUND_UP(length
, hs_ep
->ep
.maxpacket
);
707 packets
= 1; /* send one packet if length is zero. */
709 if (dir_in
&& index
!= 0)
710 epsize
= S3C_DxEPTSIZ_MC(1);
714 if (index
!= 0 && ureq
->zero
) {
715 /* test for the packets being exactly right for the
718 if (length
== (packets
* hs_ep
->ep
.maxpacket
))
722 epsize
|= S3C_DxEPTSIZ_PktCnt(packets
);
723 epsize
|= S3C_DxEPTSIZ_XferSize(length
);
725 dev_dbg(hsotg
->dev
, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
726 __func__
, packets
, length
, ureq
->length
, epsize
, epsize_reg
);
728 /* store the request as the current one we're doing */
731 /* write size / packets */
732 writel(epsize
, hsotg
->regs
+ epsize_reg
);
734 ctrl
= readl(hsotg
->regs
+ epctrl_reg
);
736 if (ctrl
& S3C_DxEPCTL_Stall
) {
737 dev_warn(hsotg
->dev
, "%s: ep%d is stalled\n", __func__
, index
);
739 /* not sure what we can do here, if it is EP0 then we should
740 * get this cleared once the endpoint has transmitted the
741 * STALL packet, otherwise it needs to be cleared by the
746 if (using_dma(hsotg
)) {
747 unsigned int dma_reg
;
749 /* write DMA address to control register, buffer already
750 * synced by s3c_hsotg_ep_queue(). */
752 dma_reg
= dir_in
? S3C_DIEPDMA(index
) : S3C_DOEPDMA(index
);
753 writel(ureq
->dma
, hsotg
->regs
+ dma_reg
);
755 dev_dbg(hsotg
->dev
, "%s: 0x%08x => 0x%08x\n",
756 __func__
, ureq
->dma
, dma_reg
);
759 ctrl
|= S3C_DxEPCTL_EPEna
; /* ensure ep enabled */
760 ctrl
|= S3C_DxEPCTL_USBActEp
;
761 ctrl
|= S3C_DxEPCTL_CNAK
; /* clear NAK set by core */
763 dev_dbg(hsotg
->dev
, "%s: DxEPCTL=0x%08x\n", __func__
, ctrl
);
764 writel(ctrl
, hsotg
->regs
+ epctrl_reg
);
766 /* set these, it seems that DMA support increments past the end
767 * of the packet buffer so we need to calculate the length from
768 * this information. */
769 hs_ep
->size_loaded
= length
;
770 hs_ep
->last_load
= ureq
->actual
;
772 if (dir_in
&& !using_dma(hsotg
)) {
773 /* set these anyway, we may need them for non-periodic in */
774 hs_ep
->fifo_load
= 0;
776 s3c_hsotg_write_fifo(hsotg
, hs_ep
, hs_req
);
779 /* clear the INTknTXFEmpMsk when we start request, more as a aide
780 * to debugging to see what is going on. */
782 writel(S3C_DIEPMSK_INTknTXFEmpMsk
,
783 hsotg
->regs
+ S3C_DIEPINT(index
));
785 /* Note, trying to clear the NAK here causes problems with transmit
786 * on the S3C6400 ending up with the TXFIFO becomming full. */
788 /* check ep is enabled */
789 if (!(readl(hsotg
->regs
+ epctrl_reg
) & S3C_DxEPCTL_EPEna
))
791 "ep%d: failed to become enabled (DxEPCTL=0x%08x)?\n",
792 index
, readl(hsotg
->regs
+ epctrl_reg
));
794 dev_dbg(hsotg
->dev
, "%s: DxEPCTL=0x%08x\n",
795 __func__
, readl(hsotg
->regs
+ epctrl_reg
));
799 * s3c_hsotg_map_dma - map the DMA memory being used for the request
800 * @hsotg: The device state.
801 * @hs_ep: The endpoint the request is on.
802 * @req: The request being processed.
804 * We've been asked to queue a request, so ensure that the memory buffer
805 * is correctly setup for DMA. If we've been passed an extant DMA address
806 * then ensure the buffer has been synced to memory. If our buffer has no
807 * DMA memory, then we map the memory and mark our request to allow us to
808 * cleanup on completion.
810 static int s3c_hsotg_map_dma(struct s3c_hsotg
*hsotg
,
811 struct s3c_hsotg_ep
*hs_ep
,
812 struct usb_request
*req
)
814 enum dma_data_direction dir
;
815 struct s3c_hsotg_req
*hs_req
= our_req(req
);
817 dir
= hs_ep
->dir_in
? DMA_TO_DEVICE
: DMA_FROM_DEVICE
;
819 /* if the length is zero, ignore the DMA data */
820 if (hs_req
->req
.length
== 0)
823 if (req
->dma
== DMA_ADDR_INVALID
) {
826 dma
= dma_map_single(hsotg
->dev
, req
->buf
, req
->length
, dir
);
828 if (unlikely(dma_mapping_error(hsotg
->dev
, dma
)))
832 dev_err(hsotg
->dev
, "%s: unaligned dma buffer\n",
835 dma_unmap_single(hsotg
->dev
, dma
, req
->length
, dir
);
842 dma_sync_single_for_cpu(hsotg
->dev
, req
->dma
, req
->length
, dir
);
849 dev_err(hsotg
->dev
, "%s: failed to map buffer %p, %d bytes\n",
850 __func__
, req
->buf
, req
->length
);
855 static int s3c_hsotg_ep_queue(struct usb_ep
*ep
, struct usb_request
*req
,
858 struct s3c_hsotg_req
*hs_req
= our_req(req
);
859 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
860 struct s3c_hsotg
*hs
= hs_ep
->parent
;
861 unsigned long irqflags
;
864 dev_dbg(hs
->dev
, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
865 ep
->name
, req
, req
->length
, req
->buf
, req
->no_interrupt
,
866 req
->zero
, req
->short_not_ok
);
868 /* initialise status of the request */
869 INIT_LIST_HEAD(&hs_req
->queue
);
871 req
->status
= -EINPROGRESS
;
873 /* if we're using DMA, sync the buffers as necessary */
875 int ret
= s3c_hsotg_map_dma(hs
, hs_ep
, req
);
880 spin_lock_irqsave(&hs_ep
->lock
, irqflags
);
882 first
= list_empty(&hs_ep
->queue
);
883 list_add_tail(&hs_req
->queue
, &hs_ep
->queue
);
886 s3c_hsotg_start_req(hs
, hs_ep
, hs_req
, false);
888 spin_unlock_irqrestore(&hs_ep
->lock
, irqflags
);
893 static void s3c_hsotg_ep_free_request(struct usb_ep
*ep
,
894 struct usb_request
*req
)
896 struct s3c_hsotg_req
*hs_req
= our_req(req
);
902 * s3c_hsotg_complete_oursetup - setup completion callback
903 * @ep: The endpoint the request was on.
904 * @req: The request completed.
906 * Called on completion of any requests the driver itself
907 * submitted that need cleaning up.
909 static void s3c_hsotg_complete_oursetup(struct usb_ep
*ep
,
910 struct usb_request
*req
)
912 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
913 struct s3c_hsotg
*hsotg
= hs_ep
->parent
;
915 dev_dbg(hsotg
->dev
, "%s: ep %p, req %p\n", __func__
, ep
, req
);
917 s3c_hsotg_ep_free_request(ep
, req
);
921 * ep_from_windex - convert control wIndex value to endpoint
922 * @hsotg: The driver state.
923 * @windex: The control request wIndex field (in host order).
925 * Convert the given wIndex into a pointer to an driver endpoint
926 * structure, or return NULL if it is not a valid endpoint.
928 static struct s3c_hsotg_ep
*ep_from_windex(struct s3c_hsotg
*hsotg
,
931 struct s3c_hsotg_ep
*ep
= &hsotg
->eps
[windex
& 0x7F];
932 int dir
= (windex
& USB_DIR_IN
) ? 1 : 0;
933 int idx
= windex
& 0x7F;
938 if (idx
> S3C_HSOTG_EPS
)
941 if (idx
&& ep
->dir_in
!= dir
)
948 * s3c_hsotg_send_reply - send reply to control request
949 * @hsotg: The device state
951 * @buff: Buffer for request
952 * @length: Length of reply.
954 * Create a request and queue it on the given endpoint. This is useful as
955 * an internal method of sending replies to certain control requests, etc.
957 static int s3c_hsotg_send_reply(struct s3c_hsotg
*hsotg
,
958 struct s3c_hsotg_ep
*ep
,
962 struct usb_request
*req
;
965 dev_dbg(hsotg
->dev
, "%s: buff %p, len %d\n", __func__
, buff
, length
);
967 req
= s3c_hsotg_ep_alloc_request(&ep
->ep
, GFP_ATOMIC
);
968 hsotg
->ep0_reply
= req
;
970 dev_warn(hsotg
->dev
, "%s: cannot alloc req\n", __func__
);
974 req
->buf
= hsotg
->ep0_buff
;
975 req
->length
= length
;
976 req
->zero
= 1; /* always do zero-length final transfer */
977 req
->complete
= s3c_hsotg_complete_oursetup
;
980 memcpy(req
->buf
, buff
, length
);
984 ret
= s3c_hsotg_ep_queue(&ep
->ep
, req
, GFP_ATOMIC
);
986 dev_warn(hsotg
->dev
, "%s: cannot queue req\n", __func__
);
994 * s3c_hsotg_process_req_status - process request GET_STATUS
995 * @hsotg: The device state
996 * @ctrl: USB control request
998 static int s3c_hsotg_process_req_status(struct s3c_hsotg
*hsotg
,
999 struct usb_ctrlrequest
*ctrl
)
1001 struct s3c_hsotg_ep
*ep0
= &hsotg
->eps
[0];
1002 struct s3c_hsotg_ep
*ep
;
1006 dev_dbg(hsotg
->dev
, "%s: USB_REQ_GET_STATUS\n", __func__
);
1009 dev_warn(hsotg
->dev
, "%s: direction out?\n", __func__
);
1013 switch (ctrl
->bRequestType
& USB_RECIP_MASK
) {
1014 case USB_RECIP_DEVICE
:
1015 reply
= cpu_to_le16(0); /* bit 0 => self powered,
1016 * bit 1 => remote wakeup */
1019 case USB_RECIP_INTERFACE
:
1020 /* currently, the data result should be zero */
1021 reply
= cpu_to_le16(0);
1024 case USB_RECIP_ENDPOINT
:
1025 ep
= ep_from_windex(hsotg
, le16_to_cpu(ctrl
->wIndex
));
1029 reply
= cpu_to_le16(ep
->halted
? 1 : 0);
1036 if (le16_to_cpu(ctrl
->wLength
) != 2)
1039 ret
= s3c_hsotg_send_reply(hsotg
, ep0
, &reply
, 2);
1041 dev_err(hsotg
->dev
, "%s: failed to send reply\n", __func__
);
1048 static int s3c_hsotg_ep_sethalt(struct usb_ep
*ep
, int value
);
1051 * s3c_hsotg_process_req_featire - process request {SET,CLEAR}_FEATURE
1052 * @hsotg: The device state
1053 * @ctrl: USB control request
1055 static int s3c_hsotg_process_req_feature(struct s3c_hsotg
*hsotg
,
1056 struct usb_ctrlrequest
*ctrl
)
1058 bool set
= (ctrl
->bRequest
== USB_REQ_SET_FEATURE
);
1059 struct s3c_hsotg_ep
*ep
;
1061 dev_dbg(hsotg
->dev
, "%s: %s_FEATURE\n",
1062 __func__
, set
? "SET" : "CLEAR");
1064 if (ctrl
->bRequestType
== USB_RECIP_ENDPOINT
) {
1065 ep
= ep_from_windex(hsotg
, le16_to_cpu(ctrl
->wIndex
));
1067 dev_dbg(hsotg
->dev
, "%s: no endpoint for 0x%04x\n",
1068 __func__
, le16_to_cpu(ctrl
->wIndex
));
1072 switch (le16_to_cpu(ctrl
->wValue
)) {
1073 case USB_ENDPOINT_HALT
:
1074 s3c_hsotg_ep_sethalt(&ep
->ep
, set
);
1081 return -ENOENT
; /* currently only deal with endpoint */
1087 * s3c_hsotg_process_control - process a control request
1088 * @hsotg: The device state
1089 * @ctrl: The control request received
1091 * The controller has received the SETUP phase of a control request, and
1092 * needs to work out what to do next (and whether to pass it on to the
1095 static void s3c_hsotg_process_control(struct s3c_hsotg
*hsotg
,
1096 struct usb_ctrlrequest
*ctrl
)
1098 struct s3c_hsotg_ep
*ep0
= &hsotg
->eps
[0];
1104 dev_dbg(hsotg
->dev
, "ctrl Req=%02x, Type=%02x, V=%04x, L=%04x\n",
1105 ctrl
->bRequest
, ctrl
->bRequestType
,
1106 ctrl
->wValue
, ctrl
->wLength
);
1108 /* record the direction of the request, for later use when enquing
1109 * packets onto EP0. */
1111 ep0
->dir_in
= (ctrl
->bRequestType
& USB_DIR_IN
) ? 1 : 0;
1112 dev_dbg(hsotg
->dev
, "ctrl: dir_in=%d\n", ep0
->dir_in
);
1114 /* if we've no data with this request, then the last part of the
1115 * transaction is going to implicitly be IN. */
1116 if (ctrl
->wLength
== 0)
1119 if ((ctrl
->bRequestType
& USB_TYPE_MASK
) == USB_TYPE_STANDARD
) {
1120 switch (ctrl
->bRequest
) {
1121 case USB_REQ_SET_ADDRESS
:
1122 dcfg
= readl(hsotg
->regs
+ S3C_DCFG
);
1123 dcfg
&= ~S3C_DCFG_DevAddr_MASK
;
1124 dcfg
|= ctrl
->wValue
<< S3C_DCFG_DevAddr_SHIFT
;
1125 writel(dcfg
, hsotg
->regs
+ S3C_DCFG
);
1127 dev_info(hsotg
->dev
, "new address %d\n", ctrl
->wValue
);
1129 ret
= s3c_hsotg_send_reply(hsotg
, ep0
, NULL
, 0);
1132 case USB_REQ_GET_STATUS
:
1133 ret
= s3c_hsotg_process_req_status(hsotg
, ctrl
);
1136 case USB_REQ_CLEAR_FEATURE
:
1137 case USB_REQ_SET_FEATURE
:
1138 ret
= s3c_hsotg_process_req_feature(hsotg
, ctrl
);
1143 /* as a fallback, try delivering it to the driver to deal with */
1145 if (ret
== 0 && hsotg
->driver
) {
1146 ret
= hsotg
->driver
->setup(&hsotg
->gadget
, ctrl
);
1148 dev_dbg(hsotg
->dev
, "driver->setup() ret %d\n", ret
);
1153 /* need to generate zlp in reply or take data */
1154 /* todo - deal with any data we might be sent? */
1155 ret
= s3c_hsotg_send_reply(hsotg
, ep0
, NULL
, 0);
1159 /* the request is either unhandlable, or is not formatted correctly
1160 * so respond with a STALL for the status stage to indicate failure.
1167 dev_dbg(hsotg
->dev
, "ep0 stall (dir=%d)\n", ep0
->dir_in
);
1168 reg
= (ep0
->dir_in
) ? S3C_DIEPCTL0
: S3C_DOEPCTL0
;
1170 /* S3C_DxEPCTL_Stall will be cleared by EP once it has
1171 * taken effect, so no need to clear later. */
1173 ctrl
= readl(hsotg
->regs
+ reg
);
1174 ctrl
|= S3C_DxEPCTL_Stall
;
1175 ctrl
|= S3C_DxEPCTL_CNAK
;
1176 writel(ctrl
, hsotg
->regs
+ reg
);
1179 "writen DxEPCTL=0x%08x to %08x (DxEPCTL=0x%08x)\n",
1180 ctrl
, reg
, readl(hsotg
->regs
+ reg
));
1182 /* don't belive we need to anything more to get the EP
1183 * to reply with a STALL packet */
1187 static void s3c_hsotg_enqueue_setup(struct s3c_hsotg
*hsotg
);
1190 * s3c_hsotg_complete_setup - completion of a setup transfer
1191 * @ep: The endpoint the request was on.
1192 * @req: The request completed.
1194 * Called on completion of any requests the driver itself submitted for
1197 static void s3c_hsotg_complete_setup(struct usb_ep
*ep
,
1198 struct usb_request
*req
)
1200 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
1201 struct s3c_hsotg
*hsotg
= hs_ep
->parent
;
1203 if (req
->status
< 0) {
1204 dev_dbg(hsotg
->dev
, "%s: failed %d\n", __func__
, req
->status
);
1208 if (req
->actual
== 0)
1209 s3c_hsotg_enqueue_setup(hsotg
);
1211 s3c_hsotg_process_control(hsotg
, req
->buf
);
1215 * s3c_hsotg_enqueue_setup - start a request for EP0 packets
1216 * @hsotg: The device state.
1218 * Enqueue a request on EP0 if necessary to received any SETUP packets
1219 * received from the host.
1221 static void s3c_hsotg_enqueue_setup(struct s3c_hsotg
*hsotg
)
1223 struct usb_request
*req
= hsotg
->ctrl_req
;
1224 struct s3c_hsotg_req
*hs_req
= our_req(req
);
1227 dev_dbg(hsotg
->dev
, "%s: queueing setup request\n", __func__
);
1231 req
->buf
= hsotg
->ctrl_buff
;
1232 req
->complete
= s3c_hsotg_complete_setup
;
1234 if (!list_empty(&hs_req
->queue
)) {
1235 dev_dbg(hsotg
->dev
, "%s already queued???\n", __func__
);
1239 hsotg
->eps
[0].dir_in
= 0;
1241 ret
= s3c_hsotg_ep_queue(&hsotg
->eps
[0].ep
, req
, GFP_ATOMIC
);
1243 dev_err(hsotg
->dev
, "%s: failed queue (%d)\n", __func__
, ret
);
1244 /* Don't think there's much we can do other than watch the
1250 * get_ep_head - return the first request on the endpoint
1251 * @hs_ep: The controller endpoint to get
1253 * Get the first request on the endpoint.
1255 static struct s3c_hsotg_req
*get_ep_head(struct s3c_hsotg_ep
*hs_ep
)
1257 if (list_empty(&hs_ep
->queue
))
1260 return list_first_entry(&hs_ep
->queue
, struct s3c_hsotg_req
, queue
);
1264 * s3c_hsotg_complete_request - complete a request given to us
1265 * @hsotg: The device state.
1266 * @hs_ep: The endpoint the request was on.
1267 * @hs_req: The request to complete.
1268 * @result: The result code (0 => Ok, otherwise errno)
1270 * The given request has finished, so call the necessary completion
1271 * if it has one and then look to see if we can start a new request
1274 * Note, expects the ep to already be locked as appropriate.
1276 static void s3c_hsotg_complete_request(struct s3c_hsotg
*hsotg
,
1277 struct s3c_hsotg_ep
*hs_ep
,
1278 struct s3c_hsotg_req
*hs_req
,
1284 dev_dbg(hsotg
->dev
, "%s: nothing to complete?\n", __func__
);
1288 dev_dbg(hsotg
->dev
, "complete: ep %p %s, req %p, %d => %p\n",
1289 hs_ep
, hs_ep
->ep
.name
, hs_req
, result
, hs_req
->req
.complete
);
1291 /* only replace the status if we've not already set an error
1292 * from a previous transaction */
1294 if (hs_req
->req
.status
== -EINPROGRESS
)
1295 hs_req
->req
.status
= result
;
1298 list_del_init(&hs_req
->queue
);
1300 if (using_dma(hsotg
))
1301 s3c_hsotg_unmap_dma(hsotg
, hs_ep
, hs_req
);
1303 /* call the complete request with the locks off, just in case the
1304 * request tries to queue more work for this endpoint. */
1306 if (hs_req
->req
.complete
) {
1307 spin_unlock(&hs_ep
->lock
);
1308 hs_req
->req
.complete(&hs_ep
->ep
, &hs_req
->req
);
1309 spin_lock(&hs_ep
->lock
);
1312 /* Look to see if there is anything else to do. Note, the completion
1313 * of the previous request may have caused a new request to be started
1314 * so be careful when doing this. */
1316 if (!hs_ep
->req
&& result
>= 0) {
1317 restart
= !list_empty(&hs_ep
->queue
);
1319 hs_req
= get_ep_head(hs_ep
);
1320 s3c_hsotg_start_req(hsotg
, hs_ep
, hs_req
, false);
1326 * s3c_hsotg_complete_request_lock - complete a request given to us (locked)
1327 * @hsotg: The device state.
1328 * @hs_ep: The endpoint the request was on.
1329 * @hs_req: The request to complete.
1330 * @result: The result code (0 => Ok, otherwise errno)
1332 * See s3c_hsotg_complete_request(), but called with the endpoint's
1335 static void s3c_hsotg_complete_request_lock(struct s3c_hsotg
*hsotg
,
1336 struct s3c_hsotg_ep
*hs_ep
,
1337 struct s3c_hsotg_req
*hs_req
,
1340 unsigned long flags
;
1342 spin_lock_irqsave(&hs_ep
->lock
, flags
);
1343 s3c_hsotg_complete_request(hsotg
, hs_ep
, hs_req
, result
);
1344 spin_unlock_irqrestore(&hs_ep
->lock
, flags
);
1348 * s3c_hsotg_rx_data - receive data from the FIFO for an endpoint
1349 * @hsotg: The device state.
1350 * @ep_idx: The endpoint index for the data
1351 * @size: The size of data in the fifo, in bytes
1353 * The FIFO status shows there is data to read from the FIFO for a given
1354 * endpoint, so sort out whether we need to read the data into a request
1355 * that has been made for that endpoint.
1357 static void s3c_hsotg_rx_data(struct s3c_hsotg
*hsotg
, int ep_idx
, int size
)
1359 struct s3c_hsotg_ep
*hs_ep
= &hsotg
->eps
[ep_idx
];
1360 struct s3c_hsotg_req
*hs_req
= hs_ep
->req
;
1361 void __iomem
*fifo
= hsotg
->regs
+ S3C_EPFIFO(ep_idx
);
1367 u32 epctl
= readl(hsotg
->regs
+ S3C_DOEPCTL(ep_idx
));
1370 dev_warn(hsotg
->dev
,
1371 "%s: FIFO %d bytes on ep%d but no req (DxEPCTl=0x%08x)\n",
1372 __func__
, size
, ep_idx
, epctl
);
1374 /* dump the data from the FIFO, we've nothing we can do */
1375 for (ptr
= 0; ptr
< size
; ptr
+= 4)
1381 spin_lock(&hs_ep
->lock
);
1384 read_ptr
= hs_req
->req
.actual
;
1385 max_req
= hs_req
->req
.length
- read_ptr
;
1387 if (to_read
> max_req
) {
1388 /* more data appeared than we where willing
1389 * to deal with in this request.
1392 /* currently we don't deal this */
1396 dev_dbg(hsotg
->dev
, "%s: read %d/%d, done %d/%d\n",
1397 __func__
, to_read
, max_req
, read_ptr
, hs_req
->req
.length
);
1399 hs_ep
->total_data
+= to_read
;
1400 hs_req
->req
.actual
+= to_read
;
1401 to_read
= DIV_ROUND_UP(to_read
, 4);
1403 /* note, we might over-write the buffer end by 3 bytes depending on
1404 * alignment of the data. */
1405 readsl(fifo
, hs_req
->req
.buf
+ read_ptr
, to_read
);
1407 spin_unlock(&hs_ep
->lock
);
1411 * s3c_hsotg_send_zlp - send zero-length packet on control endpoint
1412 * @hsotg: The device instance
1413 * @req: The request currently on this endpoint
1415 * Generate a zero-length IN packet request for terminating a SETUP
1418 * Note, since we don't write any data to the TxFIFO, then it is
1419 * currently belived that we do not need to wait for any space in
1422 static void s3c_hsotg_send_zlp(struct s3c_hsotg
*hsotg
,
1423 struct s3c_hsotg_req
*req
)
1428 dev_warn(hsotg
->dev
, "%s: no request?\n", __func__
);
1432 if (req
->req
.length
== 0) {
1433 hsotg
->eps
[0].sent_zlp
= 1;
1434 s3c_hsotg_enqueue_setup(hsotg
);
1438 hsotg
->eps
[0].dir_in
= 1;
1439 hsotg
->eps
[0].sent_zlp
= 1;
1441 dev_dbg(hsotg
->dev
, "sending zero-length packet\n");
1443 /* issue a zero-sized packet to terminate this */
1444 writel(S3C_DxEPTSIZ_MC(1) | S3C_DxEPTSIZ_PktCnt(1) |
1445 S3C_DxEPTSIZ_XferSize(0), hsotg
->regs
+ S3C_DIEPTSIZ(0));
1447 ctrl
= readl(hsotg
->regs
+ S3C_DIEPCTL0
);
1448 ctrl
|= S3C_DxEPCTL_CNAK
; /* clear NAK set by core */
1449 ctrl
|= S3C_DxEPCTL_EPEna
; /* ensure ep enabled */
1450 ctrl
|= S3C_DxEPCTL_USBActEp
;
1451 writel(ctrl
, hsotg
->regs
+ S3C_DIEPCTL0
);
1455 * s3c_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
1456 * @hsotg: The device instance
1457 * @epnum: The endpoint received from
1458 * @was_setup: Set if processing a SetupDone event.
1460 * The RXFIFO has delivered an OutDone event, which means that the data
1461 * transfer for an OUT endpoint has been completed, either by a short
1462 * packet or by the finish of a transfer.
1464 static void s3c_hsotg_handle_outdone(struct s3c_hsotg
*hsotg
,
1465 int epnum
, bool was_setup
)
1467 struct s3c_hsotg_ep
*hs_ep
= &hsotg
->eps
[epnum
];
1468 struct s3c_hsotg_req
*hs_req
= hs_ep
->req
;
1469 struct usb_request
*req
= &hs_req
->req
;
1473 dev_dbg(hsotg
->dev
, "%s: no request active\n", __func__
);
1477 if (using_dma(hsotg
)) {
1478 u32 epsize
= readl(hsotg
->regs
+ S3C_DOEPTSIZ(epnum
));
1482 /* Calculate the size of the transfer by checking how much
1483 * is left in the endpoint size register and then working it
1484 * out from the amount we loaded for the transfer.
1486 * We need to do this as DMA pointers are always 32bit aligned
1487 * so may overshoot/undershoot the transfer.
1490 size_left
= S3C_DxEPTSIZ_XferSize_GET(epsize
);
1492 size_done
= hs_ep
->size_loaded
- size_left
;
1493 size_done
+= hs_ep
->last_load
;
1495 req
->actual
= size_done
;
1498 if (req
->actual
< req
->length
&& req
->short_not_ok
) {
1499 dev_dbg(hsotg
->dev
, "%s: got %d/%d (short not ok) => error\n",
1500 __func__
, req
->actual
, req
->length
);
1502 /* todo - what should we return here? there's no one else
1503 * even bothering to check the status. */
1507 if (!was_setup
&& req
->complete
!= s3c_hsotg_complete_setup
)
1508 s3c_hsotg_send_zlp(hsotg
, hs_req
);
1511 s3c_hsotg_complete_request_lock(hsotg
, hs_ep
, hs_req
, result
);
1515 * s3c_hsotg_read_frameno - read current frame number
1516 * @hsotg: The device instance
1518 * Return the current frame number
1520 static u32
s3c_hsotg_read_frameno(struct s3c_hsotg
*hsotg
)
1524 dsts
= readl(hsotg
->regs
+ S3C_DSTS
);
1525 dsts
&= S3C_DSTS_SOFFN_MASK
;
1526 dsts
>>= S3C_DSTS_SOFFN_SHIFT
;
1532 * s3c_hsotg_handle_rx - RX FIFO has data
1533 * @hsotg: The device instance
1535 * The IRQ handler has detected that the RX FIFO has some data in it
1536 * that requires processing, so find out what is in there and do the
1539 * The RXFIFO is a true FIFO, the packets comming out are still in packet
1540 * chunks, so if you have x packets received on an endpoint you'll get x
1541 * FIFO events delivered, each with a packet's worth of data in it.
1543 * When using DMA, we should not be processing events from the RXFIFO
1544 * as the actual data should be sent to the memory directly and we turn
1545 * on the completion interrupts to get notifications of transfer completion.
1547 static void s3c_hsotg_handle_rx(struct s3c_hsotg
*hsotg
)
1549 u32 grxstsr
= readl(hsotg
->regs
+ S3C_GRXSTSP
);
1550 u32 epnum
, status
, size
;
1552 WARN_ON(using_dma(hsotg
));
1554 epnum
= grxstsr
& S3C_GRXSTS_EPNum_MASK
;
1555 status
= grxstsr
& S3C_GRXSTS_PktSts_MASK
;
1557 size
= grxstsr
& S3C_GRXSTS_ByteCnt_MASK
;
1558 size
>>= S3C_GRXSTS_ByteCnt_SHIFT
;
1561 dev_dbg(hsotg
->dev
, "%s: GRXSTSP=0x%08x (%d@%d)\n",
1562 __func__
, grxstsr
, size
, epnum
);
1564 #define __status(x) ((x) >> S3C_GRXSTS_PktSts_SHIFT)
1566 switch (status
>> S3C_GRXSTS_PktSts_SHIFT
) {
1567 case __status(S3C_GRXSTS_PktSts_GlobalOutNAK
):
1568 dev_dbg(hsotg
->dev
, "GlobalOutNAK\n");
1571 case __status(S3C_GRXSTS_PktSts_OutDone
):
1572 dev_dbg(hsotg
->dev
, "OutDone (Frame=0x%08x)\n",
1573 s3c_hsotg_read_frameno(hsotg
));
1575 if (!using_dma(hsotg
))
1576 s3c_hsotg_handle_outdone(hsotg
, epnum
, false);
1579 case __status(S3C_GRXSTS_PktSts_SetupDone
):
1581 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1582 s3c_hsotg_read_frameno(hsotg
),
1583 readl(hsotg
->regs
+ S3C_DOEPCTL(0)));
1585 s3c_hsotg_handle_outdone(hsotg
, epnum
, true);
1588 case __status(S3C_GRXSTS_PktSts_OutRX
):
1589 s3c_hsotg_rx_data(hsotg
, epnum
, size
);
1592 case __status(S3C_GRXSTS_PktSts_SetupRX
):
1594 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1595 s3c_hsotg_read_frameno(hsotg
),
1596 readl(hsotg
->regs
+ S3C_DOEPCTL(0)));
1598 s3c_hsotg_rx_data(hsotg
, epnum
, size
);
1602 dev_warn(hsotg
->dev
, "%s: unknown status %08x\n",
1605 s3c_hsotg_dump(hsotg
);
1611 * s3c_hsotg_ep0_mps - turn max packet size into register setting
1612 * @mps: The maximum packet size in bytes.
1614 static u32
s3c_hsotg_ep0_mps(unsigned int mps
)
1618 return S3C_D0EPCTL_MPS_64
;
1620 return S3C_D0EPCTL_MPS_32
;
1622 return S3C_D0EPCTL_MPS_16
;
1624 return S3C_D0EPCTL_MPS_8
;
1627 /* bad max packet size, warn and return invalid result */
1633 * s3c_hsotg_set_ep_maxpacket - set endpoint's max-packet field
1634 * @hsotg: The driver state.
1635 * @ep: The index number of the endpoint
1636 * @mps: The maximum packet size in bytes
1638 * Configure the maximum packet size for the given endpoint, updating
1639 * the hardware control registers to reflect this.
1641 static void s3c_hsotg_set_ep_maxpacket(struct s3c_hsotg
*hsotg
,
1642 unsigned int ep
, unsigned int mps
)
1644 struct s3c_hsotg_ep
*hs_ep
= &hsotg
->eps
[ep
];
1645 void __iomem
*regs
= hsotg
->regs
;
1650 /* EP0 is a special case */
1651 mpsval
= s3c_hsotg_ep0_mps(mps
);
1655 if (mps
>= S3C_DxEPCTL_MPS_LIMIT
+1)
1661 hs_ep
->ep
.maxpacket
= mps
;
1663 /* update both the in and out endpoint controldir_ registers, even
1664 * if one of the directions may not be in use. */
1666 reg
= readl(regs
+ S3C_DIEPCTL(ep
));
1667 reg
&= ~S3C_DxEPCTL_MPS_MASK
;
1669 writel(reg
, regs
+ S3C_DIEPCTL(ep
));
1671 reg
= readl(regs
+ S3C_DOEPCTL(ep
));
1672 reg
&= ~S3C_DxEPCTL_MPS_MASK
;
1674 writel(reg
, regs
+ S3C_DOEPCTL(ep
));
1679 dev_err(hsotg
->dev
, "ep%d: bad mps of %d\n", ep
, mps
);
1684 * s3c_hsotg_trytx - check to see if anything needs transmitting
1685 * @hsotg: The driver state
1686 * @hs_ep: The driver endpoint to check.
1688 * Check to see if there is a request that has data to send, and if so
1689 * make an attempt to write data into the FIFO.
1691 static int s3c_hsotg_trytx(struct s3c_hsotg
*hsotg
,
1692 struct s3c_hsotg_ep
*hs_ep
)
1694 struct s3c_hsotg_req
*hs_req
= hs_ep
->req
;
1696 if (!hs_ep
->dir_in
|| !hs_req
)
1699 if (hs_req
->req
.actual
< hs_req
->req
.length
) {
1700 dev_dbg(hsotg
->dev
, "trying to write more for ep%d\n",
1702 return s3c_hsotg_write_fifo(hsotg
, hs_ep
, hs_req
);
1709 * s3c_hsotg_complete_in - complete IN transfer
1710 * @hsotg: The device state.
1711 * @hs_ep: The endpoint that has just completed.
1713 * An IN transfer has been completed, update the transfer's state and then
1714 * call the relevant completion routines.
1716 static void s3c_hsotg_complete_in(struct s3c_hsotg
*hsotg
,
1717 struct s3c_hsotg_ep
*hs_ep
)
1719 struct s3c_hsotg_req
*hs_req
= hs_ep
->req
;
1720 u32 epsize
= readl(hsotg
->regs
+ S3C_DIEPTSIZ(hs_ep
->index
));
1721 int size_left
, size_done
;
1724 dev_dbg(hsotg
->dev
, "XferCompl but no req\n");
1728 /* Calculate the size of the transfer by checking how much is left
1729 * in the endpoint size register and then working it out from
1730 * the amount we loaded for the transfer.
1732 * We do this even for DMA, as the transfer may have incremented
1733 * past the end of the buffer (DMA transfers are always 32bit
1737 size_left
= S3C_DxEPTSIZ_XferSize_GET(epsize
);
1739 size_done
= hs_ep
->size_loaded
- size_left
;
1740 size_done
+= hs_ep
->last_load
;
1742 if (hs_req
->req
.actual
!= size_done
)
1743 dev_dbg(hsotg
->dev
, "%s: adjusting size done %d => %d\n",
1744 __func__
, hs_req
->req
.actual
, size_done
);
1746 hs_req
->req
.actual
= size_done
;
1748 /* if we did all of the transfer, and there is more data left
1749 * around, then try restarting the rest of the request */
1751 if (!size_left
&& hs_req
->req
.actual
< hs_req
->req
.length
) {
1752 dev_dbg(hsotg
->dev
, "%s trying more for req...\n", __func__
);
1753 s3c_hsotg_start_req(hsotg
, hs_ep
, hs_req
, true);
1755 s3c_hsotg_complete_request_lock(hsotg
, hs_ep
, hs_req
, 0);
1759 * s3c_hsotg_epint - handle an in/out endpoint interrupt
1760 * @hsotg: The driver state
1761 * @idx: The index for the endpoint (0..15)
1762 * @dir_in: Set if this is an IN endpoint
1764 * Process and clear any interrupt pending for an individual endpoint
1766 static void s3c_hsotg_epint(struct s3c_hsotg
*hsotg
, unsigned int idx
,
1769 struct s3c_hsotg_ep
*hs_ep
= &hsotg
->eps
[idx
];
1770 u32 epint_reg
= dir_in
? S3C_DIEPINT(idx
) : S3C_DOEPINT(idx
);
1771 u32 epctl_reg
= dir_in
? S3C_DIEPCTL(idx
) : S3C_DOEPCTL(idx
);
1772 u32 epsiz_reg
= dir_in
? S3C_DIEPTSIZ(idx
) : S3C_DOEPTSIZ(idx
);
1776 ints
= readl(hsotg
->regs
+ epint_reg
);
1778 dev_dbg(hsotg
->dev
, "%s: ep%d(%s) DxEPINT=0x%08x\n",
1779 __func__
, idx
, dir_in
? "in" : "out", ints
);
1781 if (ints
& S3C_DxEPINT_XferCompl
) {
1783 "%s: XferCompl: DxEPCTL=0x%08x, DxEPTSIZ=%08x\n",
1784 __func__
, readl(hsotg
->regs
+ epctl_reg
),
1785 readl(hsotg
->regs
+ epsiz_reg
));
1787 /* we get OutDone from the FIFO, so we only need to look
1788 * at completing IN requests here */
1790 s3c_hsotg_complete_in(hsotg
, hs_ep
);
1792 if (idx
== 0 && !hs_ep
->req
)
1793 s3c_hsotg_enqueue_setup(hsotg
);
1794 } else if (using_dma(hsotg
)) {
1795 /* We're using DMA, we need to fire an OutDone here
1796 * as we ignore the RXFIFO. */
1798 s3c_hsotg_handle_outdone(hsotg
, idx
, false);
1801 clear
|= S3C_DxEPINT_XferCompl
;
1804 if (ints
& S3C_DxEPINT_EPDisbld
) {
1805 dev_dbg(hsotg
->dev
, "%s: EPDisbld\n", __func__
);
1806 clear
|= S3C_DxEPINT_EPDisbld
;
1809 if (ints
& S3C_DxEPINT_AHBErr
) {
1810 dev_dbg(hsotg
->dev
, "%s: AHBErr\n", __func__
);
1811 clear
|= S3C_DxEPINT_AHBErr
;
1814 if (ints
& S3C_DxEPINT_Setup
) { /* Setup or Timeout */
1815 dev_dbg(hsotg
->dev
, "%s: Setup/Timeout\n", __func__
);
1817 if (using_dma(hsotg
) && idx
== 0) {
1818 /* this is the notification we've received a
1819 * setup packet. In non-DMA mode we'd get this
1820 * from the RXFIFO, instead we need to process
1821 * the setup here. */
1826 s3c_hsotg_handle_outdone(hsotg
, 0, true);
1829 clear
|= S3C_DxEPINT_Setup
;
1832 if (ints
& S3C_DxEPINT_Back2BackSetup
) {
1833 dev_dbg(hsotg
->dev
, "%s: B2BSetup/INEPNakEff\n", __func__
);
1834 clear
|= S3C_DxEPINT_Back2BackSetup
;
1838 /* not sure if this is important, but we'll clear it anyway
1840 if (ints
& S3C_DIEPMSK_INTknTXFEmpMsk
) {
1841 dev_dbg(hsotg
->dev
, "%s: ep%d: INTknTXFEmpMsk\n",
1843 clear
|= S3C_DIEPMSK_INTknTXFEmpMsk
;
1846 /* this probably means something bad is happening */
1847 if (ints
& S3C_DIEPMSK_INTknEPMisMsk
) {
1848 dev_warn(hsotg
->dev
, "%s: ep%d: INTknEP\n",
1850 clear
|= S3C_DIEPMSK_INTknEPMisMsk
;
1853 /* FIFO has space or is empty (see GAHBCFG) */
1854 if (hsotg
->dedicated_fifos
&&
1855 ints
& S3C_DIEPMSK_TxFIFOEmpty
) {
1856 dev_dbg(hsotg
->dev
, "%s: ep%d: TxFIFOEmpty\n",
1858 s3c_hsotg_trytx(hsotg
, hs_ep
);
1859 clear
|= S3C_DIEPMSK_TxFIFOEmpty
;
1863 writel(clear
, hsotg
->regs
+ epint_reg
);
1867 * s3c_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
1868 * @hsotg: The device state.
1870 * Handle updating the device settings after the enumeration phase has
1873 static void s3c_hsotg_irq_enumdone(struct s3c_hsotg
*hsotg
)
1875 u32 dsts
= readl(hsotg
->regs
+ S3C_DSTS
);
1876 int ep0_mps
= 0, ep_mps
;
1878 /* This should signal the finish of the enumeration phase
1879 * of the USB handshaking, so we should now know what rate
1880 * we connected at. */
1882 dev_dbg(hsotg
->dev
, "EnumDone (DSTS=0x%08x)\n", dsts
);
1884 /* note, since we're limited by the size of transfer on EP0, and
1885 * it seems IN transfers must be a even number of packets we do
1886 * not advertise a 64byte MPS on EP0. */
1888 /* catch both EnumSpd_FS and EnumSpd_FS48 */
1889 switch (dsts
& S3C_DSTS_EnumSpd_MASK
) {
1890 case S3C_DSTS_EnumSpd_FS
:
1891 case S3C_DSTS_EnumSpd_FS48
:
1892 hsotg
->gadget
.speed
= USB_SPEED_FULL
;
1893 dev_info(hsotg
->dev
, "new device is full-speed\n");
1895 ep0_mps
= EP0_MPS_LIMIT
;
1899 case S3C_DSTS_EnumSpd_HS
:
1900 dev_info(hsotg
->dev
, "new device is high-speed\n");
1901 hsotg
->gadget
.speed
= USB_SPEED_HIGH
;
1903 ep0_mps
= EP0_MPS_LIMIT
;
1907 case S3C_DSTS_EnumSpd_LS
:
1908 hsotg
->gadget
.speed
= USB_SPEED_LOW
;
1909 dev_info(hsotg
->dev
, "new device is low-speed\n");
1911 /* note, we don't actually support LS in this driver at the
1912 * moment, and the documentation seems to imply that it isn't
1913 * supported by the PHYs on some of the devices.
1918 /* we should now know the maximum packet size for an
1919 * endpoint, so set the endpoints to a default value. */
1923 s3c_hsotg_set_ep_maxpacket(hsotg
, 0, ep0_mps
);
1924 for (i
= 1; i
< S3C_HSOTG_EPS
; i
++)
1925 s3c_hsotg_set_ep_maxpacket(hsotg
, i
, ep_mps
);
1928 /* ensure after enumeration our EP0 is active */
1930 s3c_hsotg_enqueue_setup(hsotg
);
1932 dev_dbg(hsotg
->dev
, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
1933 readl(hsotg
->regs
+ S3C_DIEPCTL0
),
1934 readl(hsotg
->regs
+ S3C_DOEPCTL0
));
1938 * kill_all_requests - remove all requests from the endpoint's queue
1939 * @hsotg: The device state.
1940 * @ep: The endpoint the requests may be on.
1941 * @result: The result code to use.
1942 * @force: Force removal of any current requests
1944 * Go through the requests on the given endpoint and mark them
1945 * completed with the given result code.
1947 static void kill_all_requests(struct s3c_hsotg
*hsotg
,
1948 struct s3c_hsotg_ep
*ep
,
1949 int result
, bool force
)
1951 struct s3c_hsotg_req
*req
, *treq
;
1952 unsigned long flags
;
1954 spin_lock_irqsave(&ep
->lock
, flags
);
1956 list_for_each_entry_safe(req
, treq
, &ep
->queue
, queue
) {
1957 /* currently, we can't do much about an already
1958 * running request on an in endpoint */
1960 if (ep
->req
== req
&& ep
->dir_in
&& !force
)
1963 s3c_hsotg_complete_request(hsotg
, ep
, req
,
1967 spin_unlock_irqrestore(&ep
->lock
, flags
);
1970 #define call_gadget(_hs, _entry) \
1971 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \
1972 (_hs)->driver && (_hs)->driver->_entry) \
1973 (_hs)->driver->_entry(&(_hs)->gadget);
1976 * s3c_hsotg_disconnect_irq - disconnect irq service
1977 * @hsotg: The device state.
1979 * A disconnect IRQ has been received, meaning that the host has
1980 * lost contact with the bus. Remove all current transactions
1981 * and signal the gadget driver that this has happened.
1983 static void s3c_hsotg_disconnect_irq(struct s3c_hsotg
*hsotg
)
1987 for (ep
= 0; ep
< S3C_HSOTG_EPS
; ep
++)
1988 kill_all_requests(hsotg
, &hsotg
->eps
[ep
], -ESHUTDOWN
, true);
1990 call_gadget(hsotg
, disconnect
);
1994 * s3c_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
1995 * @hsotg: The device state:
1996 * @periodic: True if this is a periodic FIFO interrupt
1998 static void s3c_hsotg_irq_fifoempty(struct s3c_hsotg
*hsotg
, bool periodic
)
2000 struct s3c_hsotg_ep
*ep
;
2003 /* look through for any more data to transmit */
2005 for (epno
= 0; epno
< S3C_HSOTG_EPS
; epno
++) {
2006 ep
= &hsotg
->eps
[epno
];
2011 if ((periodic
&& !ep
->periodic
) ||
2012 (!periodic
&& ep
->periodic
))
2015 ret
= s3c_hsotg_trytx(hsotg
, ep
);
2021 static struct s3c_hsotg
*our_hsotg
;
2023 /* IRQ flags which will trigger a retry around the IRQ loop */
2024 #define IRQ_RETRY_MASK (S3C_GINTSTS_NPTxFEmp | \
2025 S3C_GINTSTS_PTxFEmp | \
2029 * s3c_hsotg_irq - handle device interrupt
2030 * @irq: The IRQ number triggered
2031 * @pw: The pw value when registered the handler.
2033 static irqreturn_t
s3c_hsotg_irq(int irq
, void *pw
)
2035 struct s3c_hsotg
*hsotg
= pw
;
2036 int retry_count
= 8;
2041 gintsts
= readl(hsotg
->regs
+ S3C_GINTSTS
);
2042 gintmsk
= readl(hsotg
->regs
+ S3C_GINTMSK
);
2044 dev_dbg(hsotg
->dev
, "%s: %08x %08x (%08x) retry %d\n",
2045 __func__
, gintsts
, gintsts
& gintmsk
, gintmsk
, retry_count
);
2049 if (gintsts
& S3C_GINTSTS_OTGInt
) {
2050 u32 otgint
= readl(hsotg
->regs
+ S3C_GOTGINT
);
2052 dev_info(hsotg
->dev
, "OTGInt: %08x\n", otgint
);
2054 writel(otgint
, hsotg
->regs
+ S3C_GOTGINT
);
2055 writel(S3C_GINTSTS_OTGInt
, hsotg
->regs
+ S3C_GINTSTS
);
2058 if (gintsts
& S3C_GINTSTS_DisconnInt
) {
2059 dev_dbg(hsotg
->dev
, "%s: DisconnInt\n", __func__
);
2060 writel(S3C_GINTSTS_DisconnInt
, hsotg
->regs
+ S3C_GINTSTS
);
2062 s3c_hsotg_disconnect_irq(hsotg
);
2065 if (gintsts
& S3C_GINTSTS_SessReqInt
) {
2066 dev_dbg(hsotg
->dev
, "%s: SessReqInt\n", __func__
);
2067 writel(S3C_GINTSTS_SessReqInt
, hsotg
->regs
+ S3C_GINTSTS
);
2070 if (gintsts
& S3C_GINTSTS_EnumDone
) {
2071 s3c_hsotg_irq_enumdone(hsotg
);
2072 writel(S3C_GINTSTS_EnumDone
, hsotg
->regs
+ S3C_GINTSTS
);
2075 if (gintsts
& S3C_GINTSTS_ConIDStsChng
) {
2076 dev_dbg(hsotg
->dev
, "ConIDStsChg (DSTS=0x%08x, GOTCTL=%08x)\n",
2077 readl(hsotg
->regs
+ S3C_DSTS
),
2078 readl(hsotg
->regs
+ S3C_GOTGCTL
));
2080 writel(S3C_GINTSTS_ConIDStsChng
, hsotg
->regs
+ S3C_GINTSTS
);
2083 if (gintsts
& (S3C_GINTSTS_OEPInt
| S3C_GINTSTS_IEPInt
)) {
2084 u32 daint
= readl(hsotg
->regs
+ S3C_DAINT
);
2085 u32 daint_out
= daint
>> S3C_DAINT_OutEP_SHIFT
;
2086 u32 daint_in
= daint
& ~(daint_out
<< S3C_DAINT_OutEP_SHIFT
);
2089 dev_dbg(hsotg
->dev
, "%s: daint=%08x\n", __func__
, daint
);
2091 for (ep
= 0; ep
< 15 && daint_out
; ep
++, daint_out
>>= 1) {
2093 s3c_hsotg_epint(hsotg
, ep
, 0);
2096 for (ep
= 0; ep
< 15 && daint_in
; ep
++, daint_in
>>= 1) {
2098 s3c_hsotg_epint(hsotg
, ep
, 1);
2101 writel(daint
, hsotg
->regs
+ S3C_DAINT
);
2102 writel(gintsts
& (S3C_GINTSTS_OEPInt
| S3C_GINTSTS_IEPInt
),
2103 hsotg
->regs
+ S3C_GINTSTS
);
2106 if (gintsts
& S3C_GINTSTS_USBRst
) {
2107 dev_info(hsotg
->dev
, "%s: USBRst\n", __func__
);
2108 dev_dbg(hsotg
->dev
, "GNPTXSTS=%08x\n",
2109 readl(hsotg
->regs
+ S3C_GNPTXSTS
));
2111 kill_all_requests(hsotg
, &hsotg
->eps
[0], -ECONNRESET
, true);
2113 /* it seems after a reset we can end up with a situation
2114 * where the TXFIFO still has data in it... the docs
2115 * suggest resetting all the fifos, so use the init_fifo
2116 * code to relayout and flush the fifos.
2119 s3c_hsotg_init_fifo(hsotg
);
2121 s3c_hsotg_enqueue_setup(hsotg
);
2123 writel(S3C_GINTSTS_USBRst
, hsotg
->regs
+ S3C_GINTSTS
);
2126 /* check both FIFOs */
2128 if (gintsts
& S3C_GINTSTS_NPTxFEmp
) {
2129 dev_dbg(hsotg
->dev
, "NPTxFEmp\n");
2131 /* Disable the interrupt to stop it happening again
2132 * unless one of these endpoint routines decides that
2133 * it needs re-enabling */
2135 s3c_hsotg_disable_gsint(hsotg
, S3C_GINTSTS_NPTxFEmp
);
2136 s3c_hsotg_irq_fifoempty(hsotg
, false);
2138 writel(S3C_GINTSTS_NPTxFEmp
, hsotg
->regs
+ S3C_GINTSTS
);
2141 if (gintsts
& S3C_GINTSTS_PTxFEmp
) {
2142 dev_dbg(hsotg
->dev
, "PTxFEmp\n");
2144 /* See note in S3C_GINTSTS_NPTxFEmp */
2146 s3c_hsotg_disable_gsint(hsotg
, S3C_GINTSTS_PTxFEmp
);
2147 s3c_hsotg_irq_fifoempty(hsotg
, true);
2149 writel(S3C_GINTSTS_PTxFEmp
, hsotg
->regs
+ S3C_GINTSTS
);
2152 if (gintsts
& S3C_GINTSTS_RxFLvl
) {
2153 /* note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
2154 * we need to retry s3c_hsotg_handle_rx if this is still
2157 s3c_hsotg_handle_rx(hsotg
);
2158 writel(S3C_GINTSTS_RxFLvl
, hsotg
->regs
+ S3C_GINTSTS
);
2161 if (gintsts
& S3C_GINTSTS_ModeMis
) {
2162 dev_warn(hsotg
->dev
, "warning, mode mismatch triggered\n");
2163 writel(S3C_GINTSTS_ModeMis
, hsotg
->regs
+ S3C_GINTSTS
);
2166 if (gintsts
& S3C_GINTSTS_USBSusp
) {
2167 dev_info(hsotg
->dev
, "S3C_GINTSTS_USBSusp\n");
2168 writel(S3C_GINTSTS_USBSusp
, hsotg
->regs
+ S3C_GINTSTS
);
2170 call_gadget(hsotg
, suspend
);
2173 if (gintsts
& S3C_GINTSTS_WkUpInt
) {
2174 dev_info(hsotg
->dev
, "S3C_GINTSTS_WkUpIn\n");
2175 writel(S3C_GINTSTS_WkUpInt
, hsotg
->regs
+ S3C_GINTSTS
);
2177 call_gadget(hsotg
, resume
);
2180 if (gintsts
& S3C_GINTSTS_ErlySusp
) {
2181 dev_dbg(hsotg
->dev
, "S3C_GINTSTS_ErlySusp\n");
2182 writel(S3C_GINTSTS_ErlySusp
, hsotg
->regs
+ S3C_GINTSTS
);
2185 /* these next two seem to crop-up occasionally causing the core
2186 * to shutdown the USB transfer, so try clearing them and logging
2189 if (gintsts
& S3C_GINTSTS_GOUTNakEff
) {
2190 dev_info(hsotg
->dev
, "GOUTNakEff triggered\n");
2192 s3c_hsotg_dump(hsotg
);
2194 writel(S3C_DCTL_CGOUTNak
, hsotg
->regs
+ S3C_DCTL
);
2195 writel(S3C_GINTSTS_GOUTNakEff
, hsotg
->regs
+ S3C_GINTSTS
);
2198 if (gintsts
& S3C_GINTSTS_GINNakEff
) {
2199 dev_info(hsotg
->dev
, "GINNakEff triggered\n");
2201 s3c_hsotg_dump(hsotg
);
2203 writel(S3C_DCTL_CGNPInNAK
, hsotg
->regs
+ S3C_DCTL
);
2204 writel(S3C_GINTSTS_GINNakEff
, hsotg
->regs
+ S3C_GINTSTS
);
2207 /* if we've had fifo events, we should try and go around the
2208 * loop again to see if there's any point in returning yet. */
2210 if (gintsts
& IRQ_RETRY_MASK
&& --retry_count
> 0)
2217 * s3c_hsotg_ep_enable - enable the given endpoint
2218 * @ep: The USB endpint to configure
2219 * @desc: The USB endpoint descriptor to configure with.
2221 * This is called from the USB gadget code's usb_ep_enable().
2223 static int s3c_hsotg_ep_enable(struct usb_ep
*ep
,
2224 const struct usb_endpoint_descriptor
*desc
)
2226 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
2227 struct s3c_hsotg
*hsotg
= hs_ep
->parent
;
2228 unsigned long flags
;
2229 int index
= hs_ep
->index
;
2237 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
2238 __func__
, ep
->name
, desc
->bEndpointAddress
, desc
->bmAttributes
,
2239 desc
->wMaxPacketSize
, desc
->bInterval
);
2241 /* not to be called for EP0 */
2242 WARN_ON(index
== 0);
2244 dir_in
= (desc
->bEndpointAddress
& USB_ENDPOINT_DIR_MASK
) ? 1 : 0;
2245 if (dir_in
!= hs_ep
->dir_in
) {
2246 dev_err(hsotg
->dev
, "%s: direction mismatch!\n", __func__
);
2250 mps
= le16_to_cpu(desc
->wMaxPacketSize
);
2252 /* note, we handle this here instead of s3c_hsotg_set_ep_maxpacket */
2254 epctrl_reg
= dir_in
? S3C_DIEPCTL(index
) : S3C_DOEPCTL(index
);
2255 epctrl
= readl(hsotg
->regs
+ epctrl_reg
);
2257 dev_dbg(hsotg
->dev
, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
2258 __func__
, epctrl
, epctrl_reg
);
2260 spin_lock_irqsave(&hs_ep
->lock
, flags
);
2262 epctrl
&= ~(S3C_DxEPCTL_EPType_MASK
| S3C_DxEPCTL_MPS_MASK
);
2263 epctrl
|= S3C_DxEPCTL_MPS(mps
);
2265 /* mark the endpoint as active, otherwise the core may ignore
2266 * transactions entirely for this endpoint */
2267 epctrl
|= S3C_DxEPCTL_USBActEp
;
2269 /* set the NAK status on the endpoint, otherwise we might try and
2270 * do something with data that we've yet got a request to process
2271 * since the RXFIFO will take data for an endpoint even if the
2272 * size register hasn't been set.
2275 epctrl
|= S3C_DxEPCTL_SNAK
;
2277 /* update the endpoint state */
2278 hs_ep
->ep
.maxpacket
= mps
;
2280 /* default, set to non-periodic */
2281 hs_ep
->periodic
= 0;
2283 switch (desc
->bmAttributes
& USB_ENDPOINT_XFERTYPE_MASK
) {
2284 case USB_ENDPOINT_XFER_ISOC
:
2285 dev_err(hsotg
->dev
, "no current ISOC support\n");
2289 case USB_ENDPOINT_XFER_BULK
:
2290 epctrl
|= S3C_DxEPCTL_EPType_Bulk
;
2293 case USB_ENDPOINT_XFER_INT
:
2295 /* Allocate our TxFNum by simply using the index
2296 * of the endpoint for the moment. We could do
2297 * something better if the host indicates how
2298 * many FIFOs we are expecting to use. */
2300 hs_ep
->periodic
= 1;
2301 epctrl
|= S3C_DxEPCTL_TxFNum(index
);
2304 epctrl
|= S3C_DxEPCTL_EPType_Intterupt
;
2307 case USB_ENDPOINT_XFER_CONTROL
:
2308 epctrl
|= S3C_DxEPCTL_EPType_Control
;
2312 /* if the hardware has dedicated fifos, we must give each IN EP
2313 * a unique tx-fifo even if it is non-periodic.
2315 if (dir_in
&& hsotg
->dedicated_fifos
)
2316 epctrl
|= S3C_DxEPCTL_TxFNum(index
);
2318 /* for non control endpoints, set PID to D0 */
2320 epctrl
|= S3C_DxEPCTL_SetD0PID
;
2322 dev_dbg(hsotg
->dev
, "%s: write DxEPCTL=0x%08x\n",
2325 writel(epctrl
, hsotg
->regs
+ epctrl_reg
);
2326 dev_dbg(hsotg
->dev
, "%s: read DxEPCTL=0x%08x\n",
2327 __func__
, readl(hsotg
->regs
+ epctrl_reg
));
2329 /* enable the endpoint interrupt */
2330 s3c_hsotg_ctrl_epint(hsotg
, index
, dir_in
, 1);
2333 spin_unlock_irqrestore(&hs_ep
->lock
, flags
);
2337 static int s3c_hsotg_ep_disable(struct usb_ep
*ep
)
2339 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
2340 struct s3c_hsotg
*hsotg
= hs_ep
->parent
;
2341 int dir_in
= hs_ep
->dir_in
;
2342 int index
= hs_ep
->index
;
2343 unsigned long flags
;
2347 dev_info(hsotg
->dev
, "%s(ep %p)\n", __func__
, ep
);
2349 if (ep
== &hsotg
->eps
[0].ep
) {
2350 dev_err(hsotg
->dev
, "%s: called for ep0\n", __func__
);
2354 epctrl_reg
= dir_in
? S3C_DIEPCTL(index
) : S3C_DOEPCTL(index
);
2356 /* terminate all requests with shutdown */
2357 kill_all_requests(hsotg
, hs_ep
, -ESHUTDOWN
, false);
2359 spin_lock_irqsave(&hs_ep
->lock
, flags
);
2361 ctrl
= readl(hsotg
->regs
+ epctrl_reg
);
2362 ctrl
&= ~S3C_DxEPCTL_EPEna
;
2363 ctrl
&= ~S3C_DxEPCTL_USBActEp
;
2364 ctrl
|= S3C_DxEPCTL_SNAK
;
2366 dev_dbg(hsotg
->dev
, "%s: DxEPCTL=0x%08x\n", __func__
, ctrl
);
2367 writel(ctrl
, hsotg
->regs
+ epctrl_reg
);
2369 /* disable endpoint interrupts */
2370 s3c_hsotg_ctrl_epint(hsotg
, hs_ep
->index
, hs_ep
->dir_in
, 0);
2372 spin_unlock_irqrestore(&hs_ep
->lock
, flags
);
2377 * on_list - check request is on the given endpoint
2378 * @ep: The endpoint to check.
2379 * @test: The request to test if it is on the endpoint.
2381 static bool on_list(struct s3c_hsotg_ep
*ep
, struct s3c_hsotg_req
*test
)
2383 struct s3c_hsotg_req
*req
, *treq
;
2385 list_for_each_entry_safe(req
, treq
, &ep
->queue
, queue
) {
2393 static int s3c_hsotg_ep_dequeue(struct usb_ep
*ep
, struct usb_request
*req
)
2395 struct s3c_hsotg_req
*hs_req
= our_req(req
);
2396 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
2397 struct s3c_hsotg
*hs
= hs_ep
->parent
;
2398 unsigned long flags
;
2400 dev_info(hs
->dev
, "ep_dequeue(%p,%p)\n", ep
, req
);
2402 if (hs_req
== hs_ep
->req
) {
2403 dev_dbg(hs
->dev
, "%s: already in progress\n", __func__
);
2404 return -EINPROGRESS
;
2407 spin_lock_irqsave(&hs_ep
->lock
, flags
);
2409 if (!on_list(hs_ep
, hs_req
)) {
2410 spin_unlock_irqrestore(&hs_ep
->lock
, flags
);
2414 s3c_hsotg_complete_request(hs
, hs_ep
, hs_req
, -ECONNRESET
);
2415 spin_unlock_irqrestore(&hs_ep
->lock
, flags
);
2420 static int s3c_hsotg_ep_sethalt(struct usb_ep
*ep
, int value
)
2422 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
2423 struct s3c_hsotg
*hs
= hs_ep
->parent
;
2424 int index
= hs_ep
->index
;
2425 unsigned long irqflags
;
2429 dev_info(hs
->dev
, "%s(ep %p %s, %d)\n", __func__
, ep
, ep
->name
, value
);
2431 spin_lock_irqsave(&hs_ep
->lock
, irqflags
);
2433 /* write both IN and OUT control registers */
2435 epreg
= S3C_DIEPCTL(index
);
2436 epctl
= readl(hs
->regs
+ epreg
);
2439 epctl
|= S3C_DxEPCTL_Stall
;
2441 epctl
&= ~S3C_DxEPCTL_Stall
;
2443 writel(epctl
, hs
->regs
+ epreg
);
2445 epreg
= S3C_DOEPCTL(index
);
2446 epctl
= readl(hs
->regs
+ epreg
);
2449 epctl
|= S3C_DxEPCTL_Stall
;
2451 epctl
&= ~S3C_DxEPCTL_Stall
;
2453 writel(epctl
, hs
->regs
+ epreg
);
2455 spin_unlock_irqrestore(&hs_ep
->lock
, irqflags
);
2460 static struct usb_ep_ops s3c_hsotg_ep_ops
= {
2461 .enable
= s3c_hsotg_ep_enable
,
2462 .disable
= s3c_hsotg_ep_disable
,
2463 .alloc_request
= s3c_hsotg_ep_alloc_request
,
2464 .free_request
= s3c_hsotg_ep_free_request
,
2465 .queue
= s3c_hsotg_ep_queue
,
2466 .dequeue
= s3c_hsotg_ep_dequeue
,
2467 .set_halt
= s3c_hsotg_ep_sethalt
,
2468 /* note, don't belive we have any call for the fifo routines */
2472 * s3c_hsotg_corereset - issue softreset to the core
2473 * @hsotg: The device state
2475 * Issue a soft reset to the core, and await the core finishing it.
2477 static int s3c_hsotg_corereset(struct s3c_hsotg
*hsotg
)
2482 dev_dbg(hsotg
->dev
, "resetting core\n");
2484 /* issue soft reset */
2485 writel(S3C_GRSTCTL_CSftRst
, hsotg
->regs
+ S3C_GRSTCTL
);
2489 grstctl
= readl(hsotg
->regs
+ S3C_GRSTCTL
);
2490 } while (!(grstctl
& S3C_GRSTCTL_CSftRst
) && timeout
-- > 0);
2492 if (!(grstctl
& S3C_GRSTCTL_CSftRst
)) {
2493 dev_err(hsotg
->dev
, "Failed to get CSftRst asserted\n");
2500 u32 grstctl
= readl(hsotg
->regs
+ S3C_GRSTCTL
);
2502 if (timeout
-- < 0) {
2503 dev_info(hsotg
->dev
,
2504 "%s: reset failed, GRSTCTL=%08x\n",
2509 if (grstctl
& S3C_GRSTCTL_CSftRst
)
2512 if (!(grstctl
& S3C_GRSTCTL_AHBIdle
))
2515 break; /* reset done */
2518 dev_dbg(hsotg
->dev
, "reset successful\n");
2522 int usb_gadget_register_driver(struct usb_gadget_driver
*driver
)
2524 struct s3c_hsotg
*hsotg
= our_hsotg
;
2528 printk(KERN_ERR
"%s: called with no device\n", __func__
);
2533 dev_err(hsotg
->dev
, "%s: no driver\n", __func__
);
2537 if (driver
->speed
!= USB_SPEED_HIGH
&&
2538 driver
->speed
!= USB_SPEED_FULL
) {
2539 dev_err(hsotg
->dev
, "%s: bad speed\n", __func__
);
2542 if (!driver
->bind
|| !driver
->setup
) {
2543 dev_err(hsotg
->dev
, "%s: missing entry points\n", __func__
);
2547 WARN_ON(hsotg
->driver
);
2549 driver
->driver
.bus
= NULL
;
2550 hsotg
->driver
= driver
;
2551 hsotg
->gadget
.dev
.driver
= &driver
->driver
;
2552 hsotg
->gadget
.dev
.dma_mask
= hsotg
->dev
->dma_mask
;
2553 hsotg
->gadget
.speed
= USB_SPEED_UNKNOWN
;
2555 ret
= device_add(&hsotg
->gadget
.dev
);
2557 dev_err(hsotg
->dev
, "failed to register gadget device\n");
2561 ret
= driver
->bind(&hsotg
->gadget
);
2563 dev_err(hsotg
->dev
, "failed bind %s\n", driver
->driver
.name
);
2565 hsotg
->gadget
.dev
.driver
= NULL
;
2566 hsotg
->driver
= NULL
;
2570 /* we must now enable ep0 ready for host detection and then
2571 * set configuration. */
2573 s3c_hsotg_corereset(hsotg
);
2575 /* set the PLL on, remove the HNP/SRP and set the PHY */
2576 writel(S3C_GUSBCFG_PHYIf16
| S3C_GUSBCFG_TOutCal(7) |
2577 (0x5 << 10), hsotg
->regs
+ S3C_GUSBCFG
);
2579 /* looks like soft-reset changes state of FIFOs */
2580 s3c_hsotg_init_fifo(hsotg
);
2582 __orr32(hsotg
->regs
+ S3C_DCTL
, S3C_DCTL_SftDiscon
);
2584 writel(1 << 18 | S3C_DCFG_DevSpd_HS
, hsotg
->regs
+ S3C_DCFG
);
2586 writel(S3C_GINTSTS_DisconnInt
| S3C_GINTSTS_SessReqInt
|
2587 S3C_GINTSTS_ConIDStsChng
| S3C_GINTSTS_USBRst
|
2588 S3C_GINTSTS_EnumDone
| S3C_GINTSTS_OTGInt
|
2589 S3C_GINTSTS_USBSusp
| S3C_GINTSTS_WkUpInt
|
2590 S3C_GINTSTS_GOUTNakEff
| S3C_GINTSTS_GINNakEff
|
2591 S3C_GINTSTS_ErlySusp
,
2592 hsotg
->regs
+ S3C_GINTMSK
);
2594 if (using_dma(hsotg
))
2595 writel(S3C_GAHBCFG_GlblIntrEn
| S3C_GAHBCFG_DMAEn
|
2596 S3C_GAHBCFG_HBstLen_Incr4
,
2597 hsotg
->regs
+ S3C_GAHBCFG
);
2599 writel(S3C_GAHBCFG_GlblIntrEn
, hsotg
->regs
+ S3C_GAHBCFG
);
2601 /* Enabling INTknTXFEmpMsk here seems to be a big mistake, we end
2602 * up being flooded with interrupts if the host is polling the
2603 * endpoint to try and read data. */
2605 writel(S3C_DIEPMSK_TimeOUTMsk
| S3C_DIEPMSK_AHBErrMsk
|
2606 S3C_DIEPMSK_INTknEPMisMsk
|
2607 S3C_DIEPMSK_EPDisbldMsk
| S3C_DIEPMSK_XferComplMsk
|
2608 ((hsotg
->dedicated_fifos
) ? S3C_DIEPMSK_TxFIFOEmpty
: 0),
2609 hsotg
->regs
+ S3C_DIEPMSK
);
2611 /* don't need XferCompl, we get that from RXFIFO in slave mode. In
2612 * DMA mode we may need this. */
2613 writel(S3C_DOEPMSK_SetupMsk
| S3C_DOEPMSK_AHBErrMsk
|
2614 S3C_DOEPMSK_EPDisbldMsk
|
2615 (using_dma(hsotg
) ? (S3C_DIEPMSK_XferComplMsk
|
2616 S3C_DIEPMSK_TimeOUTMsk
) : 0),
2617 hsotg
->regs
+ S3C_DOEPMSK
);
2619 writel(0, hsotg
->regs
+ S3C_DAINTMSK
);
2621 dev_info(hsotg
->dev
, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2622 readl(hsotg
->regs
+ S3C_DIEPCTL0
),
2623 readl(hsotg
->regs
+ S3C_DOEPCTL0
));
2625 /* enable in and out endpoint interrupts */
2626 s3c_hsotg_en_gsint(hsotg
, S3C_GINTSTS_OEPInt
| S3C_GINTSTS_IEPInt
);
2628 /* Enable the RXFIFO when in slave mode, as this is how we collect
2629 * the data. In DMA mode, we get events from the FIFO but also
2630 * things we cannot process, so do not use it. */
2631 if (!using_dma(hsotg
))
2632 s3c_hsotg_en_gsint(hsotg
, S3C_GINTSTS_RxFLvl
);
2634 /* Enable interrupts for EP0 in and out */
2635 s3c_hsotg_ctrl_epint(hsotg
, 0, 0, 1);
2636 s3c_hsotg_ctrl_epint(hsotg
, 0, 1, 1);
2638 __orr32(hsotg
->regs
+ S3C_DCTL
, S3C_DCTL_PWROnPrgDone
);
2639 udelay(10); /* see openiboot */
2640 __bic32(hsotg
->regs
+ S3C_DCTL
, S3C_DCTL_PWROnPrgDone
);
2642 dev_info(hsotg
->dev
, "DCTL=0x%08x\n", readl(hsotg
->regs
+ S3C_DCTL
));
2644 /* S3C_DxEPCTL_USBActEp says RO in manual, but seems to be set by
2645 writing to the EPCTL register.. */
2647 /* set to read 1 8byte packet */
2648 writel(S3C_DxEPTSIZ_MC(1) | S3C_DxEPTSIZ_PktCnt(1) |
2649 S3C_DxEPTSIZ_XferSize(8), hsotg
->regs
+ DOEPTSIZ0
);
2651 writel(s3c_hsotg_ep0_mps(hsotg
->eps
[0].ep
.maxpacket
) |
2652 S3C_DxEPCTL_CNAK
| S3C_DxEPCTL_EPEna
|
2653 S3C_DxEPCTL_USBActEp
,
2654 hsotg
->regs
+ S3C_DOEPCTL0
);
2656 /* enable, but don't activate EP0in */
2657 writel(s3c_hsotg_ep0_mps(hsotg
->eps
[0].ep
.maxpacket
) |
2658 S3C_DxEPCTL_USBActEp
, hsotg
->regs
+ S3C_DIEPCTL0
);
2660 s3c_hsotg_enqueue_setup(hsotg
);
2662 dev_info(hsotg
->dev
, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2663 readl(hsotg
->regs
+ S3C_DIEPCTL0
),
2664 readl(hsotg
->regs
+ S3C_DOEPCTL0
));
2666 /* clear global NAKs */
2667 writel(S3C_DCTL_CGOUTNak
| S3C_DCTL_CGNPInNAK
,
2668 hsotg
->regs
+ S3C_DCTL
);
2670 /* must be at-least 3ms to allow bus to see disconnect */
2673 /* remove the soft-disconnect and let's go */
2674 __bic32(hsotg
->regs
+ S3C_DCTL
, S3C_DCTL_SftDiscon
);
2676 /* report to the user, and return */
2678 dev_info(hsotg
->dev
, "bound driver %s\n", driver
->driver
.name
);
2682 hsotg
->driver
= NULL
;
2683 hsotg
->gadget
.dev
.driver
= NULL
;
2686 EXPORT_SYMBOL(usb_gadget_register_driver
);
2688 int usb_gadget_unregister_driver(struct usb_gadget_driver
*driver
)
2690 struct s3c_hsotg
*hsotg
= our_hsotg
;
2696 if (!driver
|| driver
!= hsotg
->driver
|| !driver
->unbind
)
2699 /* all endpoints should be shutdown */
2700 for (ep
= 0; ep
< S3C_HSOTG_EPS
; ep
++)
2701 s3c_hsotg_ep_disable(&hsotg
->eps
[ep
].ep
);
2703 call_gadget(hsotg
, disconnect
);
2705 driver
->unbind(&hsotg
->gadget
);
2706 hsotg
->driver
= NULL
;
2707 hsotg
->gadget
.speed
= USB_SPEED_UNKNOWN
;
2709 device_del(&hsotg
->gadget
.dev
);
2711 dev_info(hsotg
->dev
, "unregistered gadget driver '%s'\n",
2712 driver
->driver
.name
);
2716 EXPORT_SYMBOL(usb_gadget_unregister_driver
);
2718 static int s3c_hsotg_gadget_getframe(struct usb_gadget
*gadget
)
2720 return s3c_hsotg_read_frameno(to_hsotg(gadget
));
2723 static struct usb_gadget_ops s3c_hsotg_gadget_ops
= {
2724 .get_frame
= s3c_hsotg_gadget_getframe
,
2728 * s3c_hsotg_initep - initialise a single endpoint
2729 * @hsotg: The device state.
2730 * @hs_ep: The endpoint to be initialised.
2731 * @epnum: The endpoint number
2733 * Initialise the given endpoint (as part of the probe and device state
2734 * creation) to give to the gadget driver. Setup the endpoint name, any
2735 * direction information and other state that may be required.
2737 static void __devinit
s3c_hsotg_initep(struct s3c_hsotg
*hsotg
,
2738 struct s3c_hsotg_ep
*hs_ep
,
2746 else if ((epnum
% 2) == 0) {
2753 hs_ep
->index
= epnum
;
2755 snprintf(hs_ep
->name
, sizeof(hs_ep
->name
), "ep%d%s", epnum
, dir
);
2757 INIT_LIST_HEAD(&hs_ep
->queue
);
2758 INIT_LIST_HEAD(&hs_ep
->ep
.ep_list
);
2760 spin_lock_init(&hs_ep
->lock
);
2762 /* add to the list of endpoints known by the gadget driver */
2764 list_add_tail(&hs_ep
->ep
.ep_list
, &hsotg
->gadget
.ep_list
);
2766 hs_ep
->parent
= hsotg
;
2767 hs_ep
->ep
.name
= hs_ep
->name
;
2768 hs_ep
->ep
.maxpacket
= epnum
? 512 : EP0_MPS_LIMIT
;
2769 hs_ep
->ep
.ops
= &s3c_hsotg_ep_ops
;
2771 /* Read the FIFO size for the Periodic TX FIFO, even if we're
2772 * an OUT endpoint, we may as well do this if in future the
2773 * code is changed to make each endpoint's direction changeable.
2776 ptxfifo
= readl(hsotg
->regs
+ S3C_DPTXFSIZn(epnum
));
2777 hs_ep
->fifo_size
= S3C_DPTXFSIZn_DPTxFSize_GET(ptxfifo
) * 4;
2779 /* if we're using dma, we need to set the next-endpoint pointer
2780 * to be something valid.
2783 if (using_dma(hsotg
)) {
2784 u32 next
= S3C_DxEPCTL_NextEp((epnum
+ 1) % 15);
2785 writel(next
, hsotg
->regs
+ S3C_DIEPCTL(epnum
));
2786 writel(next
, hsotg
->regs
+ S3C_DOEPCTL(epnum
));
2791 * s3c_hsotg_otgreset - reset the OtG phy block
2792 * @hsotg: The host state.
2794 * Power up the phy, set the basic configuration and start the PHY.
2796 static void s3c_hsotg_otgreset(struct s3c_hsotg
*hsotg
)
2800 writel(0, S3C_PHYPWR
);
2803 osc
= hsotg
->plat
->is_osc
? S3C_PHYCLK_EXT_OSC
: 0;
2805 writel(osc
| 0x10, S3C_PHYCLK
);
2807 /* issue a full set of resets to the otg and core */
2809 writel(S3C_RSTCON_PHY
, S3C_RSTCON
);
2810 udelay(20); /* at-least 10uS */
2811 writel(0, S3C_RSTCON
);
2815 static void s3c_hsotg_init(struct s3c_hsotg
*hsotg
)
2819 /* unmask subset of endpoint interrupts */
2821 writel(S3C_DIEPMSK_TimeOUTMsk
| S3C_DIEPMSK_AHBErrMsk
|
2822 S3C_DIEPMSK_EPDisbldMsk
| S3C_DIEPMSK_XferComplMsk
,
2823 hsotg
->regs
+ S3C_DIEPMSK
);
2825 writel(S3C_DOEPMSK_SetupMsk
| S3C_DOEPMSK_AHBErrMsk
|
2826 S3C_DOEPMSK_EPDisbldMsk
| S3C_DOEPMSK_XferComplMsk
,
2827 hsotg
->regs
+ S3C_DOEPMSK
);
2829 writel(0, hsotg
->regs
+ S3C_DAINTMSK
);
2831 /* Be in disconnected state until gadget is registered */
2832 __orr32(hsotg
->regs
+ S3C_DCTL
, S3C_DCTL_SftDiscon
);
2835 /* post global nak until we're ready */
2836 writel(S3C_DCTL_SGNPInNAK
| S3C_DCTL_SGOUTNak
,
2837 hsotg
->regs
+ S3C_DCTL
);
2842 dev_info(hsotg
->dev
, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
2843 readl(hsotg
->regs
+ S3C_GRXFSIZ
),
2844 readl(hsotg
->regs
+ S3C_GNPTXFSIZ
));
2846 s3c_hsotg_init_fifo(hsotg
);
2848 /* set the PLL on, remove the HNP/SRP and set the PHY */
2849 writel(S3C_GUSBCFG_PHYIf16
| S3C_GUSBCFG_TOutCal(7) | (0x5 << 10),
2850 hsotg
->regs
+ S3C_GUSBCFG
);
2852 writel(using_dma(hsotg
) ? S3C_GAHBCFG_DMAEn
: 0x0,
2853 hsotg
->regs
+ S3C_GAHBCFG
);
2855 /* check hardware configuration */
2857 cfg4
= readl(hsotg
->regs
+ 0x50);
2858 hsotg
->dedicated_fifos
= (cfg4
>> 25) & 1;
2860 dev_info(hsotg
->dev
, "%s fifos\n",
2861 hsotg
->dedicated_fifos
? "dedicated" : "shared");
2864 static void s3c_hsotg_dump(struct s3c_hsotg
*hsotg
)
2866 struct device
*dev
= hsotg
->dev
;
2867 void __iomem
*regs
= hsotg
->regs
;
2871 dev_info(dev
, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
2872 readl(regs
+ S3C_DCFG
), readl(regs
+ S3C_DCTL
),
2873 readl(regs
+ S3C_DIEPMSK
));
2875 dev_info(dev
, "GAHBCFG=0x%08x, 0x44=0x%08x\n",
2876 readl(regs
+ S3C_GAHBCFG
), readl(regs
+ 0x44));
2878 dev_info(dev
, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
2879 readl(regs
+ S3C_GRXFSIZ
), readl(regs
+ S3C_GNPTXFSIZ
));
2881 /* show periodic fifo settings */
2883 for (idx
= 1; idx
<= 15; idx
++) {
2884 val
= readl(regs
+ S3C_DPTXFSIZn(idx
));
2885 dev_info(dev
, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx
,
2886 val
>> S3C_DPTXFSIZn_DPTxFSize_SHIFT
,
2887 val
& S3C_DPTXFSIZn_DPTxFStAddr_MASK
);
2890 for (idx
= 0; idx
< 15; idx
++) {
2892 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx
,
2893 readl(regs
+ S3C_DIEPCTL(idx
)),
2894 readl(regs
+ S3C_DIEPTSIZ(idx
)),
2895 readl(regs
+ S3C_DIEPDMA(idx
)));
2897 val
= readl(regs
+ S3C_DOEPCTL(idx
));
2899 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
2900 idx
, readl(regs
+ S3C_DOEPCTL(idx
)),
2901 readl(regs
+ S3C_DOEPTSIZ(idx
)),
2902 readl(regs
+ S3C_DOEPDMA(idx
)));
2906 dev_info(dev
, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
2907 readl(regs
+ S3C_DVBUSDIS
), readl(regs
+ S3C_DVBUSPULSE
));
2912 * state_show - debugfs: show overall driver and device state.
2913 * @seq: The seq file to write to.
2914 * @v: Unused parameter.
2916 * This debugfs entry shows the overall state of the hardware and
2917 * some general information about each of the endpoints available
2920 static int state_show(struct seq_file
*seq
, void *v
)
2922 struct s3c_hsotg
*hsotg
= seq
->private;
2923 void __iomem
*regs
= hsotg
->regs
;
2926 seq_printf(seq
, "DCFG=0x%08x, DCTL=0x%08x, DSTS=0x%08x\n",
2927 readl(regs
+ S3C_DCFG
),
2928 readl(regs
+ S3C_DCTL
),
2929 readl(regs
+ S3C_DSTS
));
2931 seq_printf(seq
, "DIEPMSK=0x%08x, DOEPMASK=0x%08x\n",
2932 readl(regs
+ S3C_DIEPMSK
), readl(regs
+ S3C_DOEPMSK
));
2934 seq_printf(seq
, "GINTMSK=0x%08x, GINTSTS=0x%08x\n",
2935 readl(regs
+ S3C_GINTMSK
),
2936 readl(regs
+ S3C_GINTSTS
));
2938 seq_printf(seq
, "DAINTMSK=0x%08x, DAINT=0x%08x\n",
2939 readl(regs
+ S3C_DAINTMSK
),
2940 readl(regs
+ S3C_DAINT
));
2942 seq_printf(seq
, "GNPTXSTS=0x%08x, GRXSTSR=%08x\n",
2943 readl(regs
+ S3C_GNPTXSTS
),
2944 readl(regs
+ S3C_GRXSTSR
));
2946 seq_printf(seq
, "\nEndpoint status:\n");
2948 for (idx
= 0; idx
< 15; idx
++) {
2951 in
= readl(regs
+ S3C_DIEPCTL(idx
));
2952 out
= readl(regs
+ S3C_DOEPCTL(idx
));
2954 seq_printf(seq
, "ep%d: DIEPCTL=0x%08x, DOEPCTL=0x%08x",
2957 in
= readl(regs
+ S3C_DIEPTSIZ(idx
));
2958 out
= readl(regs
+ S3C_DOEPTSIZ(idx
));
2960 seq_printf(seq
, ", DIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x",
2963 seq_printf(seq
, "\n");
2969 static int state_open(struct inode
*inode
, struct file
*file
)
2971 return single_open(file
, state_show
, inode
->i_private
);
2974 static const struct file_operations state_fops
= {
2975 .owner
= THIS_MODULE
,
2978 .llseek
= seq_lseek
,
2979 .release
= single_release
,
2983 * fifo_show - debugfs: show the fifo information
2984 * @seq: The seq_file to write data to.
2985 * @v: Unused parameter.
2987 * Show the FIFO information for the overall fifo and all the
2988 * periodic transmission FIFOs.
2990 static int fifo_show(struct seq_file
*seq
, void *v
)
2992 struct s3c_hsotg
*hsotg
= seq
->private;
2993 void __iomem
*regs
= hsotg
->regs
;
2997 seq_printf(seq
, "Non-periodic FIFOs:\n");
2998 seq_printf(seq
, "RXFIFO: Size %d\n", readl(regs
+ S3C_GRXFSIZ
));
3000 val
= readl(regs
+ S3C_GNPTXFSIZ
);
3001 seq_printf(seq
, "NPTXFIFO: Size %d, Start 0x%08x\n",
3002 val
>> S3C_GNPTXFSIZ_NPTxFDep_SHIFT
,
3003 val
& S3C_GNPTXFSIZ_NPTxFStAddr_MASK
);
3005 seq_printf(seq
, "\nPeriodic TXFIFOs:\n");
3007 for (idx
= 1; idx
<= 15; idx
++) {
3008 val
= readl(regs
+ S3C_DPTXFSIZn(idx
));
3010 seq_printf(seq
, "\tDPTXFIFO%2d: Size %d, Start 0x%08x\n", idx
,
3011 val
>> S3C_DPTXFSIZn_DPTxFSize_SHIFT
,
3012 val
& S3C_DPTXFSIZn_DPTxFStAddr_MASK
);
3018 static int fifo_open(struct inode
*inode
, struct file
*file
)
3020 return single_open(file
, fifo_show
, inode
->i_private
);
3023 static const struct file_operations fifo_fops
= {
3024 .owner
= THIS_MODULE
,
3027 .llseek
= seq_lseek
,
3028 .release
= single_release
,
3032 static const char *decode_direction(int is_in
)
3034 return is_in
? "in" : "out";
3038 * ep_show - debugfs: show the state of an endpoint.
3039 * @seq: The seq_file to write data to.
3040 * @v: Unused parameter.
3042 * This debugfs entry shows the state of the given endpoint (one is
3043 * registered for each available).
3045 static int ep_show(struct seq_file
*seq
, void *v
)
3047 struct s3c_hsotg_ep
*ep
= seq
->private;
3048 struct s3c_hsotg
*hsotg
= ep
->parent
;
3049 struct s3c_hsotg_req
*req
;
3050 void __iomem
*regs
= hsotg
->regs
;
3051 int index
= ep
->index
;
3052 int show_limit
= 15;
3053 unsigned long flags
;
3055 seq_printf(seq
, "Endpoint index %d, named %s, dir %s:\n",
3056 ep
->index
, ep
->ep
.name
, decode_direction(ep
->dir_in
));
3058 /* first show the register state */
3060 seq_printf(seq
, "\tDIEPCTL=0x%08x, DOEPCTL=0x%08x\n",
3061 readl(regs
+ S3C_DIEPCTL(index
)),
3062 readl(regs
+ S3C_DOEPCTL(index
)));
3064 seq_printf(seq
, "\tDIEPDMA=0x%08x, DOEPDMA=0x%08x\n",
3065 readl(regs
+ S3C_DIEPDMA(index
)),
3066 readl(regs
+ S3C_DOEPDMA(index
)));
3068 seq_printf(seq
, "\tDIEPINT=0x%08x, DOEPINT=0x%08x\n",
3069 readl(regs
+ S3C_DIEPINT(index
)),
3070 readl(regs
+ S3C_DOEPINT(index
)));
3072 seq_printf(seq
, "\tDIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x\n",
3073 readl(regs
+ S3C_DIEPTSIZ(index
)),
3074 readl(regs
+ S3C_DOEPTSIZ(index
)));
3076 seq_printf(seq
, "\n");
3077 seq_printf(seq
, "mps %d\n", ep
->ep
.maxpacket
);
3078 seq_printf(seq
, "total_data=%ld\n", ep
->total_data
);
3080 seq_printf(seq
, "request list (%p,%p):\n",
3081 ep
->queue
.next
, ep
->queue
.prev
);
3083 spin_lock_irqsave(&ep
->lock
, flags
);
3085 list_for_each_entry(req
, &ep
->queue
, queue
) {
3086 if (--show_limit
< 0) {
3087 seq_printf(seq
, "not showing more requests...\n");
3091 seq_printf(seq
, "%c req %p: %d bytes @%p, ",
3092 req
== ep
->req
? '*' : ' ',
3093 req
, req
->req
.length
, req
->req
.buf
);
3094 seq_printf(seq
, "%d done, res %d\n",
3095 req
->req
.actual
, req
->req
.status
);
3098 spin_unlock_irqrestore(&ep
->lock
, flags
);
3103 static int ep_open(struct inode
*inode
, struct file
*file
)
3105 return single_open(file
, ep_show
, inode
->i_private
);
3108 static const struct file_operations ep_fops
= {
3109 .owner
= THIS_MODULE
,
3112 .llseek
= seq_lseek
,
3113 .release
= single_release
,
3117 * s3c_hsotg_create_debug - create debugfs directory and files
3118 * @hsotg: The driver state
3120 * Create the debugfs files to allow the user to get information
3121 * about the state of the system. The directory name is created
3122 * with the same name as the device itself, in case we end up
3123 * with multiple blocks in future systems.
3125 static void __devinit
s3c_hsotg_create_debug(struct s3c_hsotg
*hsotg
)
3127 struct dentry
*root
;
3130 root
= debugfs_create_dir(dev_name(hsotg
->dev
), NULL
);
3131 hsotg
->debug_root
= root
;
3133 dev_err(hsotg
->dev
, "cannot create debug root\n");
3137 /* create general state file */
3139 hsotg
->debug_file
= debugfs_create_file("state", 0444, root
,
3140 hsotg
, &state_fops
);
3142 if (IS_ERR(hsotg
->debug_file
))
3143 dev_err(hsotg
->dev
, "%s: failed to create state\n", __func__
);
3145 hsotg
->debug_fifo
= debugfs_create_file("fifo", 0444, root
,
3148 if (IS_ERR(hsotg
->debug_fifo
))
3149 dev_err(hsotg
->dev
, "%s: failed to create fifo\n", __func__
);
3151 /* create one file for each endpoint */
3153 for (epidx
= 0; epidx
< S3C_HSOTG_EPS
; epidx
++) {
3154 struct s3c_hsotg_ep
*ep
= &hsotg
->eps
[epidx
];
3156 ep
->debugfs
= debugfs_create_file(ep
->name
, 0444,
3157 root
, ep
, &ep_fops
);
3159 if (IS_ERR(ep
->debugfs
))
3160 dev_err(hsotg
->dev
, "failed to create %s debug file\n",
3166 * s3c_hsotg_delete_debug - cleanup debugfs entries
3167 * @hsotg: The driver state
3169 * Cleanup (remove) the debugfs files for use on module exit.
3171 static void __devexit
s3c_hsotg_delete_debug(struct s3c_hsotg
*hsotg
)
3175 for (epidx
= 0; epidx
< S3C_HSOTG_EPS
; epidx
++) {
3176 struct s3c_hsotg_ep
*ep
= &hsotg
->eps
[epidx
];
3177 debugfs_remove(ep
->debugfs
);
3180 debugfs_remove(hsotg
->debug_file
);
3181 debugfs_remove(hsotg
->debug_fifo
);
3182 debugfs_remove(hsotg
->debug_root
);
3186 * s3c_hsotg_gate - set the hardware gate for the block
3187 * @pdev: The device we bound to
3190 * Set the hardware gate setting into the block. If we end up on
3191 * something other than an S3C64XX, then we might need to change this
3192 * to using a platform data callback, or some other mechanism.
3194 static void s3c_hsotg_gate(struct platform_device
*pdev
, bool on
)
3196 unsigned long flags
;
3199 local_irq_save(flags
);
3201 others
= __raw_readl(S3C64XX_OTHERS
);
3203 others
|= S3C64XX_OTHERS_USBMASK
;
3205 others
&= ~S3C64XX_OTHERS_USBMASK
;
3206 __raw_writel(others
, S3C64XX_OTHERS
);
3208 local_irq_restore(flags
);
3211 static struct s3c_hsotg_plat s3c_hsotg_default_pdata
;
3213 static int __devinit
s3c_hsotg_probe(struct platform_device
*pdev
)
3215 struct s3c_hsotg_plat
*plat
= pdev
->dev
.platform_data
;
3216 struct device
*dev
= &pdev
->dev
;
3217 struct s3c_hsotg
*hsotg
;
3218 struct resource
*res
;
3223 plat
= &s3c_hsotg_default_pdata
;
3225 hsotg
= kzalloc(sizeof(struct s3c_hsotg
) +
3226 sizeof(struct s3c_hsotg_ep
) * S3C_HSOTG_EPS
,
3229 dev_err(dev
, "cannot get memory\n");
3236 platform_set_drvdata(pdev
, hsotg
);
3238 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
3240 dev_err(dev
, "cannot find register resource 0\n");
3245 hsotg
->regs_res
= request_mem_region(res
->start
, resource_size(res
),
3247 if (!hsotg
->regs_res
) {
3248 dev_err(dev
, "cannot reserve registers\n");
3253 hsotg
->regs
= ioremap(res
->start
, resource_size(res
));
3255 dev_err(dev
, "cannot map registers\n");
3260 ret
= platform_get_irq(pdev
, 0);
3262 dev_err(dev
, "cannot find IRQ\n");
3268 ret
= request_irq(ret
, s3c_hsotg_irq
, 0, dev_name(dev
), hsotg
);
3270 dev_err(dev
, "cannot claim IRQ\n");
3274 dev_info(dev
, "regs %p, irq %d\n", hsotg
->regs
, hsotg
->irq
);
3276 device_initialize(&hsotg
->gadget
.dev
);
3278 dev_set_name(&hsotg
->gadget
.dev
, "gadget");
3280 hsotg
->gadget
.is_dualspeed
= 1;
3281 hsotg
->gadget
.ops
= &s3c_hsotg_gadget_ops
;
3282 hsotg
->gadget
.name
= dev_name(dev
);
3284 hsotg
->gadget
.dev
.parent
= dev
;
3285 hsotg
->gadget
.dev
.dma_mask
= dev
->dma_mask
;
3287 /* setup endpoint information */
3289 INIT_LIST_HEAD(&hsotg
->gadget
.ep_list
);
3290 hsotg
->gadget
.ep0
= &hsotg
->eps
[0].ep
;
3292 /* allocate EP0 request */
3294 hsotg
->ctrl_req
= s3c_hsotg_ep_alloc_request(&hsotg
->eps
[0].ep
,
3296 if (!hsotg
->ctrl_req
) {
3297 dev_err(dev
, "failed to allocate ctrl req\n");
3301 /* reset the system */
3303 s3c_hsotg_gate(pdev
, true);
3305 s3c_hsotg_otgreset(hsotg
);
3306 s3c_hsotg_corereset(hsotg
);
3307 s3c_hsotg_init(hsotg
);
3309 /* initialise the endpoints now the core has been initialised */
3310 for (epnum
= 0; epnum
< S3C_HSOTG_EPS
; epnum
++)
3311 s3c_hsotg_initep(hsotg
, &hsotg
->eps
[epnum
], epnum
);
3313 s3c_hsotg_create_debug(hsotg
);
3315 s3c_hsotg_dump(hsotg
);
3321 iounmap(hsotg
->regs
);
3324 release_resource(hsotg
->regs_res
);
3325 kfree(hsotg
->regs_res
);
3332 static int __devexit
s3c_hsotg_remove(struct platform_device
*pdev
)
3334 struct s3c_hsotg
*hsotg
= platform_get_drvdata(pdev
);
3336 s3c_hsotg_delete_debug(hsotg
);
3338 usb_gadget_unregister_driver(hsotg
->driver
);
3340 free_irq(hsotg
->irq
, hsotg
);
3341 iounmap(hsotg
->regs
);
3343 release_resource(hsotg
->regs_res
);
3344 kfree(hsotg
->regs_res
);
3346 s3c_hsotg_gate(pdev
, false);
3353 #define s3c_hsotg_suspend NULL
3354 #define s3c_hsotg_resume NULL
3357 static struct platform_driver s3c_hsotg_driver
= {
3359 .name
= "s3c-hsotg",
3360 .owner
= THIS_MODULE
,
3362 .probe
= s3c_hsotg_probe
,
3363 .remove
= __devexit_p(s3c_hsotg_remove
),
3364 .suspend
= s3c_hsotg_suspend
,
3365 .resume
= s3c_hsotg_resume
,
3368 static int __init
s3c_hsotg_modinit(void)
3370 return platform_driver_register(&s3c_hsotg_driver
);
3373 static void __exit
s3c_hsotg_modexit(void)
3375 platform_driver_unregister(&s3c_hsotg_driver
);
3378 module_init(s3c_hsotg_modinit
);
3379 module_exit(s3c_hsotg_modexit
);
3381 MODULE_DESCRIPTION("Samsung S3C USB High-speed/OtG device");
3382 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
3383 MODULE_LICENSE("GPL");
3384 MODULE_ALIAS("platform:s3c-hsotg");