4 * Copyright (c) 2003-2004 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * Copyright (c) 2012 Heiko Stuebner <heiko@sntech.de>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/init.h>
20 #include <linux/slab.h>
21 #include <linux/module.h>
23 #include <linux/err.h>
24 #include <linux/interrupt.h>
25 #include <linux/ioport.h>
26 #include <linux/device.h>
27 #include <linux/irqdomain.h>
29 #include <asm/mach/irq.h>
31 #include <mach/regs-irq.h>
32 #include <mach/regs-gpio.h>
35 #include <plat/regs-irqtype.h>
38 #define S3C_IRQTYPE_NONE 0
39 #define S3C_IRQTYPE_EINT 1
40 #define S3C_IRQTYPE_EDGE 2
41 #define S3C_IRQTYPE_LEVEL 3
45 unsigned long parent_irq
;
47 /* data gets filled during init */
48 struct s3c_irq_intc
*intc
;
49 unsigned long sub_bits
;
50 struct s3c_irq_intc
*sub_intc
;
54 * Sructure holding the controller data
55 * @reg_pending register holding pending irqs
56 * @reg_intpnd special register intpnd in main intc
57 * @reg_mask mask register
58 * @domain irq_domain of the controller
59 * @parent parent controller for ext and sub irqs
60 * @irqs irq-data, always s3c_irq_data[32]
63 void __iomem
*reg_pending
;
64 void __iomem
*reg_intpnd
;
65 void __iomem
*reg_mask
;
66 struct irq_domain
*domain
;
67 struct s3c_irq_intc
*parent
;
68 struct s3c_irq_data
*irqs
;
71 static void s3c_irq_mask(struct irq_data
*data
)
73 struct s3c_irq_intc
*intc
= data
->domain
->host_data
;
74 struct s3c_irq_intc
*parent_intc
= intc
->parent
;
75 struct s3c_irq_data
*irq_data
= &intc
->irqs
[data
->hwirq
];
76 struct s3c_irq_data
*parent_data
;
80 mask
= __raw_readl(intc
->reg_mask
);
81 mask
|= (1UL << data
->hwirq
);
82 __raw_writel(mask
, intc
->reg_mask
);
84 if (parent_intc
&& irq_data
->parent_irq
) {
85 parent_data
= &parent_intc
->irqs
[irq_data
->parent_irq
];
87 /* check to see if we need to mask the parent IRQ */
88 if ((mask
& parent_data
->sub_bits
) == parent_data
->sub_bits
) {
89 irqno
= irq_find_mapping(parent_intc
->domain
,
90 irq_data
->parent_irq
);
91 s3c_irq_mask(irq_get_irq_data(irqno
));
96 static void s3c_irq_unmask(struct irq_data
*data
)
98 struct s3c_irq_intc
*intc
= data
->domain
->host_data
;
99 struct s3c_irq_intc
*parent_intc
= intc
->parent
;
100 struct s3c_irq_data
*irq_data
= &intc
->irqs
[data
->hwirq
];
104 mask
= __raw_readl(intc
->reg_mask
);
105 mask
&= ~(1UL << data
->hwirq
);
106 __raw_writel(mask
, intc
->reg_mask
);
108 if (parent_intc
&& irq_data
->parent_irq
) {
109 irqno
= irq_find_mapping(parent_intc
->domain
,
110 irq_data
->parent_irq
);
111 s3c_irq_unmask(irq_get_irq_data(irqno
));
115 static inline void s3c_irq_ack(struct irq_data
*data
)
117 struct s3c_irq_intc
*intc
= data
->domain
->host_data
;
118 unsigned long bitval
= 1UL << data
->hwirq
;
120 __raw_writel(bitval
, intc
->reg_pending
);
121 if (intc
->reg_intpnd
)
122 __raw_writel(bitval
, intc
->reg_intpnd
);
125 static int s3c_irqext_type_set(void __iomem
*gpcon_reg
,
126 void __iomem
*extint_reg
,
127 unsigned long gpcon_offset
,
128 unsigned long extint_offset
,
131 unsigned long newvalue
= 0, value
;
133 /* Set the GPIO to external interrupt mode */
134 value
= __raw_readl(gpcon_reg
);
135 value
= (value
& ~(3 << gpcon_offset
)) | (0x02 << gpcon_offset
);
136 __raw_writel(value
, gpcon_reg
);
138 /* Set the external interrupt to pointed trigger type */
142 pr_warn("No edge setting!\n");
145 case IRQ_TYPE_EDGE_RISING
:
146 newvalue
= S3C2410_EXTINT_RISEEDGE
;
149 case IRQ_TYPE_EDGE_FALLING
:
150 newvalue
= S3C2410_EXTINT_FALLEDGE
;
153 case IRQ_TYPE_EDGE_BOTH
:
154 newvalue
= S3C2410_EXTINT_BOTHEDGE
;
157 case IRQ_TYPE_LEVEL_LOW
:
158 newvalue
= S3C2410_EXTINT_LOWLEV
;
161 case IRQ_TYPE_LEVEL_HIGH
:
162 newvalue
= S3C2410_EXTINT_HILEV
;
166 pr_err("No such irq type %d", type
);
170 value
= __raw_readl(extint_reg
);
171 value
= (value
& ~(7 << extint_offset
)) | (newvalue
<< extint_offset
);
172 __raw_writel(value
, extint_reg
);
177 static int s3c_irqext_type(struct irq_data
*data
, unsigned int type
)
179 void __iomem
*extint_reg
;
180 void __iomem
*gpcon_reg
;
181 unsigned long gpcon_offset
, extint_offset
;
183 if ((data
->hwirq
>= 4) && (data
->hwirq
<= 7)) {
184 gpcon_reg
= S3C2410_GPFCON
;
185 extint_reg
= S3C24XX_EXTINT0
;
186 gpcon_offset
= (data
->hwirq
) * 2;
187 extint_offset
= (data
->hwirq
) * 4;
188 } else if ((data
->hwirq
>= 8) && (data
->hwirq
<= 15)) {
189 gpcon_reg
= S3C2410_GPGCON
;
190 extint_reg
= S3C24XX_EXTINT1
;
191 gpcon_offset
= (data
->hwirq
- 8) * 2;
192 extint_offset
= (data
->hwirq
- 8) * 4;
193 } else if ((data
->hwirq
>= 16) && (data
->hwirq
<= 23)) {
194 gpcon_reg
= S3C2410_GPGCON
;
195 extint_reg
= S3C24XX_EXTINT2
;
196 gpcon_offset
= (data
->hwirq
- 8) * 2;
197 extint_offset
= (data
->hwirq
- 16) * 4;
202 return s3c_irqext_type_set(gpcon_reg
, extint_reg
, gpcon_offset
,
203 extint_offset
, type
);
206 static int s3c_irqext0_type(struct irq_data
*data
, unsigned int type
)
208 void __iomem
*extint_reg
;
209 void __iomem
*gpcon_reg
;
210 unsigned long gpcon_offset
, extint_offset
;
212 if ((data
->hwirq
>= 0) && (data
->hwirq
<= 3)) {
213 gpcon_reg
= S3C2410_GPFCON
;
214 extint_reg
= S3C24XX_EXTINT0
;
215 gpcon_offset
= (data
->hwirq
) * 2;
216 extint_offset
= (data
->hwirq
) * 4;
221 return s3c_irqext_type_set(gpcon_reg
, extint_reg
, gpcon_offset
,
222 extint_offset
, type
);
225 static struct irq_chip s3c_irq_chip
= {
227 .irq_ack
= s3c_irq_ack
,
228 .irq_mask
= s3c_irq_mask
,
229 .irq_unmask
= s3c_irq_unmask
,
230 .irq_set_wake
= s3c_irq_wake
233 static struct irq_chip s3c_irq_level_chip
= {
235 .irq_mask
= s3c_irq_mask
,
236 .irq_unmask
= s3c_irq_unmask
,
237 .irq_ack
= s3c_irq_ack
,
240 static struct irq_chip s3c_irqext_chip
= {
242 .irq_mask
= s3c_irq_mask
,
243 .irq_unmask
= s3c_irq_unmask
,
244 .irq_ack
= s3c_irq_ack
,
245 .irq_set_type
= s3c_irqext_type
,
246 .irq_set_wake
= s3c_irqext_wake
249 static struct irq_chip s3c_irq_eint0t4
= {
251 .irq_ack
= s3c_irq_ack
,
252 .irq_mask
= s3c_irq_mask
,
253 .irq_unmask
= s3c_irq_unmask
,
254 .irq_set_wake
= s3c_irq_wake
,
255 .irq_set_type
= s3c_irqext0_type
,
258 static void s3c_irq_demux(unsigned int irq
, struct irq_desc
*desc
)
260 struct irq_chip
*chip
= irq_desc_get_chip(desc
);
261 struct s3c_irq_intc
*intc
= desc
->irq_data
.domain
->host_data
;
262 struct s3c_irq_data
*irq_data
= &intc
->irqs
[desc
->irq_data
.hwirq
];
263 struct s3c_irq_intc
*sub_intc
= irq_data
->sub_intc
;
268 chained_irq_enter(chip
, desc
);
270 src
= __raw_readl(sub_intc
->reg_pending
);
271 msk
= __raw_readl(sub_intc
->reg_mask
);
274 src
&= irq_data
->sub_bits
;
279 generic_handle_irq(irq_find_mapping(sub_intc
->domain
, n
));
282 chained_irq_exit(chip
, desc
);
287 * s3c24xx_set_fiq - set the FIQ routing
288 * @irq: IRQ number to route to FIQ on processor.
289 * @on: Whether to route @irq to the FIQ, or to remove the FIQ routing.
291 * Change the state of the IRQ to FIQ routing depending on @irq and @on. If
292 * @on is true, the @irq is checked to see if it can be routed and the
293 * interrupt controller updated to route the IRQ. If @on is false, the FIQ
294 * routing is cleared, regardless of which @irq is specified.
296 int s3c24xx_set_fiq(unsigned int irq
, bool on
)
302 offs
= irq
- FIQ_START
;
311 __raw_writel(intmod
, S3C2410_INTMOD
);
315 EXPORT_SYMBOL_GPL(s3c24xx_set_fiq
);
318 static int s3c24xx_irq_map(struct irq_domain
*h
, unsigned int virq
,
321 struct s3c_irq_intc
*intc
= h
->host_data
;
322 struct s3c_irq_data
*irq_data
= &intc
->irqs
[hw
];
323 struct s3c_irq_intc
*parent_intc
;
324 struct s3c_irq_data
*parent_irq_data
;
328 pr_err("irq-s3c24xx: no controller found for hwirq %lu\n", hw
);
333 pr_err("irq-s3c24xx: no irq data found for hwirq %lu\n", hw
);
337 /* attach controller pointer to irq_data */
338 irq_data
->intc
= intc
;
340 /* set handler and flags */
341 switch (irq_data
->type
) {
342 case S3C_IRQTYPE_NONE
:
344 case S3C_IRQTYPE_EINT
:
345 if (irq_data
->parent_irq
)
346 irq_set_chip_and_handler(virq
, &s3c_irqext_chip
,
349 irq_set_chip_and_handler(virq
, &s3c_irq_eint0t4
,
352 case S3C_IRQTYPE_EDGE
:
353 if (irq_data
->parent_irq
||
354 intc
->reg_pending
== S3C2416_SRCPND2
)
355 irq_set_chip_and_handler(virq
, &s3c_irq_level_chip
,
358 irq_set_chip_and_handler(virq
, &s3c_irq_chip
,
361 case S3C_IRQTYPE_LEVEL
:
362 if (irq_data
->parent_irq
)
363 irq_set_chip_and_handler(virq
, &s3c_irq_level_chip
,
366 irq_set_chip_and_handler(virq
, &s3c_irq_chip
,
370 pr_err("irq-s3c24xx: unsupported irqtype %d\n", irq_data
->type
);
373 set_irq_flags(virq
, IRQF_VALID
);
375 if (irq_data
->parent_irq
) {
376 parent_intc
= intc
->parent
;
378 pr_err("irq-s3c24xx: no parent controller found for hwirq %lu\n",
383 parent_irq_data
= &parent_intc
->irqs
[irq_data
->parent_irq
];
385 pr_err("irq-s3c24xx: no irq data found for hwirq %lu\n",
390 parent_irq_data
->sub_intc
= intc
;
391 parent_irq_data
->sub_bits
|= (1UL << hw
);
393 /* attach the demuxer to the parent irq */
394 irqno
= irq_find_mapping(parent_intc
->domain
,
395 irq_data
->parent_irq
);
397 pr_err("irq-s3c24xx: could not find mapping for parent irq %lu\n",
398 irq_data
->parent_irq
);
401 irq_set_chained_handler(irqno
, s3c_irq_demux
);
407 set_irq_flags(virq
, 0);
409 /* the only error can result from bad mapping data*/
413 static struct irq_domain_ops s3c24xx_irq_ops
= {
414 .map
= s3c24xx_irq_map
,
415 .xlate
= irq_domain_xlate_twocell
,
418 static void s3c24xx_clear_intc(struct s3c_irq_intc
*intc
)
420 void __iomem
*reg_source
;
425 /* if intpnd is set, read the next pending irq from there */
426 reg_source
= intc
->reg_intpnd
? intc
->reg_intpnd
: intc
->reg_pending
;
429 for (i
= 0; i
< 4; i
++) {
430 pend
= __raw_readl(reg_source
);
432 if (pend
== 0 || pend
== last
)
435 __raw_writel(pend
, intc
->reg_pending
);
436 if (intc
->reg_intpnd
)
437 __raw_writel(pend
, intc
->reg_intpnd
);
439 pr_info("irq: clearing pending status %08x\n", (int)pend
);
444 struct s3c_irq_intc
*s3c24xx_init_intc(struct device_node
*np
,
445 struct s3c_irq_data
*irq_data
,
446 struct s3c_irq_intc
*parent
,
447 unsigned long address
)
449 struct s3c_irq_intc
*intc
;
450 void __iomem
*base
= (void *)0xf6000000; /* static mapping */
456 intc
= kzalloc(sizeof(struct s3c_irq_intc
), GFP_KERNEL
);
458 return ERR_PTR(-ENOMEM
);
460 intc
->irqs
= irq_data
;
463 intc
->parent
= parent
;
465 /* select the correct data for the controller.
466 * Need to hard code the irq num start and offset
467 * to preserve the static mapping for now
471 pr_debug("irq: found main intc\n");
472 intc
->reg_pending
= base
;
473 intc
->reg_mask
= base
+ 0x08;
474 intc
->reg_intpnd
= base
+ 0x10;
476 irq_start
= S3C2410_IRQ(0);
480 pr_debug("irq: found subintc\n");
481 intc
->reg_pending
= base
+ 0x18;
482 intc
->reg_mask
= base
+ 0x1c;
484 irq_start
= S3C2410_IRQSUB(0);
488 pr_debug("irq: found intc2\n");
489 intc
->reg_pending
= base
+ 0x40;
490 intc
->reg_mask
= base
+ 0x48;
491 intc
->reg_intpnd
= base
+ 0x50;
493 irq_start
= S3C2416_IRQ(0);
497 pr_debug("irq: found eintc\n");
498 base
= (void *)0xfd000000;
500 intc
->reg_mask
= base
+ 0xa4;
501 intc
->reg_pending
= base
+ 0xa8;
503 irq_start
= S3C2410_IRQ(32);
507 pr_err("irq: unsupported controller address\n");
512 /* now that all the data is complete, init the irq-domain */
513 s3c24xx_clear_intc(intc
);
514 intc
->domain
= irq_domain_add_legacy(np
, irq_num
, irq_start
,
515 irq_offset
, &s3c24xx_irq_ops
,
518 pr_err("irq: could not create irq-domain\n");
532 * Initialise S3C2410 IRQ system
535 static struct s3c_irq_data init_base
[32] = {
536 { .type
= S3C_IRQTYPE_EINT
, }, /* EINT0 */
537 { .type
= S3C_IRQTYPE_EINT
, }, /* EINT1 */
538 { .type
= S3C_IRQTYPE_EINT
, }, /* EINT2 */
539 { .type
= S3C_IRQTYPE_EINT
, }, /* EINT3 */
540 { .type
= S3C_IRQTYPE_LEVEL
, }, /* EINT4to7 */
541 { .type
= S3C_IRQTYPE_LEVEL
, }, /* EINT8to23 */
542 { .type
= S3C_IRQTYPE_NONE
, }, /* reserved */
543 { .type
= S3C_IRQTYPE_EDGE
, }, /* nBATT_FLT */
544 { .type
= S3C_IRQTYPE_EDGE
, }, /* TICK */
545 { .type
= S3C_IRQTYPE_EDGE
, }, /* WDT */
546 { .type
= S3C_IRQTYPE_EDGE
, }, /* TIMER0 */
547 { .type
= S3C_IRQTYPE_EDGE
, }, /* TIMER1 */
548 { .type
= S3C_IRQTYPE_EDGE
, }, /* TIMER2 */
549 { .type
= S3C_IRQTYPE_EDGE
, }, /* TIMER3 */
550 { .type
= S3C_IRQTYPE_EDGE
, }, /* TIMER4 */
551 { .type
= S3C_IRQTYPE_LEVEL
, }, /* UART2 */
552 { .type
= S3C_IRQTYPE_EDGE
, }, /* LCD */
553 { .type
= S3C_IRQTYPE_EDGE
, }, /* DMA0 */
554 { .type
= S3C_IRQTYPE_EDGE
, }, /* DMA1 */
555 { .type
= S3C_IRQTYPE_EDGE
, }, /* DMA2 */
556 { .type
= S3C_IRQTYPE_EDGE
, }, /* DMA3 */
557 { .type
= S3C_IRQTYPE_EDGE
, }, /* SDI */
558 { .type
= S3C_IRQTYPE_EDGE
, }, /* SPI0 */
559 { .type
= S3C_IRQTYPE_LEVEL
, }, /* UART1 */
560 { .type
= S3C_IRQTYPE_NONE
, }, /* reserved */
561 { .type
= S3C_IRQTYPE_EDGE
, }, /* USBD */
562 { .type
= S3C_IRQTYPE_EDGE
, }, /* USBH */
563 { .type
= S3C_IRQTYPE_EDGE
, }, /* IIC */
564 { .type
= S3C_IRQTYPE_LEVEL
, }, /* UART0 */
565 { .type
= S3C_IRQTYPE_EDGE
, }, /* SPI1 */
566 { .type
= S3C_IRQTYPE_EDGE
, }, /* RTC */
567 { .type
= S3C_IRQTYPE_LEVEL
, }, /* ADCPARENT */
570 static struct s3c_irq_data init_eint
[32] = {
571 { .type
= S3C_IRQTYPE_NONE
, }, /* reserved */
572 { .type
= S3C_IRQTYPE_NONE
, }, /* reserved */
573 { .type
= S3C_IRQTYPE_NONE
, }, /* reserved */
574 { .type
= S3C_IRQTYPE_NONE
, }, /* reserved */
575 { .type
= S3C_IRQTYPE_EINT
, .parent_irq
= 4 }, /* EINT4 */
576 { .type
= S3C_IRQTYPE_EINT
, .parent_irq
= 4 }, /* EINT5 */
577 { .type
= S3C_IRQTYPE_EINT
, .parent_irq
= 4 }, /* EINT6 */
578 { .type
= S3C_IRQTYPE_EINT
, .parent_irq
= 4 }, /* EINT7 */
579 { .type
= S3C_IRQTYPE_EINT
, .parent_irq
= 5 }, /* EINT8 */
580 { .type
= S3C_IRQTYPE_EINT
, .parent_irq
= 5 }, /* EINT9 */
581 { .type
= S3C_IRQTYPE_EINT
, .parent_irq
= 5 }, /* EINT10 */
582 { .type
= S3C_IRQTYPE_EINT
, .parent_irq
= 5 }, /* EINT11 */
583 { .type
= S3C_IRQTYPE_EINT
, .parent_irq
= 5 }, /* EINT12 */
584 { .type
= S3C_IRQTYPE_EINT
, .parent_irq
= 5 }, /* EINT13 */
585 { .type
= S3C_IRQTYPE_EINT
, .parent_irq
= 5 }, /* EINT14 */
586 { .type
= S3C_IRQTYPE_EINT
, .parent_irq
= 5 }, /* EINT15 */
587 { .type
= S3C_IRQTYPE_EINT
, .parent_irq
= 5 }, /* EINT16 */
588 { .type
= S3C_IRQTYPE_EINT
, .parent_irq
= 5 }, /* EINT17 */
589 { .type
= S3C_IRQTYPE_EINT
, .parent_irq
= 5 }, /* EINT18 */
590 { .type
= S3C_IRQTYPE_EINT
, .parent_irq
= 5 }, /* EINT19 */
591 { .type
= S3C_IRQTYPE_EINT
, .parent_irq
= 5 }, /* EINT20 */
592 { .type
= S3C_IRQTYPE_EINT
, .parent_irq
= 5 }, /* EINT21 */
593 { .type
= S3C_IRQTYPE_EINT
, .parent_irq
= 5 }, /* EINT22 */
594 { .type
= S3C_IRQTYPE_EINT
, .parent_irq
= 5 }, /* EINT23 */
597 static struct s3c_irq_data init_subint
[32] = {
598 { .type
= S3C_IRQTYPE_LEVEL
, .parent_irq
= 28 }, /* UART0-RX */
599 { .type
= S3C_IRQTYPE_LEVEL
, .parent_irq
= 28 }, /* UART0-TX */
600 { .type
= S3C_IRQTYPE_LEVEL
, .parent_irq
= 28 }, /* UART0-ERR */
601 { .type
= S3C_IRQTYPE_LEVEL
, .parent_irq
= 23 }, /* UART1-RX */
602 { .type
= S3C_IRQTYPE_LEVEL
, .parent_irq
= 23 }, /* UART1-TX */
603 { .type
= S3C_IRQTYPE_LEVEL
, .parent_irq
= 23 }, /* UART1-ERR */
604 { .type
= S3C_IRQTYPE_LEVEL
, .parent_irq
= 15 }, /* UART2-RX */
605 { .type
= S3C_IRQTYPE_LEVEL
, .parent_irq
= 15 }, /* UART2-TX */
606 { .type
= S3C_IRQTYPE_LEVEL
, .parent_irq
= 15 }, /* UART2-ERR */
607 { .type
= S3C_IRQTYPE_EDGE
, .parent_irq
= 31 }, /* TC */
608 { .type
= S3C_IRQTYPE_EDGE
, .parent_irq
= 31 }, /* ADC */
611 void __init
s3c24xx_init_irq(void)
613 struct s3c_irq_intc
*main_intc
;
619 main_intc
= s3c24xx_init_intc(NULL
, &init_base
[0], NULL
, 0x4a000000);
620 if (IS_ERR(main_intc
)) {
621 pr_err("irq: could not create main interrupt controller\n");
625 s3c24xx_init_intc(NULL
, &init_subint
[0], main_intc
, 0x4a000018);
626 s3c24xx_init_intc(NULL
, &init_eint
[0], main_intc
, 0x560000a4);
629 #ifdef CONFIG_CPU_S3C2416
630 static struct s3c_irq_data init_s3c2416base
[32] = {
631 { .type
= S3C_IRQTYPE_EINT
, }, /* EINT0 */
632 { .type
= S3C_IRQTYPE_EINT
, }, /* EINT1 */
633 { .type
= S3C_IRQTYPE_EINT
, }, /* EINT2 */
634 { .type
= S3C_IRQTYPE_EINT
, }, /* EINT3 */
635 { .type
= S3C_IRQTYPE_LEVEL
, }, /* EINT4to7 */
636 { .type
= S3C_IRQTYPE_LEVEL
, }, /* EINT8to23 */
637 { .type
= S3C_IRQTYPE_NONE
, }, /* reserved */
638 { .type
= S3C_IRQTYPE_EDGE
, }, /* nBATT_FLT */
639 { .type
= S3C_IRQTYPE_EDGE
, }, /* TICK */
640 { .type
= S3C_IRQTYPE_LEVEL
, }, /* WDT/AC97 */
641 { .type
= S3C_IRQTYPE_EDGE
, }, /* TIMER0 */
642 { .type
= S3C_IRQTYPE_EDGE
, }, /* TIMER1 */
643 { .type
= S3C_IRQTYPE_EDGE
, }, /* TIMER2 */
644 { .type
= S3C_IRQTYPE_EDGE
, }, /* TIMER3 */
645 { .type
= S3C_IRQTYPE_EDGE
, }, /* TIMER4 */
646 { .type
= S3C_IRQTYPE_LEVEL
, }, /* UART2 */
647 { .type
= S3C_IRQTYPE_LEVEL
, }, /* LCD */
648 { .type
= S3C_IRQTYPE_LEVEL
, }, /* DMA */
649 { .type
= S3C_IRQTYPE_LEVEL
, }, /* UART3 */
650 { .type
= S3C_IRQTYPE_NONE
, }, /* reserved */
651 { .type
= S3C_IRQTYPE_EDGE
, }, /* SDI1 */
652 { .type
= S3C_IRQTYPE_EDGE
, }, /* SDI0 */
653 { .type
= S3C_IRQTYPE_EDGE
, }, /* SPI0 */
654 { .type
= S3C_IRQTYPE_LEVEL
, }, /* UART1 */
655 { .type
= S3C_IRQTYPE_EDGE
, }, /* NAND */
656 { .type
= S3C_IRQTYPE_EDGE
, }, /* USBD */
657 { .type
= S3C_IRQTYPE_EDGE
, }, /* USBH */
658 { .type
= S3C_IRQTYPE_EDGE
, }, /* IIC */
659 { .type
= S3C_IRQTYPE_LEVEL
, }, /* UART0 */
660 { .type
= S3C_IRQTYPE_NONE
, },
661 { .type
= S3C_IRQTYPE_EDGE
, }, /* RTC */
662 { .type
= S3C_IRQTYPE_LEVEL
, }, /* ADCPARENT */
665 static struct s3c_irq_data init_s3c2416subint
[32] = {
666 { .type
= S3C_IRQTYPE_LEVEL
, .parent_irq
= 28 }, /* UART0-RX */
667 { .type
= S3C_IRQTYPE_LEVEL
, .parent_irq
= 28 }, /* UART0-TX */
668 { .type
= S3C_IRQTYPE_LEVEL
, .parent_irq
= 28 }, /* UART0-ERR */
669 { .type
= S3C_IRQTYPE_LEVEL
, .parent_irq
= 23 }, /* UART1-RX */
670 { .type
= S3C_IRQTYPE_LEVEL
, .parent_irq
= 23 }, /* UART1-TX */
671 { .type
= S3C_IRQTYPE_LEVEL
, .parent_irq
= 23 }, /* UART1-ERR */
672 { .type
= S3C_IRQTYPE_LEVEL
, .parent_irq
= 15 }, /* UART2-RX */
673 { .type
= S3C_IRQTYPE_LEVEL
, .parent_irq
= 15 }, /* UART2-TX */
674 { .type
= S3C_IRQTYPE_LEVEL
, .parent_irq
= 15 }, /* UART2-ERR */
675 { .type
= S3C_IRQTYPE_EDGE
, .parent_irq
= 31 }, /* TC */
676 { .type
= S3C_IRQTYPE_EDGE
, .parent_irq
= 31 }, /* ADC */
677 { .type
= S3C_IRQTYPE_NONE
}, /* reserved */
678 { .type
= S3C_IRQTYPE_NONE
}, /* reserved */
679 { .type
= S3C_IRQTYPE_NONE
}, /* reserved */
680 { .type
= S3C_IRQTYPE_NONE
}, /* reserved */
681 { .type
= S3C_IRQTYPE_LEVEL
, .parent_irq
= 16 }, /* LCD2 */
682 { .type
= S3C_IRQTYPE_LEVEL
, .parent_irq
= 16 }, /* LCD3 */
683 { .type
= S3C_IRQTYPE_LEVEL
, .parent_irq
= 16 }, /* LCD4 */
684 { .type
= S3C_IRQTYPE_LEVEL
, .parent_irq
= 17 }, /* DMA0 */
685 { .type
= S3C_IRQTYPE_LEVEL
, .parent_irq
= 17 }, /* DMA1 */
686 { .type
= S3C_IRQTYPE_LEVEL
, .parent_irq
= 17 }, /* DMA2 */
687 { .type
= S3C_IRQTYPE_LEVEL
, .parent_irq
= 17 }, /* DMA3 */
688 { .type
= S3C_IRQTYPE_LEVEL
, .parent_irq
= 17 }, /* DMA4 */
689 { .type
= S3C_IRQTYPE_LEVEL
, .parent_irq
= 17 }, /* DMA5 */
690 { .type
= S3C_IRQTYPE_LEVEL
, .parent_irq
= 18 }, /* UART3-RX */
691 { .type
= S3C_IRQTYPE_LEVEL
, .parent_irq
= 18 }, /* UART3-TX */
692 { .type
= S3C_IRQTYPE_LEVEL
, .parent_irq
= 18 }, /* UART3-ERR */
693 { .type
= S3C_IRQTYPE_LEVEL
, .parent_irq
= 9 }, /* WDT */
694 { .type
= S3C_IRQTYPE_LEVEL
, .parent_irq
= 9 }, /* AC97 */
697 static struct s3c_irq_data init_s3c2416_second
[32] = {
698 { .type
= S3C_IRQTYPE_EDGE
}, /* 2D */
699 { .type
= S3C_IRQTYPE_EDGE
}, /* IIC1 */
700 { .type
= S3C_IRQTYPE_NONE
}, /* reserved */
701 { .type
= S3C_IRQTYPE_NONE
}, /* reserved */
702 { .type
= S3C_IRQTYPE_EDGE
}, /* PCM0 */
703 { .type
= S3C_IRQTYPE_EDGE
}, /* PCM1 */
704 { .type
= S3C_IRQTYPE_EDGE
}, /* I2S0 */
705 { .type
= S3C_IRQTYPE_EDGE
}, /* I2S1 */
708 void __init
s3c2416_init_irq(void)
710 struct s3c_irq_intc
*main_intc
;
712 pr_info("S3C2416: IRQ Support\n");
718 main_intc
= s3c24xx_init_intc(NULL
, &init_s3c2416base
[0], NULL
, 0x4a000000);
719 if (IS_ERR(main_intc
)) {
720 pr_err("irq: could not create main interrupt controller\n");
724 s3c24xx_init_intc(NULL
, &init_eint
[0], main_intc
, 0x560000a4);
725 s3c24xx_init_intc(NULL
, &init_s3c2416subint
[0], main_intc
, 0x4a000018);
727 s3c24xx_init_intc(NULL
, &init_s3c2416_second
[0], NULL
, 0x4a000040);
732 #ifdef CONFIG_CPU_S3C2443
733 static struct s3c_irq_data init_s3c2443base
[32] = {
734 { .type
= S3C_IRQTYPE_EINT
, }, /* EINT0 */
735 { .type
= S3C_IRQTYPE_EINT
, }, /* EINT1 */
736 { .type
= S3C_IRQTYPE_EINT
, }, /* EINT2 */
737 { .type
= S3C_IRQTYPE_EINT
, }, /* EINT3 */
738 { .type
= S3C_IRQTYPE_LEVEL
, }, /* EINT4to7 */
739 { .type
= S3C_IRQTYPE_LEVEL
, }, /* EINT8to23 */
740 { .type
= S3C_IRQTYPE_LEVEL
, }, /* CAM */
741 { .type
= S3C_IRQTYPE_EDGE
, }, /* nBATT_FLT */
742 { .type
= S3C_IRQTYPE_EDGE
, }, /* TICK */
743 { .type
= S3C_IRQTYPE_LEVEL
, }, /* WDT/AC97 */
744 { .type
= S3C_IRQTYPE_EDGE
, }, /* TIMER0 */
745 { .type
= S3C_IRQTYPE_EDGE
, }, /* TIMER1 */
746 { .type
= S3C_IRQTYPE_EDGE
, }, /* TIMER2 */
747 { .type
= S3C_IRQTYPE_EDGE
, }, /* TIMER3 */
748 { .type
= S3C_IRQTYPE_EDGE
, }, /* TIMER4 */
749 { .type
= S3C_IRQTYPE_LEVEL
, }, /* UART2 */
750 { .type
= S3C_IRQTYPE_LEVEL
, }, /* LCD */
751 { .type
= S3C_IRQTYPE_LEVEL
, }, /* DMA */
752 { .type
= S3C_IRQTYPE_LEVEL
, }, /* UART3 */
753 { .type
= S3C_IRQTYPE_EDGE
, }, /* CFON */
754 { .type
= S3C_IRQTYPE_EDGE
, }, /* SDI1 */
755 { .type
= S3C_IRQTYPE_EDGE
, }, /* SDI0 */
756 { .type
= S3C_IRQTYPE_EDGE
, }, /* SPI0 */
757 { .type
= S3C_IRQTYPE_LEVEL
, }, /* UART1 */
758 { .type
= S3C_IRQTYPE_EDGE
, }, /* NAND */
759 { .type
= S3C_IRQTYPE_EDGE
, }, /* USBD */
760 { .type
= S3C_IRQTYPE_EDGE
, }, /* USBH */
761 { .type
= S3C_IRQTYPE_EDGE
, }, /* IIC */
762 { .type
= S3C_IRQTYPE_LEVEL
, }, /* UART0 */
763 { .type
= S3C_IRQTYPE_EDGE
, }, /* SPI1 */
764 { .type
= S3C_IRQTYPE_EDGE
, }, /* RTC */
765 { .type
= S3C_IRQTYPE_LEVEL
, }, /* ADCPARENT */
769 static struct s3c_irq_data init_s3c2443subint
[32] = {
770 { .type
= S3C_IRQTYPE_LEVEL
, .parent_irq
= 28 }, /* UART0-RX */
771 { .type
= S3C_IRQTYPE_LEVEL
, .parent_irq
= 28 }, /* UART0-TX */
772 { .type
= S3C_IRQTYPE_LEVEL
, .parent_irq
= 28 }, /* UART0-ERR */
773 { .type
= S3C_IRQTYPE_LEVEL
, .parent_irq
= 23 }, /* UART1-RX */
774 { .type
= S3C_IRQTYPE_LEVEL
, .parent_irq
= 23 }, /* UART1-TX */
775 { .type
= S3C_IRQTYPE_LEVEL
, .parent_irq
= 23 }, /* UART1-ERR */
776 { .type
= S3C_IRQTYPE_LEVEL
, .parent_irq
= 15 }, /* UART2-RX */
777 { .type
= S3C_IRQTYPE_LEVEL
, .parent_irq
= 15 }, /* UART2-TX */
778 { .type
= S3C_IRQTYPE_LEVEL
, .parent_irq
= 15 }, /* UART2-ERR */
779 { .type
= S3C_IRQTYPE_EDGE
, .parent_irq
= 31 }, /* TC */
780 { .type
= S3C_IRQTYPE_EDGE
, .parent_irq
= 31 }, /* ADC */
781 { .type
= S3C_IRQTYPE_LEVEL
, .parent_irq
= 6 }, /* CAM_C */
782 { .type
= S3C_IRQTYPE_LEVEL
, .parent_irq
= 6 }, /* CAM_P */
783 { .type
= S3C_IRQTYPE_NONE
}, /* reserved */
784 { .type
= S3C_IRQTYPE_LEVEL
, .parent_irq
= 16 }, /* LCD1 */
785 { .type
= S3C_IRQTYPE_LEVEL
, .parent_irq
= 16 }, /* LCD2 */
786 { .type
= S3C_IRQTYPE_LEVEL
, .parent_irq
= 16 }, /* LCD3 */
787 { .type
= S3C_IRQTYPE_LEVEL
, .parent_irq
= 16 }, /* LCD4 */
788 { .type
= S3C_IRQTYPE_LEVEL
, .parent_irq
= 17 }, /* DMA0 */
789 { .type
= S3C_IRQTYPE_LEVEL
, .parent_irq
= 17 }, /* DMA1 */
790 { .type
= S3C_IRQTYPE_LEVEL
, .parent_irq
= 17 }, /* DMA2 */
791 { .type
= S3C_IRQTYPE_LEVEL
, .parent_irq
= 17 }, /* DMA3 */
792 { .type
= S3C_IRQTYPE_LEVEL
, .parent_irq
= 17 }, /* DMA4 */
793 { .type
= S3C_IRQTYPE_LEVEL
, .parent_irq
= 17 }, /* DMA5 */
794 { .type
= S3C_IRQTYPE_LEVEL
, .parent_irq
= 18 }, /* UART3-RX */
795 { .type
= S3C_IRQTYPE_LEVEL
, .parent_irq
= 18 }, /* UART3-TX */
796 { .type
= S3C_IRQTYPE_LEVEL
, .parent_irq
= 18 }, /* UART3-ERR */
797 { .type
= S3C_IRQTYPE_LEVEL
, .parent_irq
= 9 }, /* WDT */
798 { .type
= S3C_IRQTYPE_LEVEL
, .parent_irq
= 9 }, /* AC97 */
801 void __init
s3c2443_init_irq(void)
803 struct s3c_irq_intc
*main_intc
;
805 pr_info("S3C2443: IRQ Support\n");
811 main_intc
= s3c24xx_init_intc(NULL
, &init_s3c2443base
[0], NULL
, 0x4a000000);
812 if (IS_ERR(main_intc
)) {
813 pr_err("irq: could not create main interrupt controller\n");
817 s3c24xx_init_intc(NULL
, &init_eint
[0], main_intc
, 0x560000a4);
818 s3c24xx_init_intc(NULL
, &init_s3c2443subint
[0], main_intc
, 0x4a000018);