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net: filter: Use WARN_RATELIMIT
[linux-2.6.git] / drivers / video / via / hw.c
blob47b13535ed2b6279a568a3f7c0b7ed00edd2a8c3
1 /*
2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public
7 * License as published by the Free Software Foundation;
8 * either version 2, or (at your option) any later version.
9
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12 * the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE.See the GNU General Public License
14 * for more details.
15
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22 #include <linux/via-core.h>
23 #include <asm/olpc.h>
24 #include "global.h"
25 #include "via_clock.h"
26
27 static struct pll_limit cle266_pll_limits[] = {
28 {19, 19, 4, 0},
29 {26, 102, 5, 0},
30 {53, 112, 6, 0},
31 {41, 100, 7, 0},
32 {83, 108, 8, 0},
33 {87, 118, 9, 0},
34 {95, 115, 12, 0},
35 {108, 108, 13, 0},
36 {83, 83, 17, 0},
37 {67, 98, 20, 0},
38 {121, 121, 24, 0},
39 {99, 99, 29, 0},
40 {33, 33, 3, 1},
41 {15, 23, 4, 1},
42 {37, 121, 5, 1},
43 {82, 82, 6, 1},
44 {31, 84, 7, 1},
45 {83, 83, 8, 1},
46 {76, 127, 9, 1},
47 {33, 121, 4, 2},
48 {91, 118, 5, 2},
49 {83, 109, 6, 2},
50 {90, 90, 7, 2},
51 {93, 93, 2, 3},
52 {53, 53, 3, 3},
53 {73, 117, 4, 3},
54 {101, 127, 5, 3},
55 {99, 99, 7, 3}
56 };
57
58 static struct pll_limit k800_pll_limits[] = {
59 {22, 22, 2, 0},
60 {28, 28, 3, 0},
61 {81, 112, 3, 1},
62 {86, 166, 4, 1},
63 {109, 153, 5, 1},
64 {66, 116, 3, 2},
65 {93, 137, 4, 2},
66 {117, 208, 5, 2},
67 {30, 30, 2, 3},
68 {69, 125, 3, 3},
69 {89, 161, 4, 3},
70 {121, 208, 5, 3},
71 {66, 66, 2, 4},
72 {85, 85, 3, 4},
73 {141, 161, 4, 4},
74 {177, 177, 5, 4}
75 };
76
77 static struct pll_limit cx700_pll_limits[] = {
78 {98, 98, 3, 1},
79 {86, 86, 4, 1},
80 {109, 208, 5, 1},
81 {68, 68, 2, 2},
82 {95, 116, 3, 2},
83 {93, 166, 4, 2},
84 {110, 206, 5, 2},
85 {174, 174, 7, 2},
86 {82, 109, 3, 3},
87 {117, 161, 4, 3},
88 {112, 208, 5, 3},
89 {141, 202, 5, 4}
90 };
91
92 static struct pll_limit vx855_pll_limits[] = {
93 {86, 86, 4, 1},
94 {108, 208, 5, 1},
95 {110, 208, 5, 2},
96 {83, 112, 3, 3},
97 {103, 161, 4, 3},
98 {112, 209, 5, 3},
99 {142, 161, 4, 4},
100 {141, 176, 5, 4}
101 };
102
103 /* according to VIA Technologies these values are based on experiment */
104 static struct io_reg scaling_parameters[] = {
105 {VIACR, CR7A, 0xFF, 0x01}, /* LCD Scaling Parameter 1 */
106 {VIACR, CR7B, 0xFF, 0x02}, /* LCD Scaling Parameter 2 */
107 {VIACR, CR7C, 0xFF, 0x03}, /* LCD Scaling Parameter 3 */
108 {VIACR, CR7D, 0xFF, 0x04}, /* LCD Scaling Parameter 4 */
109 {VIACR, CR7E, 0xFF, 0x07}, /* LCD Scaling Parameter 5 */
110 {VIACR, CR7F, 0xFF, 0x0A}, /* LCD Scaling Parameter 6 */
111 {VIACR, CR80, 0xFF, 0x0D}, /* LCD Scaling Parameter 7 */
112 {VIACR, CR81, 0xFF, 0x13}, /* LCD Scaling Parameter 8 */
113 {VIACR, CR82, 0xFF, 0x16}, /* LCD Scaling Parameter 9 */
114 {VIACR, CR83, 0xFF, 0x19}, /* LCD Scaling Parameter 10 */
115 {VIACR, CR84, 0xFF, 0x1C}, /* LCD Scaling Parameter 11 */
116 {VIACR, CR85, 0xFF, 0x1D}, /* LCD Scaling Parameter 12 */
117 {VIACR, CR86, 0xFF, 0x1E}, /* LCD Scaling Parameter 13 */
118 {VIACR, CR87, 0xFF, 0x1F}, /* LCD Scaling Parameter 14 */
119 };
120
121 static struct io_reg common_vga[] = {
122 {VIACR, CR07, 0x10, 0x10}, /* [0] vertical total (bit 8)
123 [1] vertical display end (bit 8)
124 [2] vertical retrace start (bit 8)
125 [3] start vertical blanking (bit 8)
126 [4] line compare (bit 8)
127 [5] vertical total (bit 9)
128 [6] vertical display end (bit 9)
129 [7] vertical retrace start (bit 9) */
130 {VIACR, CR08, 0xFF, 0x00}, /* [0-4] preset row scan
131 [5-6] byte panning */
132 {VIACR, CR09, 0xDF, 0x40}, /* [0-4] max scan line
133 [5] start vertical blanking (bit 9)
134 [6] line compare (bit 9)
135 [7] scan doubling */
136 {VIACR, CR0A, 0xFF, 0x1E}, /* [0-4] cursor start
137 [5] cursor disable */
138 {VIACR, CR0B, 0xFF, 0x00}, /* [0-4] cursor end
139 [5-6] cursor skew */
140 {VIACR, CR0E, 0xFF, 0x00}, /* [0-7] cursor location (high) */
141 {VIACR, CR0F, 0xFF, 0x00}, /* [0-7] cursor location (low) */
142 {VIACR, CR11, 0xF0, 0x80}, /* [0-3] vertical retrace end
143 [6] memory refresh bandwidth
144 [7] CRTC register protect enable */
145 {VIACR, CR14, 0xFF, 0x00}, /* [0-4] underline location
146 [5] divide memory address clock by 4
147 [6] double word addressing */
148 {VIACR, CR17, 0xFF, 0x63}, /* [0-1] mapping of display address 13-14
149 [2] divide scan line clock by 2
150 [3] divide memory address clock by 2
151 [5] address wrap
152 [6] byte mode select
153 [7] sync enable */
154 {VIACR, CR18, 0xFF, 0xFF}, /* [0-7] line compare */
155 };
156
157 static struct fifo_depth_select display_fifo_depth_reg = {
158 /* IGA1 FIFO Depth_Select */
159 {IGA1_FIFO_DEPTH_SELECT_REG_NUM, {{SR17, 0, 7} } },
160 /* IGA2 FIFO Depth_Select */
161 {IGA2_FIFO_DEPTH_SELECT_REG_NUM,
162 {{CR68, 4, 7}, {CR94, 7, 7}, {CR95, 7, 7} } }
163 };
164
165 static struct fifo_threshold_select fifo_threshold_select_reg = {
166 /* IGA1 FIFO Threshold Select */
167 {IGA1_FIFO_THRESHOLD_REG_NUM, {{SR16, 0, 5}, {SR16, 7, 7} } },
168 /* IGA2 FIFO Threshold Select */
169 {IGA2_FIFO_THRESHOLD_REG_NUM, {{CR68, 0, 3}, {CR95, 4, 6} } }
170 };
171
172 static struct fifo_high_threshold_select fifo_high_threshold_select_reg = {
173 /* IGA1 FIFO High Threshold Select */
174 {IGA1_FIFO_HIGH_THRESHOLD_REG_NUM, {{SR18, 0, 5}, {SR18, 7, 7} } },
175 /* IGA2 FIFO High Threshold Select */
176 {IGA2_FIFO_HIGH_THRESHOLD_REG_NUM, {{CR92, 0, 3}, {CR95, 0, 2} } }
177 };
178
179 static struct display_queue_expire_num display_queue_expire_num_reg = {
180 /* IGA1 Display Queue Expire Num */
181 {IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{SR22, 0, 4} } },
182 /* IGA2 Display Queue Expire Num */
183 {IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{CR94, 0, 6} } }
184 };
185
186 /* Definition Fetch Count Registers*/
187 static struct fetch_count fetch_count_reg = {
188 /* IGA1 Fetch Count Register */
189 {IGA1_FETCH_COUNT_REG_NUM, {{SR1C, 0, 7}, {SR1D, 0, 1} } },
190 /* IGA2 Fetch Count Register */
191 {IGA2_FETCH_COUNT_REG_NUM, {{CR65, 0, 7}, {CR67, 2, 3} } }
192 };
193
194 static struct iga1_crtc_timing iga1_crtc_reg = {
195 /* IGA1 Horizontal Total */
196 {IGA1_HOR_TOTAL_REG_NUM, {{CR00, 0, 7}, {CR36, 3, 3} } },
197 /* IGA1 Horizontal Addressable Video */
198 {IGA1_HOR_ADDR_REG_NUM, {{CR01, 0, 7} } },
199 /* IGA1 Horizontal Blank Start */
200 {IGA1_HOR_BLANK_START_REG_NUM, {{CR02, 0, 7} } },
201 /* IGA1 Horizontal Blank End */
202 {IGA1_HOR_BLANK_END_REG_NUM,
203 {{CR03, 0, 4}, {CR05, 7, 7}, {CR33, 5, 5} } },
204 /* IGA1 Horizontal Sync Start */
205 {IGA1_HOR_SYNC_START_REG_NUM, {{CR04, 0, 7}, {CR33, 4, 4} } },
206 /* IGA1 Horizontal Sync End */
207 {IGA1_HOR_SYNC_END_REG_NUM, {{CR05, 0, 4} } },
208 /* IGA1 Vertical Total */
209 {IGA1_VER_TOTAL_REG_NUM,
210 {{CR06, 0, 7}, {CR07, 0, 0}, {CR07, 5, 5}, {CR35, 0, 0} } },
211 /* IGA1 Vertical Addressable Video */
212 {IGA1_VER_ADDR_REG_NUM,
213 {{CR12, 0, 7}, {CR07, 1, 1}, {CR07, 6, 6}, {CR35, 2, 2} } },
214 /* IGA1 Vertical Blank Start */
215 {IGA1_VER_BLANK_START_REG_NUM,
216 {{CR15, 0, 7}, {CR07, 3, 3}, {CR09, 5, 5}, {CR35, 3, 3} } },
217 /* IGA1 Vertical Blank End */
218 {IGA1_VER_BLANK_END_REG_NUM, {{CR16, 0, 7} } },
219 /* IGA1 Vertical Sync Start */
220 {IGA1_VER_SYNC_START_REG_NUM,
221 {{CR10, 0, 7}, {CR07, 2, 2}, {CR07, 7, 7}, {CR35, 1, 1} } },
222 /* IGA1 Vertical Sync End */
223 {IGA1_VER_SYNC_END_REG_NUM, {{CR11, 0, 3} } }
224 };
225
226 static struct iga2_crtc_timing iga2_crtc_reg = {
227 /* IGA2 Horizontal Total */
228 {IGA2_HOR_TOTAL_REG_NUM, {{CR50, 0, 7}, {CR55, 0, 3} } },
229 /* IGA2 Horizontal Addressable Video */
230 {IGA2_HOR_ADDR_REG_NUM, {{CR51, 0, 7}, {CR55, 4, 6} } },
231 /* IGA2 Horizontal Blank Start */
232 {IGA2_HOR_BLANK_START_REG_NUM, {{CR52, 0, 7}, {CR54, 0, 2} } },
233 /* IGA2 Horizontal Blank End */
234 {IGA2_HOR_BLANK_END_REG_NUM,
235 {{CR53, 0, 7}, {CR54, 3, 5}, {CR5D, 6, 6} } },
236 /* IGA2 Horizontal Sync Start */
237 {IGA2_HOR_SYNC_START_REG_NUM,
238 {{CR56, 0, 7}, {CR54, 6, 7}, {CR5C, 7, 7}, {CR5D, 7, 7} } },
239 /* IGA2 Horizontal Sync End */
240 {IGA2_HOR_SYNC_END_REG_NUM, {{CR57, 0, 7}, {CR5C, 6, 6} } },
241 /* IGA2 Vertical Total */
242 {IGA2_VER_TOTAL_REG_NUM, {{CR58, 0, 7}, {CR5D, 0, 2} } },
243 /* IGA2 Vertical Addressable Video */
244 {IGA2_VER_ADDR_REG_NUM, {{CR59, 0, 7}, {CR5D, 3, 5} } },
245 /* IGA2 Vertical Blank Start */
246 {IGA2_VER_BLANK_START_REG_NUM, {{CR5A, 0, 7}, {CR5C, 0, 2} } },
247 /* IGA2 Vertical Blank End */
248 {IGA2_VER_BLANK_END_REG_NUM, {{CR5B, 0, 7}, {CR5C, 3, 5} } },
249 /* IGA2 Vertical Sync Start */
250 {IGA2_VER_SYNC_START_REG_NUM, {{CR5E, 0, 7}, {CR5F, 5, 7} } },
251 /* IGA2 Vertical Sync End */
252 {IGA2_VER_SYNC_END_REG_NUM, {{CR5F, 0, 4} } }
253 };
254
255 static struct rgbLUT palLUT_table[] = {
256 /* {R,G,B} */
257 /* Index 0x00~0x03 */
258 {0x00, 0x00, 0x00}, {0x00, 0x00, 0x2A}, {0x00, 0x2A, 0x00}, {0x00,
259 0x2A,
260 0x2A},
261 /* Index 0x04~0x07 */
262 {0x2A, 0x00, 0x00}, {0x2A, 0x00, 0x2A}, {0x2A, 0x15, 0x00}, {0x2A,
263 0x2A,
264 0x2A},
265 /* Index 0x08~0x0B */
266 {0x15, 0x15, 0x15}, {0x15, 0x15, 0x3F}, {0x15, 0x3F, 0x15}, {0x15,
267 0x3F,
268 0x3F},
269 /* Index 0x0C~0x0F */
270 {0x3F, 0x15, 0x15}, {0x3F, 0x15, 0x3F}, {0x3F, 0x3F, 0x15}, {0x3F,
271 0x3F,
272 0x3F},
273 /* Index 0x10~0x13 */
274 {0x00, 0x00, 0x00}, {0x05, 0x05, 0x05}, {0x08, 0x08, 0x08}, {0x0B,
275 0x0B,
276 0x0B},
277 /* Index 0x14~0x17 */
278 {0x0E, 0x0E, 0x0E}, {0x11, 0x11, 0x11}, {0x14, 0x14, 0x14}, {0x18,
279 0x18,
280 0x18},
281 /* Index 0x18~0x1B */
282 {0x1C, 0x1C, 0x1C}, {0x20, 0x20, 0x20}, {0x24, 0x24, 0x24}, {0x28,
283 0x28,
284 0x28},
285 /* Index 0x1C~0x1F */
286 {0x2D, 0x2D, 0x2D}, {0x32, 0x32, 0x32}, {0x38, 0x38, 0x38}, {0x3F,
287 0x3F,
288 0x3F},
289 /* Index 0x20~0x23 */
290 {0x00, 0x00, 0x3F}, {0x10, 0x00, 0x3F}, {0x1F, 0x00, 0x3F}, {0x2F,
291 0x00,
292 0x3F},
293 /* Index 0x24~0x27 */
294 {0x3F, 0x00, 0x3F}, {0x3F, 0x00, 0x2F}, {0x3F, 0x00, 0x1F}, {0x3F,
295 0x00,
296 0x10},
297 /* Index 0x28~0x2B */
298 {0x3F, 0x00, 0x00}, {0x3F, 0x10, 0x00}, {0x3F, 0x1F, 0x00}, {0x3F,
299 0x2F,
300 0x00},
301 /* Index 0x2C~0x2F */
302 {0x3F, 0x3F, 0x00}, {0x2F, 0x3F, 0x00}, {0x1F, 0x3F, 0x00}, {0x10,
303 0x3F,
304 0x00},
305 /* Index 0x30~0x33 */
306 {0x00, 0x3F, 0x00}, {0x00, 0x3F, 0x10}, {0x00, 0x3F, 0x1F}, {0x00,
307 0x3F,
308 0x2F},
309 /* Index 0x34~0x37 */
310 {0x00, 0x3F, 0x3F}, {0x00, 0x2F, 0x3F}, {0x00, 0x1F, 0x3F}, {0x00,
311 0x10,
312 0x3F},
313 /* Index 0x38~0x3B */
314 {0x1F, 0x1F, 0x3F}, {0x27, 0x1F, 0x3F}, {0x2F, 0x1F, 0x3F}, {0x37,
315 0x1F,
316 0x3F},
317 /* Index 0x3C~0x3F */
318 {0x3F, 0x1F, 0x3F}, {0x3F, 0x1F, 0x37}, {0x3F, 0x1F, 0x2F}, {0x3F,
319 0x1F,
320 0x27},
321 /* Index 0x40~0x43 */
322 {0x3F, 0x1F, 0x1F}, {0x3F, 0x27, 0x1F}, {0x3F, 0x2F, 0x1F}, {0x3F,
323 0x3F,
324 0x1F},
325 /* Index 0x44~0x47 */
326 {0x3F, 0x3F, 0x1F}, {0x37, 0x3F, 0x1F}, {0x2F, 0x3F, 0x1F}, {0x27,
327 0x3F,
328 0x1F},
329 /* Index 0x48~0x4B */
330 {0x1F, 0x3F, 0x1F}, {0x1F, 0x3F, 0x27}, {0x1F, 0x3F, 0x2F}, {0x1F,
331 0x3F,
332 0x37},
333 /* Index 0x4C~0x4F */
334 {0x1F, 0x3F, 0x3F}, {0x1F, 0x37, 0x3F}, {0x1F, 0x2F, 0x3F}, {0x1F,
335 0x27,
336 0x3F},
337 /* Index 0x50~0x53 */
338 {0x2D, 0x2D, 0x3F}, {0x31, 0x2D, 0x3F}, {0x36, 0x2D, 0x3F}, {0x3A,
339 0x2D,
340 0x3F},
341 /* Index 0x54~0x57 */
342 {0x3F, 0x2D, 0x3F}, {0x3F, 0x2D, 0x3A}, {0x3F, 0x2D, 0x36}, {0x3F,
343 0x2D,
344 0x31},
345 /* Index 0x58~0x5B */
346 {0x3F, 0x2D, 0x2D}, {0x3F, 0x31, 0x2D}, {0x3F, 0x36, 0x2D}, {0x3F,
347 0x3A,
348 0x2D},
349 /* Index 0x5C~0x5F */
350 {0x3F, 0x3F, 0x2D}, {0x3A, 0x3F, 0x2D}, {0x36, 0x3F, 0x2D}, {0x31,
351 0x3F,
352 0x2D},
353 /* Index 0x60~0x63 */
354 {0x2D, 0x3F, 0x2D}, {0x2D, 0x3F, 0x31}, {0x2D, 0x3F, 0x36}, {0x2D,
355 0x3F,
356 0x3A},
357 /* Index 0x64~0x67 */
358 {0x2D, 0x3F, 0x3F}, {0x2D, 0x3A, 0x3F}, {0x2D, 0x36, 0x3F}, {0x2D,
359 0x31,
360 0x3F},
361 /* Index 0x68~0x6B */
362 {0x00, 0x00, 0x1C}, {0x07, 0x00, 0x1C}, {0x0E, 0x00, 0x1C}, {0x15,
363 0x00,
364 0x1C},
365 /* Index 0x6C~0x6F */
366 {0x1C, 0x00, 0x1C}, {0x1C, 0x00, 0x15}, {0x1C, 0x00, 0x0E}, {0x1C,
367 0x00,
368 0x07},
369 /* Index 0x70~0x73 */
370 {0x1C, 0x00, 0x00}, {0x1C, 0x07, 0x00}, {0x1C, 0x0E, 0x00}, {0x1C,
371 0x15,
372 0x00},
373 /* Index 0x74~0x77 */
374 {0x1C, 0x1C, 0x00}, {0x15, 0x1C, 0x00}, {0x0E, 0x1C, 0x00}, {0x07,
375 0x1C,
376 0x00},
377 /* Index 0x78~0x7B */
378 {0x00, 0x1C, 0x00}, {0x00, 0x1C, 0x07}, {0x00, 0x1C, 0x0E}, {0x00,
379 0x1C,
380 0x15},
381 /* Index 0x7C~0x7F */
382 {0x00, 0x1C, 0x1C}, {0x00, 0x15, 0x1C}, {0x00, 0x0E, 0x1C}, {0x00,
383 0x07,
384 0x1C},
385 /* Index 0x80~0x83 */
386 {0x0E, 0x0E, 0x1C}, {0x11, 0x0E, 0x1C}, {0x15, 0x0E, 0x1C}, {0x18,
387 0x0E,
388 0x1C},
389 /* Index 0x84~0x87 */
390 {0x1C, 0x0E, 0x1C}, {0x1C, 0x0E, 0x18}, {0x1C, 0x0E, 0x15}, {0x1C,
391 0x0E,
392 0x11},
393 /* Index 0x88~0x8B */
394 {0x1C, 0x0E, 0x0E}, {0x1C, 0x11, 0x0E}, {0x1C, 0x15, 0x0E}, {0x1C,
395 0x18,
396 0x0E},
397 /* Index 0x8C~0x8F */
398 {0x1C, 0x1C, 0x0E}, {0x18, 0x1C, 0x0E}, {0x15, 0x1C, 0x0E}, {0x11,
399 0x1C,
400 0x0E},
401 /* Index 0x90~0x93 */
402 {0x0E, 0x1C, 0x0E}, {0x0E, 0x1C, 0x11}, {0x0E, 0x1C, 0x15}, {0x0E,
403 0x1C,
404 0x18},
405 /* Index 0x94~0x97 */
406 {0x0E, 0x1C, 0x1C}, {0x0E, 0x18, 0x1C}, {0x0E, 0x15, 0x1C}, {0x0E,
407 0x11,
408 0x1C},
409 /* Index 0x98~0x9B */
410 {0x14, 0x14, 0x1C}, {0x16, 0x14, 0x1C}, {0x18, 0x14, 0x1C}, {0x1A,
411 0x14,
412 0x1C},
413 /* Index 0x9C~0x9F */
414 {0x1C, 0x14, 0x1C}, {0x1C, 0x14, 0x1A}, {0x1C, 0x14, 0x18}, {0x1C,
415 0x14,
416 0x16},
417 /* Index 0xA0~0xA3 */
418 {0x1C, 0x14, 0x14}, {0x1C, 0x16, 0x14}, {0x1C, 0x18, 0x14}, {0x1C,
419 0x1A,
420 0x14},
421 /* Index 0xA4~0xA7 */
422 {0x1C, 0x1C, 0x14}, {0x1A, 0x1C, 0x14}, {0x18, 0x1C, 0x14}, {0x16,
423 0x1C,
424 0x14},
425 /* Index 0xA8~0xAB */
426 {0x14, 0x1C, 0x14}, {0x14, 0x1C, 0x16}, {0x14, 0x1C, 0x18}, {0x14,
427 0x1C,
428 0x1A},
429 /* Index 0xAC~0xAF */
430 {0x14, 0x1C, 0x1C}, {0x14, 0x1A, 0x1C}, {0x14, 0x18, 0x1C}, {0x14,
431 0x16,
432 0x1C},
433 /* Index 0xB0~0xB3 */
434 {0x00, 0x00, 0x10}, {0x04, 0x00, 0x10}, {0x08, 0x00, 0x10}, {0x0C,
435 0x00,
436 0x10},
437 /* Index 0xB4~0xB7 */
438 {0x10, 0x00, 0x10}, {0x10, 0x00, 0x0C}, {0x10, 0x00, 0x08}, {0x10,
439 0x00,
440 0x04},
441 /* Index 0xB8~0xBB */
442 {0x10, 0x00, 0x00}, {0x10, 0x04, 0x00}, {0x10, 0x08, 0x00}, {0x10,
443 0x0C,
444 0x00},
445 /* Index 0xBC~0xBF */
446 {0x10, 0x10, 0x00}, {0x0C, 0x10, 0x00}, {0x08, 0x10, 0x00}, {0x04,
447 0x10,
448 0x00},
449 /* Index 0xC0~0xC3 */
450 {0x00, 0x10, 0x00}, {0x00, 0x10, 0x04}, {0x00, 0x10, 0x08}, {0x00,
451 0x10,
452 0x0C},
453 /* Index 0xC4~0xC7 */
454 {0x00, 0x10, 0x10}, {0x00, 0x0C, 0x10}, {0x00, 0x08, 0x10}, {0x00,
455 0x04,
456 0x10},
457 /* Index 0xC8~0xCB */
458 {0x08, 0x08, 0x10}, {0x0A, 0x08, 0x10}, {0x0C, 0x08, 0x10}, {0x0E,
459 0x08,
460 0x10},
461 /* Index 0xCC~0xCF */
462 {0x10, 0x08, 0x10}, {0x10, 0x08, 0x0E}, {0x10, 0x08, 0x0C}, {0x10,
463 0x08,
464 0x0A},
465 /* Index 0xD0~0xD3 */
466 {0x10, 0x08, 0x08}, {0x10, 0x0A, 0x08}, {0x10, 0x0C, 0x08}, {0x10,
467 0x0E,
468 0x08},
469 /* Index 0xD4~0xD7 */
470 {0x10, 0x10, 0x08}, {0x0E, 0x10, 0x08}, {0x0C, 0x10, 0x08}, {0x0A,
471 0x10,
472 0x08},
473 /* Index 0xD8~0xDB */
474 {0x08, 0x10, 0x08}, {0x08, 0x10, 0x0A}, {0x08, 0x10, 0x0C}, {0x08,
475 0x10,
476 0x0E},
477 /* Index 0xDC~0xDF */
478 {0x08, 0x10, 0x10}, {0x08, 0x0E, 0x10}, {0x08, 0x0C, 0x10}, {0x08,
479 0x0A,
480 0x10},
481 /* Index 0xE0~0xE3 */
482 {0x0B, 0x0B, 0x10}, {0x0C, 0x0B, 0x10}, {0x0D, 0x0B, 0x10}, {0x0F,
483 0x0B,
484 0x10},
485 /* Index 0xE4~0xE7 */
486 {0x10, 0x0B, 0x10}, {0x10, 0x0B, 0x0F}, {0x10, 0x0B, 0x0D}, {0x10,
487 0x0B,
488 0x0C},
489 /* Index 0xE8~0xEB */
490 {0x10, 0x0B, 0x0B}, {0x10, 0x0C, 0x0B}, {0x10, 0x0D, 0x0B}, {0x10,
491 0x0F,
492 0x0B},
493 /* Index 0xEC~0xEF */
494 {0x10, 0x10, 0x0B}, {0x0F, 0x10, 0x0B}, {0x0D, 0x10, 0x0B}, {0x0C,
495 0x10,
496 0x0B},
497 /* Index 0xF0~0xF3 */
498 {0x0B, 0x10, 0x0B}, {0x0B, 0x10, 0x0C}, {0x0B, 0x10, 0x0D}, {0x0B,
499 0x10,
500 0x0F},
501 /* Index 0xF4~0xF7 */
502 {0x0B, 0x10, 0x10}, {0x0B, 0x0F, 0x10}, {0x0B, 0x0D, 0x10}, {0x0B,
503 0x0C,
504 0x10},
505 /* Index 0xF8~0xFB */
506 {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00,
507 0x00,
508 0x00},
509 /* Index 0xFC~0xFF */
510 {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00,
511 0x00,
512 0x00}
513 };
514
515 static struct via_device_mapping device_mapping[] = {
516 {VIA_LDVP0, "LDVP0"},
517 {VIA_LDVP1, "LDVP1"},
518 {VIA_DVP0, "DVP0"},
519 {VIA_CRT, "CRT"},
520 {VIA_DVP1, "DVP1"},
521 {VIA_LVDS1, "LVDS1"},
522 {VIA_LVDS2, "LVDS2"}
523 };
524
525 /* structure with function pointers to support clock control */
526 static struct via_clock clock;
527
528 static void load_fix_bit_crtc_reg(void);
529 static void __devinit init_gfx_chip_info(int chip_type);
530 static void __devinit init_tmds_chip_info(void);
531 static void __devinit init_lvds_chip_info(void);
532 static void device_screen_off(void);
533 static void device_screen_on(void);
534 static void set_display_channel(void);
535 static void device_off(void);
536 static void device_on(void);
537 static void enable_second_display_channel(void);
538 static void disable_second_display_channel(void);
539
540 void viafb_lock_crt(void)
541 {
542 viafb_write_reg_mask(CR11, VIACR, BIT7, BIT7);
543 }
544
545 void viafb_unlock_crt(void)
546 {
547 viafb_write_reg_mask(CR11, VIACR, 0, BIT7);
548 viafb_write_reg_mask(CR47, VIACR, 0, BIT0);
549 }
550
551 static void write_dac_reg(u8 index, u8 r, u8 g, u8 b)
552 {
553 outb(index, LUT_INDEX_WRITE);
554 outb(r, LUT_DATA);
555 outb(g, LUT_DATA);
556 outb(b, LUT_DATA);
557 }
558
559 static u32 get_dvi_devices(int output_interface)
560 {
561 switch (output_interface) {
562 case INTERFACE_DVP0:
563 return VIA_DVP0 | VIA_LDVP0;
564
565 case INTERFACE_DVP1:
566 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
567 return VIA_LDVP1;
568 else
569 return VIA_DVP1;
570
571 case INTERFACE_DFP_HIGH:
572 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
573 return 0;
574 else
575 return VIA_LVDS2 | VIA_DVP0;
576
577 case INTERFACE_DFP_LOW:
578 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
579 return 0;
580 else
581 return VIA_DVP1 | VIA_LVDS1;
582
583 case INTERFACE_TMDS:
584 return VIA_LVDS1;
585 }
586
587 return 0;
588 }
589
590 static u32 get_lcd_devices(int output_interface)
591 {
592 switch (output_interface) {
593 case INTERFACE_DVP0:
594 return VIA_DVP0;
595
596 case INTERFACE_DVP1:
597 return VIA_DVP1;
598
599 case INTERFACE_DFP_HIGH:
600 return VIA_LVDS2 | VIA_DVP0;
601
602 case INTERFACE_DFP_LOW:
603 return VIA_LVDS1 | VIA_DVP1;
604
605 case INTERFACE_DFP:
606 return VIA_LVDS1 | VIA_LVDS2;
607
608 case INTERFACE_LVDS0:
609 case INTERFACE_LVDS0LVDS1:
610 return VIA_LVDS1;
611
612 case INTERFACE_LVDS1:
613 return VIA_LVDS2;
614 }
615
616 return 0;
617 }
618
619 /*Set IGA path for each device*/
620 void viafb_set_iga_path(void)
621 {
622 int crt_iga_path = 0;
623
624 if (viafb_SAMM_ON == 1) {
625 if (viafb_CRT_ON) {
626 if (viafb_primary_dev == CRT_Device)
627 crt_iga_path = IGA1;
628 else
629 crt_iga_path = IGA2;
630 }
631
632 if (viafb_DVI_ON) {
633 if (viafb_primary_dev == DVI_Device)
634 viaparinfo->tmds_setting_info->iga_path = IGA1;
635 else
636 viaparinfo->tmds_setting_info->iga_path = IGA2;
637 }
638
639 if (viafb_LCD_ON) {
640 if (viafb_primary_dev == LCD_Device) {
641 if (viafb_dual_fb &&
642 (viaparinfo->chip_info->gfx_chip_name ==
643 UNICHROME_CLE266)) {
644 viaparinfo->
645 lvds_setting_info->iga_path = IGA2;
646 crt_iga_path = IGA1;
647 viaparinfo->
648 tmds_setting_info->iga_path = IGA1;
649 } else
650 viaparinfo->
651 lvds_setting_info->iga_path = IGA1;
652 } else {
653 viaparinfo->lvds_setting_info->iga_path = IGA2;
654 }
655 }
656 if (viafb_LCD2_ON) {
657 if (LCD2_Device == viafb_primary_dev)
658 viaparinfo->lvds_setting_info2->iga_path = IGA1;
659 else
660 viaparinfo->lvds_setting_info2->iga_path = IGA2;
661 }
662 } else {
663 viafb_SAMM_ON = 0;
664
665 if (viafb_CRT_ON && viafb_LCD_ON) {
666 crt_iga_path = IGA1;
667 viaparinfo->lvds_setting_info->iga_path = IGA2;
668 } else if (viafb_CRT_ON && viafb_DVI_ON) {
669 crt_iga_path = IGA1;
670 viaparinfo->tmds_setting_info->iga_path = IGA2;
671 } else if (viafb_LCD_ON && viafb_DVI_ON) {
672 viaparinfo->tmds_setting_info->iga_path = IGA1;
673 viaparinfo->lvds_setting_info->iga_path = IGA2;
674 } else if (viafb_LCD_ON && viafb_LCD2_ON) {
675 viaparinfo->lvds_setting_info->iga_path = IGA2;
676 viaparinfo->lvds_setting_info2->iga_path = IGA2;
677 } else if (viafb_CRT_ON) {
678 crt_iga_path = IGA1;
679 } else if (viafb_LCD_ON) {
680 viaparinfo->lvds_setting_info->iga_path = IGA2;
681 } else if (viafb_DVI_ON) {
682 viaparinfo->tmds_setting_info->iga_path = IGA1;
683 }
684 }
685
686 viaparinfo->shared->iga1_devices = 0;
687 viaparinfo->shared->iga2_devices = 0;
688 if (viafb_CRT_ON) {
689 if (crt_iga_path == IGA1)
690 viaparinfo->shared->iga1_devices |= VIA_CRT;
691 else
692 viaparinfo->shared->iga2_devices |= VIA_CRT;
693 }
694
695 if (viafb_DVI_ON) {
696 if (viaparinfo->tmds_setting_info->iga_path == IGA1)
697 viaparinfo->shared->iga1_devices |= get_dvi_devices(
698 viaparinfo->chip_info->
699 tmds_chip_info.output_interface);
700 else
701 viaparinfo->shared->iga2_devices |= get_dvi_devices(
702 viaparinfo->chip_info->
703 tmds_chip_info.output_interface);
704 }
705
706 if (viafb_LCD_ON) {
707 if (viaparinfo->lvds_setting_info->iga_path == IGA1)
708 viaparinfo->shared->iga1_devices |= get_lcd_devices(
709 viaparinfo->chip_info->
710 lvds_chip_info.output_interface);
711 else
712 viaparinfo->shared->iga2_devices |= get_lcd_devices(
713 viaparinfo->chip_info->
714 lvds_chip_info.output_interface);
715 }
716
717 if (viafb_LCD2_ON) {
718 if (viaparinfo->lvds_setting_info2->iga_path == IGA1)
719 viaparinfo->shared->iga1_devices |= get_lcd_devices(
720 viaparinfo->chip_info->
721 lvds_chip_info2.output_interface);
722 else
723 viaparinfo->shared->iga2_devices |= get_lcd_devices(
724 viaparinfo->chip_info->
725 lvds_chip_info2.output_interface);
726 }
727
728 /* looks like the OLPC has its display wired to DVP1 and LVDS2 */
729 if (machine_is_olpc())
730 viaparinfo->shared->iga2_devices = VIA_DVP1 | VIA_LVDS2;
731 }
732
733 static void set_color_register(u8 index, u8 red, u8 green, u8 blue)
734 {
735 outb(0xFF, 0x3C6); /* bit mask of palette */
736 outb(index, 0x3C8);
737 outb(red, 0x3C9);
738 outb(green, 0x3C9);
739 outb(blue, 0x3C9);
740 }
741
742 void viafb_set_primary_color_register(u8 index, u8 red, u8 green, u8 blue)
743 {
744 viafb_write_reg_mask(0x1A, VIASR, 0x00, 0x01);
745 set_color_register(index, red, green, blue);
746 }
747
748 void viafb_set_secondary_color_register(u8 index, u8 red, u8 green, u8 blue)
749 {
750 viafb_write_reg_mask(0x1A, VIASR, 0x01, 0x01);
751 set_color_register(index, red, green, blue);
752 }
753
754 static void set_source_common(u8 index, u8 offset, u8 iga)
755 {
756 u8 value, mask = 1 << offset;
757
758 switch (iga) {
759 case IGA1:
760 value = 0x00;
761 break;
762 case IGA2:
763 value = mask;
764 break;
765 default:
766 printk(KERN_WARNING "viafb: Unsupported source: %d\n", iga);
767 return;
768 }
769
770 via_write_reg_mask(VIACR, index, value, mask);
771 }
772
773 static void set_crt_source(u8 iga)
774 {
775 u8 value;
776
777 switch (iga) {
778 case IGA1:
779 value = 0x00;
780 break;
781 case IGA2:
782 value = 0x40;
783 break;
784 default:
785 printk(KERN_WARNING "viafb: Unsupported source: %d\n", iga);
786 return;
787 }
788
789 via_write_reg_mask(VIASR, 0x16, value, 0x40);
790 }
791
792 static inline void set_ldvp0_source(u8 iga)
793 {
794 set_source_common(0x6C, 7, iga);
795 }
796
797 static inline void set_ldvp1_source(u8 iga)
798 {
799 set_source_common(0x93, 7, iga);
800 }
801
802 static inline void set_dvp0_source(u8 iga)
803 {
804 set_source_common(0x96, 4, iga);
805 }
806
807 static inline void set_dvp1_source(u8 iga)
808 {
809 set_source_common(0x9B, 4, iga);
810 }
811
812 static inline void set_lvds1_source(u8 iga)
813 {
814 set_source_common(0x99, 4, iga);
815 }
816
817 static inline void set_lvds2_source(u8 iga)
818 {
819 set_source_common(0x97, 4, iga);
820 }
821
822 void via_set_source(u32 devices, u8 iga)
823 {
824 if (devices & VIA_LDVP0)
825 set_ldvp0_source(iga);
826 if (devices & VIA_LDVP1)
827 set_ldvp1_source(iga);
828 if (devices & VIA_DVP0)
829 set_dvp0_source(iga);
830 if (devices & VIA_CRT)
831 set_crt_source(iga);
832 if (devices & VIA_DVP1)
833 set_dvp1_source(iga);
834 if (devices & VIA_LVDS1)
835 set_lvds1_source(iga);
836 if (devices & VIA_LVDS2)
837 set_lvds2_source(iga);
838 }
839
840 static void set_crt_state(u8 state)
841 {
842 u8 value;
843
844 switch (state) {
845 case VIA_STATE_ON:
846 value = 0x00;
847 break;
848 case VIA_STATE_STANDBY:
849 value = 0x10;
850 break;
851 case VIA_STATE_SUSPEND:
852 value = 0x20;
853 break;
854 case VIA_STATE_OFF:
855 value = 0x30;
856 break;
857 default:
858 return;
859 }
860
861 via_write_reg_mask(VIACR, 0x36, value, 0x30);
862 }
863
864 static void set_dvp0_state(u8 state)
865 {
866 u8 value;
867
868 switch (state) {
869 case VIA_STATE_ON:
870 value = 0xC0;
871 break;
872 case VIA_STATE_OFF:
873 value = 0x00;
874 break;
875 default:
876 return;
877 }
878
879 via_write_reg_mask(VIASR, 0x1E, value, 0xC0);
880 }
881
882 static void set_dvp1_state(u8 state)
883 {
884 u8 value;
885
886 switch (state) {
887 case VIA_STATE_ON:
888 value = 0x30;
889 break;
890 case VIA_STATE_OFF:
891 value = 0x00;
892 break;
893 default:
894 return;
895 }
896
897 via_write_reg_mask(VIASR, 0x1E, value, 0x30);
898 }
899
900 static void set_lvds1_state(u8 state)
901 {
902 u8 value;
903
904 switch (state) {
905 case VIA_STATE_ON:
906 value = 0x03;
907 break;
908 case VIA_STATE_OFF:
909 value = 0x00;
910 break;
911 default:
912 return;
913 }
914
915 via_write_reg_mask(VIASR, 0x2A, value, 0x03);
916 }
917
918 static void set_lvds2_state(u8 state)
919 {
920 u8 value;
921
922 switch (state) {
923 case VIA_STATE_ON:
924 value = 0x0C;
925 break;
926 case VIA_STATE_OFF:
927 value = 0x00;
928 break;
929 default:
930 return;
931 }
932
933 via_write_reg_mask(VIASR, 0x2A, value, 0x0C);
934 }
935
936 void via_set_state(u32 devices, u8 state)
937 {
938 /*
939 TODO: Can we enable/disable these devices? How?
940 if (devices & VIA_LDVP0)
941 if (devices & VIA_LDVP1)
942 */
943 if (devices & VIA_DVP0)
944 set_dvp0_state(state);
945 if (devices & VIA_CRT)
946 set_crt_state(state);
947 if (devices & VIA_DVP1)
948 set_dvp1_state(state);
949 if (devices & VIA_LVDS1)
950 set_lvds1_state(state);
951 if (devices & VIA_LVDS2)
952 set_lvds2_state(state);
953 }
954
955 void via_set_sync_polarity(u32 devices, u8 polarity)
956 {
957 if (polarity & ~(VIA_HSYNC_NEGATIVE | VIA_VSYNC_NEGATIVE)) {
958 printk(KERN_WARNING "viafb: Unsupported polarity: %d\n",
959 polarity);
960 return;
961 }
962
963 if (devices & VIA_CRT)
964 via_write_misc_reg_mask(polarity << 6, 0xC0);
965 if (devices & VIA_DVP1)
966 via_write_reg_mask(VIACR, 0x9B, polarity << 5, 0x60);
967 if (devices & VIA_LVDS1)
968 via_write_reg_mask(VIACR, 0x99, polarity << 5, 0x60);
969 if (devices & VIA_LVDS2)
970 via_write_reg_mask(VIACR, 0x97, polarity << 5, 0x60);
971 }
972
973 u32 via_parse_odev(char *input, char **end)
974 {
975 char *ptr = input;
976 u32 odev = 0;
977 bool next = true;
978 int i, len;
979
980 while (next) {
981 next = false;
982 for (i = 0; i < ARRAY_SIZE(device_mapping); i++) {
983 len = strlen(device_mapping[i].name);
984 if (!strncmp(ptr, device_mapping[i].name, len)) {
985 odev |= device_mapping[i].device;
986 ptr += len;
987 if (*ptr == ',') {
988 ptr++;
989 next = true;
990 }
991 }
992 }
993 }
994
995 *end = ptr;
996 return odev;
997 }
998
999 void via_odev_to_seq(struct seq_file *m, u32 odev)
1000 {
1001 int i, count = 0;
1002
1003 for (i = 0; i < ARRAY_SIZE(device_mapping); i++) {
1004 if (odev & device_mapping[i].device) {
1005 if (count > 0)
1006 seq_putc(m, ',');
1007
1008 seq_puts(m, device_mapping[i].name);
1009 count++;
1010 }
1011 }
1012
1013 seq_putc(m, '\n');
1014 }
1015
1016 static void load_fix_bit_crtc_reg(void)
1017 {
1018 viafb_unlock_crt();
1019
1020 /* always set to 1 */
1021 viafb_write_reg_mask(CR03, VIACR, 0x80, BIT7);
1022 /* line compare should set all bits = 1 (extend modes) */
1023 viafb_write_reg_mask(CR35, VIACR, 0x10, BIT4);
1024 /* line compare should set all bits = 1 (extend modes) */
1025 viafb_write_reg_mask(CR33, VIACR, 0x06, BIT0 + BIT1 + BIT2);
1026 /*viafb_write_reg_mask(CR32, VIACR, 0x01, BIT0); */
1027
1028 viafb_lock_crt();
1029
1030 /* If K8M800, enable Prefetch Mode. */
1031 if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800)
1032 || (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890))
1033 viafb_write_reg_mask(CR33, VIACR, 0x08, BIT3);
1034 if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
1035 && (viaparinfo->chip_info->gfx_chip_revision == CLE266_REVISION_AX))
1036 viafb_write_reg_mask(SR1A, VIASR, 0x02, BIT1);
1037
1038 }
1039
1040 void viafb_load_reg(int timing_value, int viafb_load_reg_num,
1041 struct io_register *reg,
1042 int io_type)
1043 {
1044 int reg_mask;
1045 int bit_num = 0;
1046 int data;
1047 int i, j;
1048 int shift_next_reg;
1049 int start_index, end_index, cr_index;
1050 u16 get_bit;
1051
1052 for (i = 0; i < viafb_load_reg_num; i++) {
1053 reg_mask = 0;
1054 data = 0;
1055 start_index = reg[i].start_bit;
1056 end_index = reg[i].end_bit;
1057 cr_index = reg[i].io_addr;
1058
1059 shift_next_reg = bit_num;
1060 for (j = start_index; j <= end_index; j++) {
1061 /*if (bit_num==8) timing_value = timing_value >>8; */
1062 reg_mask = reg_mask | (BIT0 << j);
1063 get_bit = (timing_value & (BIT0 << bit_num));
1064 data =
1065 data | ((get_bit >> shift_next_reg) << start_index);
1066 bit_num++;
1067 }
1068 if (io_type == VIACR)
1069 viafb_write_reg_mask(cr_index, VIACR, data, reg_mask);
1070 else
1071 viafb_write_reg_mask(cr_index, VIASR, data, reg_mask);
1072 }
1073
1074 }
1075
1076 /* Write Registers */
1077 void viafb_write_regx(struct io_reg RegTable[], int ItemNum)
1078 {
1079 int i;
1080
1081 /*DEBUG_MSG(KERN_INFO "Table Size : %x!!\n",ItemNum ); */
1082
1083 for (i = 0; i < ItemNum; i++)
1084 via_write_reg_mask(RegTable[i].port, RegTable[i].index,
1085 RegTable[i].value, RegTable[i].mask);
1086 }
1087
1088 void viafb_load_fetch_count_reg(int h_addr, int bpp_byte, int set_iga)
1089 {
1090 int reg_value;
1091 int viafb_load_reg_num;
1092 struct io_register *reg = NULL;
1093
1094 switch (set_iga) {
1095 case IGA1:
1096 reg_value = IGA1_FETCH_COUNT_FORMULA(h_addr, bpp_byte);
1097 viafb_load_reg_num = fetch_count_reg.
1098 iga1_fetch_count_reg.reg_num;
1099 reg = fetch_count_reg.iga1_fetch_count_reg.reg;
1100 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1101 break;
1102 case IGA2:
1103 reg_value = IGA2_FETCH_COUNT_FORMULA(h_addr, bpp_byte);
1104 viafb_load_reg_num = fetch_count_reg.
1105 iga2_fetch_count_reg.reg_num;
1106 reg = fetch_count_reg.iga2_fetch_count_reg.reg;
1107 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1108 break;
1109 }
1110
1111 }
1112
1113 void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active)
1114 {
1115 int reg_value;
1116 int viafb_load_reg_num;
1117 struct io_register *reg = NULL;
1118 int iga1_fifo_max_depth = 0, iga1_fifo_threshold =
1119 0, iga1_fifo_high_threshold = 0, iga1_display_queue_expire_num = 0;
1120 int iga2_fifo_max_depth = 0, iga2_fifo_threshold =
1121 0, iga2_fifo_high_threshold = 0, iga2_display_queue_expire_num = 0;
1122
1123 if (set_iga == IGA1) {
1124 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1125 iga1_fifo_max_depth = K800_IGA1_FIFO_MAX_DEPTH;
1126 iga1_fifo_threshold = K800_IGA1_FIFO_THRESHOLD;
1127 iga1_fifo_high_threshold =
1128 K800_IGA1_FIFO_HIGH_THRESHOLD;
1129 /* If resolution > 1280x1024, expire length = 64, else
1130 expire length = 128 */
1131 if ((hor_active > 1280) && (ver_active > 1024))
1132 iga1_display_queue_expire_num = 16;
1133 else
1134 iga1_display_queue_expire_num =
1135 K800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1136
1137 }
1138
1139 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_PM800) {
1140 iga1_fifo_max_depth = P880_IGA1_FIFO_MAX_DEPTH;
1141 iga1_fifo_threshold = P880_IGA1_FIFO_THRESHOLD;
1142 iga1_fifo_high_threshold =
1143 P880_IGA1_FIFO_HIGH_THRESHOLD;
1144 iga1_display_queue_expire_num =
1145 P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1146
1147 /* If resolution > 1280x1024, expire length = 64, else
1148 expire length = 128 */
1149 if ((hor_active > 1280) && (ver_active > 1024))
1150 iga1_display_queue_expire_num = 16;
1151 else
1152 iga1_display_queue_expire_num =
1153 P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1154 }
1155
1156 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CN700) {
1157 iga1_fifo_max_depth = CN700_IGA1_FIFO_MAX_DEPTH;
1158 iga1_fifo_threshold = CN700_IGA1_FIFO_THRESHOLD;
1159 iga1_fifo_high_threshold =
1160 CN700_IGA1_FIFO_HIGH_THRESHOLD;
1161
1162 /* If resolution > 1280x1024, expire length = 64,
1163 else expire length = 128 */
1164 if ((hor_active > 1280) && (ver_active > 1024))
1165 iga1_display_queue_expire_num = 16;
1166 else
1167 iga1_display_queue_expire_num =
1168 CN700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1169 }
1170
1171 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1172 iga1_fifo_max_depth = CX700_IGA1_FIFO_MAX_DEPTH;
1173 iga1_fifo_threshold = CX700_IGA1_FIFO_THRESHOLD;
1174 iga1_fifo_high_threshold =
1175 CX700_IGA1_FIFO_HIGH_THRESHOLD;
1176 iga1_display_queue_expire_num =
1177 CX700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1178 }
1179
1180 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890) {
1181 iga1_fifo_max_depth = K8M890_IGA1_FIFO_MAX_DEPTH;
1182 iga1_fifo_threshold = K8M890_IGA1_FIFO_THRESHOLD;
1183 iga1_fifo_high_threshold =
1184 K8M890_IGA1_FIFO_HIGH_THRESHOLD;
1185 iga1_display_queue_expire_num =
1186 K8M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1187 }
1188
1189 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M890) {
1190 iga1_fifo_max_depth = P4M890_IGA1_FIFO_MAX_DEPTH;
1191 iga1_fifo_threshold = P4M890_IGA1_FIFO_THRESHOLD;
1192 iga1_fifo_high_threshold =
1193 P4M890_IGA1_FIFO_HIGH_THRESHOLD;
1194 iga1_display_queue_expire_num =
1195 P4M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1196 }
1197
1198 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M900) {
1199 iga1_fifo_max_depth = P4M900_IGA1_FIFO_MAX_DEPTH;
1200 iga1_fifo_threshold = P4M900_IGA1_FIFO_THRESHOLD;
1201 iga1_fifo_high_threshold =
1202 P4M900_IGA1_FIFO_HIGH_THRESHOLD;
1203 iga1_display_queue_expire_num =
1204 P4M900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1205 }
1206
1207 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX800) {
1208 iga1_fifo_max_depth = VX800_IGA1_FIFO_MAX_DEPTH;
1209 iga1_fifo_threshold = VX800_IGA1_FIFO_THRESHOLD;
1210 iga1_fifo_high_threshold =
1211 VX800_IGA1_FIFO_HIGH_THRESHOLD;
1212 iga1_display_queue_expire_num =
1213 VX800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1214 }
1215
1216 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX855) {
1217 iga1_fifo_max_depth = VX855_IGA1_FIFO_MAX_DEPTH;
1218 iga1_fifo_threshold = VX855_IGA1_FIFO_THRESHOLD;
1219 iga1_fifo_high_threshold =
1220 VX855_IGA1_FIFO_HIGH_THRESHOLD;
1221 iga1_display_queue_expire_num =
1222 VX855_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1223 }
1224
1225 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX900) {
1226 iga1_fifo_max_depth = VX900_IGA1_FIFO_MAX_DEPTH;
1227 iga1_fifo_threshold = VX900_IGA1_FIFO_THRESHOLD;
1228 iga1_fifo_high_threshold =
1229 VX900_IGA1_FIFO_HIGH_THRESHOLD;
1230 iga1_display_queue_expire_num =
1231 VX900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1232 }
1233
1234 /* Set Display FIFO Depath Select */
1235 reg_value = IGA1_FIFO_DEPTH_SELECT_FORMULA(iga1_fifo_max_depth);
1236 viafb_load_reg_num =
1237 display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg_num;
1238 reg = display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg;
1239 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1240
1241 /* Set Display FIFO Threshold Select */
1242 reg_value = IGA1_FIFO_THRESHOLD_FORMULA(iga1_fifo_threshold);
1243 viafb_load_reg_num =
1244 fifo_threshold_select_reg.
1245 iga1_fifo_threshold_select_reg.reg_num;
1246 reg =
1247 fifo_threshold_select_reg.
1248 iga1_fifo_threshold_select_reg.reg;
1249 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1250
1251 /* Set FIFO High Threshold Select */
1252 reg_value =
1253 IGA1_FIFO_HIGH_THRESHOLD_FORMULA(iga1_fifo_high_threshold);
1254 viafb_load_reg_num =
1255 fifo_high_threshold_select_reg.
1256 iga1_fifo_high_threshold_select_reg.reg_num;
1257 reg =
1258 fifo_high_threshold_select_reg.
1259 iga1_fifo_high_threshold_select_reg.reg;
1260 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1261
1262 /* Set Display Queue Expire Num */
1263 reg_value =
1264 IGA1_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA
1265 (iga1_display_queue_expire_num);
1266 viafb_load_reg_num =
1267 display_queue_expire_num_reg.
1268 iga1_display_queue_expire_num_reg.reg_num;
1269 reg =
1270 display_queue_expire_num_reg.
1271 iga1_display_queue_expire_num_reg.reg;
1272 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1273
1274 } else {
1275 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1276 iga2_fifo_max_depth = K800_IGA2_FIFO_MAX_DEPTH;
1277 iga2_fifo_threshold = K800_IGA2_FIFO_THRESHOLD;
1278 iga2_fifo_high_threshold =
1279 K800_IGA2_FIFO_HIGH_THRESHOLD;
1280
1281 /* If resolution > 1280x1024, expire length = 64,
1282 else expire length = 128 */
1283 if ((hor_active > 1280) && (ver_active > 1024))
1284 iga2_display_queue_expire_num = 16;
1285 else
1286 iga2_display_queue_expire_num =
1287 K800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1288 }
1289
1290 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_PM800) {
1291 iga2_fifo_max_depth = P880_IGA2_FIFO_MAX_DEPTH;
1292 iga2_fifo_threshold = P880_IGA2_FIFO_THRESHOLD;
1293 iga2_fifo_high_threshold =
1294 P880_IGA2_FIFO_HIGH_THRESHOLD;
1295
1296 /* If resolution > 1280x1024, expire length = 64,
1297 else expire length = 128 */
1298 if ((hor_active > 1280) && (ver_active > 1024))
1299 iga2_display_queue_expire_num = 16;
1300 else
1301 iga2_display_queue_expire_num =
1302 P880_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1303 }
1304
1305 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CN700) {
1306 iga2_fifo_max_depth = CN700_IGA2_FIFO_MAX_DEPTH;
1307 iga2_fifo_threshold = CN700_IGA2_FIFO_THRESHOLD;
1308 iga2_fifo_high_threshold =
1309 CN700_IGA2_FIFO_HIGH_THRESHOLD;
1310
1311 /* If resolution > 1280x1024, expire length = 64,
1312 else expire length = 128 */
1313 if ((hor_active > 1280) && (ver_active > 1024))
1314 iga2_display_queue_expire_num = 16;
1315 else
1316 iga2_display_queue_expire_num =
1317 CN700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1318 }
1319
1320 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1321 iga2_fifo_max_depth = CX700_IGA2_FIFO_MAX_DEPTH;
1322 iga2_fifo_threshold = CX700_IGA2_FIFO_THRESHOLD;
1323 iga2_fifo_high_threshold =
1324 CX700_IGA2_FIFO_HIGH_THRESHOLD;
1325 iga2_display_queue_expire_num =
1326 CX700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1327 }
1328
1329 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890) {
1330 iga2_fifo_max_depth = K8M890_IGA2_FIFO_MAX_DEPTH;
1331 iga2_fifo_threshold = K8M890_IGA2_FIFO_THRESHOLD;
1332 iga2_fifo_high_threshold =
1333 K8M890_IGA2_FIFO_HIGH_THRESHOLD;
1334 iga2_display_queue_expire_num =
1335 K8M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1336 }
1337
1338 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M890) {
1339 iga2_fifo_max_depth = P4M890_IGA2_FIFO_MAX_DEPTH;
1340 iga2_fifo_threshold = P4M890_IGA2_FIFO_THRESHOLD;
1341 iga2_fifo_high_threshold =
1342 P4M890_IGA2_FIFO_HIGH_THRESHOLD;
1343 iga2_display_queue_expire_num =
1344 P4M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1345 }
1346
1347 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M900) {
1348 iga2_fifo_max_depth = P4M900_IGA2_FIFO_MAX_DEPTH;
1349 iga2_fifo_threshold = P4M900_IGA2_FIFO_THRESHOLD;
1350 iga2_fifo_high_threshold =
1351 P4M900_IGA2_FIFO_HIGH_THRESHOLD;
1352 iga2_display_queue_expire_num =
1353 P4M900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1354 }
1355
1356 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX800) {
1357 iga2_fifo_max_depth = VX800_IGA2_FIFO_MAX_DEPTH;
1358 iga2_fifo_threshold = VX800_IGA2_FIFO_THRESHOLD;
1359 iga2_fifo_high_threshold =
1360 VX800_IGA2_FIFO_HIGH_THRESHOLD;
1361 iga2_display_queue_expire_num =
1362 VX800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1363 }
1364
1365 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX855) {
1366 iga2_fifo_max_depth = VX855_IGA2_FIFO_MAX_DEPTH;
1367 iga2_fifo_threshold = VX855_IGA2_FIFO_THRESHOLD;
1368 iga2_fifo_high_threshold =
1369 VX855_IGA2_FIFO_HIGH_THRESHOLD;
1370 iga2_display_queue_expire_num =
1371 VX855_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1372 }
1373
1374 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX900) {
1375 iga2_fifo_max_depth = VX900_IGA2_FIFO_MAX_DEPTH;
1376 iga2_fifo_threshold = VX900_IGA2_FIFO_THRESHOLD;
1377 iga2_fifo_high_threshold =
1378 VX900_IGA2_FIFO_HIGH_THRESHOLD;
1379 iga2_display_queue_expire_num =
1380 VX900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1381 }
1382
1383 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1384 /* Set Display FIFO Depath Select */
1385 reg_value =
1386 IGA2_FIFO_DEPTH_SELECT_FORMULA(iga2_fifo_max_depth)
1387 - 1;
1388 /* Patch LCD in IGA2 case */
1389 viafb_load_reg_num =
1390 display_fifo_depth_reg.
1391 iga2_fifo_depth_select_reg.reg_num;
1392 reg =
1393 display_fifo_depth_reg.
1394 iga2_fifo_depth_select_reg.reg;
1395 viafb_load_reg(reg_value,
1396 viafb_load_reg_num, reg, VIACR);
1397 } else {
1398
1399 /* Set Display FIFO Depath Select */
1400 reg_value =
1401 IGA2_FIFO_DEPTH_SELECT_FORMULA(iga2_fifo_max_depth);
1402 viafb_load_reg_num =
1403 display_fifo_depth_reg.
1404 iga2_fifo_depth_select_reg.reg_num;
1405 reg =
1406 display_fifo_depth_reg.
1407 iga2_fifo_depth_select_reg.reg;
1408 viafb_load_reg(reg_value,
1409 viafb_load_reg_num, reg, VIACR);
1410 }
1411
1412 /* Set Display FIFO Threshold Select */
1413 reg_value = IGA2_FIFO_THRESHOLD_FORMULA(iga2_fifo_threshold);
1414 viafb_load_reg_num =
1415 fifo_threshold_select_reg.
1416 iga2_fifo_threshold_select_reg.reg_num;
1417 reg =
1418 fifo_threshold_select_reg.
1419 iga2_fifo_threshold_select_reg.reg;
1420 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1421
1422 /* Set FIFO High Threshold Select */
1423 reg_value =
1424 IGA2_FIFO_HIGH_THRESHOLD_FORMULA(iga2_fifo_high_threshold);
1425 viafb_load_reg_num =
1426 fifo_high_threshold_select_reg.
1427 iga2_fifo_high_threshold_select_reg.reg_num;
1428 reg =
1429 fifo_high_threshold_select_reg.
1430 iga2_fifo_high_threshold_select_reg.reg;
1431 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1432
1433 /* Set Display Queue Expire Num */
1434 reg_value =
1435 IGA2_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA
1436 (iga2_display_queue_expire_num);
1437 viafb_load_reg_num =
1438 display_queue_expire_num_reg.
1439 iga2_display_queue_expire_num_reg.reg_num;
1440 reg =
1441 display_queue_expire_num_reg.
1442 iga2_display_queue_expire_num_reg.reg;
1443 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1444
1445 }
1446
1447 }
1448
1449 static struct via_pll_config get_pll_config(struct pll_limit *limits, int size,
1450 int clk)
1451 {
1452 struct via_pll_config cur, up, down, best = {0, 1, 0};
1453 const u32 f0 = 14318180; /* X1 frequency */
1454 int i, f;
1455
1456 for (i = 0; i < size; i++) {
1457 cur.rshift = limits[i].rshift;
1458 cur.divisor = limits[i].divisor;
1459 cur.multiplier = clk / ((f0 / cur.divisor)>>cur.rshift);
1460 f = abs(get_pll_output_frequency(f0, cur) - clk);
1461 up = down = cur;
1462 up.multiplier++;
1463 down.multiplier--;
1464 if (abs(get_pll_output_frequency(f0, up) - clk) < f)
1465 cur = up;
1466 else if (abs(get_pll_output_frequency(f0, down) - clk) < f)
1467 cur = down;
1468
1469 if (cur.multiplier < limits[i].multiplier_min)
1470 cur.multiplier = limits[i].multiplier_min;
1471 else if (cur.multiplier > limits[i].multiplier_max)
1472 cur.multiplier = limits[i].multiplier_max;
1473
1474 f = abs(get_pll_output_frequency(f0, cur) - clk);
1475 if (f < abs(get_pll_output_frequency(f0, best) - clk))
1476 best = cur;
1477 }
1478
1479 return best;
1480 }
1481
1482 static struct via_pll_config get_best_pll_config(int clk)
1483 {
1484 struct via_pll_config config;
1485
1486 switch (viaparinfo->chip_info->gfx_chip_name) {
1487 case UNICHROME_CLE266:
1488 case UNICHROME_K400:
1489 config = get_pll_config(cle266_pll_limits,
1490 ARRAY_SIZE(cle266_pll_limits), clk);
1491 break;
1492 case UNICHROME_K800:
1493 case UNICHROME_PM800:
1494 case UNICHROME_CN700:
1495 config = get_pll_config(k800_pll_limits,
1496 ARRAY_SIZE(k800_pll_limits), clk);
1497 break;
1498 case UNICHROME_CX700:
1499 case UNICHROME_CN750:
1500 case UNICHROME_K8M890:
1501 case UNICHROME_P4M890:
1502 case UNICHROME_P4M900:
1503 case UNICHROME_VX800:
1504 config = get_pll_config(cx700_pll_limits,
1505 ARRAY_SIZE(cx700_pll_limits), clk);
1506 break;
1507 case UNICHROME_VX855:
1508 case UNICHROME_VX900:
1509 config = get_pll_config(vx855_pll_limits,
1510 ARRAY_SIZE(vx855_pll_limits), clk);
1511 break;
1512 }
1513
1514 return config;
1515 }
1516
1517 /* Set VCLK*/
1518 void viafb_set_vclock(u32 clk, int set_iga)
1519 {
1520 struct via_pll_config config = get_best_pll_config(clk);
1521
1522 if (set_iga == IGA1)
1523 clock.set_primary_pll(config);
1524 if (set_iga == IGA2)
1525 clock.set_secondary_pll(config);
1526
1527 /* Fire! */
1528 via_write_misc_reg_mask(0x0C, 0x0C); /* select external clock */
1529 }
1530
1531 void viafb_load_crtc_timing(struct display_timing device_timing,
1532 int set_iga)
1533 {
1534 int i;
1535 int viafb_load_reg_num = 0;
1536 int reg_value = 0;
1537 struct io_register *reg = NULL;
1538
1539 viafb_unlock_crt();
1540
1541 for (i = 0; i < 12; i++) {
1542 if (set_iga == IGA1) {
1543 switch (i) {
1544 case H_TOTAL_INDEX:
1545 reg_value =
1546 IGA1_HOR_TOTAL_FORMULA(device_timing.
1547 hor_total);
1548 viafb_load_reg_num =
1549 iga1_crtc_reg.hor_total.reg_num;
1550 reg = iga1_crtc_reg.hor_total.reg;
1551 break;
1552 case H_ADDR_INDEX:
1553 reg_value =
1554 IGA1_HOR_ADDR_FORMULA(device_timing.
1555 hor_addr);
1556 viafb_load_reg_num =
1557 iga1_crtc_reg.hor_addr.reg_num;
1558 reg = iga1_crtc_reg.hor_addr.reg;
1559 break;
1560 case H_BLANK_START_INDEX:
1561 reg_value =
1562 IGA1_HOR_BLANK_START_FORMULA
1563 (device_timing.hor_blank_start);
1564 viafb_load_reg_num =
1565 iga1_crtc_reg.hor_blank_start.reg_num;
1566 reg = iga1_crtc_reg.hor_blank_start.reg;
1567 break;
1568 case H_BLANK_END_INDEX:
1569 reg_value =
1570 IGA1_HOR_BLANK_END_FORMULA
1571 (device_timing.hor_blank_start,
1572 device_timing.hor_blank_end);
1573 viafb_load_reg_num =
1574 iga1_crtc_reg.hor_blank_end.reg_num;
1575 reg = iga1_crtc_reg.hor_blank_end.reg;
1576 break;
1577 case H_SYNC_START_INDEX:
1578 reg_value =
1579 IGA1_HOR_SYNC_START_FORMULA
1580 (device_timing.hor_sync_start);
1581 viafb_load_reg_num =
1582 iga1_crtc_reg.hor_sync_start.reg_num;
1583 reg = iga1_crtc_reg.hor_sync_start.reg;
1584 break;
1585 case H_SYNC_END_INDEX:
1586 reg_value =
1587 IGA1_HOR_SYNC_END_FORMULA
1588 (device_timing.hor_sync_start,
1589 device_timing.hor_sync_end);
1590 viafb_load_reg_num =
1591 iga1_crtc_reg.hor_sync_end.reg_num;
1592 reg = iga1_crtc_reg.hor_sync_end.reg;
1593 break;
1594 case V_TOTAL_INDEX:
1595 reg_value =
1596 IGA1_VER_TOTAL_FORMULA(device_timing.
1597 ver_total);
1598 viafb_load_reg_num =
1599 iga1_crtc_reg.ver_total.reg_num;
1600 reg = iga1_crtc_reg.ver_total.reg;
1601 break;
1602 case V_ADDR_INDEX:
1603 reg_value =
1604 IGA1_VER_ADDR_FORMULA(device_timing.
1605 ver_addr);
1606 viafb_load_reg_num =
1607 iga1_crtc_reg.ver_addr.reg_num;
1608 reg = iga1_crtc_reg.ver_addr.reg;
1609 break;
1610 case V_BLANK_START_INDEX:
1611 reg_value =
1612 IGA1_VER_BLANK_START_FORMULA
1613 (device_timing.ver_blank_start);
1614 viafb_load_reg_num =
1615 iga1_crtc_reg.ver_blank_start.reg_num;
1616 reg = iga1_crtc_reg.ver_blank_start.reg;
1617 break;
1618 case V_BLANK_END_INDEX:
1619 reg_value =
1620 IGA1_VER_BLANK_END_FORMULA
1621 (device_timing.ver_blank_start,
1622 device_timing.ver_blank_end);
1623 viafb_load_reg_num =
1624 iga1_crtc_reg.ver_blank_end.reg_num;
1625 reg = iga1_crtc_reg.ver_blank_end.reg;
1626 break;
1627 case V_SYNC_START_INDEX:
1628 reg_value =
1629 IGA1_VER_SYNC_START_FORMULA
1630 (device_timing.ver_sync_start);
1631 viafb_load_reg_num =
1632 iga1_crtc_reg.ver_sync_start.reg_num;
1633 reg = iga1_crtc_reg.ver_sync_start.reg;
1634 break;
1635 case V_SYNC_END_INDEX:
1636 reg_value =
1637 IGA1_VER_SYNC_END_FORMULA
1638 (device_timing.ver_sync_start,
1639 device_timing.ver_sync_end);
1640 viafb_load_reg_num =
1641 iga1_crtc_reg.ver_sync_end.reg_num;
1642 reg = iga1_crtc_reg.ver_sync_end.reg;
1643 break;
1644
1645 }
1646 }
1647
1648 if (set_iga == IGA2) {
1649 switch (i) {
1650 case H_TOTAL_INDEX:
1651 reg_value =
1652 IGA2_HOR_TOTAL_FORMULA(device_timing.
1653 hor_total);
1654 viafb_load_reg_num =
1655 iga2_crtc_reg.hor_total.reg_num;
1656 reg = iga2_crtc_reg.hor_total.reg;
1657 break;
1658 case H_ADDR_INDEX:
1659 reg_value =
1660 IGA2_HOR_ADDR_FORMULA(device_timing.
1661 hor_addr);
1662 viafb_load_reg_num =
1663 iga2_crtc_reg.hor_addr.reg_num;
1664 reg = iga2_crtc_reg.hor_addr.reg;
1665 break;
1666 case H_BLANK_START_INDEX:
1667 reg_value =
1668 IGA2_HOR_BLANK_START_FORMULA
1669 (device_timing.hor_blank_start);
1670 viafb_load_reg_num =
1671 iga2_crtc_reg.hor_blank_start.reg_num;
1672 reg = iga2_crtc_reg.hor_blank_start.reg;
1673 break;
1674 case H_BLANK_END_INDEX:
1675 reg_value =
1676 IGA2_HOR_BLANK_END_FORMULA
1677 (device_timing.hor_blank_start,
1678 device_timing.hor_blank_end);
1679 viafb_load_reg_num =
1680 iga2_crtc_reg.hor_blank_end.reg_num;
1681 reg = iga2_crtc_reg.hor_blank_end.reg;
1682 break;
1683 case H_SYNC_START_INDEX:
1684 reg_value =
1685 IGA2_HOR_SYNC_START_FORMULA
1686 (device_timing.hor_sync_start);
1687 if (UNICHROME_CN700 <=
1688 viaparinfo->chip_info->gfx_chip_name)
1689 viafb_load_reg_num =
1690 iga2_crtc_reg.hor_sync_start.
1691 reg_num;
1692 else
1693 viafb_load_reg_num = 3;
1694 reg = iga2_crtc_reg.hor_sync_start.reg;
1695 break;
1696 case H_SYNC_END_INDEX:
1697 reg_value =
1698 IGA2_HOR_SYNC_END_FORMULA
1699 (device_timing.hor_sync_start,
1700 device_timing.hor_sync_end);
1701 viafb_load_reg_num =
1702 iga2_crtc_reg.hor_sync_end.reg_num;
1703 reg = iga2_crtc_reg.hor_sync_end.reg;
1704 break;
1705 case V_TOTAL_INDEX:
1706 reg_value =
1707 IGA2_VER_TOTAL_FORMULA(device_timing.
1708 ver_total);
1709 viafb_load_reg_num =
1710 iga2_crtc_reg.ver_total.reg_num;
1711 reg = iga2_crtc_reg.ver_total.reg;
1712 break;
1713 case V_ADDR_INDEX:
1714 reg_value =
1715 IGA2_VER_ADDR_FORMULA(device_timing.
1716 ver_addr);
1717 viafb_load_reg_num =
1718 iga2_crtc_reg.ver_addr.reg_num;
1719 reg = iga2_crtc_reg.ver_addr.reg;
1720 break;
1721 case V_BLANK_START_INDEX:
1722 reg_value =
1723 IGA2_VER_BLANK_START_FORMULA
1724 (device_timing.ver_blank_start);
1725 viafb_load_reg_num =
1726 iga2_crtc_reg.ver_blank_start.reg_num;
1727 reg = iga2_crtc_reg.ver_blank_start.reg;
1728 break;
1729 case V_BLANK_END_INDEX:
1730 reg_value =
1731 IGA2_VER_BLANK_END_FORMULA
1732 (device_timing.ver_blank_start,
1733 device_timing.ver_blank_end);
1734 viafb_load_reg_num =
1735 iga2_crtc_reg.ver_blank_end.reg_num;
1736 reg = iga2_crtc_reg.ver_blank_end.reg;
1737 break;
1738 case V_SYNC_START_INDEX:
1739 reg_value =
1740 IGA2_VER_SYNC_START_FORMULA
1741 (device_timing.ver_sync_start);
1742 viafb_load_reg_num =
1743 iga2_crtc_reg.ver_sync_start.reg_num;
1744 reg = iga2_crtc_reg.ver_sync_start.reg;
1745 break;
1746 case V_SYNC_END_INDEX:
1747 reg_value =
1748 IGA2_VER_SYNC_END_FORMULA
1749 (device_timing.ver_sync_start,
1750 device_timing.ver_sync_end);
1751 viafb_load_reg_num =
1752 iga2_crtc_reg.ver_sync_end.reg_num;
1753 reg = iga2_crtc_reg.ver_sync_end.reg;
1754 break;
1755
1756 }
1757 }
1758 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1759 }
1760
1761 viafb_lock_crt();
1762 }
1763
1764 void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
1765 struct VideoModeTable *video_mode, int bpp_byte, int set_iga)
1766 {
1767 struct display_timing crt_reg;
1768 int i;
1769 int index = 0;
1770 int h_addr, v_addr;
1771 u32 clock, refresh = viafb_refresh;
1772
1773 if (viafb_SAMM_ON && set_iga == IGA2)
1774 refresh = viafb_refresh1;
1775
1776 for (i = 0; i < video_mode->mode_array; i++) {
1777 index = i;
1778
1779 if (crt_table[i].refresh_rate == refresh)
1780 break;
1781 }
1782
1783 crt_reg = crt_table[index].crtc;
1784
1785 /* Mode 640x480 has border, but LCD/DFP didn't have border. */
1786 /* So we would delete border. */
1787 if ((viafb_LCD_ON | viafb_DVI_ON)
1788 && video_mode->crtc[0].crtc.hor_addr == 640
1789 && video_mode->crtc[0].crtc.ver_addr == 480
1790 && refresh == 60) {
1791 /* The border is 8 pixels. */
1792 crt_reg.hor_blank_start = crt_reg.hor_blank_start - 8;
1793
1794 /* Blanking time should add left and right borders. */
1795 crt_reg.hor_blank_end = crt_reg.hor_blank_end + 16;
1796 }
1797
1798 h_addr = crt_reg.hor_addr;
1799 v_addr = crt_reg.ver_addr;
1800 if (set_iga == IGA1) {
1801 viafb_unlock_crt();
1802 viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
1803 }
1804
1805 switch (set_iga) {
1806 case IGA1:
1807 viafb_load_crtc_timing(crt_reg, IGA1);
1808 break;
1809 case IGA2:
1810 viafb_load_crtc_timing(crt_reg, IGA2);
1811 break;
1812 }
1813
1814 viafb_lock_crt();
1815 viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
1816 viafb_load_fetch_count_reg(h_addr, bpp_byte, set_iga);
1817
1818 /* load FIFO */
1819 if ((viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266)
1820 && (viaparinfo->chip_info->gfx_chip_name != UNICHROME_K400))
1821 viafb_load_FIFO_reg(set_iga, h_addr, v_addr);
1822
1823 clock = crt_reg.hor_total * crt_reg.ver_total
1824 * crt_table[index].refresh_rate;
1825 viafb_set_vclock(clock, set_iga);
1826
1827 }
1828
1829 void __devinit viafb_init_chip_info(int chip_type)
1830 {
1831 via_clock_init(&clock, chip_type);
1832 init_gfx_chip_info(chip_type);
1833 init_tmds_chip_info();
1834 init_lvds_chip_info();
1835
1836 /*Set IGA path for each device */
1837 viafb_set_iga_path();
1838
1839 viaparinfo->lvds_setting_info->display_method = viafb_lcd_dsp_method;
1840 viaparinfo->lvds_setting_info->lcd_mode = viafb_lcd_mode;
1841 viaparinfo->lvds_setting_info2->display_method =
1842 viaparinfo->lvds_setting_info->display_method;
1843 viaparinfo->lvds_setting_info2->lcd_mode =
1844 viaparinfo->lvds_setting_info->lcd_mode;
1845 }
1846
1847 void viafb_update_device_setting(int hres, int vres, int bpp, int flag)
1848 {
1849 if (flag == 0) {
1850 viaparinfo->tmds_setting_info->h_active = hres;
1851 viaparinfo->tmds_setting_info->v_active = vres;
1852
1853 viaparinfo->lvds_setting_info->h_active = hres;
1854 viaparinfo->lvds_setting_info->v_active = vres;
1855 viaparinfo->lvds_setting_info->bpp = bpp;
1856 viaparinfo->lvds_setting_info2->h_active = hres;
1857 viaparinfo->lvds_setting_info2->v_active = vres;
1858 viaparinfo->lvds_setting_info2->bpp = bpp;
1859 } else {
1860
1861 if (viaparinfo->tmds_setting_info->iga_path == IGA2) {
1862 viaparinfo->tmds_setting_info->h_active = hres;
1863 viaparinfo->tmds_setting_info->v_active = vres;
1864 }
1865
1866 if (viaparinfo->lvds_setting_info->iga_path == IGA2) {
1867 viaparinfo->lvds_setting_info->h_active = hres;
1868 viaparinfo->lvds_setting_info->v_active = vres;
1869 viaparinfo->lvds_setting_info->bpp = bpp;
1870 }
1871 if (IGA2 == viaparinfo->lvds_setting_info2->iga_path) {
1872 viaparinfo->lvds_setting_info2->h_active = hres;
1873 viaparinfo->lvds_setting_info2->v_active = vres;
1874 viaparinfo->lvds_setting_info2->bpp = bpp;
1875 }
1876 }
1877 }
1878
1879 static void __devinit init_gfx_chip_info(int chip_type)
1880 {
1881 u8 tmp;
1882
1883 viaparinfo->chip_info->gfx_chip_name = chip_type;
1884
1885 /* Check revision of CLE266 Chip */
1886 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
1887 /* CR4F only define in CLE266.CX chip */
1888 tmp = viafb_read_reg(VIACR, CR4F);
1889 viafb_write_reg(CR4F, VIACR, 0x55);
1890 if (viafb_read_reg(VIACR, CR4F) != 0x55)
1891 viaparinfo->chip_info->gfx_chip_revision =
1892 CLE266_REVISION_AX;
1893 else
1894 viaparinfo->chip_info->gfx_chip_revision =
1895 CLE266_REVISION_CX;
1896 /* restore orignal CR4F value */
1897 viafb_write_reg(CR4F, VIACR, tmp);
1898 }
1899
1900 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1901 tmp = viafb_read_reg(VIASR, SR43);
1902 DEBUG_MSG(KERN_INFO "SR43:%X\n", tmp);
1903 if (tmp & 0x02) {
1904 viaparinfo->chip_info->gfx_chip_revision =
1905 CX700_REVISION_700M2;
1906 } else if (tmp & 0x40) {
1907 viaparinfo->chip_info->gfx_chip_revision =
1908 CX700_REVISION_700M;
1909 } else {
1910 viaparinfo->chip_info->gfx_chip_revision =
1911 CX700_REVISION_700;
1912 }
1913 }
1914
1915 /* Determine which 2D engine we have */
1916 switch (viaparinfo->chip_info->gfx_chip_name) {
1917 case UNICHROME_VX800:
1918 case UNICHROME_VX855:
1919 case UNICHROME_VX900:
1920 viaparinfo->chip_info->twod_engine = VIA_2D_ENG_M1;
1921 break;
1922 case UNICHROME_K8M890:
1923 case UNICHROME_P4M900:
1924 viaparinfo->chip_info->twod_engine = VIA_2D_ENG_H5;
1925 break;
1926 default:
1927 viaparinfo->chip_info->twod_engine = VIA_2D_ENG_H2;
1928 break;
1929 }
1930 }
1931
1932 static void __devinit init_tmds_chip_info(void)
1933 {
1934 viafb_tmds_trasmitter_identify();
1935
1936 if (INTERFACE_NONE == viaparinfo->chip_info->tmds_chip_info.
1937 output_interface) {
1938 switch (viaparinfo->chip_info->gfx_chip_name) {
1939 case UNICHROME_CX700:
1940 {
1941 /* we should check support by hardware layout.*/
1942 if ((viafb_display_hardware_layout ==
1943 HW_LAYOUT_DVI_ONLY)
1944 || (viafb_display_hardware_layout ==
1945 HW_LAYOUT_LCD_DVI)) {
1946 viaparinfo->chip_info->tmds_chip_info.
1947 output_interface = INTERFACE_TMDS;
1948 } else {
1949 viaparinfo->chip_info->tmds_chip_info.
1950 output_interface =
1951 INTERFACE_NONE;
1952 }
1953 break;
1954 }
1955 case UNICHROME_K8M890:
1956 case UNICHROME_P4M900:
1957 case UNICHROME_P4M890:
1958 /* TMDS on PCIE, we set DFPLOW as default. */
1959 viaparinfo->chip_info->tmds_chip_info.output_interface =
1960 INTERFACE_DFP_LOW;
1961 break;
1962 default:
1963 {
1964 /* set DVP1 default for DVI */
1965 viaparinfo->chip_info->tmds_chip_info
1966 .output_interface = INTERFACE_DVP1;
1967 }
1968 }
1969 }
1970
1971 DEBUG_MSG(KERN_INFO "TMDS Chip = %d\n",
1972 viaparinfo->chip_info->tmds_chip_info.tmds_chip_name);
1973 viafb_init_dvi_size(&viaparinfo->shared->chip_info.tmds_chip_info,
1974 &viaparinfo->shared->tmds_setting_info);
1975 }
1976
1977 static void __devinit init_lvds_chip_info(void)
1978 {
1979 viafb_lvds_trasmitter_identify();
1980 viafb_init_lcd_size();
1981 viafb_init_lvds_output_interface(&viaparinfo->chip_info->lvds_chip_info,
1982 viaparinfo->lvds_setting_info);
1983 if (viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name) {
1984 viafb_init_lvds_output_interface(&viaparinfo->chip_info->
1985 lvds_chip_info2, viaparinfo->lvds_setting_info2);
1986 }
1987 /*If CX700,two singel LCD, we need to reassign
1988 LCD interface to different LVDS port */
1989 if ((UNICHROME_CX700 == viaparinfo->chip_info->gfx_chip_name)
1990 && (HW_LAYOUT_LCD1_LCD2 == viafb_display_hardware_layout)) {
1991 if ((INTEGRATED_LVDS == viaparinfo->chip_info->lvds_chip_info.
1992 lvds_chip_name) && (INTEGRATED_LVDS ==
1993 viaparinfo->chip_info->
1994 lvds_chip_info2.lvds_chip_name)) {
1995 viaparinfo->chip_info->lvds_chip_info.output_interface =
1996 INTERFACE_LVDS0;
1997 viaparinfo->chip_info->lvds_chip_info2.
1998 output_interface =
1999 INTERFACE_LVDS1;
2000 }
2001 }
2002
2003 DEBUG_MSG(KERN_INFO "LVDS Chip = %d\n",
2004 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name);
2005 DEBUG_MSG(KERN_INFO "LVDS1 output_interface = %d\n",
2006 viaparinfo->chip_info->lvds_chip_info.output_interface);
2007 DEBUG_MSG(KERN_INFO "LVDS2 output_interface = %d\n",
2008 viaparinfo->chip_info->lvds_chip_info.output_interface);
2009 }
2010
2011 void __devinit viafb_init_dac(int set_iga)
2012 {
2013 int i;
2014 u8 tmp;
2015
2016 if (set_iga == IGA1) {
2017 /* access Primary Display's LUT */
2018 viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0);
2019 /* turn off LCK */
2020 viafb_write_reg_mask(SR1B, VIASR, 0x00, BIT7 + BIT6);
2021 for (i = 0; i < 256; i++) {
2022 write_dac_reg(i, palLUT_table[i].red,
2023 palLUT_table[i].green,
2024 palLUT_table[i].blue);
2025 }
2026 /* turn on LCK */
2027 viafb_write_reg_mask(SR1B, VIASR, 0xC0, BIT7 + BIT6);
2028 } else {
2029 tmp = viafb_read_reg(VIACR, CR6A);
2030 /* access Secondary Display's LUT */
2031 viafb_write_reg_mask(CR6A, VIACR, 0x40, BIT6);
2032 viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0);
2033 for (i = 0; i < 256; i++) {
2034 write_dac_reg(i, palLUT_table[i].red,
2035 palLUT_table[i].green,
2036 palLUT_table[i].blue);
2037 }
2038 /* set IGA1 DAC for default */
2039 viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0);
2040 viafb_write_reg(CR6A, VIACR, tmp);
2041 }
2042 }
2043
2044 static void device_screen_off(void)
2045 {
2046 /* turn off CRT screen (IGA1) */
2047 viafb_write_reg_mask(SR01, VIASR, 0x20, BIT5);
2048 }
2049
2050 static void device_screen_on(void)
2051 {
2052 /* turn on CRT screen (IGA1) */
2053 viafb_write_reg_mask(SR01, VIASR, 0x00, BIT5);
2054 }
2055
2056 static void set_display_channel(void)
2057 {
2058 /*If viafb_LCD2_ON, on cx700, internal lvds's information
2059 is keeped on lvds_setting_info2 */
2060 if (viafb_LCD2_ON &&
2061 viaparinfo->lvds_setting_info2->device_lcd_dualedge) {
2062 /* For dual channel LCD: */
2063 /* Set to Dual LVDS channel. */
2064 viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);
2065 } else if (viafb_LCD_ON && viafb_DVI_ON) {
2066 /* For LCD+DFP: */
2067 /* Set to LVDS1 + TMDS channel. */
2068 viafb_write_reg_mask(CRD2, VIACR, 0x10, BIT4 + BIT5);
2069 } else if (viafb_DVI_ON) {
2070 /* Set to single TMDS channel. */
2071 viafb_write_reg_mask(CRD2, VIACR, 0x30, BIT4 + BIT5);
2072 } else if (viafb_LCD_ON) {
2073 if (viaparinfo->lvds_setting_info->device_lcd_dualedge) {
2074 /* For dual channel LCD: */
2075 /* Set to Dual LVDS channel. */
2076 viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);
2077 } else {
2078 /* Set to LVDS0 + LVDS1 channel. */
2079 viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT4 + BIT5);
2080 }
2081 }
2082 }
2083
2084 static u8 get_sync(struct fb_info *info)
2085 {
2086 u8 polarity = 0;
2087
2088 if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT))
2089 polarity |= VIA_HSYNC_NEGATIVE;
2090 if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT))
2091 polarity |= VIA_VSYNC_NEGATIVE;
2092 return polarity;
2093 }
2094
2095 int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp,
2096 struct VideoModeTable *vmode_tbl1, int video_bpp1)
2097 {
2098 int i, j;
2099 int port;
2100 u32 devices = viaparinfo->shared->iga1_devices
2101 | viaparinfo->shared->iga2_devices;
2102 u8 value, index, mask;
2103 struct crt_mode_table *crt_timing;
2104 struct crt_mode_table *crt_timing1 = NULL;
2105
2106 device_screen_off();
2107 crt_timing = vmode_tbl->crtc;
2108
2109 if (viafb_SAMM_ON == 1) {
2110 crt_timing1 = vmode_tbl1->crtc;
2111 }
2112
2113 inb(VIAStatus);
2114 outb(0x00, VIAAR);
2115
2116 /* Write Common Setting for Video Mode */
2117 viafb_write_regx(common_vga, ARRAY_SIZE(common_vga));
2118 switch (viaparinfo->chip_info->gfx_chip_name) {
2119 case UNICHROME_CLE266:
2120 viafb_write_regx(CLE266_ModeXregs, NUM_TOTAL_CLE266_ModeXregs);
2121 break;
2122
2123 case UNICHROME_K400:
2124 viafb_write_regx(KM400_ModeXregs, NUM_TOTAL_KM400_ModeXregs);
2125 break;
2126
2127 case UNICHROME_K800:
2128 case UNICHROME_PM800:
2129 viafb_write_regx(CN400_ModeXregs, NUM_TOTAL_CN400_ModeXregs);
2130 break;
2131
2132 case UNICHROME_CN700:
2133 case UNICHROME_K8M890:
2134 case UNICHROME_P4M890:
2135 case UNICHROME_P4M900:
2136 viafb_write_regx(CN700_ModeXregs, NUM_TOTAL_CN700_ModeXregs);
2137 break;
2138
2139 case UNICHROME_CX700:
2140 case UNICHROME_VX800:
2141 viafb_write_regx(CX700_ModeXregs, NUM_TOTAL_CX700_ModeXregs);
2142 break;
2143
2144 case UNICHROME_VX855:
2145 case UNICHROME_VX900:
2146 viafb_write_regx(VX855_ModeXregs, NUM_TOTAL_VX855_ModeXregs);
2147 break;
2148 }
2149
2150 viafb_write_regx(scaling_parameters, ARRAY_SIZE(scaling_parameters));
2151 device_off();
2152 via_set_state(devices, VIA_STATE_OFF);
2153
2154 /* Fill VPIT Parameters */
2155 /* Write Misc Register */
2156 outb(VPIT.Misc, VIA_MISC_REG_WRITE);
2157
2158 /* Write Sequencer */
2159 for (i = 1; i <= StdSR; i++)
2160 via_write_reg(VIASR, i, VPIT.SR[i - 1]);
2161
2162 viafb_write_reg_mask(0x15, VIASR, 0xA2, 0xA2);
2163
2164 /* Write Graphic Controller */
2165 for (i = 0; i < StdGR; i++)
2166 via_write_reg(VIAGR, i, VPIT.GR[i]);
2167
2168 /* Write Attribute Controller */
2169 for (i = 0; i < StdAR; i++) {
2170 inb(VIAStatus);
2171 outb(i, VIAAR);
2172 outb(VPIT.AR[i], VIAAR);
2173 }
2174
2175 inb(VIAStatus);
2176 outb(0x20, VIAAR);
2177
2178 /* Update Patch Register */
2179
2180 if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266
2181 || viaparinfo->chip_info->gfx_chip_name == UNICHROME_K400)
2182 && vmode_tbl->crtc[0].crtc.hor_addr == 1024
2183 && vmode_tbl->crtc[0].crtc.ver_addr == 768) {
2184 for (j = 0; j < res_patch_table[0].table_length; j++) {
2185 index = res_patch_table[0].io_reg_table[j].index;
2186 port = res_patch_table[0].io_reg_table[j].port;
2187 value = res_patch_table[0].io_reg_table[j].value;
2188 mask = res_patch_table[0].io_reg_table[j].mask;
2189 viafb_write_reg_mask(index, port, value, mask);
2190 }
2191 }
2192
2193 load_fix_bit_crtc_reg();
2194 via_set_primary_pitch(viafbinfo->fix.line_length);
2195 via_set_secondary_pitch(viafb_dual_fb ? viafbinfo1->fix.line_length
2196 : viafbinfo->fix.line_length);
2197 via_set_primary_color_depth(viaparinfo->depth);
2198 via_set_secondary_color_depth(viafb_dual_fb ? viaparinfo1->depth
2199 : viaparinfo->depth);
2200 via_set_source(viaparinfo->shared->iga1_devices, IGA1);
2201 via_set_source(viaparinfo->shared->iga2_devices, IGA2);
2202 if (viaparinfo->shared->iga2_devices)
2203 enable_second_display_channel();
2204 else
2205 disable_second_display_channel();
2206
2207 /* Update Refresh Rate Setting */
2208
2209 /* Clear On Screen */
2210
2211 /* CRT set mode */
2212 if (viafb_CRT_ON) {
2213 if (viafb_SAMM_ON &&
2214 viaparinfo->shared->iga2_devices & VIA_CRT) {
2215 viafb_fill_crtc_timing(crt_timing1, vmode_tbl1,
2216 video_bpp1 / 8, IGA2);
2217 } else {
2218 viafb_fill_crtc_timing(crt_timing, vmode_tbl,
2219 video_bpp / 8,
2220 (viaparinfo->shared->iga1_devices & VIA_CRT)
2221 ? IGA1 : IGA2);
2222 }
2223
2224 /* Patch if set_hres is not 8 alignment (1366) to viafb_setmode
2225 to 8 alignment (1368),there is several pixels (2 pixels)
2226 on right side of screen. */
2227 if (vmode_tbl->crtc[0].crtc.hor_addr % 8) {
2228 viafb_unlock_crt();
2229 viafb_write_reg(CR02, VIACR,
2230 viafb_read_reg(VIACR, CR02) - 1);
2231 viafb_lock_crt();
2232 }
2233 }
2234
2235 if (viafb_DVI_ON) {
2236 if (viafb_SAMM_ON &&
2237 (viaparinfo->tmds_setting_info->iga_path == IGA2)) {
2238 viafb_dvi_set_mode(viafb_get_mode
2239 (viaparinfo->tmds_setting_info->h_active,
2240 viaparinfo->tmds_setting_info->
2241 v_active),
2242 video_bpp1, viaparinfo->
2243 tmds_setting_info->iga_path);
2244 } else {
2245 viafb_dvi_set_mode(viafb_get_mode
2246 (viaparinfo->tmds_setting_info->h_active,
2247 viaparinfo->
2248 tmds_setting_info->v_active),
2249 video_bpp, viaparinfo->
2250 tmds_setting_info->iga_path);
2251 }
2252 }
2253
2254 if (viafb_LCD_ON) {
2255 if (viafb_SAMM_ON &&
2256 (viaparinfo->lvds_setting_info->iga_path == IGA2)) {
2257 viaparinfo->lvds_setting_info->bpp = video_bpp1;
2258 viafb_lcd_set_mode(crt_timing1, viaparinfo->
2259 lvds_setting_info,
2260 &viaparinfo->chip_info->lvds_chip_info);
2261 } else {
2262 /* IGA1 doesn't have LCD scaling, so set it center. */
2263 if (viaparinfo->lvds_setting_info->iga_path == IGA1) {
2264 viaparinfo->lvds_setting_info->display_method =
2265 LCD_CENTERING;
2266 }
2267 viaparinfo->lvds_setting_info->bpp = video_bpp;
2268 viafb_lcd_set_mode(crt_timing, viaparinfo->
2269 lvds_setting_info,
2270 &viaparinfo->chip_info->lvds_chip_info);
2271 }
2272 }
2273 if (viafb_LCD2_ON) {
2274 if (viafb_SAMM_ON &&
2275 (viaparinfo->lvds_setting_info2->iga_path == IGA2)) {
2276 viaparinfo->lvds_setting_info2->bpp = video_bpp1;
2277 viafb_lcd_set_mode(crt_timing1, viaparinfo->
2278 lvds_setting_info2,
2279 &viaparinfo->chip_info->lvds_chip_info2);
2280 } else {
2281 /* IGA1 doesn't have LCD scaling, so set it center. */
2282 if (viaparinfo->lvds_setting_info2->iga_path == IGA1) {
2283 viaparinfo->lvds_setting_info2->display_method =
2284 LCD_CENTERING;
2285 }
2286 viaparinfo->lvds_setting_info2->bpp = video_bpp;
2287 viafb_lcd_set_mode(crt_timing, viaparinfo->
2288 lvds_setting_info2,
2289 &viaparinfo->chip_info->lvds_chip_info2);
2290 }
2291 }
2292
2293 if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700)
2294 && (viafb_LCD_ON || viafb_DVI_ON))
2295 set_display_channel();
2296
2297 /* If set mode normally, save resolution information for hot-plug . */
2298 if (!viafb_hotplug) {
2299 viafb_hotplug_Xres = vmode_tbl->crtc[0].crtc.hor_addr;
2300 viafb_hotplug_Yres = vmode_tbl->crtc[0].crtc.ver_addr;
2301 viafb_hotplug_bpp = video_bpp;
2302 viafb_hotplug_refresh = viafb_refresh;
2303
2304 if (viafb_DVI_ON)
2305 viafb_DeviceStatus = DVI_Device;
2306 else
2307 viafb_DeviceStatus = CRT_Device;
2308 }
2309 device_on();
2310 if (!viafb_dual_fb)
2311 via_set_sync_polarity(devices, get_sync(viafbinfo));
2312 else {
2313 via_set_sync_polarity(viaparinfo->shared->iga1_devices,
2314 get_sync(viafbinfo));
2315 via_set_sync_polarity(viaparinfo->shared->iga2_devices,
2316 get_sync(viafbinfo1));
2317 }
2318
2319 clock.set_engine_pll_state(VIA_STATE_ON);
2320 clock.set_primary_clock_source(VIA_CLKSRC_X1, true);
2321 clock.set_secondary_clock_source(VIA_CLKSRC_X1, true);
2322
2323 #ifdef CONFIG_FB_VIA_X_COMPATIBILITY
2324 clock.set_primary_pll_state(VIA_STATE_ON);
2325 clock.set_primary_clock_state(VIA_STATE_ON);
2326 clock.set_secondary_pll_state(VIA_STATE_ON);
2327 clock.set_secondary_clock_state(VIA_STATE_ON);
2328 #else
2329 if (viaparinfo->shared->iga1_devices) {
2330 clock.set_primary_pll_state(VIA_STATE_ON);
2331 clock.set_primary_clock_state(VIA_STATE_ON);
2332 } else {
2333 clock.set_primary_pll_state(VIA_STATE_OFF);
2334 clock.set_primary_clock_state(VIA_STATE_OFF);
2335 }
2336
2337 if (viaparinfo->shared->iga2_devices) {
2338 clock.set_secondary_pll_state(VIA_STATE_ON);
2339 clock.set_secondary_clock_state(VIA_STATE_ON);
2340 } else {
2341 clock.set_secondary_pll_state(VIA_STATE_OFF);
2342 clock.set_secondary_clock_state(VIA_STATE_OFF);
2343 }
2344 #endif /*CONFIG_FB_VIA_X_COMPATIBILITY*/
2345
2346 via_set_state(devices, VIA_STATE_ON);
2347 device_screen_on();
2348 return 1;
2349 }
2350
2351 int viafb_get_pixclock(int hres, int vres, int vmode_refresh)
2352 {
2353 int i;
2354 struct crt_mode_table *best;
2355 struct VideoModeTable *vmode = viafb_get_mode(hres, vres);
2356
2357 if (!vmode)
2358 return RES_640X480_60HZ_PIXCLOCK;
2359
2360 best = &vmode->crtc[0];
2361 for (i = 1; i < vmode->mode_array; i++) {
2362 if (abs(vmode->crtc[i].refresh_rate - vmode_refresh)
2363 < abs(best->refresh_rate - vmode_refresh))
2364 best = &vmode->crtc[i];
2365 }
2366
2367 return 1000000000 / (best->crtc.hor_total * best->crtc.ver_total)
2368 * 1000 / best->refresh_rate;
2369 }
2370
2371 int viafb_get_refresh(int hres, int vres, u32 long_refresh)
2372 {
2373 int i;
2374 struct crt_mode_table *best;
2375 struct VideoModeTable *vmode = viafb_get_mode(hres, vres);
2376
2377 if (!vmode)
2378 return 60;
2379
2380 best = &vmode->crtc[0];
2381 for (i = 1; i < vmode->mode_array; i++) {
2382 if (abs(vmode->crtc[i].refresh_rate - long_refresh)
2383 < abs(best->refresh_rate - long_refresh))
2384 best = &vmode->crtc[i];
2385 }
2386
2387 if (abs(best->refresh_rate - long_refresh) > 3) {
2388 if (hres == 1200 && vres == 900)
2389 return 49; /* OLPC DCON only supports 50 Hz */
2390 else
2391 return 60;
2392 }
2393
2394 return best->refresh_rate;
2395 }
2396
2397 static void device_off(void)
2398 {
2399 viafb_dvi_disable();
2400 viafb_lcd_disable();
2401 }
2402
2403 static void device_on(void)
2404 {
2405 if (viafb_DVI_ON == 1)
2406 viafb_dvi_enable();
2407 if (viafb_LCD_ON == 1)
2408 viafb_lcd_enable();
2409 }
2410
2411 static void enable_second_display_channel(void)
2412 {
2413 /* to enable second display channel. */
2414 viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6);
2415 viafb_write_reg_mask(CR6A, VIACR, BIT7, BIT7);
2416 viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);
2417 }
2418
2419 static void disable_second_display_channel(void)
2420 {
2421 /* to disable second display channel. */
2422 viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6);
2423 viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT7);
2424 viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);
2425 }
2426
2427 void viafb_set_dpa_gfx(int output_interface, struct GFX_DPA_SETTING\
2428 *p_gfx_dpa_setting)
2429 {
2430 switch (output_interface) {
2431 case INTERFACE_DVP0:
2432 {
2433 /* DVP0 Clock Polarity and Adjust: */
2434 viafb_write_reg_mask(CR96, VIACR,
2435 p_gfx_dpa_setting->DVP0, 0x0F);
2436
2437 /* DVP0 Clock and Data Pads Driving: */
2438 viafb_write_reg_mask(SR1E, VIASR,
2439 p_gfx_dpa_setting->DVP0ClockDri_S, BIT2);
2440 viafb_write_reg_mask(SR2A, VIASR,
2441 p_gfx_dpa_setting->DVP0ClockDri_S1,
2442 BIT4);
2443 viafb_write_reg_mask(SR1B, VIASR,
2444 p_gfx_dpa_setting->DVP0DataDri_S, BIT1);
2445 viafb_write_reg_mask(SR2A, VIASR,
2446 p_gfx_dpa_setting->DVP0DataDri_S1, BIT5);
2447 break;
2448 }
2449
2450 case INTERFACE_DVP1:
2451 {
2452 /* DVP1 Clock Polarity and Adjust: */
2453 viafb_write_reg_mask(CR9B, VIACR,
2454 p_gfx_dpa_setting->DVP1, 0x0F);
2455
2456 /* DVP1 Clock and Data Pads Driving: */
2457 viafb_write_reg_mask(SR65, VIASR,
2458 p_gfx_dpa_setting->DVP1Driving, 0x0F);
2459 break;
2460 }
2461
2462 case INTERFACE_DFP_HIGH:
2463 {
2464 viafb_write_reg_mask(CR97, VIACR,
2465 p_gfx_dpa_setting->DFPHigh, 0x0F);
2466 break;
2467 }
2468
2469 case INTERFACE_DFP_LOW:
2470 {
2471 viafb_write_reg_mask(CR99, VIACR,
2472 p_gfx_dpa_setting->DFPLow, 0x0F);
2473 break;
2474 }
2475
2476 case INTERFACE_DFP:
2477 {
2478 viafb_write_reg_mask(CR97, VIACR,
2479 p_gfx_dpa_setting->DFPHigh, 0x0F);
2480 viafb_write_reg_mask(CR99, VIACR,
2481 p_gfx_dpa_setting->DFPLow, 0x0F);
2482 break;
2483 }
2484 }
2485 }
2486
2487 /*According var's xres, yres fill var's other timing information*/
2488 void viafb_fill_var_timing_info(struct fb_var_screeninfo *var, int refresh,
2489 struct VideoModeTable *vmode_tbl)
2490 {
2491 struct crt_mode_table *crt_timing = NULL;
2492 struct display_timing crt_reg;
2493 int i = 0, index = 0;
2494 crt_timing = vmode_tbl->crtc;
2495 for (i = 0; i < vmode_tbl->mode_array; i++) {
2496 index = i;
2497 if (crt_timing[i].refresh_rate == refresh)
2498 break;
2499 }
2500
2501 crt_reg = crt_timing[index].crtc;
2502 var->pixclock = viafb_get_pixclock(var->xres, var->yres, refresh);
2503 var->left_margin =
2504 crt_reg.hor_total - (crt_reg.hor_sync_start + crt_reg.hor_sync_end);
2505 var->right_margin = crt_reg.hor_sync_start - crt_reg.hor_addr;
2506 var->hsync_len = crt_reg.hor_sync_end;
2507 var->upper_margin =
2508 crt_reg.ver_total - (crt_reg.ver_sync_start + crt_reg.ver_sync_end);
2509 var->lower_margin = crt_reg.ver_sync_start - crt_reg.ver_addr;
2510 var->vsync_len = crt_reg.ver_sync_end;
2511 var->sync = 0;
2512 if (crt_timing[index].h_sync_polarity == POSITIVE)
2513 var->sync |= FB_SYNC_HOR_HIGH_ACT;
2514 if (crt_timing[index].v_sync_polarity == POSITIVE)
2515 var->sync |= FB_SYNC_VERT_HIGH_ACT;
2516 }
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