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bnx2x: update driver version to 1.70.30-0
[linux-2.6.git] / drivers / staging / gma500 / psb_drv.c
blobdc676c2ce810c1d5303a36f6b034424afe8ad652
1 /**************************************************************************
2 * Copyright (c) 2007-2011, Intel Corporation.
3 * All Rights Reserved.
4 * Copyright (c) 2008, Tungsten Graphics, Inc. Cedar Park, TX., USA.
5 * All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 **************************************************************************/
21
22 #include <drm/drmP.h>
23 #include <drm/drm.h>
24 #include "psb_drm.h"
25 #include "psb_drv.h"
26 #include "framebuffer.h"
27 #include "psb_reg.h"
28 #include "psb_intel_reg.h"
29 #include "intel_bios.h"
30 #include "mid_bios.h"
31 #include "mdfld_dsi_dbi.h"
32 #include <drm/drm_pciids.h>
33 #include "power.h"
34 #include <linux/cpu.h>
35 #include <linux/notifier.h>
36 #include <linux/spinlock.h>
37 #include <linux/pm_runtime.h>
38 #include <acpi/video.h>
39
40 static int drm_psb_trap_pagefaults;
41
42 int drm_psb_no_fb;
43
44 static int psb_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
45
46 MODULE_PARM_DESC(no_fb, "Disable FBdev");
47 MODULE_PARM_DESC(trap_pagefaults, "Error and reset on MMU pagefaults");
48 module_param_named(no_fb, drm_psb_no_fb, int, 0600);
49 module_param_named(trap_pagefaults, drm_psb_trap_pagefaults, int, 0600);
50
51
52 static DEFINE_PCI_DEVICE_TABLE(pciidlist) = {
53 { 0x8086, 0x8108, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &psb_chip_ops },
54 { 0x8086, 0x8109, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &psb_chip_ops },
55 #if defined(CONFIG_DRM_PSB_MRST)
56 { 0x8086, 0x4100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mrst_chip_ops},
57 { 0x8086, 0x4101, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mrst_chip_ops},
58 { 0x8086, 0x4102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mrst_chip_ops},
59 { 0x8086, 0x4103, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mrst_chip_ops},
60 { 0x8086, 0x4104, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mrst_chip_ops},
61 { 0x8086, 0x4105, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mrst_chip_ops},
62 { 0x8086, 0x4106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mrst_chip_ops},
63 { 0x8086, 0x4107, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mrst_chip_ops},
64 #endif
65 #if defined(CONFIG_DRM_PSB_MFLD)
66 { 0x8086, 0x0130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mdfld_chip_ops},
67 { 0x8086, 0x0131, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mdfld_chip_ops},
68 { 0x8086, 0x0132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mdfld_chip_ops},
69 { 0x8086, 0x0133, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mdfld_chip_ops},
70 { 0x8086, 0x0134, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mdfld_chip_ops},
71 { 0x8086, 0x0135, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mdfld_chip_ops},
72 { 0x8086, 0x0136, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mdfld_chip_ops},
73 { 0x8086, 0x0137, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mdfld_chip_ops},
74 #endif
75 #if defined(CONFIG_DRM_PSB_CDV)
76 { 0x8086, 0x0be0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops},
77 { 0x8086, 0x0be1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops},
78 { 0x8086, 0x0be2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops},
79 { 0x8086, 0x0be3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops},
80 { 0x8086, 0x0be4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops},
81 { 0x8086, 0x0be5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops},
82 { 0x8086, 0x0be6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops},
83 { 0x8086, 0x0be7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops},
84 #endif
85 { 0, 0, 0}
86 };
87 MODULE_DEVICE_TABLE(pci, pciidlist);
88
89 /*
90 * Standard IOCTLs.
91 */
92
93 #define DRM_IOCTL_PSB_SIZES \
94 DRM_IOR(DRM_PSB_SIZES + DRM_COMMAND_BASE, \
95 struct drm_psb_sizes_arg)
96 #define DRM_IOCTL_PSB_FUSE_REG \
97 DRM_IOWR(DRM_PSB_FUSE_REG + DRM_COMMAND_BASE, uint32_t)
98 #define DRM_IOCTL_PSB_DC_STATE \
99 DRM_IOW(DRM_PSB_DC_STATE + DRM_COMMAND_BASE, \
100 struct drm_psb_dc_state_arg)
101 #define DRM_IOCTL_PSB_ADB \
102 DRM_IOWR(DRM_PSB_ADB + DRM_COMMAND_BASE, uint32_t)
103 #define DRM_IOCTL_PSB_MODE_OPERATION \
104 DRM_IOWR(DRM_PSB_MODE_OPERATION + DRM_COMMAND_BASE, \
105 struct drm_psb_mode_operation_arg)
106 #define DRM_IOCTL_PSB_STOLEN_MEMORY \
107 DRM_IOWR(DRM_PSB_STOLEN_MEMORY + DRM_COMMAND_BASE, \
108 struct drm_psb_stolen_memory_arg)
109 #define DRM_IOCTL_PSB_REGISTER_RW \
110 DRM_IOWR(DRM_PSB_REGISTER_RW + DRM_COMMAND_BASE, \
111 struct drm_psb_register_rw_arg)
112 #define DRM_IOCTL_PSB_DPST \
113 DRM_IOWR(DRM_PSB_DPST + DRM_COMMAND_BASE, \
114 uint32_t)
115 #define DRM_IOCTL_PSB_GAMMA \
116 DRM_IOWR(DRM_PSB_GAMMA + DRM_COMMAND_BASE, \
117 struct drm_psb_dpst_lut_arg)
118 #define DRM_IOCTL_PSB_DPST_BL \
119 DRM_IOWR(DRM_PSB_DPST_BL + DRM_COMMAND_BASE, \
120 uint32_t)
121 #define DRM_IOCTL_PSB_GET_PIPE_FROM_CRTC_ID \
122 DRM_IOWR(DRM_PSB_GET_PIPE_FROM_CRTC_ID + DRM_COMMAND_BASE, \
123 struct drm_psb_get_pipe_from_crtc_id_arg)
124 #define DRM_IOCTL_PSB_GEM_CREATE \
125 DRM_IOWR(DRM_PSB_GEM_CREATE + DRM_COMMAND_BASE, \
126 struct drm_psb_gem_create)
127 #define DRM_IOCTL_PSB_2D_OP \
128 DRM_IOW(DRM_PSB_2D_OP + DRM_COMMAND_BASE, \
129 struct drm_psb_2d_op)
130 #define DRM_IOCTL_PSB_GEM_MMAP \
131 DRM_IOWR(DRM_PSB_GEM_MMAP + DRM_COMMAND_BASE, \
132 struct drm_psb_gem_mmap)
133
134 static int psb_sizes_ioctl(struct drm_device *dev, void *data,
135 struct drm_file *file_priv);
136 static int psb_dc_state_ioctl(struct drm_device *dev, void * data,
137 struct drm_file *file_priv);
138 static int psb_adb_ioctl(struct drm_device *dev, void *data,
139 struct drm_file *file_priv);
140 static int psb_mode_operation_ioctl(struct drm_device *dev, void *data,
141 struct drm_file *file_priv);
142 static int psb_stolen_memory_ioctl(struct drm_device *dev, void *data,
143 struct drm_file *file_priv);
144 static int psb_register_rw_ioctl(struct drm_device *dev, void *data,
145 struct drm_file *file_priv);
146 static int psb_dpst_ioctl(struct drm_device *dev, void *data,
147 struct drm_file *file_priv);
148 static int psb_gamma_ioctl(struct drm_device *dev, void *data,
149 struct drm_file *file_priv);
150 static int psb_dpst_bl_ioctl(struct drm_device *dev, void *data,
151 struct drm_file *file_priv);
152
153 #define PSB_IOCTL_DEF(ioctl, func, flags) \
154 [DRM_IOCTL_NR(ioctl) - DRM_COMMAND_BASE] = {ioctl, flags, func}
155
156 static struct drm_ioctl_desc psb_ioctls[] = {
157 PSB_IOCTL_DEF(DRM_IOCTL_PSB_SIZES, psb_sizes_ioctl, DRM_AUTH),
158 PSB_IOCTL_DEF(DRM_IOCTL_PSB_DC_STATE, psb_dc_state_ioctl, DRM_AUTH),
159 PSB_IOCTL_DEF(DRM_IOCTL_PSB_ADB, psb_adb_ioctl, DRM_AUTH),
160 PSB_IOCTL_DEF(DRM_IOCTL_PSB_MODE_OPERATION, psb_mode_operation_ioctl,
161 DRM_AUTH),
162 PSB_IOCTL_DEF(DRM_IOCTL_PSB_STOLEN_MEMORY, psb_stolen_memory_ioctl,
163 DRM_AUTH),
164 PSB_IOCTL_DEF(DRM_IOCTL_PSB_REGISTER_RW, psb_register_rw_ioctl,
165 DRM_AUTH),
166 PSB_IOCTL_DEF(DRM_IOCTL_PSB_DPST, psb_dpst_ioctl, DRM_AUTH),
167 PSB_IOCTL_DEF(DRM_IOCTL_PSB_GAMMA, psb_gamma_ioctl, DRM_AUTH),
168 PSB_IOCTL_DEF(DRM_IOCTL_PSB_DPST_BL, psb_dpst_bl_ioctl, DRM_AUTH),
169 PSB_IOCTL_DEF(DRM_IOCTL_PSB_GET_PIPE_FROM_CRTC_ID,
170 psb_intel_get_pipe_from_crtc_id, 0),
171 PSB_IOCTL_DEF(DRM_IOCTL_PSB_GEM_CREATE, psb_gem_create_ioctl,
172 DRM_UNLOCKED | DRM_AUTH),
173 PSB_IOCTL_DEF(DRM_IOCTL_PSB_2D_OP, psb_accel_ioctl,
174 DRM_UNLOCKED| DRM_AUTH),
175 PSB_IOCTL_DEF(DRM_IOCTL_PSB_GEM_MMAP, psb_gem_mmap_ioctl,
176 DRM_UNLOCKED | DRM_AUTH),
177 };
178
179 static void psb_lastclose(struct drm_device *dev)
180 {
181 return;
182 }
183
184 static void psb_do_takedown(struct drm_device *dev)
185 {
186 }
187
188 static int psb_do_init(struct drm_device *dev)
189 {
190 struct drm_psb_private *dev_priv = dev->dev_private;
191 struct psb_gtt *pg = &dev_priv->gtt;
192
193 uint32_t stolen_gtt;
194
195 int ret = -ENOMEM;
196
197 if (pg->mmu_gatt_start & 0x0FFFFFFF) {
198 dev_err(dev->dev, "Gatt must be 256M aligned. This is a bug.\n");
199 ret = -EINVAL;
200 goto out_err;
201 }
202
203
204 stolen_gtt = (pg->stolen_size >> PAGE_SHIFT) * 4;
205 stolen_gtt = (stolen_gtt + PAGE_SIZE - 1) >> PAGE_SHIFT;
206 stolen_gtt =
207 (stolen_gtt < pg->gtt_pages) ? stolen_gtt : pg->gtt_pages;
208
209 dev_priv->gatt_free_offset = pg->mmu_gatt_start +
210 (stolen_gtt << PAGE_SHIFT) * 1024;
211
212 if (1 || drm_debug) {
213 uint32_t core_id = PSB_RSGX32(PSB_CR_CORE_ID);
214 uint32_t core_rev = PSB_RSGX32(PSB_CR_CORE_REVISION);
215 DRM_INFO("SGX core id = 0x%08x\n", core_id);
216 DRM_INFO("SGX core rev major = 0x%02x, minor = 0x%02x\n",
217 (core_rev & _PSB_CC_REVISION_MAJOR_MASK) >>
218 _PSB_CC_REVISION_MAJOR_SHIFT,
219 (core_rev & _PSB_CC_REVISION_MINOR_MASK) >>
220 _PSB_CC_REVISION_MINOR_SHIFT);
221 DRM_INFO
222 ("SGX core rev maintenance = 0x%02x, designer = 0x%02x\n",
223 (core_rev & _PSB_CC_REVISION_MAINTENANCE_MASK) >>
224 _PSB_CC_REVISION_MAINTENANCE_SHIFT,
225 (core_rev & _PSB_CC_REVISION_DESIGNER_MASK) >>
226 _PSB_CC_REVISION_DESIGNER_SHIFT);
227 }
228
229
230 spin_lock_init(&dev_priv->irqmask_lock);
231 spin_lock_init(&dev_priv->lock_2d);
232
233 PSB_WSGX32(0x00000000, PSB_CR_BIF_BANK0);
234 PSB_WSGX32(0x00000000, PSB_CR_BIF_BANK1);
235 PSB_RSGX32(PSB_CR_BIF_BANK1);
236 PSB_WSGX32(PSB_RSGX32(PSB_CR_BIF_CTRL) | _PSB_MMU_ER_MASK,
237 PSB_CR_BIF_CTRL);
238 psb_spank(dev_priv);
239
240 /* mmu_gatt ?? */
241 PSB_WSGX32(pg->gatt_start, PSB_CR_BIF_TWOD_REQ_BASE);
242 return 0;
243 out_err:
244 psb_do_takedown(dev);
245 return ret;
246 }
247
248 static int psb_driver_unload(struct drm_device *dev)
249 {
250 struct drm_psb_private *dev_priv = dev->dev_private;
251
252 /* Kill vblank etc here */
253
254 gma_backlight_exit(dev);
255
256 if (drm_psb_no_fb == 0)
257 psb_modeset_cleanup(dev);
258
259 if (dev_priv) {
260 psb_lid_timer_takedown(dev_priv);
261 gma_intel_opregion_exit(dev);
262
263 if (dev_priv->ops->chip_teardown)
264 dev_priv->ops->chip_teardown(dev);
265 psb_do_takedown(dev);
266
267
268 if (dev_priv->pf_pd) {
269 psb_mmu_free_pagedir(dev_priv->pf_pd);
270 dev_priv->pf_pd = NULL;
271 }
272 if (dev_priv->mmu) {
273 struct psb_gtt *pg = &dev_priv->gtt;
274
275 down_read(&pg->sem);
276 psb_mmu_remove_pfn_sequence(
277 psb_mmu_get_default_pd
278 (dev_priv->mmu),
279 pg->mmu_gatt_start,
280 dev_priv->vram_stolen_size >> PAGE_SHIFT);
281 up_read(&pg->sem);
282 psb_mmu_driver_takedown(dev_priv->mmu);
283 dev_priv->mmu = NULL;
284 }
285 psb_gtt_takedown(dev);
286 if (dev_priv->scratch_page) {
287 __free_page(dev_priv->scratch_page);
288 dev_priv->scratch_page = NULL;
289 }
290 if (dev_priv->vdc_reg) {
291 iounmap(dev_priv->vdc_reg);
292 dev_priv->vdc_reg = NULL;
293 }
294 if (dev_priv->sgx_reg) {
295 iounmap(dev_priv->sgx_reg);
296 dev_priv->sgx_reg = NULL;
297 }
298
299 kfree(dev_priv);
300 dev->dev_private = NULL;
301
302 /*destroy VBT data*/
303 psb_intel_destroy_bios(dev);
304 }
305
306 gma_power_uninit(dev);
307
308 return 0;
309 }
310
311
312 static int psb_driver_load(struct drm_device *dev, unsigned long chipset)
313 {
314 struct drm_psb_private *dev_priv;
315 unsigned long resource_start;
316 struct psb_gtt *pg;
317 unsigned long irqflags;
318 int ret = -ENOMEM;
319 uint32_t tt_pages;
320 struct drm_connector *connector;
321 struct psb_intel_output *psb_intel_output;
322
323 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
324 if (dev_priv == NULL)
325 return -ENOMEM;
326
327 dev_priv->ops = (struct psb_ops *)chipset;
328 dev_priv->dev = dev;
329 dev->dev_private = (void *) dev_priv;
330
331 if (!IS_PSB(dev)) {
332 if (pci_enable_msi(dev->pdev))
333 dev_warn(dev->dev, "Enabling MSI failed!\n");
334 }
335
336 dev_priv->num_pipe = dev_priv->ops->pipes;
337
338 resource_start = pci_resource_start(dev->pdev, PSB_MMIO_RESOURCE);
339
340 dev_priv->vdc_reg =
341 ioremap(resource_start + PSB_VDC_OFFSET, PSB_VDC_SIZE);
342 if (!dev_priv->vdc_reg)
343 goto out_err;
344
345 dev_priv->sgx_reg = ioremap(resource_start + dev_priv->ops->sgx_offset,
346 PSB_SGX_SIZE);
347 if (!dev_priv->sgx_reg)
348 goto out_err;
349
350 ret = dev_priv->ops->chip_setup(dev);
351 if (ret)
352 goto out_err;
353
354 /* Init OSPM support */
355 gma_power_init(dev);
356
357 ret = -ENOMEM;
358
359 dev_priv->scratch_page = alloc_page(GFP_DMA32 | __GFP_ZERO);
360 if (!dev_priv->scratch_page)
361 goto out_err;
362
363 set_pages_uc(dev_priv->scratch_page, 1);
364
365 ret = psb_gtt_init(dev, 0);
366 if (ret)
367 goto out_err;
368
369 dev_priv->mmu = psb_mmu_driver_init((void *)0,
370 drm_psb_trap_pagefaults, 0,
371 dev_priv);
372 if (!dev_priv->mmu)
373 goto out_err;
374
375 pg = &dev_priv->gtt;
376
377 tt_pages = (pg->gatt_pages < PSB_TT_PRIV0_PLIMIT) ?
378 (pg->gatt_pages) : PSB_TT_PRIV0_PLIMIT;
379
380
381 dev_priv->pf_pd = psb_mmu_alloc_pd(dev_priv->mmu, 1, 0);
382 if (!dev_priv->pf_pd)
383 goto out_err;
384
385 psb_mmu_set_pd_context(psb_mmu_get_default_pd(dev_priv->mmu), 0);
386 psb_mmu_set_pd_context(dev_priv->pf_pd, 1);
387
388 ret = psb_do_init(dev);
389 if (ret)
390 return ret;
391
392 PSB_WSGX32(0x20000000, PSB_CR_PDS_EXEC_BASE);
393 PSB_WSGX32(0x30000000, PSB_CR_BIF_3D_REQ_BASE);
394
395 /* igd_opregion_init(&dev_priv->opregion_dev); */
396 acpi_video_register();
397 if (dev_priv->lid_state)
398 psb_lid_timer_init(dev_priv);
399
400 ret = drm_vblank_init(dev, dev_priv->num_pipe);
401 if (ret)
402 goto out_err;
403
404 /*
405 * Install interrupt handlers prior to powering off SGX or else we will
406 * crash.
407 */
408 dev_priv->vdc_irq_mask = 0;
409 dev_priv->pipestat[0] = 0;
410 dev_priv->pipestat[1] = 0;
411 dev_priv->pipestat[2] = 0;
412 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
413 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
414 PSB_WVDC32(0x00000000, PSB_INT_ENABLE_R);
415 PSB_WVDC32(0xFFFFFFFF, PSB_INT_MASK_R);
416 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
417 if (IS_PSB(dev) && drm_core_check_feature(dev, DRIVER_MODESET))
418 drm_irq_install(dev);
419
420 dev->vblank_disable_allowed = 1;
421
422 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
423
424 dev->driver->get_vblank_counter = psb_get_vblank_counter;
425
426 #if defined(CONFIG_DRM_PSB_MFLD)
427 /* FIXME: this is not the right place for this stuff ! */
428 mdfld_output_setup(dev);
429 #endif
430 if (drm_psb_no_fb == 0) {
431 psb_modeset_init(dev);
432 psb_fbdev_init(dev);
433 drm_kms_helper_poll_init(dev);
434 }
435
436 /* Only add backlight support if we have LVDS output */
437 list_for_each_entry(connector, &dev->mode_config.connector_list,
438 head) {
439 psb_intel_output = to_psb_intel_output(connector);
440
441 switch (psb_intel_output->type) {
442 case INTEL_OUTPUT_LVDS:
443 case INTEL_OUTPUT_MIPI:
444 ret = gma_backlight_init(dev);
445 break;
446 }
447 }
448
449 if (ret)
450 return ret;
451
452 /* Enable runtime pm at last */
453 pm_runtime_set_active(&dev->pdev->dev);
454 return 0;
455 out_err:
456 psb_driver_unload(dev);
457 return ret;
458 }
459
460 int psb_driver_device_is_agp(struct drm_device *dev)
461 {
462 return 0;
463 }
464
465
466 static int psb_sizes_ioctl(struct drm_device *dev, void *data,
467 struct drm_file *file_priv)
468 {
469 struct drm_psb_private *dev_priv = psb_priv(dev);
470 struct drm_psb_sizes_arg *arg = data;
471
472 *arg = dev_priv->sizes;
473 return 0;
474 }
475
476 static int psb_dc_state_ioctl(struct drm_device *dev, void *data,
477 struct drm_file *file_priv)
478 {
479 uint32_t flags;
480 uint32_t obj_id;
481 struct drm_mode_object *obj;
482 struct drm_connector *connector;
483 struct drm_crtc *crtc;
484 struct drm_psb_dc_state_arg *arg = data;
485
486
487 /* Double check MRST case */
488 if (IS_MRST(dev) || IS_MFLD(dev))
489 return -EOPNOTSUPP;
490
491 flags = arg->flags;
492 obj_id = arg->obj_id;
493
494 if (flags & PSB_DC_CRTC_MASK) {
495 obj = drm_mode_object_find(dev, obj_id,
496 DRM_MODE_OBJECT_CRTC);
497 if (!obj) {
498 dev_dbg(dev->dev, "Invalid CRTC object.\n");
499 return -EINVAL;
500 }
501
502 crtc = obj_to_crtc(obj);
503
504 mutex_lock(&dev->mode_config.mutex);
505 if (drm_helper_crtc_in_use(crtc)) {
506 if (flags & PSB_DC_CRTC_SAVE)
507 crtc->funcs->save(crtc);
508 else
509 crtc->funcs->restore(crtc);
510 }
511 mutex_unlock(&dev->mode_config.mutex);
512
513 return 0;
514 } else if (flags & PSB_DC_OUTPUT_MASK) {
515 obj = drm_mode_object_find(dev, obj_id,
516 DRM_MODE_OBJECT_CONNECTOR);
517 if (!obj) {
518 dev_dbg(dev->dev, "Invalid connector id.\n");
519 return -EINVAL;
520 }
521
522 connector = obj_to_connector(obj);
523 if (flags & PSB_DC_OUTPUT_SAVE)
524 connector->funcs->save(connector);
525 else
526 connector->funcs->restore(connector);
527
528 return 0;
529 }
530 return -EINVAL;
531 }
532
533 static inline void get_brightness(struct backlight_device *bd)
534 {
535 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
536 if (bd) {
537 bd->props.brightness = bd->ops->get_brightness(bd);
538 backlight_update_status(bd);
539 }
540 #endif
541 }
542
543 static int psb_dpst_bl_ioctl(struct drm_device *dev, void *data,
544 struct drm_file *file_priv)
545 {
546 struct drm_psb_private *dev_priv = psb_priv(dev);
547 uint32_t *arg = data;
548
549 dev_priv->blc_adj2 = *arg;
550 get_brightness(dev_priv->backlight_device);
551 return 0;
552 }
553
554 static int psb_adb_ioctl(struct drm_device *dev, void *data,
555 struct drm_file *file_priv)
556 {
557 struct drm_psb_private *dev_priv = psb_priv(dev);
558 uint32_t *arg = data;
559
560 dev_priv->blc_adj1 = *arg;
561 get_brightness(dev_priv->backlight_device);
562 return 0;
563 }
564
565 /* return the current mode to the dpst module */
566 static int psb_dpst_ioctl(struct drm_device *dev, void *data,
567 struct drm_file *file_priv)
568 {
569 struct drm_psb_private *dev_priv = psb_priv(dev);
570 uint32_t *arg = data;
571 uint32_t x;
572 uint32_t y;
573 uint32_t reg;
574
575 if (!gma_power_begin(dev, 0))
576 return -EIO;
577
578 reg = PSB_RVDC32(PIPEASRC);
579
580 gma_power_end(dev);
581
582 /* horizontal is the left 16 bits */
583 x = reg >> 16;
584 /* vertical is the right 16 bits */
585 y = reg & 0x0000ffff;
586
587 /* the values are the image size minus one */
588 x++;
589 y++;
590
591 *arg = (x << 16) | y;
592
593 return 0;
594 }
595 static int psb_gamma_ioctl(struct drm_device *dev, void *data,
596 struct drm_file *file_priv)
597 {
598 struct drm_psb_dpst_lut_arg *lut_arg = data;
599 struct drm_mode_object *obj;
600 struct drm_crtc *crtc;
601 struct drm_connector *connector;
602 struct psb_intel_crtc *psb_intel_crtc;
603 int i = 0;
604 int32_t obj_id;
605
606 obj_id = lut_arg->output_id;
607 obj = drm_mode_object_find(dev, obj_id, DRM_MODE_OBJECT_CONNECTOR);
608 if (!obj) {
609 dev_dbg(dev->dev, "Invalid Connector object.\n");
610 return -EINVAL;
611 }
612
613 connector = obj_to_connector(obj);
614 crtc = connector->encoder->crtc;
615 psb_intel_crtc = to_psb_intel_crtc(crtc);
616
617 for (i = 0; i < 256; i++)
618 psb_intel_crtc->lut_adj[i] = lut_arg->lut[i];
619
620 psb_intel_crtc_load_lut(crtc);
621
622 return 0;
623 }
624
625 static int psb_mode_operation_ioctl(struct drm_device *dev, void *data,
626 struct drm_file *file_priv)
627 {
628 uint32_t obj_id;
629 uint16_t op;
630 struct drm_mode_modeinfo *umode;
631 struct drm_display_mode *mode = NULL;
632 struct drm_psb_mode_operation_arg *arg;
633 struct drm_mode_object *obj;
634 struct drm_connector *connector;
635 struct drm_framebuffer *drm_fb;
636 struct psb_framebuffer *psb_fb;
637 struct drm_connector_helper_funcs *connector_funcs;
638 int ret = 0;
639 int resp = MODE_OK;
640 struct drm_psb_private *dev_priv = psb_priv(dev);
641
642 arg = (struct drm_psb_mode_operation_arg *)data;
643 obj_id = arg->obj_id;
644 op = arg->operation;
645
646 switch (op) {
647 case PSB_MODE_OPERATION_SET_DC_BASE:
648 obj = drm_mode_object_find(dev, obj_id, DRM_MODE_OBJECT_FB);
649 if (!obj) {
650 dev_dbg(dev->dev, "Invalid FB id %d\n", obj_id);
651 return -EINVAL;
652 }
653
654 drm_fb = obj_to_fb(obj);
655 psb_fb = to_psb_fb(drm_fb);
656
657 if (gma_power_begin(dev, 0)) {
658 REG_WRITE(DSPASURF, psb_fb->gtt->offset);
659 REG_READ(DSPASURF);
660 gma_power_end(dev);
661 } else {
662 dev_priv->saveDSPASURF = psb_fb->gtt->offset;
663 }
664
665 return 0;
666 case PSB_MODE_OPERATION_MODE_VALID:
667 umode = &arg->mode;
668
669 mutex_lock(&dev->mode_config.mutex);
670
671 obj = drm_mode_object_find(dev, obj_id,
672 DRM_MODE_OBJECT_CONNECTOR);
673 if (!obj) {
674 ret = -EINVAL;
675 goto mode_op_out;
676 }
677
678 connector = obj_to_connector(obj);
679
680 mode = drm_mode_create(dev);
681 if (!mode) {
682 ret = -ENOMEM;
683 goto mode_op_out;
684 }
685
686 /* drm_crtc_convert_umode(mode, umode); */
687 {
688 mode->clock = umode->clock;
689 mode->hdisplay = umode->hdisplay;
690 mode->hsync_start = umode->hsync_start;
691 mode->hsync_end = umode->hsync_end;
692 mode->htotal = umode->htotal;
693 mode->hskew = umode->hskew;
694 mode->vdisplay = umode->vdisplay;
695 mode->vsync_start = umode->vsync_start;
696 mode->vsync_end = umode->vsync_end;
697 mode->vtotal = umode->vtotal;
698 mode->vscan = umode->vscan;
699 mode->vrefresh = umode->vrefresh;
700 mode->flags = umode->flags;
701 mode->type = umode->type;
702 strncpy(mode->name, umode->name, DRM_DISPLAY_MODE_LEN);
703 mode->name[DRM_DISPLAY_MODE_LEN-1] = 0;
704 }
705
706 connector_funcs = (struct drm_connector_helper_funcs *)
707 connector->helper_private;
708
709 if (connector_funcs->mode_valid) {
710 resp = connector_funcs->mode_valid(connector, mode);
711 arg->data = (void *)resp;
712 }
713
714 /*do some clean up work*/
715 if (mode)
716 drm_mode_destroy(dev, mode);
717 mode_op_out:
718 mutex_unlock(&dev->mode_config.mutex);
719 return ret;
720
721 default:
722 dev_dbg(dev->dev, "Unsupported psb mode operation\n");
723 return -EOPNOTSUPP;
724 }
725
726 return 0;
727 }
728
729 static int psb_stolen_memory_ioctl(struct drm_device *dev, void *data,
730 struct drm_file *file_priv)
731 {
732 struct drm_psb_private *dev_priv = psb_priv(dev);
733 struct drm_psb_stolen_memory_arg *arg = data;
734
735 arg->base = dev_priv->stolen_base;
736 arg->size = dev_priv->vram_stolen_size;
737
738 return 0;
739 }
740
741 /* FIXME: needs Medfield changes */
742 static int psb_register_rw_ioctl(struct drm_device *dev, void *data,
743 struct drm_file *file_priv)
744 {
745 struct drm_psb_private *dev_priv = psb_priv(dev);
746 struct drm_psb_register_rw_arg *arg = data;
747 bool usage = arg->b_force_hw_on ? true : false;
748
749 if (arg->display_write_mask != 0) {
750 if (gma_power_begin(dev, usage)) {
751 if (arg->display_write_mask & REGRWBITS_PFIT_CONTROLS)
752 PSB_WVDC32(arg->display.pfit_controls,
753 PFIT_CONTROL);
754 if (arg->display_write_mask &
755 REGRWBITS_PFIT_AUTOSCALE_RATIOS)
756 PSB_WVDC32(arg->display.pfit_autoscale_ratios,
757 PFIT_AUTO_RATIOS);
758 if (arg->display_write_mask &
759 REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS)
760 PSB_WVDC32(
761 arg->display.pfit_programmed_scale_ratios,
762 PFIT_PGM_RATIOS);
763 if (arg->display_write_mask & REGRWBITS_PIPEASRC)
764 PSB_WVDC32(arg->display.pipeasrc,
765 PIPEASRC);
766 if (arg->display_write_mask & REGRWBITS_PIPEBSRC)
767 PSB_WVDC32(arg->display.pipebsrc,
768 PIPEBSRC);
769 if (arg->display_write_mask & REGRWBITS_VTOTAL_A)
770 PSB_WVDC32(arg->display.vtotal_a,
771 VTOTAL_A);
772 if (arg->display_write_mask & REGRWBITS_VTOTAL_B)
773 PSB_WVDC32(arg->display.vtotal_b,
774 VTOTAL_B);
775 gma_power_end(dev);
776 } else {
777 if (arg->display_write_mask & REGRWBITS_PFIT_CONTROLS)
778 dev_priv->savePFIT_CONTROL =
779 arg->display.pfit_controls;
780 if (arg->display_write_mask &
781 REGRWBITS_PFIT_AUTOSCALE_RATIOS)
782 dev_priv->savePFIT_AUTO_RATIOS =
783 arg->display.pfit_autoscale_ratios;
784 if (arg->display_write_mask &
785 REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS)
786 dev_priv->savePFIT_PGM_RATIOS =
787 arg->display.pfit_programmed_scale_ratios;
788 if (arg->display_write_mask & REGRWBITS_PIPEASRC)
789 dev_priv->savePIPEASRC = arg->display.pipeasrc;
790 if (arg->display_write_mask & REGRWBITS_PIPEBSRC)
791 dev_priv->savePIPEBSRC = arg->display.pipebsrc;
792 if (arg->display_write_mask & REGRWBITS_VTOTAL_A)
793 dev_priv->saveVTOTAL_A = arg->display.vtotal_a;
794 if (arg->display_write_mask & REGRWBITS_VTOTAL_B)
795 dev_priv->saveVTOTAL_B = arg->display.vtotal_b;
796 }
797 }
798
799 if (arg->display_read_mask != 0) {
800 if (gma_power_begin(dev, usage)) {
801 if (arg->display_read_mask &
802 REGRWBITS_PFIT_CONTROLS)
803 arg->display.pfit_controls =
804 PSB_RVDC32(PFIT_CONTROL);
805 if (arg->display_read_mask &
806 REGRWBITS_PFIT_AUTOSCALE_RATIOS)
807 arg->display.pfit_autoscale_ratios =
808 PSB_RVDC32(PFIT_AUTO_RATIOS);
809 if (arg->display_read_mask &
810 REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS)
811 arg->display.pfit_programmed_scale_ratios =
812 PSB_RVDC32(PFIT_PGM_RATIOS);
813 if (arg->display_read_mask & REGRWBITS_PIPEASRC)
814 arg->display.pipeasrc = PSB_RVDC32(PIPEASRC);
815 if (arg->display_read_mask & REGRWBITS_PIPEBSRC)
816 arg->display.pipebsrc = PSB_RVDC32(PIPEBSRC);
817 if (arg->display_read_mask & REGRWBITS_VTOTAL_A)
818 arg->display.vtotal_a = PSB_RVDC32(VTOTAL_A);
819 if (arg->display_read_mask & REGRWBITS_VTOTAL_B)
820 arg->display.vtotal_b = PSB_RVDC32(VTOTAL_B);
821 gma_power_end(dev);
822 } else {
823 if (arg->display_read_mask &
824 REGRWBITS_PFIT_CONTROLS)
825 arg->display.pfit_controls =
826 dev_priv->savePFIT_CONTROL;
827 if (arg->display_read_mask &
828 REGRWBITS_PFIT_AUTOSCALE_RATIOS)
829 arg->display.pfit_autoscale_ratios =
830 dev_priv->savePFIT_AUTO_RATIOS;
831 if (arg->display_read_mask &
832 REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS)
833 arg->display.pfit_programmed_scale_ratios =
834 dev_priv->savePFIT_PGM_RATIOS;
835 if (arg->display_read_mask & REGRWBITS_PIPEASRC)
836 arg->display.pipeasrc = dev_priv->savePIPEASRC;
837 if (arg->display_read_mask & REGRWBITS_PIPEBSRC)
838 arg->display.pipebsrc = dev_priv->savePIPEBSRC;
839 if (arg->display_read_mask & REGRWBITS_VTOTAL_A)
840 arg->display.vtotal_a = dev_priv->saveVTOTAL_A;
841 if (arg->display_read_mask & REGRWBITS_VTOTAL_B)
842 arg->display.vtotal_b = dev_priv->saveVTOTAL_B;
843 }
844 }
845
846 if (arg->overlay_write_mask != 0) {
847 if (gma_power_begin(dev, usage)) {
848 if (arg->overlay_write_mask & OV_REGRWBITS_OGAM_ALL) {
849 PSB_WVDC32(arg->overlay.OGAMC5, OV_OGAMC5);
850 PSB_WVDC32(arg->overlay.OGAMC4, OV_OGAMC4);
851 PSB_WVDC32(arg->overlay.OGAMC3, OV_OGAMC3);
852 PSB_WVDC32(arg->overlay.OGAMC2, OV_OGAMC2);
853 PSB_WVDC32(arg->overlay.OGAMC1, OV_OGAMC1);
854 PSB_WVDC32(arg->overlay.OGAMC0, OV_OGAMC0);
855 }
856 if (arg->overlay_write_mask & OVC_REGRWBITS_OGAM_ALL) {
857 PSB_WVDC32(arg->overlay.OGAMC5, OVC_OGAMC5);
858 PSB_WVDC32(arg->overlay.OGAMC4, OVC_OGAMC4);
859 PSB_WVDC32(arg->overlay.OGAMC3, OVC_OGAMC3);
860 PSB_WVDC32(arg->overlay.OGAMC2, OVC_OGAMC2);
861 PSB_WVDC32(arg->overlay.OGAMC1, OVC_OGAMC1);
862 PSB_WVDC32(arg->overlay.OGAMC0, OVC_OGAMC0);
863 }
864
865 if (arg->overlay_write_mask & OV_REGRWBITS_OVADD) {
866 PSB_WVDC32(arg->overlay.OVADD, OV_OVADD);
867
868 if (arg->overlay.b_wait_vblank) {
869 /* Wait for 20ms.*/
870 unsigned long vblank_timeout = jiffies
871 + HZ/50;
872 uint32_t temp;
873 while (time_before_eq(jiffies,
874 vblank_timeout)) {
875 temp = PSB_RVDC32(OV_DOVASTA);
876 if ((temp & (0x1 << 31)) != 0)
877 break;
878 cpu_relax();
879 }
880 }
881 }
882 if (arg->overlay_write_mask & OVC_REGRWBITS_OVADD) {
883 PSB_WVDC32(arg->overlay.OVADD, OVC_OVADD);
884 if (arg->overlay.b_wait_vblank) {
885 /* Wait for 20ms.*/
886 unsigned long vblank_timeout =
887 jiffies + HZ/50;
888 uint32_t temp;
889 while (time_before_eq(jiffies,
890 vblank_timeout)) {
891 temp = PSB_RVDC32(OVC_DOVCSTA);
892 if ((temp & (0x1 << 31)) != 0)
893 break;
894 cpu_relax();
895 }
896 }
897 }
898 gma_power_end(dev);
899 } else {
900 if (arg->overlay_write_mask & OV_REGRWBITS_OGAM_ALL) {
901 dev_priv->saveOV_OGAMC5 = arg->overlay.OGAMC5;
902 dev_priv->saveOV_OGAMC4 = arg->overlay.OGAMC4;
903 dev_priv->saveOV_OGAMC3 = arg->overlay.OGAMC3;
904 dev_priv->saveOV_OGAMC2 = arg->overlay.OGAMC2;
905 dev_priv->saveOV_OGAMC1 = arg->overlay.OGAMC1;
906 dev_priv->saveOV_OGAMC0 = arg->overlay.OGAMC0;
907 }
908 if (arg->overlay_write_mask & OVC_REGRWBITS_OGAM_ALL) {
909 dev_priv->saveOVC_OGAMC5 = arg->overlay.OGAMC5;
910 dev_priv->saveOVC_OGAMC4 = arg->overlay.OGAMC4;
911 dev_priv->saveOVC_OGAMC3 = arg->overlay.OGAMC3;
912 dev_priv->saveOVC_OGAMC2 = arg->overlay.OGAMC2;
913 dev_priv->saveOVC_OGAMC1 = arg->overlay.OGAMC1;
914 dev_priv->saveOVC_OGAMC0 = arg->overlay.OGAMC0;
915 }
916 if (arg->overlay_write_mask & OV_REGRWBITS_OVADD)
917 dev_priv->saveOV_OVADD = arg->overlay.OVADD;
918 if (arg->overlay_write_mask & OVC_REGRWBITS_OVADD)
919 dev_priv->saveOVC_OVADD = arg->overlay.OVADD;
920 }
921 }
922
923 if (arg->overlay_read_mask != 0) {
924 if (gma_power_begin(dev, usage)) {
925 if (arg->overlay_read_mask & OV_REGRWBITS_OGAM_ALL) {
926 arg->overlay.OGAMC5 = PSB_RVDC32(OV_OGAMC5);
927 arg->overlay.OGAMC4 = PSB_RVDC32(OV_OGAMC4);
928 arg->overlay.OGAMC3 = PSB_RVDC32(OV_OGAMC3);
929 arg->overlay.OGAMC2 = PSB_RVDC32(OV_OGAMC2);
930 arg->overlay.OGAMC1 = PSB_RVDC32(OV_OGAMC1);
931 arg->overlay.OGAMC0 = PSB_RVDC32(OV_OGAMC0);
932 }
933 if (arg->overlay_read_mask & OVC_REGRWBITS_OGAM_ALL) {
934 arg->overlay.OGAMC5 = PSB_RVDC32(OVC_OGAMC5);
935 arg->overlay.OGAMC4 = PSB_RVDC32(OVC_OGAMC4);
936 arg->overlay.OGAMC3 = PSB_RVDC32(OVC_OGAMC3);
937 arg->overlay.OGAMC2 = PSB_RVDC32(OVC_OGAMC2);
938 arg->overlay.OGAMC1 = PSB_RVDC32(OVC_OGAMC1);
939 arg->overlay.OGAMC0 = PSB_RVDC32(OVC_OGAMC0);
940 }
941 if (arg->overlay_read_mask & OV_REGRWBITS_OVADD)
942 arg->overlay.OVADD = PSB_RVDC32(OV_OVADD);
943 if (arg->overlay_read_mask & OVC_REGRWBITS_OVADD)
944 arg->overlay.OVADD = PSB_RVDC32(OVC_OVADD);
945 gma_power_end(dev);
946 } else {
947 if (arg->overlay_read_mask & OV_REGRWBITS_OGAM_ALL) {
948 arg->overlay.OGAMC5 = dev_priv->saveOV_OGAMC5;
949 arg->overlay.OGAMC4 = dev_priv->saveOV_OGAMC4;
950 arg->overlay.OGAMC3 = dev_priv->saveOV_OGAMC3;
951 arg->overlay.OGAMC2 = dev_priv->saveOV_OGAMC2;
952 arg->overlay.OGAMC1 = dev_priv->saveOV_OGAMC1;
953 arg->overlay.OGAMC0 = dev_priv->saveOV_OGAMC0;
954 }
955 if (arg->overlay_read_mask & OVC_REGRWBITS_OGAM_ALL) {
956 arg->overlay.OGAMC5 = dev_priv->saveOVC_OGAMC5;
957 arg->overlay.OGAMC4 = dev_priv->saveOVC_OGAMC4;
958 arg->overlay.OGAMC3 = dev_priv->saveOVC_OGAMC3;
959 arg->overlay.OGAMC2 = dev_priv->saveOVC_OGAMC2;
960 arg->overlay.OGAMC1 = dev_priv->saveOVC_OGAMC1;
961 arg->overlay.OGAMC0 = dev_priv->saveOVC_OGAMC0;
962 }
963 if (arg->overlay_read_mask & OV_REGRWBITS_OVADD)
964 arg->overlay.OVADD = dev_priv->saveOV_OVADD;
965 if (arg->overlay_read_mask & OVC_REGRWBITS_OVADD)
966 arg->overlay.OVADD = dev_priv->saveOVC_OVADD;
967 }
968 }
969
970 if (arg->sprite_enable_mask != 0) {
971 if (gma_power_begin(dev, usage)) {
972 PSB_WVDC32(0x1F3E, DSPARB);
973 PSB_WVDC32(arg->sprite.dspa_control
974 | PSB_RVDC32(DSPACNTR), DSPACNTR);
975 PSB_WVDC32(arg->sprite.dspa_key_value, DSPAKEYVAL);
976 PSB_WVDC32(arg->sprite.dspa_key_mask, DSPAKEYMASK);
977 PSB_WVDC32(PSB_RVDC32(DSPASURF), DSPASURF);
978 PSB_RVDC32(DSPASURF);
979 PSB_WVDC32(arg->sprite.dspc_control, DSPCCNTR);
980 PSB_WVDC32(arg->sprite.dspc_stride, DSPCSTRIDE);
981 PSB_WVDC32(arg->sprite.dspc_position, DSPCPOS);
982 PSB_WVDC32(arg->sprite.dspc_linear_offset, DSPCLINOFF);
983 PSB_WVDC32(arg->sprite.dspc_size, DSPCSIZE);
984 PSB_WVDC32(arg->sprite.dspc_surface, DSPCSURF);
985 PSB_RVDC32(DSPCSURF);
986 gma_power_end(dev);
987 }
988 }
989
990 if (arg->sprite_disable_mask != 0) {
991 if (gma_power_begin(dev, usage)) {
992 PSB_WVDC32(0x3F3E, DSPARB);
993 PSB_WVDC32(0x0, DSPCCNTR);
994 PSB_WVDC32(arg->sprite.dspc_surface, DSPCSURF);
995 PSB_RVDC32(DSPCSURF);
996 gma_power_end(dev);
997 }
998 }
999
1000 if (arg->subpicture_enable_mask != 0) {
1001 if (gma_power_begin(dev, usage)) {
1002 uint32_t temp;
1003 if (arg->subpicture_enable_mask & REGRWBITS_DSPACNTR) {
1004 temp = PSB_RVDC32(DSPACNTR);
1005 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1006 temp &= ~DISPPLANE_BOTTOM;
1007 temp |= DISPPLANE_32BPP;
1008 PSB_WVDC32(temp, DSPACNTR);
1009
1010 temp = PSB_RVDC32(DSPABASE);
1011 PSB_WVDC32(temp, DSPABASE);
1012 PSB_RVDC32(DSPABASE);
1013 temp = PSB_RVDC32(DSPASURF);
1014 PSB_WVDC32(temp, DSPASURF);
1015 PSB_RVDC32(DSPASURF);
1016 }
1017 if (arg->subpicture_enable_mask & REGRWBITS_DSPBCNTR) {
1018 temp = PSB_RVDC32(DSPBCNTR);
1019 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1020 temp &= ~DISPPLANE_BOTTOM;
1021 temp |= DISPPLANE_32BPP;
1022 PSB_WVDC32(temp, DSPBCNTR);
1023
1024 temp = PSB_RVDC32(DSPBBASE);
1025 PSB_WVDC32(temp, DSPBBASE);
1026 PSB_RVDC32(DSPBBASE);
1027 temp = PSB_RVDC32(DSPBSURF);
1028 PSB_WVDC32(temp, DSPBSURF);
1029 PSB_RVDC32(DSPBSURF);
1030 }
1031 if (arg->subpicture_enable_mask & REGRWBITS_DSPCCNTR) {
1032 temp = PSB_RVDC32(DSPCCNTR);
1033 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1034 temp &= ~DISPPLANE_BOTTOM;
1035 temp |= DISPPLANE_32BPP;
1036 PSB_WVDC32(temp, DSPCCNTR);
1037
1038 temp = PSB_RVDC32(DSPCBASE);
1039 PSB_WVDC32(temp, DSPCBASE);
1040 PSB_RVDC32(DSPCBASE);
1041 temp = PSB_RVDC32(DSPCSURF);
1042 PSB_WVDC32(temp, DSPCSURF);
1043 PSB_RVDC32(DSPCSURF);
1044 }
1045 gma_power_end(dev);
1046 }
1047 }
1048
1049 if (arg->subpicture_disable_mask != 0) {
1050 if (gma_power_begin(dev, usage)) {
1051 uint32_t temp;
1052 if (arg->subpicture_disable_mask & REGRWBITS_DSPACNTR) {
1053 temp = PSB_RVDC32(DSPACNTR);
1054 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1055 temp |= DISPPLANE_32BPP_NO_ALPHA;
1056 PSB_WVDC32(temp, DSPACNTR);
1057
1058 temp = PSB_RVDC32(DSPABASE);
1059 PSB_WVDC32(temp, DSPABASE);
1060 PSB_RVDC32(DSPABASE);
1061 temp = PSB_RVDC32(DSPASURF);
1062 PSB_WVDC32(temp, DSPASURF);
1063 PSB_RVDC32(DSPASURF);
1064 }
1065 if (arg->subpicture_disable_mask & REGRWBITS_DSPBCNTR) {
1066 temp = PSB_RVDC32(DSPBCNTR);
1067 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1068 temp |= DISPPLANE_32BPP_NO_ALPHA;
1069 PSB_WVDC32(temp, DSPBCNTR);
1070
1071 temp = PSB_RVDC32(DSPBBASE);
1072 PSB_WVDC32(temp, DSPBBASE);
1073 PSB_RVDC32(DSPBBASE);
1074 temp = PSB_RVDC32(DSPBSURF);
1075 PSB_WVDC32(temp, DSPBSURF);
1076 PSB_RVDC32(DSPBSURF);
1077 }
1078 if (arg->subpicture_disable_mask & REGRWBITS_DSPCCNTR) {
1079 temp = PSB_RVDC32(DSPCCNTR);
1080 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1081 temp |= DISPPLANE_32BPP_NO_ALPHA;
1082 PSB_WVDC32(temp, DSPCCNTR);
1083
1084 temp = PSB_RVDC32(DSPCBASE);
1085 PSB_WVDC32(temp, DSPCBASE);
1086 PSB_RVDC32(DSPCBASE);
1087 temp = PSB_RVDC32(DSPCSURF);
1088 PSB_WVDC32(temp, DSPCSURF);
1089 PSB_RVDC32(DSPCSURF);
1090 }
1091 gma_power_end(dev);
1092 }
1093 }
1094
1095 return 0;
1096 }
1097
1098 static int psb_driver_open(struct drm_device *dev, struct drm_file *priv)
1099 {
1100 return 0;
1101 }
1102
1103 static void psb_driver_close(struct drm_device *dev, struct drm_file *priv)
1104 {
1105 }
1106
1107 static long psb_unlocked_ioctl(struct file *filp, unsigned int cmd,
1108 unsigned long arg)
1109 {
1110 struct drm_file *file_priv = filp->private_data;
1111 struct drm_device *dev = file_priv->minor->dev;
1112 int ret;
1113
1114 pm_runtime_forbid(dev->dev);
1115 ret = drm_ioctl(filp, cmd, arg);
1116 pm_runtime_allow(dev->dev);
1117 return ret;
1118 /* FIXME: do we need to wrap the other side of this */
1119 }
1120
1121
1122 /* When a client dies:
1123 * - Check for and clean up flipped page state
1124 */
1125 void psb_driver_preclose(struct drm_device *dev, struct drm_file *priv)
1126 {
1127 }
1128
1129 static void psb_remove(struct pci_dev *pdev)
1130 {
1131 struct drm_device *dev = pci_get_drvdata(pdev);
1132 drm_put_dev(dev);
1133 }
1134
1135 static const struct dev_pm_ops psb_pm_ops = {
1136 .suspend = gma_power_suspend,
1137 .resume = gma_power_resume,
1138 .freeze = gma_power_suspend,
1139 .thaw = gma_power_resume,
1140 .poweroff = gma_power_suspend,
1141 .restore = gma_power_resume,
1142 .runtime_suspend = psb_runtime_suspend,
1143 .runtime_resume = psb_runtime_resume,
1144 .runtime_idle = psb_runtime_idle,
1145 };
1146
1147 static struct vm_operations_struct psb_gem_vm_ops = {
1148 .fault = psb_gem_fault,
1149 .open = drm_gem_vm_open,
1150 .close = drm_gem_vm_close,
1151 };
1152
1153 static struct drm_driver driver = {
1154 .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | \
1155 DRIVER_IRQ_VBL | DRIVER_MODESET | DRIVER_GEM ,
1156 .load = psb_driver_load,
1157 .unload = psb_driver_unload,
1158
1159 .ioctls = psb_ioctls,
1160 .num_ioctls = DRM_ARRAY_SIZE(psb_ioctls),
1161 .device_is_agp = psb_driver_device_is_agp,
1162 .irq_preinstall = psb_irq_preinstall,
1163 .irq_postinstall = psb_irq_postinstall,
1164 .irq_uninstall = psb_irq_uninstall,
1165 .irq_handler = psb_irq_handler,
1166 .enable_vblank = psb_enable_vblank,
1167 .disable_vblank = psb_disable_vblank,
1168 .get_vblank_counter = psb_get_vblank_counter,
1169 .lastclose = psb_lastclose,
1170 .open = psb_driver_open,
1171 .preclose = psb_driver_preclose,
1172 .postclose = psb_driver_close,
1173 .reclaim_buffers = drm_core_reclaim_buffers,
1174
1175 .gem_init_object = psb_gem_init_object,
1176 .gem_free_object = psb_gem_free_object,
1177 .gem_vm_ops = &psb_gem_vm_ops,
1178 .dumb_create = psb_gem_dumb_create,
1179 .dumb_map_offset = psb_gem_dumb_map_gtt,
1180 .dumb_destroy = psb_gem_dumb_destroy,
1181
1182 .fops = {
1183 .owner = THIS_MODULE,
1184 .open = drm_open,
1185 .release = drm_release,
1186 .unlocked_ioctl = psb_unlocked_ioctl,
1187 .mmap = drm_gem_mmap,
1188 .poll = drm_poll,
1189 .fasync = drm_fasync,
1190 .read = drm_read,
1191 },
1192 .name = DRIVER_NAME,
1193 .desc = DRIVER_DESC,
1194 .date = PSB_DRM_DRIVER_DATE,
1195 .major = PSB_DRM_DRIVER_MAJOR,
1196 .minor = PSB_DRM_DRIVER_MINOR,
1197 .patchlevel = PSB_DRM_DRIVER_PATCHLEVEL
1198 };
1199
1200 static struct pci_driver psb_pci_driver = {
1201 .name = DRIVER_NAME,
1202 .id_table = pciidlist,
1203 .probe = psb_probe,
1204 .remove = psb_remove,
1205 .driver.pm = &psb_pm_ops,
1206 };
1207
1208 static int psb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1209 {
1210 return drm_get_pci_dev(pdev, ent, &driver);
1211 }
1212
1213 static int __init psb_init(void)
1214 {
1215 return drm_pci_init(&driver, &psb_pci_driver);
1216 }
1217
1218 static void __exit psb_exit(void)
1219 {
1220 drm_pci_exit(&driver, &psb_pci_driver);
1221 }
1222
1223 late_initcall(psb_init);
1224 module_exit(psb_exit);
1225
1226 MODULE_AUTHOR("Alan Cox <alan@linux.intel.com> and others");
1227 MODULE_DESCRIPTION(DRIVER_DESC);
1228 MODULE_LICENSE("GPL");
Linus' kernel tree