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bnx2x: update driver version to 1.70.30-0
[linux-2.6.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x.h
blobaec7212ac9835a4aba89b24641238a0e2d08448e
1 /* bnx2x.h: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2011 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 */
13
14 #ifndef BNX2X_H
15 #define BNX2X_H
16 #include <linux/netdevice.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/types.h>
19
20 /* compilation time flags */
21
22 /* define this to make the driver freeze on error to allow getting debug info
23 * (you will need to reboot afterwards) */
24 /* #define BNX2X_STOP_ON_ERROR */
25
26 #define DRV_MODULE_VERSION "1.70.30-0"
27 #define DRV_MODULE_RELDATE "2011/10/25"
28 #define BNX2X_BC_VER 0x040200
29
30 #if defined(CONFIG_DCB)
31 #define BCM_DCBNL
32 #endif
33 #if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE)
34 #define BCM_CNIC 1
35 #include "../cnic_if.h"
36 #endif
37
38 #ifdef BCM_CNIC
39 #define BNX2X_MIN_MSIX_VEC_CNT 3
40 #define BNX2X_MSIX_VEC_FP_START 2
41 #else
42 #define BNX2X_MIN_MSIX_VEC_CNT 2
43 #define BNX2X_MSIX_VEC_FP_START 1
44 #endif
45
46 #include <linux/mdio.h>
47
48 #include "bnx2x_reg.h"
49 #include "bnx2x_fw_defs.h"
50 #include "bnx2x_hsi.h"
51 #include "bnx2x_link.h"
52 #include "bnx2x_sp.h"
53 #include "bnx2x_dcb.h"
54 #include "bnx2x_stats.h"
55
56 /* error/debug prints */
57
58 #define DRV_MODULE_NAME "bnx2x"
59
60 /* for messages that are currently off */
61 #define BNX2X_MSG_OFF 0
62 #define BNX2X_MSG_MCP 0x010000 /* was: NETIF_MSG_HW */
63 #define BNX2X_MSG_STATS 0x020000 /* was: NETIF_MSG_TIMER */
64 #define BNX2X_MSG_NVM 0x040000 /* was: NETIF_MSG_HW */
65 #define BNX2X_MSG_DMAE 0x080000 /* was: NETIF_MSG_HW */
66 #define BNX2X_MSG_SP 0x100000 /* was: NETIF_MSG_INTR */
67 #define BNX2X_MSG_FP 0x200000 /* was: NETIF_MSG_INTR */
68
69 /* regular debug print */
70 #define DP(__mask, fmt, ...) \
71 do { \
72 if (bp->msg_enable & (__mask)) \
73 pr_notice("[%s:%d(%s)]" fmt, \
74 __func__, __LINE__, \
75 bp->dev ? (bp->dev->name) : "?", \
76 ##__VA_ARGS__); \
77 } while (0)
78
79 #define DP_CONT(__mask, fmt, ...) \
80 do { \
81 if (bp->msg_enable & (__mask)) \
82 pr_cont(fmt, ##__VA_ARGS__); \
83 } while (0)
84
85 /* errors debug print */
86 #define BNX2X_DBG_ERR(fmt, ...) \
87 do { \
88 if (netif_msg_probe(bp)) \
89 pr_err("[%s:%d(%s)]" fmt, \
90 __func__, __LINE__, \
91 bp->dev ? (bp->dev->name) : "?", \
92 ##__VA_ARGS__); \
93 } while (0)
94
95 /* for errors (never masked) */
96 #define BNX2X_ERR(fmt, ...) \
97 do { \
98 pr_err("[%s:%d(%s)]" fmt, \
99 __func__, __LINE__, \
100 bp->dev ? (bp->dev->name) : "?", \
101 ##__VA_ARGS__); \
102 } while (0)
103
104 #define BNX2X_ERROR(fmt, ...) \
105 pr_err("[%s:%d]" fmt, __func__, __LINE__, ##__VA_ARGS__)
106
107
108 /* before we have a dev->name use dev_info() */
109 #define BNX2X_DEV_INFO(fmt, ...) \
110 do { \
111 if (netif_msg_probe(bp)) \
112 dev_info(&bp->pdev->dev, fmt, ##__VA_ARGS__); \
113 } while (0)
114
115 #ifdef BNX2X_STOP_ON_ERROR
116 void bnx2x_int_disable(struct bnx2x *bp);
117 #define bnx2x_panic() \
118 do { \
119 bp->panic = 1; \
120 BNX2X_ERR("driver assert\n"); \
121 bnx2x_int_disable(bp); \
122 bnx2x_panic_dump(bp); \
123 } while (0)
124 #else
125 #define bnx2x_panic() \
126 do { \
127 bp->panic = 1; \
128 BNX2X_ERR("driver assert\n"); \
129 bnx2x_panic_dump(bp); \
130 } while (0)
131 #endif
132
133 #define bnx2x_mc_addr(ha) ((ha)->addr)
134 #define bnx2x_uc_addr(ha) ((ha)->addr)
135
136 #define U64_LO(x) (u32)(((u64)(x)) & 0xffffffff)
137 #define U64_HI(x) (u32)(((u64)(x)) >> 32)
138 #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
139
140
141 #define REG_ADDR(bp, offset) ((bp->regview) + (offset))
142
143 #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset))
144 #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset))
145 #define REG_RD16(bp, offset) readw(REG_ADDR(bp, offset))
146
147 #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset))
148 #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset))
149 #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset))
150
151 #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset)
152 #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val)
153
154 #define REG_RD_DMAE(bp, offset, valp, len32) \
155 do { \
156 bnx2x_read_dmae(bp, offset, len32);\
157 memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \
158 } while (0)
159
160 #define REG_WR_DMAE(bp, offset, valp, len32) \
161 do { \
162 memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \
163 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
164 offset, len32); \
165 } while (0)
166
167 #define REG_WR_DMAE_LEN(bp, offset, valp, len32) \
168 REG_WR_DMAE(bp, offset, valp, len32)
169
170 #define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \
171 do { \
172 memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \
173 bnx2x_write_big_buf_wb(bp, addr, len32); \
174 } while (0)
175
176 #define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \
177 offsetof(struct shmem_region, field))
178 #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field))
179 #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val)
180
181 #define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \
182 offsetof(struct shmem2_region, field))
183 #define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field))
184 #define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val)
185 #define MF_CFG_ADDR(bp, field) (bp->common.mf_cfg_base + \
186 offsetof(struct mf_cfg, field))
187 #define MF2_CFG_ADDR(bp, field) (bp->common.mf2_cfg_base + \
188 offsetof(struct mf2_cfg, field))
189
190 #define MF_CFG_RD(bp, field) REG_RD(bp, MF_CFG_ADDR(bp, field))
191 #define MF_CFG_WR(bp, field, val) REG_WR(bp,\
192 MF_CFG_ADDR(bp, field), (val))
193 #define MF2_CFG_RD(bp, field) REG_RD(bp, MF2_CFG_ADDR(bp, field))
194
195 #define SHMEM2_HAS(bp, field) ((bp)->common.shmem2_base && \
196 (SHMEM2_RD((bp), size) > \
197 offsetof(struct shmem2_region, field)))
198
199 #define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg)
200 #define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val)
201
202 /* SP SB indices */
203
204 /* General SP events - stats query, cfc delete, etc */
205 #define HC_SP_INDEX_ETH_DEF_CONS 3
206
207 /* EQ completions */
208 #define HC_SP_INDEX_EQ_CONS 7
209
210 /* FCoE L2 connection completions */
211 #define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6
212 #define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4
213 /* iSCSI L2 */
214 #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5
215 #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1
216
217 /* Special clients parameters */
218
219 /* SB indices */
220 /* FCoE L2 */
221 #define BNX2X_FCOE_L2_RX_INDEX \
222 (&bp->def_status_blk->sp_sb.\
223 index_values[HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS])
224
225 #define BNX2X_FCOE_L2_TX_INDEX \
226 (&bp->def_status_blk->sp_sb.\
227 index_values[HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS])
228
229 /**
230 * CIDs and CLIDs:
231 * CLIDs below is a CLID for func 0, then the CLID for other
232 * functions will be calculated by the formula:
233 *
234 * FUNC_N_CLID_X = N * NUM_SPECIAL_CLIENTS + FUNC_0_CLID_X
235 *
236 */
237 enum {
238 BNX2X_ISCSI_ETH_CL_ID_IDX,
239 BNX2X_FCOE_ETH_CL_ID_IDX,
240 BNX2X_MAX_CNIC_ETH_CL_ID_IDX,
241 };
242
243 #define BNX2X_CNIC_START_ETH_CID 48
244 enum {
245 /* iSCSI L2 */
246 BNX2X_ISCSI_ETH_CID = BNX2X_CNIC_START_ETH_CID,
247 /* FCoE L2 */
248 BNX2X_FCOE_ETH_CID,
249 };
250
251 /** Additional rings budgeting */
252 #ifdef BCM_CNIC
253 #define CNIC_PRESENT 1
254 #define FCOE_PRESENT 1
255 #else
256 #define CNIC_PRESENT 0
257 #define FCOE_PRESENT 0
258 #endif /* BCM_CNIC */
259 #define NON_ETH_CONTEXT_USE (FCOE_PRESENT)
260
261 #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \
262 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR
263
264 #define SM_RX_ID 0
265 #define SM_TX_ID 1
266
267 /* defines for multiple tx priority indices */
268 #define FIRST_TX_ONLY_COS_INDEX 1
269 #define FIRST_TX_COS_INDEX 0
270
271 /* defines for decodeing the fastpath index and the cos index out of the
272 * transmission queue index
273 */
274 #define MAX_TXQS_PER_COS FP_SB_MAX_E1x
275
276 #define TXQ_TO_FP(txq_index) ((txq_index) % MAX_TXQS_PER_COS)
277 #define TXQ_TO_COS(txq_index) ((txq_index) / MAX_TXQS_PER_COS)
278
279 /* rules for calculating the cids of tx-only connections */
280 #define CID_TO_FP(cid) ((cid) % MAX_TXQS_PER_COS)
281 #define CID_COS_TO_TX_ONLY_CID(cid, cos) (cid + cos * MAX_TXQS_PER_COS)
282
283 /* fp index inside class of service range */
284 #define FP_COS_TO_TXQ(fp, cos) ((fp)->index + cos * MAX_TXQS_PER_COS)
285
286 /*
287 * 0..15 eth cos0
288 * 16..31 eth cos1 if applicable
289 * 32..47 eth cos2 If applicable
290 * fcoe queue follows eth queues (16, 32, 48 depending on cos)
291 */
292 #define MAX_ETH_TXQ_IDX(bp) (MAX_TXQS_PER_COS * (bp)->max_cos)
293 #define FCOE_TXQ_IDX(bp) (MAX_ETH_TXQ_IDX(bp))
294
295 /* fast path */
296 struct sw_rx_bd {
297 struct sk_buff *skb;
298 DEFINE_DMA_UNMAP_ADDR(mapping);
299 };
300
301 struct sw_tx_bd {
302 struct sk_buff *skb;
303 u16 first_bd;
304 u8 flags;
305 /* Set on the first BD descriptor when there is a split BD */
306 #define BNX2X_TSO_SPLIT_BD (1<<0)
307 };
308
309 struct sw_rx_page {
310 struct page *page;
311 DEFINE_DMA_UNMAP_ADDR(mapping);
312 };
313
314 union db_prod {
315 struct doorbell_set_prod data;
316 u32 raw;
317 };
318
319 /* dropless fc FW/HW related params */
320 #define BRB_SIZE(bp) (CHIP_IS_E3(bp) ? 1024 : 512)
321 #define MAX_AGG_QS(bp) (CHIP_IS_E1(bp) ? \
322 ETH_MAX_AGGREGATION_QUEUES_E1 :\
323 ETH_MAX_AGGREGATION_QUEUES_E1H_E2)
324 #define FW_DROP_LEVEL(bp) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(bp))
325 #define FW_PREFETCH_CNT 16
326 #define DROPLESS_FC_HEADROOM 100
327
328 /* MC hsi */
329 #define BCM_PAGE_SHIFT 12
330 #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT)
331 #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1))
332 #define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
333
334 #define PAGES_PER_SGE_SHIFT 0
335 #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT)
336 #define SGE_PAGE_SIZE PAGE_SIZE
337 #define SGE_PAGE_SHIFT PAGE_SHIFT
338 #define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))(addr))
339
340 /* SGE ring related macros */
341 #define NUM_RX_SGE_PAGES 2
342 #define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
343 #define NEXT_PAGE_SGE_DESC_CNT 2
344 #define MAX_RX_SGE_CNT (RX_SGE_CNT - NEXT_PAGE_SGE_DESC_CNT)
345 /* RX_SGE_CNT is promised to be a power of 2 */
346 #define RX_SGE_MASK (RX_SGE_CNT - 1)
347 #define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES)
348 #define MAX_RX_SGE (NUM_RX_SGE - 1)
349 #define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \
350 (MAX_RX_SGE_CNT - 1)) ? \
351 (x) + 1 + NEXT_PAGE_SGE_DESC_CNT : \
352 (x) + 1)
353 #define RX_SGE(x) ((x) & MAX_RX_SGE)
354
355 /*
356 * Number of required SGEs is the sum of two:
357 * 1. Number of possible opened aggregations (next packet for
358 * these aggregations will probably consume SGE immidiatelly)
359 * 2. Rest of BRB blocks divided by 2 (block will consume new SGE only
360 * after placement on BD for new TPA aggregation)
361 *
362 * Takes into account NEXT_PAGE_SGE_DESC_CNT "next" elements on each page
363 */
364 #define NUM_SGE_REQ (MAX_AGG_QS(bp) + \
365 (BRB_SIZE(bp) - MAX_AGG_QS(bp)) / 2)
366 #define NUM_SGE_PG_REQ ((NUM_SGE_REQ + MAX_RX_SGE_CNT - 1) / \
367 MAX_RX_SGE_CNT)
368 #define SGE_TH_LO(bp) (NUM_SGE_REQ + \
369 NUM_SGE_PG_REQ * NEXT_PAGE_SGE_DESC_CNT)
370 #define SGE_TH_HI(bp) (SGE_TH_LO(bp) + DROPLESS_FC_HEADROOM)
371
372 /* Manipulate a bit vector defined as an array of u64 */
373
374 /* Number of bits in one sge_mask array element */
375 #define BIT_VEC64_ELEM_SZ 64
376 #define BIT_VEC64_ELEM_SHIFT 6
377 #define BIT_VEC64_ELEM_MASK ((u64)BIT_VEC64_ELEM_SZ - 1)
378
379
380 #define __BIT_VEC64_SET_BIT(el, bit) \
381 do { \
382 el = ((el) | ((u64)0x1 << (bit))); \
383 } while (0)
384
385 #define __BIT_VEC64_CLEAR_BIT(el, bit) \
386 do { \
387 el = ((el) & (~((u64)0x1 << (bit)))); \
388 } while (0)
389
390
391 #define BIT_VEC64_SET_BIT(vec64, idx) \
392 __BIT_VEC64_SET_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \
393 (idx) & BIT_VEC64_ELEM_MASK)
394
395 #define BIT_VEC64_CLEAR_BIT(vec64, idx) \
396 __BIT_VEC64_CLEAR_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \
397 (idx) & BIT_VEC64_ELEM_MASK)
398
399 #define BIT_VEC64_TEST_BIT(vec64, idx) \
400 (((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT] >> \
401 ((idx) & BIT_VEC64_ELEM_MASK)) & 0x1)
402
403 /* Creates a bitmask of all ones in less significant bits.
404 idx - index of the most significant bit in the created mask */
405 #define BIT_VEC64_ONES_MASK(idx) \
406 (((u64)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1)
407 #define BIT_VEC64_ELEM_ONE_MASK ((u64)(~0))
408
409 /*******************************************************/
410
411
412
413 /* Number of u64 elements in SGE mask array */
414 #define RX_SGE_MASK_LEN ((NUM_RX_SGE_PAGES * RX_SGE_CNT) / \
415 BIT_VEC64_ELEM_SZ)
416 #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1)
417 #define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK)
418
419 union host_hc_status_block {
420 /* pointer to fp status block e1x */
421 struct host_hc_status_block_e1x *e1x_sb;
422 /* pointer to fp status block e2 */
423 struct host_hc_status_block_e2 *e2_sb;
424 };
425
426 struct bnx2x_agg_info {
427 /*
428 * First aggregation buffer is an skb, the following - are pages.
429 * We will preallocate the skbs for each aggregation when
430 * we open the interface and will replace the BD at the consumer
431 * with this one when we receive the TPA_START CQE in order to
432 * keep the Rx BD ring consistent.
433 */
434 struct sw_rx_bd first_buf;
435 u8 tpa_state;
436 #define BNX2X_TPA_START 1
437 #define BNX2X_TPA_STOP 2
438 #define BNX2X_TPA_ERROR 3
439 u8 placement_offset;
440 u16 parsing_flags;
441 u16 vlan_tag;
442 u16 len_on_bd;
443 };
444
445 #define Q_STATS_OFFSET32(stat_name) \
446 (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4)
447
448 struct bnx2x_fp_txdata {
449
450 struct sw_tx_bd *tx_buf_ring;
451
452 union eth_tx_bd_types *tx_desc_ring;
453 dma_addr_t tx_desc_mapping;
454
455 u32 cid;
456
457 union db_prod tx_db;
458
459 u16 tx_pkt_prod;
460 u16 tx_pkt_cons;
461 u16 tx_bd_prod;
462 u16 tx_bd_cons;
463
464 unsigned long tx_pkt;
465
466 __le16 *tx_cons_sb;
467
468 int txq_index;
469 };
470
471 struct bnx2x_fastpath {
472 struct bnx2x *bp; /* parent */
473
474 #define BNX2X_NAPI_WEIGHT 128
475 struct napi_struct napi;
476 union host_hc_status_block status_blk;
477 /* chip independed shortcuts into sb structure */
478 __le16 *sb_index_values;
479 __le16 *sb_running_index;
480 /* chip independed shortcut into rx_prods_offset memory */
481 u32 ustorm_rx_prods_offset;
482
483 u32 rx_buf_size;
484
485 dma_addr_t status_blk_mapping;
486
487 u8 max_cos; /* actual number of active tx coses */
488 struct bnx2x_fp_txdata txdata[BNX2X_MULTI_TX_COS];
489
490 struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */
491 struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */
492
493 struct eth_rx_bd *rx_desc_ring;
494 dma_addr_t rx_desc_mapping;
495
496 union eth_rx_cqe *rx_comp_ring;
497 dma_addr_t rx_comp_mapping;
498
499 /* SGE ring */
500 struct eth_rx_sge *rx_sge_ring;
501 dma_addr_t rx_sge_mapping;
502
503 u64 sge_mask[RX_SGE_MASK_LEN];
504
505 u32 cid;
506
507 __le16 fp_hc_idx;
508
509 u8 index; /* number in fp array */
510 u8 cl_id; /* eth client id */
511 u8 cl_qzone_id;
512 u8 fw_sb_id; /* status block number in FW */
513 u8 igu_sb_id; /* status block number in HW */
514
515 u16 rx_bd_prod;
516 u16 rx_bd_cons;
517 u16 rx_comp_prod;
518 u16 rx_comp_cons;
519 u16 rx_sge_prod;
520 /* The last maximal completed SGE */
521 u16 last_max_sge;
522 __le16 *rx_cons_sb;
523 unsigned long rx_pkt,
524 rx_calls;
525
526 /* TPA related */
527 struct bnx2x_agg_info tpa_info[ETH_MAX_AGGREGATION_QUEUES_E1H_E2];
528 u8 disable_tpa;
529 #ifdef BNX2X_STOP_ON_ERROR
530 u64 tpa_queue_used;
531 #endif
532
533 struct tstorm_per_queue_stats old_tclient;
534 struct ustorm_per_queue_stats old_uclient;
535 struct xstorm_per_queue_stats old_xclient;
536 struct bnx2x_eth_q_stats eth_q_stats;
537
538 /* The size is calculated using the following:
539 sizeof name field from netdev structure +
540 4 ('-Xx-' string) +
541 4 (for the digits and to make it DWORD aligned) */
542 #define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8)
543 char name[FP_NAME_SIZE];
544
545 /* MACs object */
546 struct bnx2x_vlan_mac_obj mac_obj;
547
548 /* Queue State object */
549 struct bnx2x_queue_sp_obj q_obj;
550
551 };
552
553 #define bnx2x_fp(bp, nr, var) (bp->fp[nr].var)
554
555 /* Use 2500 as a mini-jumbo MTU for FCoE */
556 #define BNX2X_FCOE_MINI_JUMBO_MTU 2500
557
558 /* FCoE L2 `fastpath' entry is right after the eth entries */
559 #define FCOE_IDX BNX2X_NUM_ETH_QUEUES(bp)
560 #define bnx2x_fcoe_fp(bp) (&bp->fp[FCOE_IDX])
561 #define bnx2x_fcoe(bp, var) (bnx2x_fcoe_fp(bp)->var)
562 #define bnx2x_fcoe_tx(bp, var) (bnx2x_fcoe_fp(bp)-> \
563 txdata[FIRST_TX_COS_INDEX].var)
564
565
566 #define IS_ETH_FP(fp) (fp->index < \
567 BNX2X_NUM_ETH_QUEUES(fp->bp))
568 #ifdef BCM_CNIC
569 #define IS_FCOE_FP(fp) (fp->index == FCOE_IDX)
570 #define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX)
571 #else
572 #define IS_FCOE_FP(fp) false
573 #define IS_FCOE_IDX(idx) false
574 #endif
575
576
577 /* MC hsi */
578 #define MAX_FETCH_BD 13 /* HW max BDs per packet */
579 #define RX_COPY_THRESH 92
580
581 #define NUM_TX_RINGS 16
582 #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types))
583 #define NEXT_PAGE_TX_DESC_CNT 1
584 #define MAX_TX_DESC_CNT (TX_DESC_CNT - NEXT_PAGE_TX_DESC_CNT)
585 #define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS)
586 #define MAX_TX_BD (NUM_TX_BD - 1)
587 #define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
588 #define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \
589 (MAX_TX_DESC_CNT - 1)) ? \
590 (x) + 1 + NEXT_PAGE_TX_DESC_CNT : \
591 (x) + 1)
592 #define TX_BD(x) ((x) & MAX_TX_BD)
593 #define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT)
594
595 /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */
596 #define NUM_RX_RINGS 8
597 #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
598 #define NEXT_PAGE_RX_DESC_CNT 2
599 #define MAX_RX_DESC_CNT (RX_DESC_CNT - NEXT_PAGE_RX_DESC_CNT)
600 #define RX_DESC_MASK (RX_DESC_CNT - 1)
601 #define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS)
602 #define MAX_RX_BD (NUM_RX_BD - 1)
603 #define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
604
605 /* dropless fc calculations for BDs
606 *
607 * Number of BDs should as number of buffers in BRB:
608 * Low threshold takes into account NEXT_PAGE_RX_DESC_CNT
609 * "next" elements on each page
610 */
611 #define NUM_BD_REQ BRB_SIZE(bp)
612 #define NUM_BD_PG_REQ ((NUM_BD_REQ + MAX_RX_DESC_CNT - 1) / \
613 MAX_RX_DESC_CNT)
614 #define BD_TH_LO(bp) (NUM_BD_REQ + \
615 NUM_BD_PG_REQ * NEXT_PAGE_RX_DESC_CNT + \
616 FW_DROP_LEVEL(bp))
617 #define BD_TH_HI(bp) (BD_TH_LO(bp) + DROPLESS_FC_HEADROOM)
618
619 #define MIN_RX_AVAIL ((bp)->dropless_fc ? BD_TH_HI(bp) + 128 : 128)
620
621 #define MIN_RX_SIZE_TPA_HW (CHIP_IS_E1(bp) ? \
622 ETH_MIN_RX_CQES_WITH_TPA_E1 : \
623 ETH_MIN_RX_CQES_WITH_TPA_E1H_E2)
624 #define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA
625 #define MIN_RX_SIZE_TPA (max_t(u32, MIN_RX_SIZE_TPA_HW, MIN_RX_AVAIL))
626 #define MIN_RX_SIZE_NONTPA (max_t(u32, MIN_RX_SIZE_NONTPA_HW,\
627 MIN_RX_AVAIL))
628
629 #define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \
630 (MAX_RX_DESC_CNT - 1)) ? \
631 (x) + 1 + NEXT_PAGE_RX_DESC_CNT : \
632 (x) + 1)
633 #define RX_BD(x) ((x) & MAX_RX_BD)
634
635 /*
636 * As long as CQE is X times bigger than BD entry we have to allocate X times
637 * more pages for CQ ring in order to keep it balanced with BD ring
638 */
639 #define CQE_BD_REL (sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd))
640 #define NUM_RCQ_RINGS (NUM_RX_RINGS * CQE_BD_REL)
641 #define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
642 #define NEXT_PAGE_RCQ_DESC_CNT 1
643 #define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - NEXT_PAGE_RCQ_DESC_CNT)
644 #define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS)
645 #define MAX_RCQ_BD (NUM_RCQ_BD - 1)
646 #define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
647 #define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \
648 (MAX_RCQ_DESC_CNT - 1)) ? \
649 (x) + 1 + NEXT_PAGE_RCQ_DESC_CNT : \
650 (x) + 1)
651 #define RCQ_BD(x) ((x) & MAX_RCQ_BD)
652
653 /* dropless fc calculations for RCQs
654 *
655 * Number of RCQs should be as number of buffers in BRB:
656 * Low threshold takes into account NEXT_PAGE_RCQ_DESC_CNT
657 * "next" elements on each page
658 */
659 #define NUM_RCQ_REQ BRB_SIZE(bp)
660 #define NUM_RCQ_PG_REQ ((NUM_BD_REQ + MAX_RCQ_DESC_CNT - 1) / \
661 MAX_RCQ_DESC_CNT)
662 #define RCQ_TH_LO(bp) (NUM_RCQ_REQ + \
663 NUM_RCQ_PG_REQ * NEXT_PAGE_RCQ_DESC_CNT + \
664 FW_DROP_LEVEL(bp))
665 #define RCQ_TH_HI(bp) (RCQ_TH_LO(bp) + DROPLESS_FC_HEADROOM)
666
667
668 /* This is needed for determining of last_max */
669 #define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b))
670 #define SUB_S32(a, b) (s32)((s32)(a) - (s32)(b))
671
672
673 #define BNX2X_SWCID_SHIFT 17
674 #define BNX2X_SWCID_MASK ((0x1 << BNX2X_SWCID_SHIFT) - 1)
675
676 /* used on a CID received from the HW */
677 #define SW_CID(x) (le32_to_cpu(x) & BNX2X_SWCID_MASK)
678 #define CQE_CMD(x) (le32_to_cpu(x) >> \
679 COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
680
681 #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \
682 le32_to_cpu((bd)->addr_lo))
683 #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes))
684
685 #define BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */
686 #define BNX2X_DB_SHIFT 7 /* 128 bytes*/
687 #if (BNX2X_DB_SHIFT < BNX2X_DB_MIN_SHIFT)
688 #error "Min DB doorbell stride is 8"
689 #endif
690 #define DPM_TRIGER_TYPE 0x40
691 #define DOORBELL(bp, cid, val) \
692 do { \
693 writel((u32)(val), bp->doorbells + (bp->db_size * (cid)) + \
694 DPM_TRIGER_TYPE); \
695 } while (0)
696
697
698 /* TX CSUM helpers */
699 #define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \
700 skb->csum_offset)
701 #define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \
702 skb->csum_offset))
703
704 #define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff)
705
706 #define XMIT_PLAIN 0
707 #define XMIT_CSUM_V4 0x1
708 #define XMIT_CSUM_V6 0x2
709 #define XMIT_CSUM_TCP 0x4
710 #define XMIT_GSO_V4 0x8
711 #define XMIT_GSO_V6 0x10
712
713 #define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6)
714 #define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6)
715
716
717 /* stuff added to make the code fit 80Col */
718 #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
719 #define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG)
720 #define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG)
721 #define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD)
722 #define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH)
723
724 #define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG
725
726 #define BNX2X_IP_CSUM_ERR(cqe) \
727 (!((cqe)->fast_path_cqe.status_flags & \
728 ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG) && \
729 ((cqe)->fast_path_cqe.type_error_flags & \
730 ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG))
731
732 #define BNX2X_L4_CSUM_ERR(cqe) \
733 (!((cqe)->fast_path_cqe.status_flags & \
734 ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG) && \
735 ((cqe)->fast_path_cqe.type_error_flags & \
736 ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG))
737
738 #define BNX2X_RX_CSUM_OK(cqe) \
739 (!(BNX2X_L4_CSUM_ERR(cqe) || BNX2X_IP_CSUM_ERR(cqe)))
740
741 #define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \
742 (((le16_to_cpu(flags) & \
743 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \
744 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \
745 == PRS_FLAG_OVERETH_IPV4)
746 #define BNX2X_RX_SUM_FIX(cqe) \
747 BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags)
748
749
750 #define FP_USB_FUNC_OFF \
751 offsetof(struct cstorm_status_block_u, func)
752 #define FP_CSB_FUNC_OFF \
753 offsetof(struct cstorm_status_block_c, func)
754
755 #define HC_INDEX_ETH_RX_CQ_CONS 1
756
757 #define HC_INDEX_OOO_TX_CQ_CONS 4
758
759 #define HC_INDEX_ETH_TX_CQ_CONS_COS0 5
760
761 #define HC_INDEX_ETH_TX_CQ_CONS_COS1 6
762
763 #define HC_INDEX_ETH_TX_CQ_CONS_COS2 7
764
765 #define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0
766
767 #define BNX2X_RX_SB_INDEX \
768 (&fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS])
769
770 #define BNX2X_TX_SB_INDEX_BASE BNX2X_TX_SB_INDEX_COS0
771
772 #define BNX2X_TX_SB_INDEX_COS0 \
773 (&fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0])
774
775 /* end of fast path */
776
777 /* common */
778
779 struct bnx2x_common {
780
781 u32 chip_id;
782 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
783 #define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0)
784
785 #define CHIP_NUM(bp) (bp->common.chip_id >> 16)
786 #define CHIP_NUM_57710 0x164e
787 #define CHIP_NUM_57711 0x164f
788 #define CHIP_NUM_57711E 0x1650
789 #define CHIP_NUM_57712 0x1662
790 #define CHIP_NUM_57712_MF 0x1663
791 #define CHIP_NUM_57713 0x1651
792 #define CHIP_NUM_57713E 0x1652
793 #define CHIP_NUM_57800 0x168a
794 #define CHIP_NUM_57800_MF 0x16a5
795 #define CHIP_NUM_57810 0x168e
796 #define CHIP_NUM_57810_MF 0x16ae
797 #define CHIP_NUM_57840 0x168d
798 #define CHIP_NUM_57840_MF 0x16ab
799 #define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710)
800 #define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711)
801 #define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E)
802 #define CHIP_IS_57712(bp) (CHIP_NUM(bp) == CHIP_NUM_57712)
803 #define CHIP_IS_57712_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_MF)
804 #define CHIP_IS_57800(bp) (CHIP_NUM(bp) == CHIP_NUM_57800)
805 #define CHIP_IS_57800_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_MF)
806 #define CHIP_IS_57810(bp) (CHIP_NUM(bp) == CHIP_NUM_57810)
807 #define CHIP_IS_57810_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_MF)
808 #define CHIP_IS_57840(bp) (CHIP_NUM(bp) == CHIP_NUM_57840)
809 #define CHIP_IS_57840_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57840_MF)
810 #define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \
811 CHIP_IS_57711E(bp))
812 #define CHIP_IS_E2(bp) (CHIP_IS_57712(bp) || \
813 CHIP_IS_57712_MF(bp))
814 #define CHIP_IS_E3(bp) (CHIP_IS_57800(bp) || \
815 CHIP_IS_57800_MF(bp) || \
816 CHIP_IS_57810(bp) || \
817 CHIP_IS_57810_MF(bp) || \
818 CHIP_IS_57840(bp) || \
819 CHIP_IS_57840_MF(bp))
820 #define CHIP_IS_E1x(bp) (CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp)))
821 #define USES_WARPCORE(bp) (CHIP_IS_E3(bp))
822 #define IS_E1H_OFFSET (!CHIP_IS_E1(bp))
823
824 #define CHIP_REV_SHIFT 12
825 #define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT)
826 #define CHIP_REV_VAL(bp) (bp->common.chip_id & CHIP_REV_MASK)
827 #define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT)
828 #define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT)
829 /* assume maximum 5 revisions */
830 #define CHIP_REV_IS_SLOW(bp) (CHIP_REV_VAL(bp) > 0x00005000)
831 /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */
832 #define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \
833 !(CHIP_REV_VAL(bp) & 0x00001000))
834 /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */
835 #define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \
836 (CHIP_REV_VAL(bp) & 0x00001000))
837
838 #define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \
839 ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1))
840
841 #define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0)
842 #define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f)
843 #define CHIP_REV_SIM(bp) (((CHIP_REV_MASK - CHIP_REV_VAL(bp)) >>\
844 (CHIP_REV_SHIFT + 1)) \
845 << CHIP_REV_SHIFT)
846 #define CHIP_REV(bp) (CHIP_REV_IS_SLOW(bp) ? \
847 CHIP_REV_SIM(bp) :\
848 CHIP_REV_VAL(bp))
849 #define CHIP_IS_E3B0(bp) (CHIP_IS_E3(bp) && \
850 (CHIP_REV(bp) == CHIP_REV_Bx))
851 #define CHIP_IS_E3A0(bp) (CHIP_IS_E3(bp) && \
852 (CHIP_REV(bp) == CHIP_REV_Ax))
853
854 int flash_size;
855 #define BNX2X_NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */
856 #define BNX2X_NVRAM_TIMEOUT_COUNT 30000
857 #define BNX2X_NVRAM_PAGE_SIZE 256
858
859 u32 shmem_base;
860 u32 shmem2_base;
861 u32 mf_cfg_base;
862 u32 mf2_cfg_base;
863
864 u32 hw_config;
865
866 u32 bc_ver;
867
868 u8 int_block;
869 #define INT_BLOCK_HC 0
870 #define INT_BLOCK_IGU 1
871 #define INT_BLOCK_MODE_NORMAL 0
872 #define INT_BLOCK_MODE_BW_COMP 2
873 #define CHIP_INT_MODE_IS_NBC(bp) \
874 (!CHIP_IS_E1x(bp) && \
875 !((bp)->common.int_block & INT_BLOCK_MODE_BW_COMP))
876 #define CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp))
877
878 u8 chip_port_mode;
879 #define CHIP_4_PORT_MODE 0x0
880 #define CHIP_2_PORT_MODE 0x1
881 #define CHIP_PORT_MODE_NONE 0x2
882 #define CHIP_MODE(bp) (bp->common.chip_port_mode)
883 #define CHIP_MODE_IS_4_PORT(bp) (CHIP_MODE(bp) == CHIP_4_PORT_MODE)
884 };
885
886 /* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */
887 #define BNX2X_IGU_STAS_MSG_VF_CNT 64
888 #define BNX2X_IGU_STAS_MSG_PF_CNT 4
889
890 /* end of common */
891
892 /* port */
893
894 struct bnx2x_port {
895 u32 pmf;
896
897 u32 link_config[LINK_CONFIG_SIZE];
898
899 u32 supported[LINK_CONFIG_SIZE];
900 /* link settings - missing defines */
901 #define SUPPORTED_2500baseX_Full (1 << 15)
902
903 u32 advertising[LINK_CONFIG_SIZE];
904 /* link settings - missing defines */
905 #define ADVERTISED_2500baseX_Full (1 << 15)
906
907 u32 phy_addr;
908
909 /* used to synchronize phy accesses */
910 struct mutex phy_mutex;
911 int need_hw_lock;
912
913 u32 port_stx;
914
915 struct nig_stats old_nig_stats;
916 };
917
918 /* end of port */
919
920 #define STATS_OFFSET32(stat_name) \
921 (offsetof(struct bnx2x_eth_stats, stat_name) / 4)
922
923 /* slow path */
924
925 /* slow path work-queue */
926 extern struct workqueue_struct *bnx2x_wq;
927
928 #define BNX2X_MAX_NUM_OF_VFS 64
929 #define BNX2X_VF_ID_INVALID 0xFF
930
931 /*
932 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is
933 * control by the number of fast-path status blocks supported by the
934 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default
935 * status block represents an independent interrupts context that can
936 * serve a regular L2 networking queue. However special L2 queues such
937 * as the FCoE queue do not require a FP-SB and other components like
938 * the CNIC may consume FP-SB reducing the number of possible L2 queues
939 *
940 * If the maximum number of FP-SB available is X then:
941 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of
942 * regular L2 queues is Y=X-1
943 * b. in MF mode the actual number of L2 queues is Y= (X-1/MF_factor)
944 * c. If the FCoE L2 queue is supported the actual number of L2 queues
945 * is Y+1
946 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for
947 * slow-path interrupts) or Y+2 if CNIC is supported (one additional
948 * FP interrupt context for the CNIC).
949 * e. The number of HW context (CID count) is always X or X+1 if FCoE
950 * L2 queue is supported. the cid for the FCoE L2 queue is always X.
951 */
952
953 /* fast-path interrupt contexts E1x */
954 #define FP_SB_MAX_E1x 16
955 /* fast-path interrupt contexts E2 */
956 #define FP_SB_MAX_E2 HC_SB_MAX_SB_E2
957
958 union cdu_context {
959 struct eth_context eth;
960 char pad[1024];
961 };
962
963 /* CDU host DB constants */
964 #define CDU_ILT_PAGE_SZ_HW 3
965 #define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 64K */
966 #define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context))
967
968 #ifdef BCM_CNIC
969 #define CNIC_ISCSI_CID_MAX 256
970 #define CNIC_FCOE_CID_MAX 2048
971 #define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX)
972 #define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS)
973 #endif
974
975 #define QM_ILT_PAGE_SZ_HW 0
976 #define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */
977 #define QM_CID_ROUND 1024
978
979 #ifdef BCM_CNIC
980 /* TM (timers) host DB constants */
981 #define TM_ILT_PAGE_SZ_HW 0
982 #define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */
983 /* #define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */
984 #define TM_CONN_NUM 1024
985 #define TM_ILT_SZ (8 * TM_CONN_NUM)
986 #define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ)
987
988 /* SRC (Searcher) host DB constants */
989 #define SRC_ILT_PAGE_SZ_HW 0
990 #define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */
991 #define SRC_HASH_BITS 10
992 #define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */
993 #define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM)
994 #define SRC_T2_SZ SRC_ILT_SZ
995 #define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ)
996
997 #endif
998
999 #define MAX_DMAE_C 8
1000
1001 /* DMA memory not used in fastpath */
1002 struct bnx2x_slowpath {
1003 union {
1004 struct mac_configuration_cmd e1x;
1005 struct eth_classify_rules_ramrod_data e2;
1006 } mac_rdata;
1007
1008
1009 union {
1010 struct tstorm_eth_mac_filter_config e1x;
1011 struct eth_filter_rules_ramrod_data e2;
1012 } rx_mode_rdata;
1013
1014 union {
1015 struct mac_configuration_cmd e1;
1016 struct eth_multicast_rules_ramrod_data e2;
1017 } mcast_rdata;
1018
1019 struct eth_rss_update_ramrod_data rss_rdata;
1020
1021 /* Queue State related ramrods are always sent under rtnl_lock */
1022 union {
1023 struct client_init_ramrod_data init_data;
1024 struct client_update_ramrod_data update_data;
1025 } q_rdata;
1026
1027 union {
1028 struct function_start_data func_start;
1029 /* pfc configuration for DCBX ramrod */
1030 struct flow_control_configuration pfc_config;
1031 } func_rdata;
1032
1033 /* used by dmae command executer */
1034 struct dmae_command dmae[MAX_DMAE_C];
1035
1036 u32 stats_comp;
1037 union mac_stats mac_stats;
1038 struct nig_stats nig_stats;
1039 struct host_port_stats port_stats;
1040 struct host_func_stats func_stats;
1041 struct host_func_stats func_stats_base;
1042
1043 u32 wb_comp;
1044 u32 wb_data[4];
1045 };
1046
1047 #define bnx2x_sp(bp, var) (&bp->slowpath->var)
1048 #define bnx2x_sp_mapping(bp, var) \
1049 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))
1050
1051
1052 /* attn group wiring */
1053 #define MAX_DYNAMIC_ATTN_GRPS 8
1054
1055 struct attn_route {
1056 u32 sig[5];
1057 };
1058
1059 struct iro {
1060 u32 base;
1061 u16 m1;
1062 u16 m2;
1063 u16 m3;
1064 u16 size;
1065 };
1066
1067 struct hw_context {
1068 union cdu_context *vcxt;
1069 dma_addr_t cxt_mapping;
1070 size_t size;
1071 };
1072
1073 /* forward */
1074 struct bnx2x_ilt;
1075
1076
1077 enum bnx2x_recovery_state {
1078 BNX2X_RECOVERY_DONE,
1079 BNX2X_RECOVERY_INIT,
1080 BNX2X_RECOVERY_WAIT,
1081 BNX2X_RECOVERY_FAILED
1082 };
1083
1084 /*
1085 * Event queue (EQ or event ring) MC hsi
1086 * NUM_EQ_PAGES and EQ_DESC_CNT_PAGE must be power of 2
1087 */
1088 #define NUM_EQ_PAGES 1
1089 #define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem))
1090 #define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1)
1091 #define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES)
1092 #define EQ_DESC_MASK (NUM_EQ_DESC - 1)
1093 #define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2)
1094
1095 /* depends on EQ_DESC_CNT_PAGE being a power of 2 */
1096 #define NEXT_EQ_IDX(x) ((((x) & EQ_DESC_MAX_PAGE) == \
1097 (EQ_DESC_MAX_PAGE - 1)) ? (x) + 2 : (x) + 1)
1098
1099 /* depends on the above and on NUM_EQ_PAGES being a power of 2 */
1100 #define EQ_DESC(x) ((x) & EQ_DESC_MASK)
1101
1102 #define BNX2X_EQ_INDEX \
1103 (&bp->def_status_blk->sp_sb.\
1104 index_values[HC_SP_INDEX_EQ_CONS])
1105
1106 /* This is a data that will be used to create a link report message.
1107 * We will keep the data used for the last link report in order
1108 * to prevent reporting the same link parameters twice.
1109 */
1110 struct bnx2x_link_report_data {
1111 u16 line_speed; /* Effective line speed */
1112 unsigned long link_report_flags;/* BNX2X_LINK_REPORT_XXX flags */
1113 };
1114
1115 enum {
1116 BNX2X_LINK_REPORT_FD, /* Full DUPLEX */
1117 BNX2X_LINK_REPORT_LINK_DOWN,
1118 BNX2X_LINK_REPORT_RX_FC_ON,
1119 BNX2X_LINK_REPORT_TX_FC_ON,
1120 };
1121
1122 enum {
1123 BNX2X_PORT_QUERY_IDX,
1124 BNX2X_PF_QUERY_IDX,
1125 BNX2X_FIRST_QUEUE_QUERY_IDX,
1126 };
1127
1128 struct bnx2x_fw_stats_req {
1129 struct stats_query_header hdr;
1130 struct stats_query_entry query[STATS_QUERY_CMD_COUNT];
1131 };
1132
1133 struct bnx2x_fw_stats_data {
1134 struct stats_counter storm_counters;
1135 struct per_port_stats port;
1136 struct per_pf_stats pf;
1137 struct per_queue_stats queue_stats[1];
1138 };
1139
1140 /* Public slow path states */
1141 enum {
1142 BNX2X_SP_RTNL_SETUP_TC,
1143 BNX2X_SP_RTNL_TX_TIMEOUT,
1144 };
1145
1146
1147 struct bnx2x {
1148 /* Fields used in the tx and intr/napi performance paths
1149 * are grouped together in the beginning of the structure
1150 */
1151 struct bnx2x_fastpath *fp;
1152 void __iomem *regview;
1153 void __iomem *doorbells;
1154 u16 db_size;
1155
1156 u8 pf_num; /* absolute PF number */
1157 u8 pfid; /* per-path PF number */
1158 int base_fw_ndsb; /**/
1159 #define BP_PATH(bp) (CHIP_IS_E1x(bp) ? 0 : (bp->pf_num & 1))
1160 #define BP_PORT(bp) (bp->pfid & 1)
1161 #define BP_FUNC(bp) (bp->pfid)
1162 #define BP_ABS_FUNC(bp) (bp->pf_num)
1163 #define BP_VN(bp) ((bp)->pfid >> 1)
1164 #define BP_MAX_VN_NUM(bp) (CHIP_MODE_IS_4_PORT(bp) ? 2 : 4)
1165 #define BP_L_ID(bp) (BP_VN(bp) << 2)
1166 #define BP_FW_MB_IDX_VN(bp, vn) (BP_PORT(bp) +\
1167 (vn) * ((CHIP_IS_E1x(bp) || (CHIP_MODE_IS_4_PORT(bp))) ? 2 : 1))
1168 #define BP_FW_MB_IDX(bp) BP_FW_MB_IDX_VN(bp, BP_VN(bp))
1169
1170 struct net_device *dev;
1171 struct pci_dev *pdev;
1172
1173 const struct iro *iro_arr;
1174 #define IRO (bp->iro_arr)
1175
1176 enum bnx2x_recovery_state recovery_state;
1177 int is_leader;
1178 struct msix_entry *msix_table;
1179
1180 int tx_ring_size;
1181
1182 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
1183 #define ETH_OVREHEAD (ETH_HLEN + 8 + 8)
1184 #define ETH_MIN_PACKET_SIZE 60
1185 #define ETH_MAX_PACKET_SIZE 1500
1186 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
1187
1188 /* Max supported alignment is 256 (8 shift) */
1189 #define BNX2X_RX_ALIGN_SHIFT ((L1_CACHE_SHIFT < 8) ? \
1190 L1_CACHE_SHIFT : 8)
1191 /* FW use 2 Cache lines Alignment for start packet and size */
1192 #define BNX2X_FW_RX_ALIGN (2 << BNX2X_RX_ALIGN_SHIFT)
1193 #define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5)
1194
1195 struct host_sp_status_block *def_status_blk;
1196 #define DEF_SB_IGU_ID 16
1197 #define DEF_SB_ID HC_SP_SB_ID
1198 __le16 def_idx;
1199 __le16 def_att_idx;
1200 u32 attn_state;
1201 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
1202
1203 /* slow path ring */
1204 struct eth_spe *spq;
1205 dma_addr_t spq_mapping;
1206 u16 spq_prod_idx;
1207 struct eth_spe *spq_prod_bd;
1208 struct eth_spe *spq_last_bd;
1209 __le16 *dsb_sp_prod;
1210 atomic_t cq_spq_left; /* ETH_XXX ramrods credit */
1211 /* used to synchronize spq accesses */
1212 spinlock_t spq_lock;
1213
1214 /* event queue */
1215 union event_ring_elem *eq_ring;
1216 dma_addr_t eq_mapping;
1217 u16 eq_prod;
1218 u16 eq_cons;
1219 __le16 *eq_cons_sb;
1220 atomic_t eq_spq_left; /* COMMON_XXX ramrods credit */
1221
1222
1223
1224 /* Counter for marking that there is a STAT_QUERY ramrod pending */
1225 u16 stats_pending;
1226 /* Counter for completed statistics ramrods */
1227 u16 stats_comp;
1228
1229 /* End of fields used in the performance code paths */
1230
1231 int panic;
1232 int msg_enable;
1233
1234 u32 flags;
1235 #define PCIX_FLAG (1 << 0)
1236 #define PCI_32BIT_FLAG (1 << 1)
1237 #define ONE_PORT_FLAG (1 << 2)
1238 #define NO_WOL_FLAG (1 << 3)
1239 #define USING_DAC_FLAG (1 << 4)
1240 #define USING_MSIX_FLAG (1 << 5)
1241 #define USING_MSI_FLAG (1 << 6)
1242 #define DISABLE_MSI_FLAG (1 << 7)
1243 #define TPA_ENABLE_FLAG (1 << 8)
1244 #define NO_MCP_FLAG (1 << 9)
1245
1246 #define BP_NOMCP(bp) (bp->flags & NO_MCP_FLAG)
1247 #define MF_FUNC_DIS (1 << 11)
1248 #define OWN_CNIC_IRQ (1 << 12)
1249 #define NO_ISCSI_OOO_FLAG (1 << 13)
1250 #define NO_ISCSI_FLAG (1 << 14)
1251 #define NO_FCOE_FLAG (1 << 15)
1252
1253 #define NO_ISCSI(bp) ((bp)->flags & NO_ISCSI_FLAG)
1254 #define NO_ISCSI_OOO(bp) ((bp)->flags & NO_ISCSI_OOO_FLAG)
1255 #define NO_FCOE(bp) ((bp)->flags & NO_FCOE_FLAG)
1256
1257 int pm_cap;
1258 int mrrs;
1259
1260 struct delayed_work sp_task;
1261 struct delayed_work sp_rtnl_task;
1262
1263 struct delayed_work period_task;
1264 struct timer_list timer;
1265 int current_interval;
1266
1267 u16 fw_seq;
1268 u16 fw_drv_pulse_wr_seq;
1269 u32 func_stx;
1270
1271 struct link_params link_params;
1272 struct link_vars link_vars;
1273 u32 link_cnt;
1274 struct bnx2x_link_report_data last_reported_link;
1275
1276 struct mdio_if_info mdio;
1277
1278 struct bnx2x_common common;
1279 struct bnx2x_port port;
1280
1281 struct cmng_struct_per_port cmng;
1282 u32 vn_weight_sum;
1283 u32 mf_config[E1HVN_MAX];
1284 u32 mf2_config[E2_FUNC_MAX];
1285 u32 path_has_ovlan; /* E3 */
1286 u16 mf_ov;
1287 u8 mf_mode;
1288 #define IS_MF(bp) (bp->mf_mode != 0)
1289 #define IS_MF_SI(bp) (bp->mf_mode == MULTI_FUNCTION_SI)
1290 #define IS_MF_SD(bp) (bp->mf_mode == MULTI_FUNCTION_SD)
1291
1292 u8 wol;
1293
1294 int rx_ring_size;
1295
1296 u16 tx_quick_cons_trip_int;
1297 u16 tx_quick_cons_trip;
1298 u16 tx_ticks_int;
1299 u16 tx_ticks;
1300
1301 u16 rx_quick_cons_trip_int;
1302 u16 rx_quick_cons_trip;
1303 u16 rx_ticks_int;
1304 u16 rx_ticks;
1305 /* Maximal coalescing timeout in us */
1306 #define BNX2X_MAX_COALESCE_TOUT (0xf0*12)
1307
1308 u32 lin_cnt;
1309
1310 u16 state;
1311 #define BNX2X_STATE_CLOSED 0
1312 #define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000
1313 #define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000
1314 #define BNX2X_STATE_OPEN 0x3000
1315 #define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000
1316 #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
1317
1318 #define BNX2X_STATE_DIAG 0xe000
1319 #define BNX2X_STATE_ERROR 0xf000
1320
1321 int multi_mode;
1322 #define BNX2X_MAX_PRIORITY 8
1323 #define BNX2X_MAX_ENTRIES_PER_PRI 16
1324 #define BNX2X_MAX_COS 3
1325 #define BNX2X_MAX_TX_COS 2
1326 int num_queues;
1327 int disable_tpa;
1328
1329 u32 rx_mode;
1330 #define BNX2X_RX_MODE_NONE 0
1331 #define BNX2X_RX_MODE_NORMAL 1
1332 #define BNX2X_RX_MODE_ALLMULTI 2
1333 #define BNX2X_RX_MODE_PROMISC 3
1334 #define BNX2X_MAX_MULTICAST 64
1335
1336 u8 igu_dsb_id;
1337 u8 igu_base_sb;
1338 u8 igu_sb_cnt;
1339 dma_addr_t def_status_blk_mapping;
1340
1341 struct bnx2x_slowpath *slowpath;
1342 dma_addr_t slowpath_mapping;
1343
1344 /* Total number of FW statistics requests */
1345 u8 fw_stats_num;
1346
1347 /*
1348 * This is a memory buffer that will contain both statistics
1349 * ramrod request and data.
1350 */
1351 void *fw_stats;
1352 dma_addr_t fw_stats_mapping;
1353
1354 /*
1355 * FW statistics request shortcut (points at the
1356 * beginning of fw_stats buffer).
1357 */
1358 struct bnx2x_fw_stats_req *fw_stats_req;
1359 dma_addr_t fw_stats_req_mapping;
1360 int fw_stats_req_sz;
1361
1362 /*
1363 * FW statistics data shortcut (points at the begining of
1364 * fw_stats buffer + fw_stats_req_sz).
1365 */
1366 struct bnx2x_fw_stats_data *fw_stats_data;
1367 dma_addr_t fw_stats_data_mapping;
1368 int fw_stats_data_sz;
1369
1370 struct hw_context context;
1371
1372 struct bnx2x_ilt *ilt;
1373 #define BP_ILT(bp) ((bp)->ilt)
1374 #define ILT_MAX_LINES 256
1375 /*
1376 * Maximum supported number of RSS queues: number of IGU SBs minus one that goes
1377 * to CNIC.
1378 */
1379 #define BNX2X_MAX_RSS_COUNT(bp) ((bp)->igu_sb_cnt - CNIC_PRESENT)
1380
1381 /*
1382 * Maximum CID count that might be required by the bnx2x:
1383 * Max Tss * Max_Tx_Multi_Cos + CNIC L2 Clients (FCoE and iSCSI related)
1384 */
1385 #define BNX2X_L2_CID_COUNT(bp) (MAX_TXQS_PER_COS * BNX2X_MULTI_TX_COS +\
1386 NON_ETH_CONTEXT_USE + CNIC_PRESENT)
1387 #define L2_ILT_LINES(bp) (DIV_ROUND_UP(BNX2X_L2_CID_COUNT(bp),\
1388 ILT_PAGE_CIDS))
1389 #define BNX2X_DB_SIZE(bp) (BNX2X_L2_CID_COUNT(bp) * (1 << BNX2X_DB_SHIFT))
1390
1391 int qm_cid_count;
1392
1393 int dropless_fc;
1394
1395 #ifdef BCM_CNIC
1396 u32 cnic_flags;
1397 #define BNX2X_CNIC_FLAG_MAC_SET 1
1398 void *t2;
1399 dma_addr_t t2_mapping;
1400 struct cnic_ops __rcu *cnic_ops;
1401 void *cnic_data;
1402 u32 cnic_tag;
1403 struct cnic_eth_dev cnic_eth_dev;
1404 union host_hc_status_block cnic_sb;
1405 dma_addr_t cnic_sb_mapping;
1406 struct eth_spe *cnic_kwq;
1407 struct eth_spe *cnic_kwq_prod;
1408 struct eth_spe *cnic_kwq_cons;
1409 struct eth_spe *cnic_kwq_last;
1410 u16 cnic_kwq_pending;
1411 u16 cnic_spq_pending;
1412 u8 fip_mac[ETH_ALEN];
1413 struct mutex cnic_mutex;
1414 struct bnx2x_vlan_mac_obj iscsi_l2_mac_obj;
1415
1416 /* Start index of the "special" (CNIC related) L2 cleints */
1417 u8 cnic_base_cl_id;
1418 #endif
1419
1420 int dmae_ready;
1421 /* used to synchronize dmae accesses */
1422 spinlock_t dmae_lock;
1423
1424 /* used to protect the FW mail box */
1425 struct mutex fw_mb_mutex;
1426
1427 /* used to synchronize stats collecting */
1428 int stats_state;
1429
1430 /* used for synchronization of concurrent threads statistics handling */
1431 spinlock_t stats_lock;
1432
1433 /* used by dmae command loader */
1434 struct dmae_command stats_dmae;
1435 int executer_idx;
1436
1437 u16 stats_counter;
1438 struct bnx2x_eth_stats eth_stats;
1439
1440 struct z_stream_s *strm;
1441 void *gunzip_buf;
1442 dma_addr_t gunzip_mapping;
1443 int gunzip_outlen;
1444 #define FW_BUF_SIZE 0x8000
1445 #define GUNZIP_BUF(bp) (bp->gunzip_buf)
1446 #define GUNZIP_PHYS(bp) (bp->gunzip_mapping)
1447 #define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen)
1448
1449 struct raw_op *init_ops;
1450 /* Init blocks offsets inside init_ops */
1451 u16 *init_ops_offsets;
1452 /* Data blob - has 32 bit granularity */
1453 u32 *init_data;
1454 u32 init_mode_flags;
1455 #define INIT_MODE_FLAGS(bp) (bp->init_mode_flags)
1456 /* Zipped PRAM blobs - raw data */
1457 const u8 *tsem_int_table_data;
1458 const u8 *tsem_pram_data;
1459 const u8 *usem_int_table_data;
1460 const u8 *usem_pram_data;
1461 const u8 *xsem_int_table_data;
1462 const u8 *xsem_pram_data;
1463 const u8 *csem_int_table_data;
1464 const u8 *csem_pram_data;
1465 #define INIT_OPS(bp) (bp->init_ops)
1466 #define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets)
1467 #define INIT_DATA(bp) (bp->init_data)
1468 #define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data)
1469 #define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data)
1470 #define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data)
1471 #define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data)
1472 #define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data)
1473 #define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data)
1474 #define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data)
1475 #define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data)
1476
1477 #define PHY_FW_VER_LEN 20
1478 char fw_ver[32];
1479 const struct firmware *firmware;
1480
1481 /* DCB support on/off */
1482 u16 dcb_state;
1483 #define BNX2X_DCB_STATE_OFF 0
1484 #define BNX2X_DCB_STATE_ON 1
1485
1486 /* DCBX engine mode */
1487 int dcbx_enabled;
1488 #define BNX2X_DCBX_ENABLED_OFF 0
1489 #define BNX2X_DCBX_ENABLED_ON_NEG_OFF 1
1490 #define BNX2X_DCBX_ENABLED_ON_NEG_ON 2
1491 #define BNX2X_DCBX_ENABLED_INVALID (-1)
1492
1493 bool dcbx_mode_uset;
1494
1495 struct bnx2x_config_dcbx_params dcbx_config_params;
1496 struct bnx2x_dcbx_port_params dcbx_port_params;
1497 int dcb_version;
1498
1499 /* CAM credit pools */
1500 struct bnx2x_credit_pool_obj macs_pool;
1501
1502 /* RX_MODE object */
1503 struct bnx2x_rx_mode_obj rx_mode_obj;
1504
1505 /* MCAST object */
1506 struct bnx2x_mcast_obj mcast_obj;
1507
1508 /* RSS configuration object */
1509 struct bnx2x_rss_config_obj rss_conf_obj;
1510
1511 /* Function State controlling object */
1512 struct bnx2x_func_sp_obj func_obj;
1513
1514 unsigned long sp_state;
1515
1516 /* operation indication for the sp_rtnl task */
1517 unsigned long sp_rtnl_state;
1518
1519 /* DCBX Negotation results */
1520 struct dcbx_features dcbx_local_feat;
1521 u32 dcbx_error;
1522
1523 #ifdef BCM_DCBNL
1524 struct dcbx_features dcbx_remote_feat;
1525 u32 dcbx_remote_flags;
1526 #endif
1527 u32 pending_max;
1528
1529 /* multiple tx classes of service */
1530 u8 max_cos;
1531
1532 /* priority to cos mapping */
1533 u8 prio_to_cos[8];
1534 };
1535
1536 /* Tx queues may be less or equal to Rx queues */
1537 extern int num_queues;
1538 #define BNX2X_NUM_QUEUES(bp) (bp->num_queues)
1539 #define BNX2X_NUM_ETH_QUEUES(bp) (BNX2X_NUM_QUEUES(bp) - NON_ETH_CONTEXT_USE)
1540 #define BNX2X_NUM_RX_QUEUES(bp) BNX2X_NUM_QUEUES(bp)
1541
1542 #define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1)
1543
1544 #define BNX2X_MAX_QUEUES(bp) BNX2X_MAX_RSS_COUNT(bp)
1545 /* #define is_eth_multi(bp) (BNX2X_NUM_ETH_QUEUES(bp) > 1) */
1546
1547 #define RSS_IPV4_CAP_MASK \
1548 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY
1549
1550 #define RSS_IPV4_TCP_CAP_MASK \
1551 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY
1552
1553 #define RSS_IPV6_CAP_MASK \
1554 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY
1555
1556 #define RSS_IPV6_TCP_CAP_MASK \
1557 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY
1558
1559 /* func init flags */
1560 #define FUNC_FLG_RSS 0x0001
1561 #define FUNC_FLG_STATS 0x0002
1562 /* removed FUNC_FLG_UNMATCHED 0x0004 */
1563 #define FUNC_FLG_TPA 0x0008
1564 #define FUNC_FLG_SPQ 0x0010
1565 #define FUNC_FLG_LEADING 0x0020 /* PF only */
1566
1567
1568 struct bnx2x_func_init_params {
1569 /* dma */
1570 dma_addr_t fw_stat_map; /* valid iff FUNC_FLG_STATS */
1571 dma_addr_t spq_map; /* valid iff FUNC_FLG_SPQ */
1572
1573 u16 func_flgs;
1574 u16 func_id; /* abs fid */
1575 u16 pf_id;
1576 u16 spq_prod; /* valid iff FUNC_FLG_SPQ */
1577 };
1578
1579 #define for_each_eth_queue(bp, var) \
1580 for ((var) = 0; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++)
1581
1582 #define for_each_nondefault_eth_queue(bp, var) \
1583 for ((var) = 1; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++)
1584
1585 #define for_each_queue(bp, var) \
1586 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1587 if (skip_queue(bp, var)) \
1588 continue; \
1589 else
1590
1591 /* Skip forwarding FP */
1592 #define for_each_rx_queue(bp, var) \
1593 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1594 if (skip_rx_queue(bp, var)) \
1595 continue; \
1596 else
1597
1598 /* Skip OOO FP */
1599 #define for_each_tx_queue(bp, var) \
1600 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1601 if (skip_tx_queue(bp, var)) \
1602 continue; \
1603 else
1604
1605 #define for_each_nondefault_queue(bp, var) \
1606 for ((var) = 1; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1607 if (skip_queue(bp, var)) \
1608 continue; \
1609 else
1610
1611 #define for_each_cos_in_tx_queue(fp, var) \
1612 for ((var) = 0; (var) < (fp)->max_cos; (var)++)
1613
1614 /* skip rx queue
1615 * if FCOE l2 support is disabled and this is the fcoe L2 queue
1616 */
1617 #define skip_rx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1618
1619 /* skip tx queue
1620 * if FCOE l2 support is disabled and this is the fcoe L2 queue
1621 */
1622 #define skip_tx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1623
1624 #define skip_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1625
1626
1627
1628
1629 /**
1630 * bnx2x_set_mac_one - configure a single MAC address
1631 *
1632 * @bp: driver handle
1633 * @mac: MAC to configure
1634 * @obj: MAC object handle
1635 * @set: if 'true' add a new MAC, otherwise - delete
1636 * @mac_type: the type of the MAC to configure (e.g. ETH, UC list)
1637 * @ramrod_flags: RAMROD_XXX flags (e.g. RAMROD_CONT, RAMROD_COMP_WAIT)
1638 *
1639 * Configures one MAC according to provided parameters or continues the
1640 * execution of previously scheduled commands if RAMROD_CONT is set in
1641 * ramrod_flags.
1642 *
1643 * Returns zero if operation has successfully completed, a positive value if the
1644 * operation has been successfully scheduled and a negative - if a requested
1645 * operations has failed.
1646 */
1647 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
1648 struct bnx2x_vlan_mac_obj *obj, bool set,
1649 int mac_type, unsigned long *ramrod_flags);
1650 /**
1651 * Deletes all MACs configured for the specific MAC object.
1652 *
1653 * @param bp Function driver instance
1654 * @param mac_obj MAC object to cleanup
1655 *
1656 * @return zero if all MACs were cleaned
1657 */
1658
1659 /**
1660 * bnx2x_del_all_macs - delete all MACs configured for the specific MAC object
1661 *
1662 * @bp: driver handle
1663 * @mac_obj: MAC object handle
1664 * @mac_type: type of the MACs to clear (BNX2X_XXX_MAC)
1665 * @wait_for_comp: if 'true' block until completion
1666 *
1667 * Deletes all MACs of the specific type (e.g. ETH, UC list).
1668 *
1669 * Returns zero if operation has successfully completed, a positive value if the
1670 * operation has been successfully scheduled and a negative - if a requested
1671 * operations has failed.
1672 */
1673 int bnx2x_del_all_macs(struct bnx2x *bp,
1674 struct bnx2x_vlan_mac_obj *mac_obj,
1675 int mac_type, bool wait_for_comp);
1676
1677 /* Init Function API */
1678 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p);
1679 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port);
1680 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
1681 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode);
1682 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
1683 void bnx2x_read_mf_cfg(struct bnx2x *bp);
1684
1685
1686 /* dmae */
1687 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
1688 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
1689 u32 len32);
1690 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx);
1691 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type);
1692 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode);
1693 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
1694 bool with_comp, u8 comp_type);
1695
1696
1697 void bnx2x_calc_fc_adv(struct bnx2x *bp);
1698 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
1699 u32 data_hi, u32 data_lo, int cmd_type);
1700 void bnx2x_update_coalesce(struct bnx2x *bp);
1701 int bnx2x_get_cur_phy_idx(struct bnx2x *bp);
1702
1703 static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
1704 int wait)
1705 {
1706 u32 val;
1707
1708 do {
1709 val = REG_RD(bp, reg);
1710 if (val == expected)
1711 break;
1712 ms -= wait;
1713 msleep(wait);
1714
1715 } while (ms > 0);
1716
1717 return val;
1718 }
1719
1720 #define BNX2X_ILT_ZALLOC(x, y, size) \
1721 do { \
1722 x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \
1723 if (x) \
1724 memset(x, 0, size); \
1725 } while (0)
1726
1727 #define BNX2X_ILT_FREE(x, y, size) \
1728 do { \
1729 if (x) { \
1730 dma_free_coherent(&bp->pdev->dev, size, x, y); \
1731 x = NULL; \
1732 y = 0; \
1733 } \
1734 } while (0)
1735
1736 #define ILOG2(x) (ilog2((x)))
1737
1738 #define ILT_NUM_PAGE_ENTRIES (3072)
1739 /* In 57710/11 we use whole table since we have 8 func
1740 * In 57712 we have only 4 func, but use same size per func, then only half of
1741 * the table in use
1742 */
1743 #define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES/8)
1744
1745 #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC)
1746 /*
1747 * the phys address is shifted right 12 bits and has an added
1748 * 1=valid bit added to the 53rd bit
1749 * then since this is a wide register(TM)
1750 * we split it into two 32 bit writes
1751 */
1752 #define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF))
1753 #define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44)))
1754
1755 /* load/unload mode */
1756 #define LOAD_NORMAL 0
1757 #define LOAD_OPEN 1
1758 #define LOAD_DIAG 2
1759 #define UNLOAD_NORMAL 0
1760 #define UNLOAD_CLOSE 1
1761 #define UNLOAD_RECOVERY 2
1762
1763
1764 /* DMAE command defines */
1765 #define DMAE_TIMEOUT -1
1766 #define DMAE_PCI_ERROR -2 /* E2 and onward */
1767 #define DMAE_NOT_RDY -3
1768 #define DMAE_PCI_ERR_FLAG 0x80000000
1769
1770 #define DMAE_SRC_PCI 0
1771 #define DMAE_SRC_GRC 1
1772
1773 #define DMAE_DST_NONE 0
1774 #define DMAE_DST_PCI 1
1775 #define DMAE_DST_GRC 2
1776
1777 #define DMAE_COMP_PCI 0
1778 #define DMAE_COMP_GRC 1
1779
1780 /* E2 and onward - PCI error handling in the completion */
1781
1782 #define DMAE_COMP_REGULAR 0
1783 #define DMAE_COM_SET_ERR 1
1784
1785 #define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << \
1786 DMAE_COMMAND_SRC_SHIFT)
1787 #define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << \
1788 DMAE_COMMAND_SRC_SHIFT)
1789
1790 #define DMAE_CMD_DST_PCI (DMAE_DST_PCI << \
1791 DMAE_COMMAND_DST_SHIFT)
1792 #define DMAE_CMD_DST_GRC (DMAE_DST_GRC << \
1793 DMAE_COMMAND_DST_SHIFT)
1794
1795 #define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << \
1796 DMAE_COMMAND_C_DST_SHIFT)
1797 #define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << \
1798 DMAE_COMMAND_C_DST_SHIFT)
1799
1800 #define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE
1801
1802 #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
1803 #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
1804 #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
1805 #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
1806
1807 #define DMAE_CMD_PORT_0 0
1808 #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
1809
1810 #define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET
1811 #define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET
1812 #define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT
1813
1814 #define DMAE_SRC_PF 0
1815 #define DMAE_SRC_VF 1
1816
1817 #define DMAE_DST_PF 0
1818 #define DMAE_DST_VF 1
1819
1820 #define DMAE_C_SRC 0
1821 #define DMAE_C_DST 1
1822
1823 #define DMAE_LEN32_RD_MAX 0x80
1824 #define DMAE_LEN32_WR_MAX(bp) (CHIP_IS_E1(bp) ? 0x400 : 0x2000)
1825
1826 #define DMAE_COMP_VAL 0x60d0d0ae /* E2 and on - upper bit
1827 indicates eror */
1828
1829 #define MAX_DMAE_C_PER_PORT 8
1830 #define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
1831 BP_VN(bp))
1832 #define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
1833 E1HVN_MAX)
1834
1835 /* PCIE link and speed */
1836 #define PCICFG_LINK_WIDTH 0x1f00000
1837 #define PCICFG_LINK_WIDTH_SHIFT 20
1838 #define PCICFG_LINK_SPEED 0xf0000
1839 #define PCICFG_LINK_SPEED_SHIFT 16
1840
1841
1842 #define BNX2X_NUM_TESTS 7
1843
1844 #define BNX2X_PHY_LOOPBACK 0
1845 #define BNX2X_MAC_LOOPBACK 1
1846 #define BNX2X_PHY_LOOPBACK_FAILED 1
1847 #define BNX2X_MAC_LOOPBACK_FAILED 2
1848 #define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \
1849 BNX2X_PHY_LOOPBACK_FAILED)
1850
1851
1852 #define STROM_ASSERT_ARRAY_SIZE 50
1853
1854
1855 /* must be used on a CID before placing it on a HW ring */
1856 #define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \
1857 (BP_VN(bp) << BNX2X_SWCID_SHIFT) | \
1858 (x))
1859
1860 #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
1861 #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
1862
1863
1864 #define BNX2X_BTR 4
1865 #define MAX_SPQ_PENDING 8
1866
1867 /* CMNG constants, as derived from system spec calculations */
1868 /* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */
1869 #define DEF_MIN_RATE 100
1870 /* resolution of the rate shaping timer - 400 usec */
1871 #define RS_PERIODIC_TIMEOUT_USEC 400
1872 /* number of bytes in single QM arbitration cycle -
1873 * coefficient for calculating the fairness timer */
1874 #define QM_ARB_BYTES 160000
1875 /* resolution of Min algorithm 1:100 */
1876 #define MIN_RES 100
1877 /* how many bytes above threshold for the minimal credit of Min algorithm*/
1878 #define MIN_ABOVE_THRESH 32768
1879 /* Fairness algorithm integration time coefficient -
1880 * for calculating the actual Tfair */
1881 #define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES)
1882 /* Memory of fairness algorithm . 2 cycles */
1883 #define FAIR_MEM 2
1884
1885
1886 #define ATTN_NIG_FOR_FUNC (1L << 8)
1887 #define ATTN_SW_TIMER_4_FUNC (1L << 9)
1888 #define GPIO_2_FUNC (1L << 10)
1889 #define GPIO_3_FUNC (1L << 11)
1890 #define GPIO_4_FUNC (1L << 12)
1891 #define ATTN_GENERAL_ATTN_1 (1L << 13)
1892 #define ATTN_GENERAL_ATTN_2 (1L << 14)
1893 #define ATTN_GENERAL_ATTN_3 (1L << 15)
1894 #define ATTN_GENERAL_ATTN_4 (1L << 13)
1895 #define ATTN_GENERAL_ATTN_5 (1L << 14)
1896 #define ATTN_GENERAL_ATTN_6 (1L << 15)
1897
1898 #define ATTN_HARD_WIRED_MASK 0xff00
1899 #define ATTENTION_ID 4
1900
1901
1902 /* stuff added to make the code fit 80Col */
1903
1904 #define BNX2X_PMF_LINK_ASSERT \
1905 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp))
1906
1907 #define BNX2X_MC_ASSERT_BITS \
1908 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1909 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1910 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1911 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
1912
1913 #define BNX2X_MCP_ASSERT \
1914 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
1915
1916 #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
1917 #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
1918 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
1919 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
1920 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
1921 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
1922 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
1923
1924 #define HW_INTERRUT_ASSERT_SET_0 \
1925 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
1926 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
1927 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
1928 AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT)
1929 #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
1930 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
1931 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
1932 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
1933 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\
1934 AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\
1935 AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR)
1936 #define HW_INTERRUT_ASSERT_SET_1 \
1937 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
1938 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
1939 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \
1940 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \
1941 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \
1942 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \
1943 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \
1944 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \
1945 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
1946 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
1947 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
1948 #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\
1949 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
1950 AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\
1951 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
1952 AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\
1953 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
1954 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
1955 AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\
1956 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
1957 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
1958 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
1959 AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\
1960 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
1961 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
1962 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\
1963 AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR)
1964 #define HW_INTERRUT_ASSERT_SET_2 \
1965 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
1966 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
1967 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
1968 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
1969 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
1970 #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
1971 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
1972 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
1973 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
1974 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
1975 AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\
1976 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
1977 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
1978
1979 #define HW_PRTY_ASSERT_SET_3 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
1980 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
1981 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \
1982 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
1983
1984 #define HW_PRTY_ASSERT_SET_4 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | \
1985 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)
1986
1987 #define RSS_FLAGS(bp) \
1988 (TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | \
1989 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | \
1990 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | \
1991 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \
1992 (bp->multi_mode << \
1993 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT))
1994 #define MULTI_MASK 0x7f
1995
1996
1997 #define DEF_USB_FUNC_OFF offsetof(struct cstorm_def_status_block_u, func)
1998 #define DEF_CSB_FUNC_OFF offsetof(struct cstorm_def_status_block_c, func)
1999 #define DEF_XSB_FUNC_OFF offsetof(struct xstorm_def_status_block, func)
2000 #define DEF_TSB_FUNC_OFF offsetof(struct tstorm_def_status_block, func)
2001
2002 #define DEF_USB_IGU_INDEX_OFF \
2003 offsetof(struct cstorm_def_status_block_u, igu_index)
2004 #define DEF_CSB_IGU_INDEX_OFF \
2005 offsetof(struct cstorm_def_status_block_c, igu_index)
2006 #define DEF_XSB_IGU_INDEX_OFF \
2007 offsetof(struct xstorm_def_status_block, igu_index)
2008 #define DEF_TSB_IGU_INDEX_OFF \
2009 offsetof(struct tstorm_def_status_block, igu_index)
2010
2011 #define DEF_USB_SEGMENT_OFF \
2012 offsetof(struct cstorm_def_status_block_u, segment)
2013 #define DEF_CSB_SEGMENT_OFF \
2014 offsetof(struct cstorm_def_status_block_c, segment)
2015 #define DEF_XSB_SEGMENT_OFF \
2016 offsetof(struct xstorm_def_status_block, segment)
2017 #define DEF_TSB_SEGMENT_OFF \
2018 offsetof(struct tstorm_def_status_block, segment)
2019
2020 #define BNX2X_SP_DSB_INDEX \
2021 (&bp->def_status_blk->sp_sb.\
2022 index_values[HC_SP_INDEX_ETH_DEF_CONS])
2023
2024 #define SET_FLAG(value, mask, flag) \
2025 do {\
2026 (value) &= ~(mask);\
2027 (value) |= ((flag) << (mask##_SHIFT));\
2028 } while (0)
2029
2030 #define GET_FLAG(value, mask) \
2031 (((value) & (mask)) >> (mask##_SHIFT))
2032
2033 #define GET_FIELD(value, fname) \
2034 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
2035
2036 #define CAM_IS_INVALID(x) \
2037 (GET_FLAG(x.flags, \
2038 MAC_CONFIGURATION_ENTRY_ACTION_TYPE) == \
2039 (T_ETH_MAC_COMMAND_INVALIDATE))
2040
2041 /* Number of u32 elements in MC hash array */
2042 #define MC_HASH_SIZE 8
2043 #define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \
2044 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4)
2045
2046
2047 #ifndef PXP2_REG_PXP2_INT_STS
2048 #define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0
2049 #endif
2050
2051 #ifndef ETH_MAX_RX_CLIENTS_E2
2052 #define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H
2053 #endif
2054
2055 #define BNX2X_VPD_LEN 128
2056 #define VENDOR_ID_LEN 4
2057
2058 /* Congestion management fairness mode */
2059 #define CMNG_FNS_NONE 0
2060 #define CMNG_FNS_MINMAX 1
2061
2062 #define HC_SEG_ACCESS_DEF 0 /*Driver decision 0-3*/
2063 #define HC_SEG_ACCESS_ATTN 4
2064 #define HC_SEG_ACCESS_NORM 0 /*Driver decision 0-1*/
2065
2066 static const u32 dmae_reg_go_c[] = {
2067 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
2068 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
2069 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
2070 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
2071 };
2072
2073 void bnx2x_set_ethtool_ops(struct net_device *netdev);
2074 void bnx2x_notify_link_changed(struct bnx2x *bp);
2075 #endif /* bnx2x.h */
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