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PCI: add default busn_resource
[linux-2.6.git] / include / linux / pci.h
blob8c8b44d62105903791a529d194fe9e22d7725ad7
1 /*
2 * pci.h
3 *
4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
7 *
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
10 *
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
15 */
16
17 #ifndef LINUX_PCI_H
18 #define LINUX_PCI_H
19
20 #include <linux/pci_regs.h> /* The pci register defines */
21
22 /*
23 * The PCI interface treats multi-function devices as independent
24 * devices. The slot/function address of each device is encoded
25 * in a single byte as follows:
26 *
27 * 7:3 = slot
28 * 2:0 = function
29 */
30 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
31 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
32 #define PCI_FUNC(devfn) ((devfn) & 0x07)
33
34 /* Ioctls for /proc/bus/pci/X/Y nodes. */
35 #define PCIIOC_BASE ('P' << 24 | 'C' << 16 | 'I' << 8)
36 #define PCIIOC_CONTROLLER (PCIIOC_BASE | 0x00) /* Get controller for PCI device. */
37 #define PCIIOC_MMAP_IS_IO (PCIIOC_BASE | 0x01) /* Set mmap state to I/O space. */
38 #define PCIIOC_MMAP_IS_MEM (PCIIOC_BASE | 0x02) /* Set mmap state to MEM space. */
39 #define PCIIOC_WRITE_COMBINE (PCIIOC_BASE | 0x03) /* Enable/disable write-combining. */
40
41 #ifdef __KERNEL__
42
43 #include <linux/mod_devicetable.h>
44
45 #include <linux/types.h>
46 #include <linux/init.h>
47 #include <linux/ioport.h>
48 #include <linux/list.h>
49 #include <linux/compiler.h>
50 #include <linux/errno.h>
51 #include <linux/kobject.h>
52 #include <linux/atomic.h>
53 #include <linux/device.h>
54 #include <linux/io.h>
55 #include <linux/irqreturn.h>
56
57 /* Include the ID list */
58 #include <linux/pci_ids.h>
59
60 /* pci_slot represents a physical slot */
61 struct pci_slot {
62 struct pci_bus *bus; /* The bus this slot is on */
63 struct list_head list; /* node in list of slots on this bus */
64 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */
65 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
66 struct kobject kobj;
67 };
68
69 static inline const char *pci_slot_name(const struct pci_slot *slot)
70 {
71 return kobject_name(&slot->kobj);
72 }
73
74 /* File state for mmap()s on /proc/bus/pci/X/Y */
75 enum pci_mmap_state {
76 pci_mmap_io,
77 pci_mmap_mem
78 };
79
80 /* This defines the direction arg to the DMA mapping routines. */
81 #define PCI_DMA_BIDIRECTIONAL 0
82 #define PCI_DMA_TODEVICE 1
83 #define PCI_DMA_FROMDEVICE 2
84 #define PCI_DMA_NONE 3
85
86 /*
87 * For PCI devices, the region numbers are assigned this way:
88 */
89 enum {
90 /* #0-5: standard PCI resources */
91 PCI_STD_RESOURCES,
92 PCI_STD_RESOURCE_END = 5,
93
94 /* #6: expansion ROM resource */
95 PCI_ROM_RESOURCE,
96
97 /* device specific resources */
98 #ifdef CONFIG_PCI_IOV
99 PCI_IOV_RESOURCES,
100 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
101 #endif
102
103 /* resources assigned to buses behind the bridge */
104 #define PCI_BRIDGE_RESOURCE_NUM 4
105
106 PCI_BRIDGE_RESOURCES,
107 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
108 PCI_BRIDGE_RESOURCE_NUM - 1,
109
110 /* total resources associated with a PCI device */
111 PCI_NUM_RESOURCES,
112
113 /* preserve this for compatibility */
114 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
115 };
116
117 typedef int __bitwise pci_power_t;
118
119 #define PCI_D0 ((pci_power_t __force) 0)
120 #define PCI_D1 ((pci_power_t __force) 1)
121 #define PCI_D2 ((pci_power_t __force) 2)
122 #define PCI_D3hot ((pci_power_t __force) 3)
123 #define PCI_D3cold ((pci_power_t __force) 4)
124 #define PCI_UNKNOWN ((pci_power_t __force) 5)
125 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
126
127 /* Remember to update this when the list above changes! */
128 extern const char *pci_power_names[];
129
130 static inline const char *pci_power_name(pci_power_t state)
131 {
132 return pci_power_names[1 + (int) state];
133 }
134
135 #define PCI_PM_D2_DELAY 200
136 #define PCI_PM_D3_WAIT 10
137 #define PCI_PM_BUS_WAIT 50
138
139 /** The pci_channel state describes connectivity between the CPU and
140 * the pci device. If some PCI bus between here and the pci device
141 * has crashed or locked up, this info is reflected here.
142 */
143 typedef unsigned int __bitwise pci_channel_state_t;
144
145 enum pci_channel_state {
146 /* I/O channel is in normal state */
147 pci_channel_io_normal = (__force pci_channel_state_t) 1,
148
149 /* I/O to channel is blocked */
150 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
151
152 /* PCI card is dead */
153 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
154 };
155
156 typedef unsigned int __bitwise pcie_reset_state_t;
157
158 enum pcie_reset_state {
159 /* Reset is NOT asserted (Use to deassert reset) */
160 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
161
162 /* Use #PERST to reset PCI-E device */
163 pcie_warm_reset = (__force pcie_reset_state_t) 2,
164
165 /* Use PCI-E Hot Reset to reset device */
166 pcie_hot_reset = (__force pcie_reset_state_t) 3
167 };
168
169 typedef unsigned short __bitwise pci_dev_flags_t;
170 enum pci_dev_flags {
171 /* INTX_DISABLE in PCI_COMMAND register disables MSI
172 * generation too.
173 */
174 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) 1,
175 /* Device configuration is irrevocably lost if disabled into D3 */
176 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2,
177 /* Provide indication device is assigned by a Virtual Machine Manager */
178 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) 4,
179 };
180
181 enum pci_irq_reroute_variant {
182 INTEL_IRQ_REROUTE_VARIANT = 1,
183 MAX_IRQ_REROUTE_VARIANTS = 3
184 };
185
186 typedef unsigned short __bitwise pci_bus_flags_t;
187 enum pci_bus_flags {
188 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
189 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
190 };
191
192 /* Based on the PCI Hotplug Spec, but some values are made up by us */
193 enum pci_bus_speed {
194 PCI_SPEED_33MHz = 0x00,
195 PCI_SPEED_66MHz = 0x01,
196 PCI_SPEED_66MHz_PCIX = 0x02,
197 PCI_SPEED_100MHz_PCIX = 0x03,
198 PCI_SPEED_133MHz_PCIX = 0x04,
199 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
200 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
201 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
202 PCI_SPEED_66MHz_PCIX_266 = 0x09,
203 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
204 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
205 AGP_UNKNOWN = 0x0c,
206 AGP_1X = 0x0d,
207 AGP_2X = 0x0e,
208 AGP_4X = 0x0f,
209 AGP_8X = 0x10,
210 PCI_SPEED_66MHz_PCIX_533 = 0x11,
211 PCI_SPEED_100MHz_PCIX_533 = 0x12,
212 PCI_SPEED_133MHz_PCIX_533 = 0x13,
213 PCIE_SPEED_2_5GT = 0x14,
214 PCIE_SPEED_5_0GT = 0x15,
215 PCIE_SPEED_8_0GT = 0x16,
216 PCI_SPEED_UNKNOWN = 0xff,
217 };
218
219 struct pci_cap_saved_data {
220 char cap_nr;
221 unsigned int size;
222 u32 data[0];
223 };
224
225 struct pci_cap_saved_state {
226 struct hlist_node next;
227 struct pci_cap_saved_data cap;
228 };
229
230 struct pcie_link_state;
231 struct pci_vpd;
232 struct pci_sriov;
233 struct pci_ats;
234
235 /*
236 * The pci_dev structure is used to describe PCI devices.
237 */
238 struct pci_dev {
239 struct list_head bus_list; /* node in per-bus list */
240 struct pci_bus *bus; /* bus this device is on */
241 struct pci_bus *subordinate; /* bus this device bridges to */
242
243 void *sysdata; /* hook for sys-specific extension */
244 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
245 struct pci_slot *slot; /* Physical slot this device is in */
246
247 unsigned int devfn; /* encoded device & function index */
248 unsigned short vendor;
249 unsigned short device;
250 unsigned short subsystem_vendor;
251 unsigned short subsystem_device;
252 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
253 u8 revision; /* PCI revision, low byte of class word */
254 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
255 u8 pcie_cap; /* PCI-E capability offset */
256 u8 pcie_type:4; /* PCI-E device/port type */
257 u8 pcie_mpss:3; /* PCI-E Max Payload Size Supported */
258 u8 rom_base_reg; /* which config register controls the ROM */
259 u8 pin; /* which interrupt pin this device uses */
260
261 struct pci_driver *driver; /* which driver has allocated this device */
262 u64 dma_mask; /* Mask of the bits of bus address this
263 device implements. Normally this is
264 0xffffffff. You only need to change
265 this if your device has broken DMA
266 or supports 64-bit transfers. */
267
268 struct device_dma_parameters dma_parms;
269
270 pci_power_t current_state; /* Current operating state. In ACPI-speak,
271 this is D0-D3, D0 being fully functional,
272 and D3 being off. */
273 int pm_cap; /* PM capability offset in the
274 configuration space */
275 unsigned int pme_support:5; /* Bitmask of states from which PME#
276 can be generated */
277 unsigned int pme_interrupt:1;
278 unsigned int pme_poll:1; /* Poll device's PME status bit */
279 unsigned int d1_support:1; /* Low power state D1 is supported */
280 unsigned int d2_support:1; /* Low power state D2 is supported */
281 unsigned int no_d1d2:1; /* Only allow D0 and D3 */
282 unsigned int mmio_always_on:1; /* disallow turning off io/mem
283 decoding during bar sizing */
284 unsigned int wakeup_prepared:1;
285 unsigned int d3_delay; /* D3->D0 transition time in ms */
286
287 #ifdef CONFIG_PCIEASPM
288 struct pcie_link_state *link_state; /* ASPM link state. */
289 #endif
290
291 pci_channel_state_t error_state; /* current connectivity state */
292 struct device dev; /* Generic device interface */
293
294 int cfg_size; /* Size of configuration space */
295
296 /*
297 * Instead of touching interrupt line and base address registers
298 * directly, use the values stored here. They might be different!
299 */
300 unsigned int irq;
301 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
302
303 /* These fields are used by common fixups */
304 unsigned int transparent:1; /* Transparent PCI bridge */
305 unsigned int multifunction:1;/* Part of multi-function device */
306 /* keep track of device state */
307 unsigned int is_added:1;
308 unsigned int is_busmaster:1; /* device is busmaster */
309 unsigned int no_msi:1; /* device may not use msi */
310 unsigned int block_cfg_access:1; /* config space access is blocked */
311 unsigned int broken_parity_status:1; /* Device generates false positive parity */
312 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */
313 unsigned int msi_enabled:1;
314 unsigned int msix_enabled:1;
315 unsigned int ari_enabled:1; /* ARI forwarding */
316 unsigned int is_managed:1;
317 unsigned int is_pcie:1; /* Obsolete. Will be removed.
318 Use pci_is_pcie() instead */
319 unsigned int needs_freset:1; /* Dev requires fundamental reset */
320 unsigned int state_saved:1;
321 unsigned int is_physfn:1;
322 unsigned int is_virtfn:1;
323 unsigned int reset_fn:1;
324 unsigned int is_hotplug_bridge:1;
325 unsigned int __aer_firmware_first_valid:1;
326 unsigned int __aer_firmware_first:1;
327 pci_dev_flags_t dev_flags;
328 atomic_t enable_cnt; /* pci_enable_device has been called */
329
330 u32 saved_config_space[16]; /* config space saved at suspend time */
331 struct hlist_head saved_cap_space;
332 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
333 int rom_attr_enabled; /* has display of the rom attribute been enabled? */
334 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
335 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
336 #ifdef CONFIG_PCI_MSI
337 struct list_head msi_list;
338 struct kset *msi_kset;
339 #endif
340 struct pci_vpd *vpd;
341 #ifdef CONFIG_PCI_ATS
342 union {
343 struct pci_sriov *sriov; /* SR-IOV capability related */
344 struct pci_dev *physfn; /* the PF this VF is associated with */
345 };
346 struct pci_ats *ats; /* Address Translation Service */
347 #endif
348 };
349
350 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
351 {
352 #ifdef CONFIG_PCI_IOV
353 if (dev->is_virtfn)
354 dev = dev->physfn;
355 #endif
356
357 return dev;
358 }
359
360 extern struct pci_dev *alloc_pci_dev(void);
361
362 #define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list)
363 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
364 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
365
366 static inline int pci_channel_offline(struct pci_dev *pdev)
367 {
368 return (pdev->error_state != pci_channel_io_normal);
369 }
370
371 extern struct resource busn_resource;
372
373 struct pci_host_bridge_window {
374 struct list_head list;
375 struct resource *res; /* host bridge aperture (CPU address) */
376 resource_size_t offset; /* bus address + offset = CPU address */
377 };
378
379 struct pci_host_bridge {
380 struct device dev;
381 struct pci_bus *bus; /* root bus */
382 struct list_head windows; /* pci_host_bridge_windows */
383 void (*release_fn)(struct pci_host_bridge *);
384 void *release_data;
385 };
386
387 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
388 void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
389 void (*release_fn)(struct pci_host_bridge *),
390 void *release_data);
391
392 /*
393 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
394 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
395 * buses below host bridges or subtractive decode bridges) go in the list.
396 * Use pci_bus_for_each_resource() to iterate through all the resources.
397 */
398
399 /*
400 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
401 * and there's no way to program the bridge with the details of the window.
402 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
403 * decode bit set, because they are explicit and can be programmed with _SRS.
404 */
405 #define PCI_SUBTRACTIVE_DECODE 0x1
406
407 struct pci_bus_resource {
408 struct list_head list;
409 struct resource *res;
410 unsigned int flags;
411 };
412
413 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
414
415 struct pci_bus {
416 struct list_head node; /* node in list of buses */
417 struct pci_bus *parent; /* parent bus this bridge is on */
418 struct list_head children; /* list of child buses */
419 struct list_head devices; /* list of devices on this bus */
420 struct pci_dev *self; /* bridge device as seen by parent */
421 struct list_head slots; /* list of slots on this bus */
422 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
423 struct list_head resources; /* address space routed to this bus */
424 struct resource busn_res; /* bus numbers routed to this bus */
425
426 struct pci_ops *ops; /* configuration access functions */
427 void *sysdata; /* hook for sys-specific extension */
428 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
429
430 unsigned char number; /* bus number */
431 unsigned char primary; /* number of primary bridge */
432 unsigned char max_bus_speed; /* enum pci_bus_speed */
433 unsigned char cur_bus_speed; /* enum pci_bus_speed */
434
435 char name[48];
436
437 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
438 pci_bus_flags_t bus_flags; /* Inherited by child busses */
439 struct device *bridge;
440 struct device dev;
441 struct bin_attribute *legacy_io; /* legacy I/O for this bus */
442 struct bin_attribute *legacy_mem; /* legacy mem */
443 unsigned int is_added:1;
444 };
445
446 #define pci_bus_b(n) list_entry(n, struct pci_bus, node)
447 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
448
449 /*
450 * Returns true if the pci bus is root (behind host-pci bridge),
451 * false otherwise
452 */
453 static inline bool pci_is_root_bus(struct pci_bus *pbus)
454 {
455 return !(pbus->parent);
456 }
457
458 #ifdef CONFIG_PCI_MSI
459 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
460 {
461 return pci_dev->msi_enabled || pci_dev->msix_enabled;
462 }
463 #else
464 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
465 #endif
466
467 /*
468 * Error values that may be returned by PCI functions.
469 */
470 #define PCIBIOS_SUCCESSFUL 0x00
471 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
472 #define PCIBIOS_BAD_VENDOR_ID 0x83
473 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
474 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
475 #define PCIBIOS_SET_FAILED 0x88
476 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
477
478 /* Low-level architecture-dependent routines */
479
480 struct pci_ops {
481 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
482 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
483 };
484
485 /*
486 * ACPI needs to be able to access PCI config space before we've done a
487 * PCI bus scan and created pci_bus structures.
488 */
489 extern int raw_pci_read(unsigned int domain, unsigned int bus,
490 unsigned int devfn, int reg, int len, u32 *val);
491 extern int raw_pci_write(unsigned int domain, unsigned int bus,
492 unsigned int devfn, int reg, int len, u32 val);
493
494 struct pci_bus_region {
495 resource_size_t start;
496 resource_size_t end;
497 };
498
499 struct pci_dynids {
500 spinlock_t lock; /* protects list, index */
501 struct list_head list; /* for IDs added at runtime */
502 };
503
504 /* ---------------------------------------------------------------- */
505 /** PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
506 * a set of callbacks in struct pci_error_handlers, then that device driver
507 * will be notified of PCI bus errors, and will be driven to recovery
508 * when an error occurs.
509 */
510
511 typedef unsigned int __bitwise pci_ers_result_t;
512
513 enum pci_ers_result {
514 /* no result/none/not supported in device driver */
515 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
516
517 /* Device driver can recover without slot reset */
518 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
519
520 /* Device driver wants slot to be reset. */
521 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
522
523 /* Device has completely failed, is unrecoverable */
524 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
525
526 /* Device driver is fully recovered and operational */
527 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
528 };
529
530 /* PCI bus error event callbacks */
531 struct pci_error_handlers {
532 /* PCI bus error detected on this device */
533 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
534 enum pci_channel_state error);
535
536 /* MMIO has been re-enabled, but not DMA */
537 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
538
539 /* PCI Express link has been reset */
540 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
541
542 /* PCI slot has been reset */
543 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
544
545 /* Device driver may resume normal operations */
546 void (*resume)(struct pci_dev *dev);
547 };
548
549 /* ---------------------------------------------------------------- */
550
551 struct module;
552 struct pci_driver {
553 struct list_head node;
554 const char *name;
555 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
556 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
557 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
558 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
559 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
560 int (*resume_early) (struct pci_dev *dev);
561 int (*resume) (struct pci_dev *dev); /* Device woken up */
562 void (*shutdown) (struct pci_dev *dev);
563 struct pci_error_handlers *err_handler;
564 struct device_driver driver;
565 struct pci_dynids dynids;
566 };
567
568 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
569
570 /**
571 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table
572 * @_table: device table name
573 *
574 * This macro is used to create a struct pci_device_id array (a device table)
575 * in a generic manner.
576 */
577 #define DEFINE_PCI_DEVICE_TABLE(_table) \
578 const struct pci_device_id _table[] __devinitconst
579
580 /**
581 * PCI_DEVICE - macro used to describe a specific pci device
582 * @vend: the 16 bit PCI Vendor ID
583 * @dev: the 16 bit PCI Device ID
584 *
585 * This macro is used to create a struct pci_device_id that matches a
586 * specific device. The subvendor and subdevice fields will be set to
587 * PCI_ANY_ID.
588 */
589 #define PCI_DEVICE(vend,dev) \
590 .vendor = (vend), .device = (dev), \
591 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
592
593 /**
594 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
595 * @dev_class: the class, subclass, prog-if triple for this device
596 * @dev_class_mask: the class mask for this device
597 *
598 * This macro is used to create a struct pci_device_id that matches a
599 * specific PCI class. The vendor, device, subvendor, and subdevice
600 * fields will be set to PCI_ANY_ID.
601 */
602 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
603 .class = (dev_class), .class_mask = (dev_class_mask), \
604 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
605 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
606
607 /**
608 * PCI_VDEVICE - macro used to describe a specific pci device in short form
609 * @vendor: the vendor name
610 * @device: the 16 bit PCI Device ID
611 *
612 * This macro is used to create a struct pci_device_id that matches a
613 * specific PCI device. The subvendor, and subdevice fields will be set
614 * to PCI_ANY_ID. The macro allows the next field to follow as the device
615 * private data.
616 */
617
618 #define PCI_VDEVICE(vendor, device) \
619 PCI_VENDOR_ID_##vendor, (device), \
620 PCI_ANY_ID, PCI_ANY_ID, 0, 0
621
622 /* these external functions are only available when PCI support is enabled */
623 #ifdef CONFIG_PCI
624
625 extern void pcie_bus_configure_settings(struct pci_bus *bus, u8 smpss);
626
627 enum pcie_bus_config_types {
628 PCIE_BUS_TUNE_OFF,
629 PCIE_BUS_SAFE,
630 PCIE_BUS_PERFORMANCE,
631 PCIE_BUS_PEER2PEER,
632 };
633
634 extern enum pcie_bus_config_types pcie_bus_config;
635
636 extern struct bus_type pci_bus_type;
637
638 /* Do NOT directly access these two variables, unless you are arch specific pci
639 * code, or pci core code. */
640 extern struct list_head pci_root_buses; /* list of all known PCI buses */
641 /* Some device drivers need know if pci is initiated */
642 extern int no_pci_devices(void);
643
644 void pcibios_fixup_bus(struct pci_bus *);
645 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
646 char *pcibios_setup(char *str);
647
648 /* Used only when drivers/pci/setup.c is used */
649 resource_size_t pcibios_align_resource(void *, const struct resource *,
650 resource_size_t,
651 resource_size_t);
652 void pcibios_update_irq(struct pci_dev *, int irq);
653
654 /* Weak but can be overriden by arch */
655 void pci_fixup_cardbus(struct pci_bus *);
656
657 /* Generic PCI functions used internally */
658
659 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
660 struct resource *res);
661 void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
662 struct pci_bus_region *region);
663 void pcibios_scan_specific_bus(int busn);
664 extern struct pci_bus *pci_find_bus(int domain, int busnr);
665 void pci_bus_add_devices(const struct pci_bus *bus);
666 struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus,
667 struct pci_ops *ops, void *sysdata);
668 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
669 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
670 struct pci_ops *ops, void *sysdata,
671 struct list_head *resources);
672 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
673 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
674 void pci_bus_release_busn_res(struct pci_bus *b);
675 struct pci_bus * __devinit pci_scan_root_bus(struct device *parent, int bus,
676 struct pci_ops *ops, void *sysdata,
677 struct list_head *resources);
678 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
679 int busnr);
680 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
681 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
682 const char *name,
683 struct hotplug_slot *hotplug);
684 void pci_destroy_slot(struct pci_slot *slot);
685 void pci_renumber_slot(struct pci_slot *slot, int slot_nr);
686 int pci_scan_slot(struct pci_bus *bus, int devfn);
687 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
688 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
689 unsigned int pci_scan_child_bus(struct pci_bus *bus);
690 int __must_check pci_bus_add_device(struct pci_dev *dev);
691 void pci_read_bridge_bases(struct pci_bus *child);
692 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
693 struct resource *res);
694 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
695 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
696 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
697 extern struct pci_dev *pci_dev_get(struct pci_dev *dev);
698 extern void pci_dev_put(struct pci_dev *dev);
699 extern void pci_remove_bus(struct pci_bus *b);
700 extern void __pci_remove_bus_device(struct pci_dev *dev);
701 extern void pci_stop_and_remove_bus_device(struct pci_dev *dev);
702 extern void pci_stop_bus_device(struct pci_dev *dev);
703 void pci_setup_cardbus(struct pci_bus *bus);
704 extern void pci_sort_breadthfirst(void);
705 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
706 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
707 #define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0))
708
709 /* Generic PCI functions exported to card drivers */
710
711 enum pci_lost_interrupt_reason {
712 PCI_LOST_IRQ_NO_INFORMATION = 0,
713 PCI_LOST_IRQ_DISABLE_MSI,
714 PCI_LOST_IRQ_DISABLE_MSIX,
715 PCI_LOST_IRQ_DISABLE_ACPI,
716 };
717 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
718 int pci_find_capability(struct pci_dev *dev, int cap);
719 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
720 int pci_find_ext_capability(struct pci_dev *dev, int cap);
721 int pci_bus_find_ext_capability(struct pci_bus *bus, unsigned int devfn,
722 int cap);
723 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
724 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
725 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
726
727 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
728 struct pci_dev *from);
729 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
730 unsigned int ss_vendor, unsigned int ss_device,
731 struct pci_dev *from);
732 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
733 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
734 unsigned int devfn);
735 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
736 unsigned int devfn)
737 {
738 return pci_get_domain_bus_and_slot(0, bus, devfn);
739 }
740 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
741 int pci_dev_present(const struct pci_device_id *ids);
742
743 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
744 int where, u8 *val);
745 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
746 int where, u16 *val);
747 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
748 int where, u32 *val);
749 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
750 int where, u8 val);
751 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
752 int where, u16 val);
753 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
754 int where, u32 val);
755 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
756
757 static inline int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val)
758 {
759 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
760 }
761 static inline int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val)
762 {
763 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
764 }
765 static inline int pci_read_config_dword(const struct pci_dev *dev, int where,
766 u32 *val)
767 {
768 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
769 }
770 static inline int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val)
771 {
772 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
773 }
774 static inline int pci_write_config_word(const struct pci_dev *dev, int where, u16 val)
775 {
776 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
777 }
778 static inline int pci_write_config_dword(const struct pci_dev *dev, int where,
779 u32 val)
780 {
781 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
782 }
783
784 int __must_check pci_enable_device(struct pci_dev *dev);
785 int __must_check pci_enable_device_io(struct pci_dev *dev);
786 int __must_check pci_enable_device_mem(struct pci_dev *dev);
787 int __must_check pci_reenable_device(struct pci_dev *);
788 int __must_check pcim_enable_device(struct pci_dev *pdev);
789 void pcim_pin_device(struct pci_dev *pdev);
790
791 static inline int pci_is_enabled(struct pci_dev *pdev)
792 {
793 return (atomic_read(&pdev->enable_cnt) > 0);
794 }
795
796 static inline int pci_is_managed(struct pci_dev *pdev)
797 {
798 return pdev->is_managed;
799 }
800
801 void pci_disable_device(struct pci_dev *dev);
802
803 extern unsigned int pcibios_max_latency;
804 void pci_set_master(struct pci_dev *dev);
805 void pci_clear_master(struct pci_dev *dev);
806
807 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
808 int pci_set_cacheline_size(struct pci_dev *dev);
809 #define HAVE_PCI_SET_MWI
810 int __must_check pci_set_mwi(struct pci_dev *dev);
811 int pci_try_set_mwi(struct pci_dev *dev);
812 void pci_clear_mwi(struct pci_dev *dev);
813 void pci_intx(struct pci_dev *dev, int enable);
814 bool pci_intx_mask_supported(struct pci_dev *dev);
815 bool pci_check_and_mask_intx(struct pci_dev *dev);
816 bool pci_check_and_unmask_intx(struct pci_dev *dev);
817 void pci_msi_off(struct pci_dev *dev);
818 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size);
819 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask);
820 int pcix_get_max_mmrbc(struct pci_dev *dev);
821 int pcix_get_mmrbc(struct pci_dev *dev);
822 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
823 int pcie_get_readrq(struct pci_dev *dev);
824 int pcie_set_readrq(struct pci_dev *dev, int rq);
825 int pcie_get_mps(struct pci_dev *dev);
826 int pcie_set_mps(struct pci_dev *dev, int mps);
827 int __pci_reset_function(struct pci_dev *dev);
828 int __pci_reset_function_locked(struct pci_dev *dev);
829 int pci_reset_function(struct pci_dev *dev);
830 void pci_update_resource(struct pci_dev *dev, int resno);
831 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
832 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
833 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
834
835 /* ROM control related routines */
836 int pci_enable_rom(struct pci_dev *pdev);
837 void pci_disable_rom(struct pci_dev *pdev);
838 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
839 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
840 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
841
842 /* Power management related routines */
843 int pci_save_state(struct pci_dev *dev);
844 void pci_restore_state(struct pci_dev *dev);
845 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
846 int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state);
847 int pci_load_and_free_saved_state(struct pci_dev *dev,
848 struct pci_saved_state **state);
849 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
850 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
851 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
852 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
853 void pci_pme_active(struct pci_dev *dev, bool enable);
854 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
855 bool runtime, bool enable);
856 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
857 pci_power_t pci_target_state(struct pci_dev *dev);
858 int pci_prepare_to_sleep(struct pci_dev *dev);
859 int pci_back_from_sleep(struct pci_dev *dev);
860 bool pci_dev_run_wake(struct pci_dev *dev);
861 bool pci_check_pme_status(struct pci_dev *dev);
862 void pci_pme_wakeup_bus(struct pci_bus *bus);
863
864 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
865 bool enable)
866 {
867 return __pci_enable_wake(dev, state, false, enable);
868 }
869
870 #define PCI_EXP_IDO_REQUEST (1<<0)
871 #define PCI_EXP_IDO_COMPLETION (1<<1)
872 void pci_enable_ido(struct pci_dev *dev, unsigned long type);
873 void pci_disable_ido(struct pci_dev *dev, unsigned long type);
874
875 enum pci_obff_signal_type {
876 PCI_EXP_OBFF_SIGNAL_L0 = 0,
877 PCI_EXP_OBFF_SIGNAL_ALWAYS = 1,
878 };
879 int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type);
880 void pci_disable_obff(struct pci_dev *dev);
881
882 bool pci_ltr_supported(struct pci_dev *dev);
883 int pci_enable_ltr(struct pci_dev *dev);
884 void pci_disable_ltr(struct pci_dev *dev);
885 int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns);
886
887 /* For use by arch with custom probe code */
888 void set_pcie_port_type(struct pci_dev *pdev);
889 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
890
891 /* Functions for PCI Hotplug drivers to use */
892 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
893 #ifdef CONFIG_HOTPLUG
894 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
895 unsigned int pci_rescan_bus(struct pci_bus *bus);
896 #endif
897
898 /* Vital product data routines */
899 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
900 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
901 int pci_vpd_truncate(struct pci_dev *dev, size_t size);
902
903 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
904 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
905 void pci_bus_assign_resources(const struct pci_bus *bus);
906 void pci_bus_size_bridges(struct pci_bus *bus);
907 int pci_claim_resource(struct pci_dev *, int);
908 void pci_assign_unassigned_resources(void);
909 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
910 void pdev_enable_device(struct pci_dev *);
911 int pci_enable_resources(struct pci_dev *, int mask);
912 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
913 int (*)(const struct pci_dev *, u8, u8));
914 #define HAVE_PCI_REQ_REGIONS 2
915 int __must_check pci_request_regions(struct pci_dev *, const char *);
916 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
917 void pci_release_regions(struct pci_dev *);
918 int __must_check pci_request_region(struct pci_dev *, int, const char *);
919 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
920 void pci_release_region(struct pci_dev *, int);
921 int pci_request_selected_regions(struct pci_dev *, int, const char *);
922 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
923 void pci_release_selected_regions(struct pci_dev *, int);
924
925 /* drivers/pci/bus.c */
926 void pci_add_resource(struct list_head *resources, struct resource *res);
927 void pci_add_resource_offset(struct list_head *resources, struct resource *res,
928 resource_size_t offset);
929 void pci_free_resource_list(struct list_head *resources);
930 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, unsigned int flags);
931 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
932 void pci_bus_remove_resources(struct pci_bus *bus);
933
934 #define pci_bus_for_each_resource(bus, res, i) \
935 for (i = 0; \
936 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
937 i++)
938
939 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
940 struct resource *res, resource_size_t size,
941 resource_size_t align, resource_size_t min,
942 unsigned int type_mask,
943 resource_size_t (*alignf)(void *,
944 const struct resource *,
945 resource_size_t,
946 resource_size_t),
947 void *alignf_data);
948 void pci_enable_bridges(struct pci_bus *bus);
949
950 /* Proper probing supporting hot-pluggable devices */
951 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
952 const char *mod_name);
953
954 /*
955 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
956 */
957 #define pci_register_driver(driver) \
958 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
959
960 void pci_unregister_driver(struct pci_driver *dev);
961
962 /**
963 * module_pci_driver() - Helper macro for registering a PCI driver
964 * @__pci_driver: pci_driver struct
965 *
966 * Helper macro for PCI drivers which do not do anything special in module
967 * init/exit. This eliminates a lot of boilerplate. Each module may only
968 * use this macro once, and calling it replaces module_init() and module_exit()
969 */
970 #define module_pci_driver(__pci_driver) \
971 module_driver(__pci_driver, pci_register_driver, \
972 pci_unregister_driver)
973
974 void pci_stop_and_remove_behind_bridge(struct pci_dev *dev);
975 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
976 int pci_add_dynid(struct pci_driver *drv,
977 unsigned int vendor, unsigned int device,
978 unsigned int subvendor, unsigned int subdevice,
979 unsigned int class, unsigned int class_mask,
980 unsigned long driver_data);
981 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
982 struct pci_dev *dev);
983 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
984 int pass);
985
986 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
987 void *userdata);
988 int pci_cfg_space_size_ext(struct pci_dev *dev);
989 int pci_cfg_space_size(struct pci_dev *dev);
990 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
991 void pci_setup_bridge(struct pci_bus *bus);
992
993 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
994 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
995
996 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
997 unsigned int command_bits, u32 flags);
998 /* kmem_cache style wrapper around pci_alloc_consistent() */
999
1000 #include <linux/pci-dma.h>
1001 #include <linux/dmapool.h>
1002
1003 #define pci_pool dma_pool
1004 #define pci_pool_create(name, pdev, size, align, allocation) \
1005 dma_pool_create(name, &pdev->dev, size, align, allocation)
1006 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
1007 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1008 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1009
1010 enum pci_dma_burst_strategy {
1011 PCI_DMA_BURST_INFINITY, /* make bursts as large as possible,
1012 strategy_parameter is N/A */
1013 PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter
1014 byte boundaries */
1015 PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of
1016 strategy_parameter byte boundaries */
1017 };
1018
1019 struct msix_entry {
1020 u32 vector; /* kernel uses to write allocated vector */
1021 u16 entry; /* driver uses to specify entry, OS writes */
1022 };
1023
1024
1025 #ifndef CONFIG_PCI_MSI
1026 static inline int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec)
1027 {
1028 return -1;
1029 }
1030
1031 static inline void pci_msi_shutdown(struct pci_dev *dev)
1032 { }
1033 static inline void pci_disable_msi(struct pci_dev *dev)
1034 { }
1035
1036 static inline int pci_msix_table_size(struct pci_dev *dev)
1037 {
1038 return 0;
1039 }
1040 static inline int pci_enable_msix(struct pci_dev *dev,
1041 struct msix_entry *entries, int nvec)
1042 {
1043 return -1;
1044 }
1045
1046 static inline void pci_msix_shutdown(struct pci_dev *dev)
1047 { }
1048 static inline void pci_disable_msix(struct pci_dev *dev)
1049 { }
1050
1051 static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev)
1052 { }
1053
1054 static inline void pci_restore_msi_state(struct pci_dev *dev)
1055 { }
1056 static inline int pci_msi_enabled(void)
1057 {
1058 return 0;
1059 }
1060 #else
1061 extern int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec);
1062 extern void pci_msi_shutdown(struct pci_dev *dev);
1063 extern void pci_disable_msi(struct pci_dev *dev);
1064 extern int pci_msix_table_size(struct pci_dev *dev);
1065 extern int pci_enable_msix(struct pci_dev *dev,
1066 struct msix_entry *entries, int nvec);
1067 extern void pci_msix_shutdown(struct pci_dev *dev);
1068 extern void pci_disable_msix(struct pci_dev *dev);
1069 extern void msi_remove_pci_irq_vectors(struct pci_dev *dev);
1070 extern void pci_restore_msi_state(struct pci_dev *dev);
1071 extern int pci_msi_enabled(void);
1072 #endif
1073
1074 #ifdef CONFIG_PCIEPORTBUS
1075 extern bool pcie_ports_disabled;
1076 extern bool pcie_ports_auto;
1077 #else
1078 #define pcie_ports_disabled true
1079 #define pcie_ports_auto false
1080 #endif
1081
1082 #ifndef CONFIG_PCIEASPM
1083 static inline int pcie_aspm_enabled(void) { return 0; }
1084 static inline bool pcie_aspm_support_enabled(void) { return false; }
1085 #else
1086 extern int pcie_aspm_enabled(void);
1087 extern bool pcie_aspm_support_enabled(void);
1088 #endif
1089
1090 #ifdef CONFIG_PCIEAER
1091 void pci_no_aer(void);
1092 bool pci_aer_available(void);
1093 #else
1094 static inline void pci_no_aer(void) { }
1095 static inline bool pci_aer_available(void) { return false; }
1096 #endif
1097
1098 #ifndef CONFIG_PCIE_ECRC
1099 static inline void pcie_set_ecrc_checking(struct pci_dev *dev)
1100 {
1101 return;
1102 }
1103 static inline void pcie_ecrc_get_policy(char *str) {};
1104 #else
1105 extern void pcie_set_ecrc_checking(struct pci_dev *dev);
1106 extern void pcie_ecrc_get_policy(char *str);
1107 #endif
1108
1109 #define pci_enable_msi(pdev) pci_enable_msi_block(pdev, 1)
1110
1111 #ifdef CONFIG_HT_IRQ
1112 /* The functions a driver should call */
1113 int ht_create_irq(struct pci_dev *dev, int idx);
1114 void ht_destroy_irq(unsigned int irq);
1115 #endif /* CONFIG_HT_IRQ */
1116
1117 extern void pci_cfg_access_lock(struct pci_dev *dev);
1118 extern bool pci_cfg_access_trylock(struct pci_dev *dev);
1119 extern void pci_cfg_access_unlock(struct pci_dev *dev);
1120
1121 /*
1122 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1123 * a PCI domain is defined to be a set of PCI busses which share
1124 * configuration space.
1125 */
1126 #ifdef CONFIG_PCI_DOMAINS
1127 extern int pci_domains_supported;
1128 #else
1129 enum { pci_domains_supported = 0 };
1130 static inline int pci_domain_nr(struct pci_bus *bus)
1131 {
1132 return 0;
1133 }
1134
1135 static inline int pci_proc_domain(struct pci_bus *bus)
1136 {
1137 return 0;
1138 }
1139 #endif /* CONFIG_PCI_DOMAINS */
1140
1141 /* some architectures require additional setup to direct VGA traffic */
1142 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1143 unsigned int command_bits, u32 flags);
1144 extern void pci_register_set_vga_state(arch_set_vga_state_t func);
1145
1146 #else /* CONFIG_PCI is not enabled */
1147
1148 /*
1149 * If the system does not have PCI, clearly these return errors. Define
1150 * these as simple inline functions to avoid hair in drivers.
1151 */
1152
1153 #define _PCI_NOP(o, s, t) \
1154 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1155 int where, t val) \
1156 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1157
1158 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1159 _PCI_NOP(o, word, u16 x) \
1160 _PCI_NOP(o, dword, u32 x)
1161 _PCI_NOP_ALL(read, *)
1162 _PCI_NOP_ALL(write,)
1163
1164 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1165 unsigned int device,
1166 struct pci_dev *from)
1167 {
1168 return NULL;
1169 }
1170
1171 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1172 unsigned int device,
1173 unsigned int ss_vendor,
1174 unsigned int ss_device,
1175 struct pci_dev *from)
1176 {
1177 return NULL;
1178 }
1179
1180 static inline struct pci_dev *pci_get_class(unsigned int class,
1181 struct pci_dev *from)
1182 {
1183 return NULL;
1184 }
1185
1186 #define pci_dev_present(ids) (0)
1187 #define no_pci_devices() (1)
1188 #define pci_dev_put(dev) do { } while (0)
1189
1190 static inline void pci_set_master(struct pci_dev *dev)
1191 { }
1192
1193 static inline int pci_enable_device(struct pci_dev *dev)
1194 {
1195 return -EIO;
1196 }
1197
1198 static inline void pci_disable_device(struct pci_dev *dev)
1199 { }
1200
1201 static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
1202 {
1203 return -EIO;
1204 }
1205
1206 static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
1207 {
1208 return -EIO;
1209 }
1210
1211 static inline int pci_set_dma_max_seg_size(struct pci_dev *dev,
1212 unsigned int size)
1213 {
1214 return -EIO;
1215 }
1216
1217 static inline int pci_set_dma_seg_boundary(struct pci_dev *dev,
1218 unsigned long mask)
1219 {
1220 return -EIO;
1221 }
1222
1223 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1224 {
1225 return -EBUSY;
1226 }
1227
1228 static inline int __pci_register_driver(struct pci_driver *drv,
1229 struct module *owner)
1230 {
1231 return 0;
1232 }
1233
1234 static inline int pci_register_driver(struct pci_driver *drv)
1235 {
1236 return 0;
1237 }
1238
1239 static inline void pci_unregister_driver(struct pci_driver *drv)
1240 { }
1241
1242 static inline int pci_find_capability(struct pci_dev *dev, int cap)
1243 {
1244 return 0;
1245 }
1246
1247 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1248 int cap)
1249 {
1250 return 0;
1251 }
1252
1253 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1254 {
1255 return 0;
1256 }
1257
1258 /* Power management related routines */
1259 static inline int pci_save_state(struct pci_dev *dev)
1260 {
1261 return 0;
1262 }
1263
1264 static inline void pci_restore_state(struct pci_dev *dev)
1265 { }
1266
1267 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1268 {
1269 return 0;
1270 }
1271
1272 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1273 {
1274 return 0;
1275 }
1276
1277 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1278 pm_message_t state)
1279 {
1280 return PCI_D0;
1281 }
1282
1283 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1284 int enable)
1285 {
1286 return 0;
1287 }
1288
1289 static inline void pci_enable_ido(struct pci_dev *dev, unsigned long type)
1290 {
1291 }
1292
1293 static inline void pci_disable_ido(struct pci_dev *dev, unsigned long type)
1294 {
1295 }
1296
1297 static inline int pci_enable_obff(struct pci_dev *dev, unsigned long type)
1298 {
1299 return 0;
1300 }
1301
1302 static inline void pci_disable_obff(struct pci_dev *dev)
1303 {
1304 }
1305
1306 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1307 {
1308 return -EIO;
1309 }
1310
1311 static inline void pci_release_regions(struct pci_dev *dev)
1312 { }
1313
1314 #define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
1315
1316 static inline void pci_block_cfg_access(struct pci_dev *dev)
1317 { }
1318
1319 static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev)
1320 { return 0; }
1321
1322 static inline void pci_unblock_cfg_access(struct pci_dev *dev)
1323 { }
1324
1325 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1326 { return NULL; }
1327
1328 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1329 unsigned int devfn)
1330 { return NULL; }
1331
1332 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1333 unsigned int devfn)
1334 { return NULL; }
1335
1336 static inline int pci_domain_nr(struct pci_bus *bus)
1337 { return 0; }
1338
1339 #define dev_is_pci(d) (false)
1340 #define dev_is_pf(d) (false)
1341 #define dev_num_vf(d) (0)
1342 #endif /* CONFIG_PCI */
1343
1344 /* Include architecture-dependent settings and functions */
1345
1346 #include <asm/pci.h>
1347
1348 #ifndef PCIBIOS_MAX_MEM_32
1349 #define PCIBIOS_MAX_MEM_32 (-1)
1350 #endif
1351
1352 /* these helpers provide future and backwards compatibility
1353 * for accessing popular PCI BAR info */
1354 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1355 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1356 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1357 #define pci_resource_len(dev,bar) \
1358 ((pci_resource_start((dev), (bar)) == 0 && \
1359 pci_resource_end((dev), (bar)) == \
1360 pci_resource_start((dev), (bar))) ? 0 : \
1361 \
1362 (pci_resource_end((dev), (bar)) - \
1363 pci_resource_start((dev), (bar)) + 1))
1364
1365 /* Similar to the helpers above, these manipulate per-pci_dev
1366 * driver-specific data. They are really just a wrapper around
1367 * the generic device structure functions of these calls.
1368 */
1369 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1370 {
1371 return dev_get_drvdata(&pdev->dev);
1372 }
1373
1374 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1375 {
1376 dev_set_drvdata(&pdev->dev, data);
1377 }
1378
1379 /* If you want to know what to call your pci_dev, ask this function.
1380 * Again, it's a wrapper around the generic device.
1381 */
1382 static inline const char *pci_name(const struct pci_dev *pdev)
1383 {
1384 return dev_name(&pdev->dev);
1385 }
1386
1387
1388 /* Some archs don't want to expose struct resource to userland as-is
1389 * in sysfs and /proc
1390 */
1391 #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
1392 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1393 const struct resource *rsrc, resource_size_t *start,
1394 resource_size_t *end)
1395 {
1396 *start = rsrc->start;
1397 *end = rsrc->end;
1398 }
1399 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1400
1401
1402 /*
1403 * The world is not perfect and supplies us with broken PCI devices.
1404 * For at least a part of these bugs we need a work-around, so both
1405 * generic (drivers/pci/quirks.c) and per-architecture code can define
1406 * fixup hooks to be called for particular buggy devices.
1407 */
1408
1409 struct pci_fixup {
1410 u16 vendor; /* You can use PCI_ANY_ID here of course */
1411 u16 device; /* You can use PCI_ANY_ID here of course */
1412 u32 class; /* You can use PCI_ANY_ID here too */
1413 unsigned int class_shift; /* should be 0, 8, 16 */
1414 void (*hook)(struct pci_dev *dev);
1415 };
1416
1417 enum pci_fixup_pass {
1418 pci_fixup_early, /* Before probing BARs */
1419 pci_fixup_header, /* After reading configuration header */
1420 pci_fixup_final, /* Final phase of device fixups */
1421 pci_fixup_enable, /* pci_enable_device() time */
1422 pci_fixup_resume, /* pci_device_resume() */
1423 pci_fixup_suspend, /* pci_device_suspend */
1424 pci_fixup_resume_early, /* pci_device_resume_early() */
1425 };
1426
1427 /* Anonymous variables would be nice... */
1428 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1429 class_shift, hook) \
1430 static const struct pci_fixup const __pci_fixup_##name __used \
1431 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1432 = { vendor, device, class, class_shift, hook };
1433
1434 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1435 class_shift, hook) \
1436 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1437 vendor##device##hook, vendor, device, class, class_shift, hook)
1438 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1439 class_shift, hook) \
1440 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1441 vendor##device##hook, vendor, device, class, class_shift, hook)
1442 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1443 class_shift, hook) \
1444 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1445 vendor##device##hook, vendor, device, class, class_shift, hook)
1446 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1447 class_shift, hook) \
1448 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1449 vendor##device##hook, vendor, device, class, class_shift, hook)
1450 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1451 class_shift, hook) \
1452 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1453 resume##vendor##device##hook, vendor, device, class, \
1454 class_shift, hook)
1455 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1456 class_shift, hook) \
1457 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1458 resume_early##vendor##device##hook, vendor, device, \
1459 class, class_shift, hook)
1460 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1461 class_shift, hook) \
1462 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1463 suspend##vendor##device##hook, vendor, device, class, \
1464 class_shift, hook)
1465
1466 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1467 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1468 vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1469 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1470 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1471 vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1472 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1473 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1474 vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1475 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1476 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1477 vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1478 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1479 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1480 resume##vendor##device##hook, vendor, device, \
1481 PCI_ANY_ID, 0, hook)
1482 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1483 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1484 resume_early##vendor##device##hook, vendor, device, \
1485 PCI_ANY_ID, 0, hook)
1486 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1487 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1488 suspend##vendor##device##hook, vendor, device, \
1489 PCI_ANY_ID, 0, hook)
1490
1491 #ifdef CONFIG_PCI_QUIRKS
1492 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1493 #else
1494 static inline void pci_fixup_device(enum pci_fixup_pass pass,
1495 struct pci_dev *dev) {}
1496 #endif
1497
1498 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1499 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1500 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1501 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
1502 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
1503 const char *name);
1504 void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
1505
1506 extern int pci_pci_problems;
1507 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1508 #define PCIPCI_TRITON 2
1509 #define PCIPCI_NATOMA 4
1510 #define PCIPCI_VIAETBF 8
1511 #define PCIPCI_VSFX 16
1512 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1513 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1514
1515 extern unsigned long pci_cardbus_io_size;
1516 extern unsigned long pci_cardbus_mem_size;
1517 extern u8 __devinitdata pci_dfl_cache_line_size;
1518 extern u8 pci_cache_line_size;
1519
1520 extern unsigned long pci_hotplug_io_size;
1521 extern unsigned long pci_hotplug_mem_size;
1522
1523 /* Architecture specific versions may override these (weak) */
1524 int pcibios_add_platform_entries(struct pci_dev *dev);
1525 void pcibios_disable_device(struct pci_dev *dev);
1526 void pcibios_set_master(struct pci_dev *dev);
1527 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1528 enum pcie_reset_state state);
1529
1530 #ifdef CONFIG_PCI_MMCONFIG
1531 extern void __init pci_mmcfg_early_init(void);
1532 extern void __init pci_mmcfg_late_init(void);
1533 #else
1534 static inline void pci_mmcfg_early_init(void) { }
1535 static inline void pci_mmcfg_late_init(void) { }
1536 #endif
1537
1538 int pci_ext_cfg_avail(struct pci_dev *dev);
1539
1540 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
1541
1542 #ifdef CONFIG_PCI_IOV
1543 extern int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1544 extern void pci_disable_sriov(struct pci_dev *dev);
1545 extern irqreturn_t pci_sriov_migration(struct pci_dev *dev);
1546 extern int pci_num_vf(struct pci_dev *dev);
1547 #else
1548 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
1549 {
1550 return -ENODEV;
1551 }
1552 static inline void pci_disable_sriov(struct pci_dev *dev)
1553 {
1554 }
1555 static inline irqreturn_t pci_sriov_migration(struct pci_dev *dev)
1556 {
1557 return IRQ_NONE;
1558 }
1559 static inline int pci_num_vf(struct pci_dev *dev)
1560 {
1561 return 0;
1562 }
1563 #endif
1564
1565 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1566 extern void pci_hp_create_module_link(struct pci_slot *pci_slot);
1567 extern void pci_hp_remove_module_link(struct pci_slot *pci_slot);
1568 #endif
1569
1570 /**
1571 * pci_pcie_cap - get the saved PCIe capability offset
1572 * @dev: PCI device
1573 *
1574 * PCIe capability offset is calculated at PCI device initialization
1575 * time and saved in the data structure. This function returns saved
1576 * PCIe capability offset. Using this instead of pci_find_capability()
1577 * reduces unnecessary search in the PCI configuration space. If you
1578 * need to calculate PCIe capability offset from raw device for some
1579 * reasons, please use pci_find_capability() instead.
1580 */
1581 static inline int pci_pcie_cap(struct pci_dev *dev)
1582 {
1583 return dev->pcie_cap;
1584 }
1585
1586 /**
1587 * pci_is_pcie - check if the PCI device is PCI Express capable
1588 * @dev: PCI device
1589 *
1590 * Retrun true if the PCI device is PCI Express capable, false otherwise.
1591 */
1592 static inline bool pci_is_pcie(struct pci_dev *dev)
1593 {
1594 return !!pci_pcie_cap(dev);
1595 }
1596
1597 void pci_request_acs(void);
1598
1599
1600 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
1601 #define PCI_VPD_LRDT_ID(x) (x | PCI_VPD_LRDT)
1602
1603 /* Large Resource Data Type Tag Item Names */
1604 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
1605 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
1606 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
1607
1608 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
1609 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
1610 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
1611
1612 /* Small Resource Data Type Tag Item Names */
1613 #define PCI_VPD_STIN_END 0x78 /* End */
1614
1615 #define PCI_VPD_SRDT_END PCI_VPD_STIN_END
1616
1617 #define PCI_VPD_SRDT_TIN_MASK 0x78
1618 #define PCI_VPD_SRDT_LEN_MASK 0x07
1619
1620 #define PCI_VPD_LRDT_TAG_SIZE 3
1621 #define PCI_VPD_SRDT_TAG_SIZE 1
1622
1623 #define PCI_VPD_INFO_FLD_HDR_SIZE 3
1624
1625 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
1626 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
1627 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
1628 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
1629
1630 /**
1631 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
1632 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
1633 *
1634 * Returns the extracted Large Resource Data Type length.
1635 */
1636 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
1637 {
1638 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
1639 }
1640
1641 /**
1642 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
1643 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
1644 *
1645 * Returns the extracted Small Resource Data Type length.
1646 */
1647 static inline u8 pci_vpd_srdt_size(const u8 *srdt)
1648 {
1649 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
1650 }
1651
1652 /**
1653 * pci_vpd_info_field_size - Extracts the information field length
1654 * @lrdt: Pointer to the beginning of an information field header
1655 *
1656 * Returns the extracted information field length.
1657 */
1658 static inline u8 pci_vpd_info_field_size(const u8 *info_field)
1659 {
1660 return info_field[2];
1661 }
1662
1663 /**
1664 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
1665 * @buf: Pointer to buffered vpd data
1666 * @off: The offset into the buffer at which to begin the search
1667 * @len: The length of the vpd buffer
1668 * @rdt: The Resource Data Type to search for
1669 *
1670 * Returns the index where the Resource Data Type was found or
1671 * -ENOENT otherwise.
1672 */
1673 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
1674
1675 /**
1676 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
1677 * @buf: Pointer to buffered vpd data
1678 * @off: The offset into the buffer at which to begin the search
1679 * @len: The length of the buffer area, relative to off, in which to search
1680 * @kw: The keyword to search for
1681 *
1682 * Returns the index where the information field keyword was found or
1683 * -ENOENT otherwise.
1684 */
1685 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
1686 unsigned int len, const char *kw);
1687
1688 /* PCI <-> OF binding helpers */
1689 #ifdef CONFIG_OF
1690 struct device_node;
1691 extern void pci_set_of_node(struct pci_dev *dev);
1692 extern void pci_release_of_node(struct pci_dev *dev);
1693 extern void pci_set_bus_of_node(struct pci_bus *bus);
1694 extern void pci_release_bus_of_node(struct pci_bus *bus);
1695
1696 /* Arch may override this (weak) */
1697 extern struct device_node * __weak pcibios_get_phb_of_node(struct pci_bus *bus);
1698
1699 static inline struct device_node *
1700 pci_device_to_OF_node(const struct pci_dev *pdev)
1701 {
1702 return pdev ? pdev->dev.of_node : NULL;
1703 }
1704
1705 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
1706 {
1707 return bus ? bus->dev.of_node : NULL;
1708 }
1709
1710 #else /* CONFIG_OF */
1711 static inline void pci_set_of_node(struct pci_dev *dev) { }
1712 static inline void pci_release_of_node(struct pci_dev *dev) { }
1713 static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
1714 static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
1715 #endif /* CONFIG_OF */
1716
1717 #ifdef CONFIG_EEH
1718 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
1719 {
1720 return pdev->dev.archdata.edev;
1721 }
1722 #endif
1723
1724 /**
1725 * pci_find_upstream_pcie_bridge - find upstream PCIe-to-PCI bridge of a device
1726 * @pdev: the PCI device
1727 *
1728 * if the device is PCIE, return NULL
1729 * if the device isn't connected to a PCIe bridge (that is its parent is a
1730 * legacy PCI bridge and the bridge is directly connected to bus 0), return its
1731 * parent
1732 */
1733 struct pci_dev *pci_find_upstream_pcie_bridge(struct pci_dev *pdev);
1734
1735 #endif /* __KERNEL__ */
1736 #endif /* LINUX_PCI_H */
Linus' kernel tree