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ARM: at91: add pinctrl support
[linux-2.6.git] / drivers / pinctrl / pinctrl-at91.c
blob01bf92459fdca71934f5776ee84e41ce78b69919
1 /*
2 * at91 pinctrl driver based on at91 pinmux core
3 *
4 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Under GPLv2 only
7 */
8
9 #include <linux/clk.h>
10 #include <linux/err.h>
11 #include <linux/init.h>
12 #include <linux/module.h>
13 #include <linux/of.h>
14 #include <linux/of_device.h>
15 #include <linux/of_address.h>
16 #include <linux/of_irq.h>
17 #include <linux/slab.h>
18 #include <linux/interrupt.h>
19 #include <linux/irq.h>
20 #include <linux/irqdomain.h>
21 #include <linux/io.h>
22 #include <linux/gpio.h>
23 #include <linux/irqdomain.h>
24 #include <linux/pinctrl/machine.h>
25 #include <linux/pinctrl/pinconf.h>
26 #include <linux/pinctrl/pinctrl.h>
27 #include <linux/pinctrl/pinmux.h>
28 /* Since we request GPIOs from ourself */
29 #include <linux/pinctrl/consumer.h>
30
31 #include <asm/mach/irq.h>
32
33 #include <mach/hardware.h>
34 #include <mach/at91_pio.h>
35
36 #include "core.h"
37
38 #define MAX_NB_GPIO_PER_BANK 32
39
40 struct at91_pinctrl_mux_ops;
41
42 struct at91_gpio_chip {
43 struct gpio_chip chip;
44 struct pinctrl_gpio_range range;
45 struct at91_gpio_chip *next; /* Bank sharing same clock */
46 int pioc_hwirq; /* PIO bank interrupt identifier on AIC */
47 int pioc_virq; /* PIO bank Linux virtual interrupt */
48 int pioc_idx; /* PIO bank index */
49 void __iomem *regbase; /* PIO bank virtual address */
50 struct clk *clock; /* associated clock */
51 struct irq_domain *domain; /* associated irq domain */
52 struct at91_pinctrl_mux_ops *ops; /* ops */
53 };
54
55 #define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip)
56
57 static struct at91_gpio_chip *gpio_chips[MAX_GPIO_BANKS];
58
59 static int gpio_banks;
60
61 #define PULL_UP (0 << 1)
62 #define MULTI_DRIVE (1 << 1)
63
64 /**
65 * struct at91_pmx_func - describes AT91 pinmux functions
66 * @name: the name of this specific function
67 * @groups: corresponding pin groups
68 * @ngroups: the number of groups
69 */
70 struct at91_pmx_func {
71 const char *name;
72 const char **groups;
73 unsigned ngroups;
74 };
75
76 enum at91_mux {
77 AT91_MUX_GPIO = 0,
78 AT91_MUX_PERIPH_A = 1,
79 AT91_MUX_PERIPH_B = 2,
80 AT91_MUX_PERIPH_C = 3,
81 AT91_MUX_PERIPH_D = 4,
82 };
83
84 /**
85 * struct at91_pmx_pin - describes an At91 pin mux
86 * @bank: the bank of the pin
87 * @pin: the pin number in the @bank
88 * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function.
89 * @conf: the configuration of the pin: PULL_UP, MULTIDRIVE etc...
90 */
91 struct at91_pmx_pin {
92 uint32_t bank;
93 uint32_t pin;
94 enum at91_mux mux;
95 unsigned long conf;
96 };
97
98 /**
99 * struct at91_pin_group - describes an At91 pin group
100 * @name: the name of this specific pin group
101 * @pins_conf: the mux mode for each pin in this group. The size of this
102 * array is the same as pins.
103 * @pins: an array of discrete physical pins used in this group, taken
104 * from the driver-local pin enumeration space
105 * @npins: the number of pins in this group array, i.e. the number of
106 * elements in .pins so we can iterate over that array
107 */
108 struct at91_pin_group {
109 const char *name;
110 struct at91_pmx_pin *pins_conf;
111 unsigned int *pins;
112 unsigned npins;
113 };
114
115 /**
116 * struct at91_pinctrl_mux_ops - describes an At91 mux ops group
117 * on new IP with support for periph C and D the way to mux in
118 * periph A and B has changed
119 * So provide the right call back
120 * if not present means the IP does not support it
121 * @get_periph: return the periph mode configured
122 * @mux_A_periph: mux as periph A
123 * @mux_B_periph: mux as periph B
124 * @mux_C_periph: mux as periph C
125 * @mux_D_periph: mux as periph D
126 * @irq_type: return irq type
127 */
128 struct at91_pinctrl_mux_ops {
129 enum at91_mux (*get_periph)(void __iomem *pio, unsigned mask);
130 void (*mux_A_periph)(void __iomem *pio, unsigned mask);
131 void (*mux_B_periph)(void __iomem *pio, unsigned mask);
132 void (*mux_C_periph)(void __iomem *pio, unsigned mask);
133 void (*mux_D_periph)(void __iomem *pio, unsigned mask);
134 /* irq */
135 int (*irq_type)(struct irq_data *d, unsigned type);
136 };
137
138 static int gpio_irq_type(struct irq_data *d, unsigned type);
139 static int alt_gpio_irq_type(struct irq_data *d, unsigned type);
140
141 struct at91_pinctrl {
142 struct device *dev;
143 struct pinctrl_dev *pctl;
144
145 int nbanks;
146
147 uint32_t *mux_mask;
148 int nmux;
149
150 struct at91_pmx_func *functions;
151 int nfunctions;
152
153 struct at91_pin_group *groups;
154 int ngroups;
155
156 struct at91_pinctrl_mux_ops *ops;
157 };
158
159 static const inline struct at91_pin_group *at91_pinctrl_find_group_by_name(
160 const struct at91_pinctrl *info,
161 const char *name)
162 {
163 const struct at91_pin_group *grp = NULL;
164 int i;
165
166 for (i = 0; i < info->ngroups; i++) {
167 if (strcmp(info->groups[i].name, name))
168 continue;
169
170 grp = &info->groups[i];
171 dev_dbg(info->dev, "%s: %d 0:%d\n", name, grp->npins, grp->pins[0]);
172 break;
173 }
174
175 return grp;
176 }
177
178 static int at91_get_groups_count(struct pinctrl_dev *pctldev)
179 {
180 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
181
182 return info->ngroups;
183 }
184
185 static const char *at91_get_group_name(struct pinctrl_dev *pctldev,
186 unsigned selector)
187 {
188 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
189
190 return info->groups[selector].name;
191 }
192
193 static int at91_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
194 const unsigned **pins,
195 unsigned *npins)
196 {
197 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
198
199 if (selector >= info->ngroups)
200 return -EINVAL;
201
202 *pins = info->groups[selector].pins;
203 *npins = info->groups[selector].npins;
204
205 return 0;
206 }
207
208 static void at91_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
209 unsigned offset)
210 {
211 seq_printf(s, "%s", dev_name(pctldev->dev));
212 }
213
214 static int at91_dt_node_to_map(struct pinctrl_dev *pctldev,
215 struct device_node *np,
216 struct pinctrl_map **map, unsigned *num_maps)
217 {
218 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
219 const struct at91_pin_group *grp;
220 struct pinctrl_map *new_map;
221 struct device_node *parent;
222 int map_num = 1;
223 int i;
224 struct at91_pmx_pin *pin;
225
226 /*
227 * first find the group of this node and check if we need create
228 * config maps for pins
229 */
230 grp = at91_pinctrl_find_group_by_name(info, np->name);
231 if (!grp) {
232 dev_err(info->dev, "unable to find group for node %s\n",
233 np->name);
234 return -EINVAL;
235 }
236
237 map_num += grp->npins;
238 new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num, GFP_KERNEL);
239 if (!new_map)
240 return -ENOMEM;
241
242 *map = new_map;
243 *num_maps = map_num;
244
245 /* create mux map */
246 parent = of_get_parent(np);
247 if (!parent) {
248 kfree(new_map);
249 return -EINVAL;
250 }
251 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
252 new_map[0].data.mux.function = parent->name;
253 new_map[0].data.mux.group = np->name;
254 of_node_put(parent);
255
256 /* create config map */
257 new_map++;
258 for (i = 0; i < grp->npins; i++) {
259 pin = &grp->pins_conf[i];
260
261 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
262 new_map[i].data.configs.group_or_pin =
263 pin_get_name(pctldev, grp->pins[i]);
264 new_map[i].data.configs.configs = &grp->pins_conf[i].conf;
265 new_map[i].data.configs.num_configs = 1;
266 }
267
268 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
269 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
270
271 return 0;
272 }
273
274 static void at91_dt_free_map(struct pinctrl_dev *pctldev,
275 struct pinctrl_map *map, unsigned num_maps)
276 {
277 }
278
279 static struct pinctrl_ops at91_pctrl_ops = {
280 .get_groups_count = at91_get_groups_count,
281 .get_group_name = at91_get_group_name,
282 .get_group_pins = at91_get_group_pins,
283 .pin_dbg_show = at91_pin_dbg_show,
284 .dt_node_to_map = at91_dt_node_to_map,
285 .dt_free_map = at91_dt_free_map,
286 };
287
288 static void __iomem * pin_to_controller(struct at91_pinctrl *info,
289 unsigned int bank)
290 {
291 return gpio_chips[bank]->regbase;
292 }
293
294 static inline int pin_to_bank(unsigned pin)
295 {
296 return pin /= MAX_NB_GPIO_PER_BANK;
297 }
298
299 static unsigned pin_to_mask(unsigned int pin)
300 {
301 return 1 << pin;
302 }
303
304 static void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask)
305 {
306 writel_relaxed(mask, pio + PIO_IDR);
307 }
308
309 static unsigned at91_mux_get_pullup(void __iomem *pio, unsigned pin)
310 {
311 return (readl_relaxed(pio + PIO_PUSR) >> pin) & 0x1;
312 }
313
314 static void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on)
315 {
316 writel_relaxed(mask, pio + (on ? PIO_PUER : PIO_PUDR));
317 }
318
319 static unsigned at91_mux_get_multidrive(void __iomem *pio, unsigned pin)
320 {
321 return (readl_relaxed(pio + PIO_MDSR) >> pin) & 0x1;
322 }
323
324 static void at91_mux_set_multidrive(void __iomem *pio, unsigned mask, bool on)
325 {
326 writel_relaxed(mask, pio + (on ? PIO_MDER : PIO_MDDR));
327 }
328
329 static void at91_mux_set_A_periph(void __iomem *pio, unsigned mask)
330 {
331 writel_relaxed(mask, pio + PIO_ASR);
332 }
333
334 static void at91_mux_set_B_periph(void __iomem *pio, unsigned mask)
335 {
336 writel_relaxed(mask, pio + PIO_BSR);
337 }
338
339 static void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned mask)
340 {
341
342 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask,
343 pio + PIO_ABCDSR1);
344 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask,
345 pio + PIO_ABCDSR2);
346 }
347
348 static void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned mask)
349 {
350 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask,
351 pio + PIO_ABCDSR1);
352 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask,
353 pio + PIO_ABCDSR2);
354 }
355
356 static void at91_mux_pio3_set_C_periph(void __iomem *pio, unsigned mask)
357 {
358 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1);
359 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
360 }
361
362 static void at91_mux_pio3_set_D_periph(void __iomem *pio, unsigned mask)
363 {
364 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1);
365 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
366 }
367
368 static enum at91_mux at91_mux_pio3_get_periph(void __iomem *pio, unsigned mask)
369 {
370 unsigned select;
371
372 if (readl_relaxed(pio + PIO_PSR) & mask)
373 return AT91_MUX_GPIO;
374
375 select = !!(readl_relaxed(pio + PIO_ABCDSR1) & mask);
376 select |= (!!(readl_relaxed(pio + PIO_ABCDSR2) & mask) << 1);
377
378 return select + 1;
379 }
380
381 static enum at91_mux at91_mux_get_periph(void __iomem *pio, unsigned mask)
382 {
383 unsigned select;
384
385 if (readl_relaxed(pio + PIO_PSR) & mask)
386 return AT91_MUX_GPIO;
387
388 select = readl_relaxed(pio + PIO_ABSR) & mask;
389
390 return select + 1;
391 }
392
393 static struct at91_pinctrl_mux_ops at91rm9200_ops = {
394 .get_periph = at91_mux_get_periph,
395 .mux_A_periph = at91_mux_set_A_periph,
396 .mux_B_periph = at91_mux_set_B_periph,
397 .irq_type = gpio_irq_type,
398 };
399
400 static struct at91_pinctrl_mux_ops at91sam9x5_ops = {
401 .get_periph = at91_mux_pio3_get_periph,
402 .mux_A_periph = at91_mux_pio3_set_A_periph,
403 .mux_B_periph = at91_mux_pio3_set_B_periph,
404 .mux_C_periph = at91_mux_pio3_set_C_periph,
405 .mux_D_periph = at91_mux_pio3_set_D_periph,
406 .irq_type = alt_gpio_irq_type,
407 };
408
409 static void at91_pin_dbg(const struct device *dev, const struct at91_pmx_pin *pin)
410 {
411 if (pin->mux) {
412 dev_dbg(dev, "pio%c%d configured as periph%c with conf = 0x%lu\n",
413 pin->bank + 'A', pin->pin, pin->mux - 1 + 'A', pin->conf);
414 } else {
415 dev_dbg(dev, "pio%c%d configured as gpio with conf = 0x%lu\n",
416 pin->bank + 'A', pin->pin, pin->conf);
417 }
418 }
419
420 static int pin_check_config(struct at91_pinctrl *info, const char* name,
421 int index, const struct at91_pmx_pin *pin)
422 {
423 int mux;
424
425 /* check if it's a valid config */
426 if (pin->bank >= info->nbanks) {
427 dev_err(info->dev, "%s: pin conf %d bank_id %d >= nbanks %d\n",
428 name, index, pin->bank, info->nbanks);
429 return -EINVAL;
430 }
431
432 if (pin->pin >= MAX_NB_GPIO_PER_BANK) {
433 dev_err(info->dev, "%s: pin conf %d pin_bank_id %d >= %d\n",
434 name, index, pin->pin, MAX_NB_GPIO_PER_BANK);
435 return -EINVAL;
436 }
437
438 if (!pin->mux)
439 return 0;
440
441 mux = pin->mux - 1;
442
443 if (mux >= info->nmux) {
444 dev_err(info->dev, "%s: pin conf %d mux_id %d >= nmux %d\n",
445 name, index, mux, info->nmux);
446 return -EINVAL;
447 }
448
449 if (!(info->mux_mask[pin->bank * info->nmux + mux] & 1 << pin->pin)) {
450 dev_err(info->dev, "%s: pin conf %d mux_id %d not supported for pio%c%d\n",
451 name, index, mux, pin->bank + 'A', pin->pin);
452 return -EINVAL;
453 }
454
455 return 0;
456 }
457
458 static void at91_mux_gpio_disable(void __iomem *pio, unsigned mask)
459 {
460 writel_relaxed(mask, pio + PIO_PDR);
461 }
462
463 static void at91_mux_gpio_enable(void __iomem *pio, unsigned mask, bool input)
464 {
465 writel_relaxed(mask, pio + PIO_PER);
466 writel_relaxed(mask, pio + (input ? PIO_ODR : PIO_OER));
467 }
468
469 static int at91_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
470 unsigned group)
471 {
472 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
473 const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf;
474 const struct at91_pmx_pin *pin;
475 uint32_t npins = info->groups[group].npins;
476 int i, ret;
477 unsigned mask;
478 void __iomem *pio;
479
480 dev_dbg(info->dev, "enable function %s group %s\n",
481 info->functions[selector].name, info->groups[group].name);
482
483 /* first check that all the pins of the group are valid with a valid
484 * paramter */
485 for (i = 0; i < npins; i++) {
486 pin = &pins_conf[i];
487 ret = pin_check_config(info, info->groups[group].name, i, pin);
488 if (ret)
489 return ret;
490 }
491
492 for (i = 0; i < npins; i++) {
493 pin = &pins_conf[i];
494 at91_pin_dbg(info->dev, pin);
495 pio = pin_to_controller(info, pin->bank);
496 mask = pin_to_mask(pin->pin);
497 at91_mux_disable_interrupt(pio, mask);
498 switch(pin->mux) {
499 case AT91_MUX_GPIO:
500 at91_mux_gpio_enable(pio, mask, 1);
501 break;
502 case AT91_MUX_PERIPH_A:
503 info->ops->mux_A_periph(pio, mask);
504 break;
505 case AT91_MUX_PERIPH_B:
506 info->ops->mux_B_periph(pio, mask);
507 break;
508 case AT91_MUX_PERIPH_C:
509 if (!info->ops->mux_C_periph)
510 return -EINVAL;
511 info->ops->mux_C_periph(pio, mask);
512 break;
513 case AT91_MUX_PERIPH_D:
514 if (!info->ops->mux_D_periph)
515 return -EINVAL;
516 info->ops->mux_D_periph(pio, mask);
517 break;
518 }
519 if (pin->mux)
520 at91_mux_gpio_disable(pio, mask);
521 }
522
523 return 0;
524 }
525
526 static void at91_pmx_disable(struct pinctrl_dev *pctldev, unsigned selector,
527 unsigned group)
528 {
529 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
530 const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf;
531 const struct at91_pmx_pin *pin;
532 uint32_t npins = info->groups[group].npins;
533 int i;
534 unsigned mask;
535 void __iomem *pio;
536
537 for (i = 0; i < npins; i++) {
538 pin = &pins_conf[i];
539 at91_pin_dbg(info->dev, pin);
540 pio = pin_to_controller(info, pin->bank);
541 mask = pin_to_mask(pin->pin);
542 at91_mux_gpio_enable(pio, mask, 1);
543 }
544 }
545
546 static int at91_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
547 {
548 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
549
550 return info->nfunctions;
551 }
552
553 static const char *at91_pmx_get_func_name(struct pinctrl_dev *pctldev,
554 unsigned selector)
555 {
556 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
557
558 return info->functions[selector].name;
559 }
560
561 static int at91_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
562 const char * const **groups,
563 unsigned * const num_groups)
564 {
565 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
566
567 *groups = info->functions[selector].groups;
568 *num_groups = info->functions[selector].ngroups;
569
570 return 0;
571 }
572
573 int at91_gpio_request_enable(struct pinctrl_dev *pctldev,
574 struct pinctrl_gpio_range *range,
575 unsigned offset)
576 {
577 struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
578 struct at91_gpio_chip *at91_chip;
579 struct gpio_chip *chip;
580 unsigned mask;
581
582 if (!range) {
583 dev_err(npct->dev, "invalid range\n");
584 return -EINVAL;
585 }
586 if (!range->gc) {
587 dev_err(npct->dev, "missing GPIO chip in range\n");
588 return -EINVAL;
589 }
590 chip = range->gc;
591 at91_chip = container_of(chip, struct at91_gpio_chip, chip);
592
593 dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
594
595 mask = 1 << (offset - chip->base);
596
597 dev_dbg(npct->dev, "enable pin %u as PIO%c%d 0x%x\n",
598 offset, 'A' + range->id, offset - chip->base, mask);
599
600 writel_relaxed(mask, at91_chip->regbase + PIO_PER);
601
602 return 0;
603 }
604
605 void at91_gpio_disable_free(struct pinctrl_dev *pctldev,
606 struct pinctrl_gpio_range *range,
607 unsigned offset)
608 {
609 struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
610
611 dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
612 /* Set the pin to some default state, GPIO is usually default */
613 }
614
615 static struct pinmux_ops at91_pmx_ops = {
616 .get_functions_count = at91_pmx_get_funcs_count,
617 .get_function_name = at91_pmx_get_func_name,
618 .get_function_groups = at91_pmx_get_groups,
619 .enable = at91_pmx_enable,
620 .disable = at91_pmx_disable,
621 .gpio_request_enable = at91_gpio_request_enable,
622 .gpio_disable_free = at91_gpio_disable_free,
623 };
624
625 static int at91_pinconf_get(struct pinctrl_dev *pctldev,
626 unsigned pin_id, unsigned long *config)
627 {
628 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
629 void __iomem *pio;
630 unsigned pin;
631
632 dev_dbg(info->dev, "%s:%d, pin_id=%d, config=0x%lx", __func__, __LINE__, pin_id, *config);
633 pio = pin_to_controller(info, pin_to_bank(pin_id));
634 pin = pin_id % MAX_NB_GPIO_PER_BANK;
635
636 if (at91_mux_get_multidrive(pio, pin))
637 *config |= MULTI_DRIVE;
638
639 if (at91_mux_get_pullup(pio, pin))
640 *config |= PULL_UP;
641
642 return 0;
643 }
644
645 static int at91_pinconf_set(struct pinctrl_dev *pctldev,
646 unsigned pin_id, unsigned long config)
647 {
648 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
649 unsigned mask;
650 void __iomem *pio;
651
652 dev_dbg(info->dev, "%s:%d, pin_id=%d, config=0x%lx", __func__, __LINE__, pin_id, config);
653 pio = pin_to_controller(info, pin_to_bank(pin_id));
654 mask = pin_to_mask(pin_id % MAX_NB_GPIO_PER_BANK);
655
656 at91_mux_set_pullup(pio, mask, config & PULL_UP);
657 at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE);
658 return 0;
659 }
660
661 static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev,
662 struct seq_file *s, unsigned pin_id)
663 {
664
665 }
666
667 static void at91_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
668 struct seq_file *s, unsigned group)
669 {
670 }
671
672 struct pinconf_ops at91_pinconf_ops = {
673 .pin_config_get = at91_pinconf_get,
674 .pin_config_set = at91_pinconf_set,
675 .pin_config_dbg_show = at91_pinconf_dbg_show,
676 .pin_config_group_dbg_show = at91_pinconf_group_dbg_show,
677 };
678
679 static struct pinctrl_desc at91_pinctrl_desc = {
680 .pctlops = &at91_pctrl_ops,
681 .pmxops = &at91_pmx_ops,
682 .confops = &at91_pinconf_ops,
683 .owner = THIS_MODULE,
684 };
685
686 static const char *gpio_compat = "atmel,at91rm9200-gpio";
687
688 static void __devinit at91_pinctrl_child_count(struct at91_pinctrl *info,
689 struct device_node *np)
690 {
691 struct device_node *child;
692
693 for_each_child_of_node(np, child) {
694 if (of_device_is_compatible(child, gpio_compat)) {
695 info->nbanks++;
696 } else {
697 info->nfunctions++;
698 info->ngroups += of_get_child_count(child);
699 }
700 }
701 }
702
703 static int __devinit at91_pinctrl_mux_mask(struct at91_pinctrl *info,
704 struct device_node *np)
705 {
706 int ret = 0;
707 int size;
708 const const __be32 *list;
709
710 list = of_get_property(np, "atmel,mux-mask", &size);
711 if (!list) {
712 dev_err(info->dev, "can not read the mux-mask of %d\n", size);
713 return -EINVAL;
714 }
715
716 size /= sizeof(*list);
717 if (!size || size % info->nbanks) {
718 dev_err(info->dev, "wrong mux mask array should be by %d\n", info->nbanks);
719 return -EINVAL;
720 }
721 info->nmux = size / info->nbanks;
722
723 info->mux_mask = devm_kzalloc(info->dev, sizeof(u32) * size, GFP_KERNEL);
724 if (!info->mux_mask) {
725 dev_err(info->dev, "could not alloc mux_mask\n");
726 return -ENOMEM;
727 }
728
729 ret = of_property_read_u32_array(np, "atmel,mux-mask",
730 info->mux_mask, size);
731 if (ret)
732 dev_err(info->dev, "can not read the mux-mask of %d\n", size);
733 return ret;
734 }
735
736 static int __devinit at91_pinctrl_parse_groups(struct device_node *np,
737 struct at91_pin_group *grp,
738 struct at91_pinctrl *info,
739 u32 index)
740 {
741 struct at91_pmx_pin *pin;
742 int size;
743 const const __be32 *list;
744 int i, j;
745
746 dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
747
748 /* Initialise group */
749 grp->name = np->name;
750
751 /*
752 * the binding format is atmel,pins = <bank pin mux CONFIG ...>,
753 * do sanity check and calculate pins number
754 */
755 list = of_get_property(np, "atmel,pins", &size);
756 /* we do not check return since it's safe node passed down */
757 size /= sizeof(*list);
758 if (!size || size % 4) {
759 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
760 return -EINVAL;
761 }
762
763 grp->npins = size / 4;
764 pin = grp->pins_conf = devm_kzalloc(info->dev, grp->npins * sizeof(struct at91_pmx_pin),
765 GFP_KERNEL);
766 grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
767 GFP_KERNEL);
768 if (!grp->pins_conf || !grp->pins)
769 return -ENOMEM;
770
771 for (i = 0, j = 0; i < size; i += 4, j++) {
772 pin->bank = be32_to_cpu(*list++);
773 pin->pin = be32_to_cpu(*list++);
774 grp->pins[j] = pin->bank * MAX_NB_GPIO_PER_BANK + pin->pin;
775 pin->mux = be32_to_cpu(*list++);
776 pin->conf = be32_to_cpu(*list++);
777
778 at91_pin_dbg(info->dev, pin);
779 pin++;
780 }
781
782 return 0;
783 }
784
785 static int __devinit at91_pinctrl_parse_functions(struct device_node *np,
786 struct at91_pinctrl *info, u32 index)
787 {
788 struct device_node *child;
789 struct at91_pmx_func *func;
790 struct at91_pin_group *grp;
791 int ret;
792 static u32 grp_index;
793 u32 i = 0;
794
795 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
796
797 func = &info->functions[index];
798
799 /* Initialise function */
800 func->name = np->name;
801 func->ngroups = of_get_child_count(np);
802 if (func->ngroups <= 0) {
803 dev_err(info->dev, "no groups defined\n");
804 return -EINVAL;
805 }
806 func->groups = devm_kzalloc(info->dev,
807 func->ngroups * sizeof(char *), GFP_KERNEL);
808 if (!func->groups)
809 return -ENOMEM;
810
811 for_each_child_of_node(np, child) {
812 func->groups[i] = child->name;
813 grp = &info->groups[grp_index++];
814 ret = at91_pinctrl_parse_groups(child, grp, info, i++);
815 if (ret)
816 return ret;
817 }
818
819 return 0;
820 }
821
822 static struct of_device_id at91_pinctrl_of_match[] __devinitdata = {
823 { .compatible = "atmel,at91sam9x5-pinctrl", .data = &at91sam9x5_ops },
824 { .compatible = "atmel,at91rm9200-pinctrl", .data = &at91rm9200_ops },
825 { /* sentinel */ }
826 };
827
828 static int __devinit at91_pinctrl_probe_dt(struct platform_device *pdev,
829 struct at91_pinctrl *info)
830 {
831 int ret = 0;
832 int i, j;
833 uint32_t *tmp;
834 struct device_node *np = pdev->dev.of_node;
835 struct device_node *child;
836
837 if (!np)
838 return -ENODEV;
839
840 info->dev = &pdev->dev;
841 info->ops =
842 of_match_device(at91_pinctrl_of_match, &pdev->dev)->data;
843 at91_pinctrl_child_count(info, np);
844
845 if (info->nbanks < 1) {
846 dev_err(&pdev->dev, "you need to specify atleast one gpio-controller\n");
847 return -EINVAL;
848 }
849
850 ret = at91_pinctrl_mux_mask(info, np);
851 if (ret)
852 return ret;
853
854 dev_dbg(&pdev->dev, "nmux = %d\n", info->nmux);
855
856 dev_dbg(&pdev->dev, "mux-mask\n");
857 tmp = info->mux_mask;
858 for (i = 0; i < info->nbanks; i++) {
859 for (j = 0; j < info->nmux; j++, tmp++) {
860 dev_dbg(&pdev->dev, "%d:%d\t0x%x\n", i, j, tmp[0]);
861 }
862 }
863
864 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
865 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
866 info->functions = devm_kzalloc(&pdev->dev, info->nfunctions * sizeof(struct at91_pmx_func),
867 GFP_KERNEL);
868 if (!info->functions)
869 return -ENOMEM;
870
871 info->groups = devm_kzalloc(&pdev->dev, info->ngroups * sizeof(struct at91_pin_group),
872 GFP_KERNEL);
873 if (!info->groups)
874 return -ENOMEM;
875
876 dev_dbg(&pdev->dev, "nbanks = %d\n", info->nbanks);
877 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
878 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
879
880 i = 0;
881
882 for_each_child_of_node(np, child) {
883 if (of_device_is_compatible(child, gpio_compat))
884 continue;
885 ret = at91_pinctrl_parse_functions(child, info, i++);
886 if (ret) {
887 dev_err(&pdev->dev, "failed to parse function\n");
888 return ret;
889 }
890 }
891
892 return 0;
893 }
894
895 static int __devinit at91_pinctrl_probe(struct platform_device *pdev)
896 {
897 struct at91_pinctrl *info;
898 struct pinctrl_pin_desc *pdesc;
899 int ret, i, j ,k;
900
901 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
902 if (!info)
903 return -ENOMEM;
904
905 ret = at91_pinctrl_probe_dt(pdev, info);
906 if (ret)
907 return ret;
908
909 /*
910 * We need all the GPIO drivers to probe FIRST, or we will not be able
911 * to obtain references to the struct gpio_chip * for them, and we
912 * need this to proceed.
913 */
914 for (i = 0; i < info->nbanks; i++) {
915 if (!gpio_chips[i]) {
916 dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i);
917 devm_kfree(&pdev->dev, info);
918 return -EPROBE_DEFER;
919 }
920 }
921
922 at91_pinctrl_desc.name = dev_name(&pdev->dev);
923 at91_pinctrl_desc.npins = info->nbanks * MAX_NB_GPIO_PER_BANK;
924 at91_pinctrl_desc.pins = pdesc =
925 devm_kzalloc(&pdev->dev, sizeof(*pdesc) * at91_pinctrl_desc.npins, GFP_KERNEL);
926
927 if (!at91_pinctrl_desc.pins)
928 return -ENOMEM;
929
930 for (i = 0 , k = 0; i < info->nbanks; i++) {
931 for (j = 0; j < MAX_NB_GPIO_PER_BANK; j++, k++) {
932 pdesc->number = k;
933 pdesc->name = kasprintf(GFP_KERNEL, "pio%c%d", i + 'A', j);
934 pdesc++;
935 }
936 }
937
938 platform_set_drvdata(pdev, info);
939 info->pctl = pinctrl_register(&at91_pinctrl_desc, &pdev->dev, info);
940
941 if (!info->pctl) {
942 dev_err(&pdev->dev, "could not register AT91 pinctrl driver\n");
943 ret = -EINVAL;
944 goto err;
945 }
946
947 /* We will handle a range of GPIO pins */
948 for (i = 0; i < info->nbanks; i++)
949 pinctrl_add_gpio_range(info->pctl, &gpio_chips[i]->range);
950
951 dev_info(&pdev->dev, "initialized AT91 pinctrl driver\n");
952
953 return 0;
954
955 err:
956 return ret;
957 }
958
959 int __devexit at91_pinctrl_remove(struct platform_device *pdev)
960 {
961 struct at91_pinctrl *info = platform_get_drvdata(pdev);
962
963 pinctrl_unregister(info->pctl);
964
965 return 0;
966 }
967
968 static int at91_gpio_request(struct gpio_chip *chip, unsigned offset)
969 {
970 /*
971 * Map back to global GPIO space and request muxing, the direction
972 * parameter does not matter for this controller.
973 */
974 int gpio = chip->base + offset;
975 int bank = chip->base / chip->ngpio;
976
977 dev_dbg(chip->dev, "%s:%d pio%c%d(%d)\n", __func__, __LINE__,
978 'A' + bank, offset, gpio);
979
980 return pinctrl_request_gpio(gpio);
981 }
982
983 static void at91_gpio_free(struct gpio_chip *chip, unsigned offset)
984 {
985 int gpio = chip->base + offset;
986
987 pinctrl_free_gpio(gpio);
988 }
989
990 static int at91_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
991 {
992 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
993 void __iomem *pio = at91_gpio->regbase;
994 unsigned mask = 1 << offset;
995
996 writel_relaxed(mask, pio + PIO_ODR);
997 return 0;
998 }
999
1000 static int at91_gpio_get(struct gpio_chip *chip, unsigned offset)
1001 {
1002 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1003 void __iomem *pio = at91_gpio->regbase;
1004 unsigned mask = 1 << offset;
1005 u32 pdsr;
1006
1007 pdsr = readl_relaxed(pio + PIO_PDSR);
1008 return (pdsr & mask) != 0;
1009 }
1010
1011 static void at91_gpio_set(struct gpio_chip *chip, unsigned offset,
1012 int val)
1013 {
1014 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1015 void __iomem *pio = at91_gpio->regbase;
1016 unsigned mask = 1 << offset;
1017
1018 writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
1019 }
1020
1021 static int at91_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
1022 int val)
1023 {
1024 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1025 void __iomem *pio = at91_gpio->regbase;
1026 unsigned mask = 1 << offset;
1027
1028 writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
1029 writel_relaxed(mask, pio + PIO_OER);
1030
1031 return 0;
1032 }
1033
1034 static int at91_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
1035 {
1036 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1037 int virq;
1038
1039 if (offset < chip->ngpio)
1040 virq = irq_create_mapping(at91_gpio->domain, offset);
1041 else
1042 virq = -ENXIO;
1043
1044 dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n",
1045 chip->label, offset + chip->base, virq);
1046 return virq;
1047 }
1048
1049 #ifdef CONFIG_DEBUG_FS
1050 static void at91_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1051 {
1052 enum at91_mux mode;
1053 int i;
1054 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1055 void __iomem *pio = at91_gpio->regbase;
1056
1057 for (i = 0; i < chip->ngpio; i++) {
1058 unsigned pin = chip->base + i;
1059 unsigned mask = pin_to_mask(pin);
1060 const char *gpio_label;
1061 u32 pdsr;
1062
1063 gpio_label = gpiochip_is_requested(chip, i);
1064 if (!gpio_label)
1065 continue;
1066 mode = at91_gpio->ops->get_periph(pio, mask);
1067 seq_printf(s, "[%s] GPIO%s%d: ",
1068 gpio_label, chip->label, i);
1069 if (mode == AT91_MUX_GPIO) {
1070 pdsr = readl_relaxed(pio + PIO_PDSR);
1071
1072 seq_printf(s, "[gpio] %s\n",
1073 pdsr & mask ?
1074 "set" : "clear");
1075 } else {
1076 seq_printf(s, "[periph %c]\n",
1077 mode + 'A' - 1);
1078 }
1079 }
1080 }
1081 #else
1082 #define at91_gpio_dbg_show NULL
1083 #endif
1084
1085 /* Several AIC controller irqs are dispatched through this GPIO handler.
1086 * To use any AT91_PIN_* as an externally triggered IRQ, first call
1087 * at91_set_gpio_input() then maybe enable its glitch filter.
1088 * Then just request_irq() with the pin ID; it works like any ARM IRQ
1089 * handler.
1090 * First implementation always triggers on rising and falling edges
1091 * whereas the newer PIO3 can be additionally configured to trigger on
1092 * level, edge with any polarity.
1093 *
1094 * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
1095 * configuring them with at91_set_a_periph() or at91_set_b_periph().
1096 * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
1097 */
1098
1099 static void gpio_irq_mask(struct irq_data *d)
1100 {
1101 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1102 void __iomem *pio = at91_gpio->regbase;
1103 unsigned mask = 1 << d->hwirq;
1104
1105 if (pio)
1106 writel_relaxed(mask, pio + PIO_IDR);
1107 }
1108
1109 static void gpio_irq_unmask(struct irq_data *d)
1110 {
1111 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1112 void __iomem *pio = at91_gpio->regbase;
1113 unsigned mask = 1 << d->hwirq;
1114
1115 if (pio)
1116 writel_relaxed(mask, pio + PIO_IER);
1117 }
1118
1119 static int gpio_irq_type(struct irq_data *d, unsigned type)
1120 {
1121 switch (type) {
1122 case IRQ_TYPE_NONE:
1123 case IRQ_TYPE_EDGE_BOTH:
1124 return 0;
1125 default:
1126 return -EINVAL;
1127 }
1128 }
1129
1130 /* Alternate irq type for PIO3 support */
1131 static int alt_gpio_irq_type(struct irq_data *d, unsigned type)
1132 {
1133 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1134 void __iomem *pio = at91_gpio->regbase;
1135 unsigned mask = 1 << d->hwirq;
1136
1137 switch (type) {
1138 case IRQ_TYPE_EDGE_RISING:
1139 writel_relaxed(mask, pio + PIO_ESR);
1140 writel_relaxed(mask, pio + PIO_REHLSR);
1141 break;
1142 case IRQ_TYPE_EDGE_FALLING:
1143 writel_relaxed(mask, pio + PIO_ESR);
1144 writel_relaxed(mask, pio + PIO_FELLSR);
1145 break;
1146 case IRQ_TYPE_LEVEL_LOW:
1147 writel_relaxed(mask, pio + PIO_LSR);
1148 writel_relaxed(mask, pio + PIO_FELLSR);
1149 break;
1150 case IRQ_TYPE_LEVEL_HIGH:
1151 writel_relaxed(mask, pio + PIO_LSR);
1152 writel_relaxed(mask, pio + PIO_REHLSR);
1153 break;
1154 case IRQ_TYPE_EDGE_BOTH:
1155 /*
1156 * disable additional interrupt modes:
1157 * fall back to default behavior
1158 */
1159 writel_relaxed(mask, pio + PIO_AIMDR);
1160 return 0;
1161 case IRQ_TYPE_NONE:
1162 default:
1163 pr_warn("AT91: No type for irq %d\n", gpio_to_irq(d->irq));
1164 return -EINVAL;
1165 }
1166
1167 /* enable additional interrupt modes */
1168 writel_relaxed(mask, pio + PIO_AIMER);
1169
1170 return 0;
1171 }
1172
1173 #ifdef CONFIG_PM
1174 static int gpio_irq_set_wake(struct irq_data *d, unsigned state)
1175 {
1176 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1177 unsigned bank = at91_gpio->pioc_idx;
1178
1179 if (unlikely(bank >= MAX_GPIO_BANKS))
1180 return -EINVAL;
1181
1182 irq_set_irq_wake(at91_gpio->pioc_virq, state);
1183
1184 return 0;
1185 }
1186 #else
1187 #define gpio_irq_set_wake NULL
1188 #endif
1189
1190 static struct irq_chip gpio_irqchip = {
1191 .name = "GPIO",
1192 .irq_disable = gpio_irq_mask,
1193 .irq_mask = gpio_irq_mask,
1194 .irq_unmask = gpio_irq_unmask,
1195 /* .irq_set_type is set dynamically */
1196 .irq_set_wake = gpio_irq_set_wake,
1197 };
1198
1199 static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
1200 {
1201 struct irq_chip *chip = irq_desc_get_chip(desc);
1202 struct irq_data *idata = irq_desc_get_irq_data(desc);
1203 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(idata);
1204 void __iomem *pio = at91_gpio->regbase;
1205 unsigned long isr;
1206 int n;
1207
1208 chained_irq_enter(chip, desc);
1209 for (;;) {
1210 /* Reading ISR acks pending (edge triggered) GPIO interrupts.
1211 * When there none are pending, we're finished unless we need
1212 * to process multiple banks (like ID_PIOCDE on sam9263).
1213 */
1214 isr = readl_relaxed(pio + PIO_ISR) & readl_relaxed(pio + PIO_IMR);
1215 if (!isr) {
1216 if (!at91_gpio->next)
1217 break;
1218 at91_gpio = at91_gpio->next;
1219 pio = at91_gpio->regbase;
1220 continue;
1221 }
1222
1223 n = find_first_bit(&isr, BITS_PER_LONG);
1224 while (n < BITS_PER_LONG) {
1225 generic_handle_irq(irq_find_mapping(at91_gpio->domain, n));
1226 n = find_next_bit(&isr, BITS_PER_LONG, n + 1);
1227 }
1228 }
1229 chained_irq_exit(chip, desc);
1230 /* now it may re-trigger */
1231 }
1232
1233 /*
1234 * This lock class tells lockdep that GPIO irqs are in a different
1235 * category than their parents, so it won't report false recursion.
1236 */
1237 static struct lock_class_key gpio_lock_class;
1238
1239 static int at91_gpio_irq_map(struct irq_domain *h, unsigned int virq,
1240 irq_hw_number_t hw)
1241 {
1242 struct at91_gpio_chip *at91_gpio = h->host_data;
1243
1244 irq_set_lockdep_class(virq, &gpio_lock_class);
1245
1246 /*
1247 * Can use the "simple" and not "edge" handler since it's
1248 * shorter, and the AIC handles interrupts sanely.
1249 */
1250 irq_set_chip_and_handler(virq, &gpio_irqchip,
1251 handle_simple_irq);
1252 set_irq_flags(virq, IRQF_VALID);
1253 irq_set_chip_data(virq, at91_gpio);
1254
1255 return 0;
1256 }
1257
1258 static struct irq_domain_ops at91_gpio_ops = {
1259 .map = at91_gpio_irq_map,
1260 .xlate = irq_domain_xlate_twocell,
1261 };
1262
1263 static int at91_gpio_of_irq_setup(struct device_node *node,
1264 struct at91_gpio_chip *at91_gpio)
1265 {
1266 struct at91_gpio_chip *prev = NULL;
1267 struct irq_data *d = irq_get_irq_data(at91_gpio->pioc_virq);
1268
1269 at91_gpio->pioc_hwirq = irqd_to_hwirq(d);
1270
1271 /* Setup proper .irq_set_type function */
1272 gpio_irqchip.irq_set_type = at91_gpio->ops->irq_type;
1273
1274 /* Disable irqs of this PIO controller */
1275 writel_relaxed(~0, at91_gpio->regbase + PIO_IDR);
1276
1277 /* Setup irq domain */
1278 at91_gpio->domain = irq_domain_add_linear(node, at91_gpio->chip.ngpio,
1279 &at91_gpio_ops, at91_gpio);
1280 if (!at91_gpio->domain)
1281 panic("at91_gpio.%d: couldn't allocate irq domain (DT).\n",
1282 at91_gpio->pioc_idx);
1283
1284 /* Setup chained handler */
1285 if (at91_gpio->pioc_idx)
1286 prev = gpio_chips[at91_gpio->pioc_idx - 1];
1287
1288 /* The toplevel handler handles one bank of GPIOs, except
1289 * on some SoC it can handles up to three...
1290 * We only set up the handler for the first of the list.
1291 */
1292 if (prev && prev->next == at91_gpio)
1293 return 0;
1294
1295 irq_set_chip_data(at91_gpio->pioc_virq, at91_gpio);
1296 irq_set_chained_handler(at91_gpio->pioc_virq, gpio_irq_handler);
1297
1298 return 0;
1299 }
1300
1301 /* This structure is replicated for each GPIO block allocated at probe time */
1302 static struct gpio_chip at91_gpio_template = {
1303 .request = at91_gpio_request,
1304 .free = at91_gpio_free,
1305 .direction_input = at91_gpio_direction_input,
1306 .get = at91_gpio_get,
1307 .direction_output = at91_gpio_direction_output,
1308 .set = at91_gpio_set,
1309 .to_irq = at91_gpio_to_irq,
1310 .dbg_show = at91_gpio_dbg_show,
1311 .can_sleep = 0,
1312 .ngpio = MAX_NB_GPIO_PER_BANK,
1313 };
1314
1315 static void __devinit at91_gpio_probe_fixup(void)
1316 {
1317 unsigned i;
1318 struct at91_gpio_chip *at91_gpio, *last = NULL;
1319
1320 for (i = 0; i < gpio_banks; i++) {
1321 at91_gpio = gpio_chips[i];
1322
1323 /*
1324 * GPIO controller are grouped on some SoC:
1325 * PIOC, PIOD and PIOE can share the same IRQ line
1326 */
1327 if (last && last->pioc_virq == at91_gpio->pioc_virq)
1328 last->next = at91_gpio;
1329 last = at91_gpio;
1330 }
1331 }
1332
1333 static struct of_device_id at91_gpio_of_match[] __devinitdata = {
1334 { .compatible = "atmel,at91sam9x5-gpio", .data = &at91sam9x5_ops, },
1335 { .compatible = "atmel,at91rm9200-gpio", .data = &at91rm9200_ops },
1336 { /* sentinel */ }
1337 };
1338
1339 static int __devinit at91_gpio_probe(struct platform_device *pdev)
1340 {
1341 struct device_node *np = pdev->dev.of_node;
1342 struct resource *res;
1343 struct at91_gpio_chip *at91_chip = NULL;
1344 struct gpio_chip *chip;
1345 struct pinctrl_gpio_range *range;
1346 int ret = 0;
1347 int irq;
1348 int alias_idx = of_alias_get_id(np, "gpio");
1349 uint32_t ngpio;
1350
1351 BUG_ON(alias_idx >= ARRAY_SIZE(gpio_chips));
1352 if (gpio_chips[alias_idx]) {
1353 ret = -EBUSY;
1354 goto err;
1355 }
1356
1357 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1358 if (!res) {
1359 ret = -ENOENT;
1360 goto err;
1361 }
1362
1363 irq = platform_get_irq(pdev, 0);
1364 if (irq < 0) {
1365 ret = irq;
1366 goto err;
1367 }
1368
1369 at91_chip = devm_kzalloc(&pdev->dev, sizeof(*at91_chip), GFP_KERNEL);
1370 if (!at91_chip) {
1371 ret = -ENOMEM;
1372 goto err;
1373 }
1374
1375 at91_chip->regbase = devm_request_and_ioremap(&pdev->dev, res);
1376 if (!at91_chip->regbase) {
1377 dev_err(&pdev->dev, "failed to map registers, ignoring.\n");
1378 ret = -EBUSY;
1379 goto err;
1380 }
1381
1382 at91_chip->ops =
1383 of_match_device(at91_gpio_of_match, &pdev->dev)->data;
1384 at91_chip->pioc_virq = irq;
1385 at91_chip->pioc_idx = alias_idx;
1386
1387 at91_chip->clock = clk_get(&pdev->dev, NULL);
1388 if (IS_ERR(at91_chip->clock)) {
1389 dev_err(&pdev->dev, "failed to get clock, ignoring.\n");
1390 goto err;
1391 }
1392
1393 if (clk_prepare(at91_chip->clock))
1394 goto clk_prep_err;
1395
1396 /* enable PIO controller's clock */
1397 if (clk_enable(at91_chip->clock)) {
1398 dev_err(&pdev->dev, "failed to enable clock, ignoring.\n");
1399 goto clk_err;
1400 }
1401
1402 at91_chip->chip = at91_gpio_template;
1403
1404 chip = &at91_chip->chip;
1405 chip->of_node = np;
1406 chip->label = dev_name(&pdev->dev);
1407 chip->dev = &pdev->dev;
1408 chip->owner = THIS_MODULE;
1409 chip->base = alias_idx * MAX_NB_GPIO_PER_BANK;
1410
1411 if (!of_property_read_u32(np, "#gpio-lines", &ngpio)) {
1412 if (ngpio >= MAX_NB_GPIO_PER_BANK)
1413 pr_err("at91_gpio.%d, gpio-nb >= %d failback to %d\n",
1414 alias_idx, MAX_NB_GPIO_PER_BANK, MAX_NB_GPIO_PER_BANK);
1415 else
1416 chip->ngpio = ngpio;
1417 }
1418
1419 range = &at91_chip->range;
1420 range->name = chip->label;
1421 range->id = alias_idx;
1422 range->pin_base = range->base = range->id * MAX_NB_GPIO_PER_BANK;
1423
1424 range->npins = chip->ngpio;
1425 range->gc = chip;
1426
1427 ret = gpiochip_add(chip);
1428 if (ret)
1429 goto clk_err;
1430
1431 gpio_chips[alias_idx] = at91_chip;
1432 gpio_banks = max(gpio_banks, alias_idx + 1);
1433
1434 at91_gpio_probe_fixup();
1435
1436 at91_gpio_of_irq_setup(np, at91_chip);
1437
1438 dev_info(&pdev->dev, "at address %p\n", at91_chip->regbase);
1439
1440 return 0;
1441
1442 clk_err:
1443 clk_unprepare(at91_chip->clock);
1444 clk_prep_err:
1445 clk_put(at91_chip->clock);
1446 err:
1447 dev_err(&pdev->dev, "Failure %i for GPIO %i\n", ret, alias_idx);
1448
1449 return ret;
1450 }
1451
1452 static struct platform_driver at91_gpio_driver = {
1453 .driver = {
1454 .name = "gpio-at91",
1455 .owner = THIS_MODULE,
1456 .of_match_table = of_match_ptr(at91_gpio_of_match),
1457 },
1458 .probe = at91_gpio_probe,
1459 };
1460
1461 static struct platform_driver at91_pinctrl_driver = {
1462 .driver = {
1463 .name = "pinctrl-at91",
1464 .owner = THIS_MODULE,
1465 .of_match_table = of_match_ptr(at91_pinctrl_of_match),
1466 },
1467 .probe = at91_pinctrl_probe,
1468 .remove = __devexit_p(at91_pinctrl_remove),
1469 };
1470
1471 static int __init at91_pinctrl_init(void)
1472 {
1473 int ret;
1474
1475 ret = platform_driver_register(&at91_gpio_driver);
1476 if (ret)
1477 return ret;
1478 return platform_driver_register(&at91_pinctrl_driver);
1479 }
1480 arch_initcall(at91_pinctrl_init);
1481
1482 static void __exit at91_pinctrl_exit(void)
1483 {
1484 platform_driver_unregister(&at91_pinctrl_driver);
1485 }
1486
1487 module_exit(at91_pinctrl_exit);
1488 MODULE_AUTHOR("Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>");
1489 MODULE_DESCRIPTION("Atmel AT91 pinctrl driver");
1490 MODULE_LICENSE("GPL v2");
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