| blob | 3d7f11fe610d0fcdd7bdf946c3796c8c6cd82e2b |
1 config ARM
2 bool
3 default y
4 select ARCH_HAVE_CUSTOM_GPIO_H
5 select HAVE_AOUT
6 select HAVE_DMA_API_DEBUG
7 select HAVE_IDE if PCI || ISA || PCMCIA
8 select HAVE_DMA_ATTRS
9 select HAVE_DMA_CONTIGUOUS if MMU
10 select HAVE_MEMBLOCK
11 select RTC_LIB
12 select SYS_SUPPORTS_APM_EMULATION
13 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
14 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
15 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
16 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
17 select HAVE_ARCH_KGDB
18 select HAVE_ARCH_TRACEHOOK
19 select HAVE_SYSCALL_TRACEPOINTS
20 select HAVE_KPROBES if !XIP_KERNEL
21 select HAVE_KRETPROBES if (HAVE_KPROBES)
22 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
23 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
24 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
25 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
26 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
27 select HAVE_GENERIC_DMA_COHERENT
28 select HAVE_DEBUG_KMEMLEAK
29 select HAVE_KERNEL_GZIP
30 select HAVE_KERNEL_LZO
31 select HAVE_KERNEL_LZMA
32 select HAVE_KERNEL_XZ
33 select HAVE_IRQ_WORK
34 select HAVE_PERF_EVENTS
35 select PERF_USE_VMALLOC
36 select HAVE_REGS_AND_STACK_ACCESS_API
37 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
38 select HAVE_C_RECORDMCOUNT
39 select HAVE_GENERIC_HARDIRQS
40 select HARDIRQS_SW_RESEND
41 select GENERIC_IRQ_PROBE
42 select GENERIC_IRQ_SHOW
43 select HAVE_UID16
44 select ARCH_WANT_IPC_PARSE_VERSION
45 select HARDIRQS_SW_RESEND
46 select CPU_PM if (SUSPEND || CPU_IDLE)
47 select GENERIC_PCI_IOMAP
48 select HAVE_BPF_JIT
49 select GENERIC_SMP_IDLE_THREAD
50 select KTIME_SCALAR
51 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
52 select GENERIC_STRNCPY_FROM_USER
53 select GENERIC_STRNLEN_USER
54 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN
55 select GENERIC_KERNEL_THREAD
56 select GENERIC_KERNEL_EXECVE
57 help
58 The ARM series is a line of low-power-consumption RISC chip designs
59 licensed by ARM Ltd and targeted at embedded applications and
60 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
61 manufactured, but legacy ARM-based PC hardware remains popular in
62 Europe. There is an ARM Linux project with a web page at
63 <http://www.arm.linux.org.uk/>.
65 config ARM_HAS_SG_CHAIN
66 bool
68 config NEED_SG_DMA_LENGTH
69 bool
71 config ARM_DMA_USE_IOMMU
72 select NEED_SG_DMA_LENGTH
73 select ARM_HAS_SG_CHAIN
74 bool
76 config HAVE_PWM
77 bool
79 config MIGHT_HAVE_PCI
80 bool
82 config SYS_SUPPORTS_APM_EMULATION
83 bool
85 config GENERIC_GPIO
86 bool
88 config HAVE_TCM
89 bool
90 select GENERIC_ALLOCATOR
92 config HAVE_PROC_CPU
93 bool
95 config NO_IOPORT
96 bool
98 config EISA
99 bool
100 ---help---
101 The Extended Industry Standard Architecture (EISA) bus was
102 developed as an open alternative to the IBM MicroChannel bus.
104 The EISA bus provided some of the features of the IBM MicroChannel
105 bus while maintaining backward compatibility with cards made for
106 the older ISA bus. The EISA bus saw limited use between 1988 and
107 1995 when it was made obsolete by the PCI bus.
109 Say Y here if you are building a kernel for an EISA-based machine.
111 Otherwise, say N.
113 config SBUS
114 bool
116 config STACKTRACE_SUPPORT
117 bool
118 default y
120 config HAVE_LATENCYTOP_SUPPORT
121 bool
122 depends on !SMP
123 default y
125 config LOCKDEP_SUPPORT
126 bool
127 default y
129 config TRACE_IRQFLAGS_SUPPORT
130 bool
131 default y
133 config RWSEM_GENERIC_SPINLOCK
134 bool
135 default y
137 config RWSEM_XCHGADD_ALGORITHM
138 bool
140 config ARCH_HAS_ILOG2_U32
141 bool
143 config ARCH_HAS_ILOG2_U64
144 bool
146 config ARCH_HAS_CPUFREQ
147 bool
148 help
149 Internal node to signify that the ARCH has CPUFREQ support
150 and that the relevant menu configurations are displayed for
151 it.
153 config GENERIC_HWEIGHT
154 bool
155 default y
157 config GENERIC_CALIBRATE_DELAY
158 bool
159 default y
161 config ARCH_MAY_HAVE_PC_FDC
162 bool
164 config ZONE_DMA
165 bool
167 config NEED_DMA_MAP_STATE
168 def_bool y
170 config ARCH_HAS_DMA_SET_COHERENT_MASK
171 bool
173 config GENERIC_ISA_DMA
174 bool
176 config FIQ
177 bool
179 config NEED_RET_TO_USER
180 bool
182 config ARCH_MTD_XIP
183 bool
185 config VECTORS_BASE
186 hex
187 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
188 default DRAM_BASE if REMAP_VECTORS_TO_RAM
189 default 0x00000000
190 help
191 The base address of exception vectors.
193 config ARM_PATCH_PHYS_VIRT
194 bool "Patch physical to virtual translations at runtime" if EMBEDDED
195 default y
196 depends on !XIP_KERNEL && MMU
197 depends on !ARCH_REALVIEW || !SPARSEMEM
198 help
199 Patch phys-to-virt and virt-to-phys translation functions at
200 boot and module load time according to the position of the
201 kernel in system memory.
203 This can only be used with non-XIP MMU kernels where the base
204 of physical memory is at a 16MB boundary.
206 Only disable this option if you know that you do not require
207 this feature (eg, building a kernel for a single machine) and
208 you need to shrink the kernel to the minimal size.
210 config NEED_MACH_GPIO_H
211 bool
212 help
213 Select this when mach/gpio.h is required to provide special
214 definitions for this platform. The need for mach/gpio.h should
215 be avoided when possible.
217 config NEED_MACH_IO_H
218 bool
219 help
220 Select this when mach/io.h is required to provide special
221 definitions for this platform. The need for mach/io.h should
222 be avoided when possible.
224 config NEED_MACH_MEMORY_H
225 bool
226 help
227 Select this when mach/memory.h is required to provide special
228 definitions for this platform. The need for mach/memory.h should
229 be avoided when possible.
231 config PHYS_OFFSET
232 hex "Physical address of main memory" if MMU
233 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
234 default DRAM_BASE if !MMU
235 help
236 Please provide the physical address corresponding to the
237 location of main memory in your system.
239 config GENERIC_BUG
240 def_bool y
241 depends on BUG
243 source "init/Kconfig"
245 source "kernel/Kconfig.freezer"
247 menu "System Type"
249 config MMU
250 bool "MMU-based Paged Memory Management Support"
251 default y
252 help
253 Select if you want MMU-based virtualised addressing space
254 support by paged memory management. If unsure, say 'Y'.
256 #
257 # The "ARM system type" choice list is ordered alphabetically by option
258 # text. Please add new entries in the option alphabetic order.
259 #
260 choice
261 prompt "ARM system type"
262 default ARCH_MULTIPLATFORM
264 config ARCH_MULTIPLATFORM
265 bool "Allow multiple platforms to be selected"
266 select ARM_PATCH_PHYS_VIRT
267 select AUTO_ZRELADDR
268 select COMMON_CLK
269 select MULTI_IRQ_HANDLER
270 select SPARSE_IRQ
271 select USE_OF
272 depends on MMU
274 config ARCH_INTEGRATOR
275 bool "ARM Ltd. Integrator family"
276 select ARM_AMBA
277 select ARCH_HAS_CPUFREQ
278 select COMMON_CLK
279 select COMMON_CLK_VERSATILE
280 select HAVE_TCM
281 select ICST
282 select GENERIC_CLOCKEVENTS
283 select PLAT_VERSATILE
284 select PLAT_VERSATILE_FPGA_IRQ
285 select NEED_MACH_MEMORY_H
286 select SPARSE_IRQ
287 select MULTI_IRQ_HANDLER
288 help
289 Support for ARM's Integrator platform.
291 config ARCH_REALVIEW
292 bool "ARM Ltd. RealView family"
293 select ARM_AMBA
294 select COMMON_CLK
295 select COMMON_CLK_VERSATILE
296 select ICST
297 select GENERIC_CLOCKEVENTS
298 select ARCH_WANT_OPTIONAL_GPIOLIB
299 select PLAT_VERSATILE
300 select PLAT_VERSATILE_CLCD
301 select ARM_TIMER_SP804
302 select GPIO_PL061 if GPIOLIB
303 select NEED_MACH_MEMORY_H
304 help
305 This enables support for ARM Ltd RealView boards.
307 config ARCH_VERSATILE
308 bool "ARM Ltd. Versatile family"
309 select ARM_AMBA
310 select ARM_VIC
311 select CLKDEV_LOOKUP
312 select HAVE_MACH_CLKDEV
313 select ICST
314 select GENERIC_CLOCKEVENTS
315 select ARCH_WANT_OPTIONAL_GPIOLIB
316 select PLAT_VERSATILE
317 select PLAT_VERSATILE_CLOCK
318 select PLAT_VERSATILE_CLCD
319 select PLAT_VERSATILE_FPGA_IRQ
320 select ARM_TIMER_SP804
321 help
322 This enables support for ARM Ltd Versatile board.
324 config ARCH_AT91
325 bool "Atmel AT91"
326 select ARCH_REQUIRE_GPIOLIB
327 select HAVE_CLK
328 select CLKDEV_LOOKUP
329 select IRQ_DOMAIN
330 select NEED_MACH_GPIO_H
331 select NEED_MACH_IO_H if PCCARD
332 select PINCTRL
333 select PINCTRL_AT91 if USE_OF
334 help
335 This enables support for systems based on Atmel
336 AT91RM9200 and AT91SAM9* processors.
338 config ARCH_BCM2835
339 bool "Broadcom BCM2835 family"
340 select ARCH_WANT_OPTIONAL_GPIOLIB
341 select ARM_AMBA
342 select ARM_ERRATA_411920
343 select ARM_TIMER_SP804
344 select CLKDEV_LOOKUP
345 select COMMON_CLK
346 select CPU_V6
347 select GENERIC_CLOCKEVENTS
348 select MULTI_IRQ_HANDLER
349 select SPARSE_IRQ
350 select USE_OF
351 help
352 This enables support for the Broadcom BCM2835 SoC. This SoC is
353 use in the Raspberry Pi, and Roku 2 devices.
355 config ARCH_CLPS711X
356 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
357 select CPU_ARM720T
358 select ARCH_USES_GETTIMEOFFSET
359 select COMMON_CLK
360 select CLKDEV_LOOKUP
361 select NEED_MACH_MEMORY_H
362 help
363 Support for Cirrus Logic 711x/721x/731x based boards.
365 config ARCH_CNS3XXX
366 bool "Cavium Networks CNS3XXX family"
367 select CPU_V6K
368 select GENERIC_CLOCKEVENTS
369 select ARM_GIC
370 select MIGHT_HAVE_CACHE_L2X0
371 select MIGHT_HAVE_PCI
372 select PCI_DOMAINS if PCI
373 help
374 Support for Cavium Networks CNS3XXX platform.
376 config ARCH_GEMINI
377 bool "Cortina Systems Gemini"
378 select CPU_FA526
379 select ARCH_REQUIRE_GPIOLIB
380 select ARCH_USES_GETTIMEOFFSET
381 help
382 Support for the Cortina Systems Gemini family SoCs
384 config ARCH_SIRF
385 bool "CSR SiRF"
386 select NO_IOPORT
387 select ARCH_REQUIRE_GPIOLIB
388 select GENERIC_CLOCKEVENTS
389 select COMMON_CLK
390 select GENERIC_IRQ_CHIP
391 select MIGHT_HAVE_CACHE_L2X0
392 select PINCTRL
393 select PINCTRL_SIRF
394 select USE_OF
395 help
396 Support for CSR SiRFprimaII/Marco/Polo platforms
398 config ARCH_EBSA110
399 bool "EBSA-110"
400 select CPU_SA110
401 select ISA
402 select NO_IOPORT
403 select ARCH_USES_GETTIMEOFFSET
404 select NEED_MACH_IO_H
405 select NEED_MACH_MEMORY_H
406 help
407 This is an evaluation board for the StrongARM processor available
408 from Digital. It has limited hardware on-board, including an
409 Ethernet interface, two PCMCIA sockets, two serial ports and a
410 parallel port.
412 config ARCH_EP93XX
413 bool "EP93xx-based"
414 select CPU_ARM920T
415 select ARM_AMBA
416 select ARM_VIC
417 select CLKDEV_LOOKUP
418 select ARCH_REQUIRE_GPIOLIB
419 select ARCH_HAS_HOLES_MEMORYMODEL
420 select ARCH_USES_GETTIMEOFFSET
421 select NEED_MACH_MEMORY_H
422 help
423 This enables support for the Cirrus EP93xx series of CPUs.
425 config ARCH_FOOTBRIDGE
426 bool "FootBridge"
427 select CPU_SA110
428 select FOOTBRIDGE
429 select GENERIC_CLOCKEVENTS
430 select HAVE_IDE
431 select NEED_MACH_IO_H if !MMU
432 select NEED_MACH_MEMORY_H
433 help
434 Support for systems based on the DC21285 companion chip
435 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
437 config ARCH_MXC
438 bool "Freescale MXC/iMX-based"
439 select GENERIC_CLOCKEVENTS
440 select ARCH_REQUIRE_GPIOLIB
441 select CLKDEV_LOOKUP
442 select CLKSRC_MMIO
443 select GENERIC_IRQ_CHIP
444 select MULTI_IRQ_HANDLER
445 select SPARSE_IRQ
446 select USE_OF
447 help
448 Support for Freescale MXC/iMX-based family of processors
450 config ARCH_MXS
451 bool "Freescale MXS-based"
452 select GENERIC_CLOCKEVENTS
453 select ARCH_REQUIRE_GPIOLIB
454 select CLKDEV_LOOKUP
455 select CLKSRC_MMIO
456 select COMMON_CLK
457 select HAVE_CLK_PREPARE
458 select MULTI_IRQ_HANDLER
459 select PINCTRL
460 select SPARSE_IRQ
461 select USE_OF
462 help
463 Support for Freescale MXS-based family of processors
465 config ARCH_NETX
466 bool "Hilscher NetX based"
467 select CLKSRC_MMIO
468 select CPU_ARM926T
469 select ARM_VIC
470 select GENERIC_CLOCKEVENTS
471 help
472 This enables support for systems based on the Hilscher NetX Soc
474 config ARCH_H720X
475 bool "Hynix HMS720x-based"
476 select CPU_ARM720T
477 select ISA_DMA_API
478 select ARCH_USES_GETTIMEOFFSET
479 help
480 This enables support for systems based on the Hynix HMS720x
482 config ARCH_IOP13XX
483 bool "IOP13xx-based"
484 depends on MMU
485 select CPU_XSC3
486 select PLAT_IOP
487 select PCI
488 select ARCH_SUPPORTS_MSI
489 select VMSPLIT_1G
490 select NEED_MACH_MEMORY_H
491 select NEED_RET_TO_USER
492 help
493 Support for Intel's IOP13XX (XScale) family of processors.
495 config ARCH_IOP32X
496 bool "IOP32x-based"
497 depends on MMU
498 select CPU_XSCALE
499 select NEED_MACH_GPIO_H
500 select NEED_RET_TO_USER
501 select PLAT_IOP
502 select PCI
503 select ARCH_REQUIRE_GPIOLIB
504 help
505 Support for Intel's 80219 and IOP32X (XScale) family of
506 processors.
508 config ARCH_IOP33X
509 bool "IOP33x-based"
510 depends on MMU
511 select CPU_XSCALE
512 select NEED_MACH_GPIO_H
513 select NEED_RET_TO_USER
514 select PLAT_IOP
515 select PCI
516 select ARCH_REQUIRE_GPIOLIB
517 help
518 Support for Intel's IOP33X (XScale) family of processors.
520 config ARCH_IXP4XX
521 bool "IXP4xx-based"
522 depends on MMU
523 select ARCH_HAS_DMA_SET_COHERENT_MASK
524 select CLKSRC_MMIO
525 select CPU_XSCALE
526 select ARCH_REQUIRE_GPIOLIB
527 select GENERIC_CLOCKEVENTS
528 select MIGHT_HAVE_PCI
529 select NEED_MACH_IO_H
530 select DMABOUNCE if PCI
531 help
532 Support for Intel's IXP4XX (XScale) family of processors.
534 config ARCH_DOVE
535 bool "Marvell Dove"
536 select CPU_V7
537 select ARCH_REQUIRE_GPIOLIB
538 select GENERIC_CLOCKEVENTS
539 select MIGHT_HAVE_PCI
540 select PLAT_ORION_LEGACY
541 select USB_ARCH_HAS_EHCI
542 help
543 Support for the Marvell Dove SoC 88AP510
545 config ARCH_KIRKWOOD
546 bool "Marvell Kirkwood"
547 select CPU_FEROCEON
548 select PCI
549 select ARCH_REQUIRE_GPIOLIB
550 select GENERIC_CLOCKEVENTS
551 select PLAT_ORION_LEGACY
552 help
553 Support for the following Marvell Kirkwood series SoCs:
554 88F6180, 88F6192 and 88F6281.
556 config ARCH_LPC32XX
557 bool "NXP LPC32XX"
558 select CLKSRC_MMIO
559 select CPU_ARM926T
560 select ARCH_REQUIRE_GPIOLIB
561 select HAVE_IDE
562 select ARM_AMBA
563 select USB_ARCH_HAS_OHCI
564 select CLKDEV_LOOKUP
565 select GENERIC_CLOCKEVENTS
566 select USE_OF
567 select HAVE_PWM
568 help
569 Support for the NXP LPC32XX family of processors
571 config ARCH_MV78XX0
572 bool "Marvell MV78xx0"
573 select CPU_FEROCEON
574 select PCI
575 select ARCH_REQUIRE_GPIOLIB
576 select GENERIC_CLOCKEVENTS
577 select PLAT_ORION_LEGACY
578 help
579 Support for the following Marvell MV78xx0 series SoCs:
580 MV781x0, MV782x0.
582 config ARCH_ORION5X
583 bool "Marvell Orion"
584 depends on MMU
585 select CPU_FEROCEON
586 select PCI
587 select ARCH_REQUIRE_GPIOLIB
588 select GENERIC_CLOCKEVENTS
589 select PLAT_ORION_LEGACY
590 help
591 Support for the following Marvell Orion 5x series SoCs:
592 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
593 Orion-2 (5281), Orion-1-90 (6183).
595 config ARCH_MMP
596 bool "Marvell PXA168/910/MMP2"
597 depends on MMU
598 select ARCH_REQUIRE_GPIOLIB
599 select CLKDEV_LOOKUP
600 select GENERIC_CLOCKEVENTS
601 select GPIO_PXA
602 select IRQ_DOMAIN
603 select PLAT_PXA
604 select SPARSE_IRQ
605 select GENERIC_ALLOCATOR
606 select NEED_MACH_GPIO_H
607 help
608 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
610 config ARCH_KS8695
611 bool "Micrel/Kendin KS8695"
612 select CPU_ARM922T
613 select ARCH_REQUIRE_GPIOLIB
614 select NEED_MACH_MEMORY_H
615 select CLKSRC_MMIO
616 select GENERIC_CLOCKEVENTS
617 help
618 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
619 System-on-Chip devices.
621 config ARCH_W90X900
622 bool "Nuvoton W90X900 CPU"
623 select CPU_ARM926T
624 select ARCH_REQUIRE_GPIOLIB
625 select CLKDEV_LOOKUP
626 select CLKSRC_MMIO
627 select GENERIC_CLOCKEVENTS
628 help
629 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
630 At present, the w90x900 has been renamed nuc900, regarding
631 the ARM series product line, you can login the following
632 link address to know more.
634 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
635 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
637 config ARCH_TEGRA
638 bool "NVIDIA Tegra"
639 select CLKDEV_LOOKUP
640 select CLKSRC_MMIO
641 select GENERIC_CLOCKEVENTS
642 select GENERIC_GPIO
643 select HAVE_CLK
644 select HAVE_SMP
645 select MIGHT_HAVE_CACHE_L2X0
646 select ARCH_HAS_CPUFREQ
647 select USE_OF
648 select COMMON_CLK
649 help
650 This enables support for NVIDIA Tegra based systems (Tegra APX,
651 Tegra 6xx and Tegra 2 series).
653 config ARCH_PXA
654 bool "PXA2xx/PXA3xx-based"
655 depends on MMU
656 select ARCH_MTD_XIP
657 select ARCH_HAS_CPUFREQ
658 select CLKDEV_LOOKUP
659 select CLKSRC_MMIO
660 select ARCH_REQUIRE_GPIOLIB
661 select GENERIC_CLOCKEVENTS
662 select GPIO_PXA
663 select PLAT_PXA
664 select SPARSE_IRQ
665 select AUTO_ZRELADDR
666 select MULTI_IRQ_HANDLER
667 select ARM_CPU_SUSPEND if PM
668 select HAVE_IDE
669 select NEED_MACH_GPIO_H
670 help
671 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
673 config ARCH_MSM
674 bool "Qualcomm MSM"
675 select HAVE_CLK
676 select GENERIC_CLOCKEVENTS
677 select ARCH_REQUIRE_GPIOLIB
678 select CLKDEV_LOOKUP
679 help
680 Support for Qualcomm MSM/QSD based systems. This runs on the
681 apps processor of the MSM/QSD and depends on a shared memory
682 interface to the modem processor which runs the baseband
683 stack and controls some vital subsystems
684 (clock and power control, etc).
686 config ARCH_SHMOBILE
687 bool "Renesas SH-Mobile / R-Mobile"
688 select HAVE_CLK
689 select CLKDEV_LOOKUP
690 select HAVE_MACH_CLKDEV
691 select HAVE_SMP
692 select GENERIC_CLOCKEVENTS
693 select MIGHT_HAVE_CACHE_L2X0
694 select NO_IOPORT
695 select SPARSE_IRQ
696 select MULTI_IRQ_HANDLER
697 select PM_GENERIC_DOMAINS if PM
698 select NEED_MACH_MEMORY_H
699 help
700 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
702 config ARCH_RPC
703 bool "RiscPC"
704 select ARCH_ACORN
705 select FIQ
706 select ARCH_MAY_HAVE_PC_FDC
707 select HAVE_PATA_PLATFORM
708 select ISA_DMA_API
709 select NO_IOPORT
710 select ARCH_SPARSEMEM_ENABLE
711 select ARCH_USES_GETTIMEOFFSET
712 select HAVE_IDE
713 select NEED_MACH_IO_H
714 select NEED_MACH_MEMORY_H
715 help
716 On the Acorn Risc-PC, Linux can support the internal IDE disk and
717 CD-ROM interface, serial and parallel port, and the floppy drive.
719 config ARCH_SA1100
720 bool "SA1100-based"
721 select CLKSRC_MMIO
722 select CPU_SA1100
723 select ISA
724 select ARCH_SPARSEMEM_ENABLE
725 select ARCH_MTD_XIP
726 select ARCH_HAS_CPUFREQ
727 select CPU_FREQ
728 select GENERIC_CLOCKEVENTS
729 select CLKDEV_LOOKUP
730 select ARCH_REQUIRE_GPIOLIB
731 select HAVE_IDE
732 select NEED_MACH_GPIO_H
733 select NEED_MACH_MEMORY_H
734 select SPARSE_IRQ
735 help
736 Support for StrongARM 11x0 based boards.
738 config ARCH_S3C24XX
739 bool "Samsung S3C24XX SoCs"
740 select GENERIC_GPIO
741 select ARCH_HAS_CPUFREQ
742 select HAVE_CLK
743 select CLKDEV_LOOKUP
744 select ARCH_USES_GETTIMEOFFSET
745 select HAVE_S3C2410_I2C if I2C
746 select HAVE_S3C_RTC if RTC_CLASS
747 select HAVE_S3C2410_WATCHDOG if WATCHDOG
748 select NEED_MACH_GPIO_H
749 select NEED_MACH_IO_H
750 help
751 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
752 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
753 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
754 Samsung SMDK2410 development board (and derivatives).
756 config ARCH_S3C64XX
757 bool "Samsung S3C64XX"
758 select PLAT_SAMSUNG
759 select CPU_V6
760 select ARM_VIC
761 select HAVE_CLK
762 select HAVE_TCM
763 select CLKDEV_LOOKUP
764 select NO_IOPORT
765 select ARCH_USES_GETTIMEOFFSET
766 select ARCH_HAS_CPUFREQ
767 select ARCH_REQUIRE_GPIOLIB
768 select SAMSUNG_CLKSRC
769 select SAMSUNG_IRQ_VIC_TIMER
770 select S3C_GPIO_TRACK
771 select S3C_DEV_NAND
772 select USB_ARCH_HAS_OHCI
773 select SAMSUNG_GPIOLIB_4BIT
774 select HAVE_S3C2410_I2C if I2C
775 select HAVE_S3C2410_WATCHDOG if WATCHDOG
776 select NEED_MACH_GPIO_H
777 help
778 Samsung S3C64XX series based systems
780 config ARCH_S5P64X0
781 bool "Samsung S5P6440 S5P6450"
782 select CPU_V6
783 select GENERIC_GPIO
784 select HAVE_CLK
785 select CLKDEV_LOOKUP
786 select CLKSRC_MMIO
787 select HAVE_S3C2410_WATCHDOG if WATCHDOG
788 select GENERIC_CLOCKEVENTS
789 select HAVE_S3C2410_I2C if I2C
790 select HAVE_S3C_RTC if RTC_CLASS
791 select NEED_MACH_GPIO_H
792 help
793 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
794 SMDK6450.
796 config ARCH_S5PC100
797 bool "Samsung S5PC100"
798 select GENERIC_GPIO
799 select HAVE_CLK
800 select CLKDEV_LOOKUP
801 select CPU_V7
802 select ARCH_USES_GETTIMEOFFSET
803 select HAVE_S3C2410_I2C if I2C
804 select HAVE_S3C_RTC if RTC_CLASS
805 select HAVE_S3C2410_WATCHDOG if WATCHDOG
806 select NEED_MACH_GPIO_H
807 help
808 Samsung S5PC100 series based systems
810 config ARCH_S5PV210
811 bool "Samsung S5PV210/S5PC110"
812 select CPU_V7
813 select ARCH_SPARSEMEM_ENABLE
814 select ARCH_HAS_HOLES_MEMORYMODEL
815 select GENERIC_GPIO
816 select HAVE_CLK
817 select CLKDEV_LOOKUP
818 select CLKSRC_MMIO
819 select ARCH_HAS_CPUFREQ
820 select GENERIC_CLOCKEVENTS
821 select HAVE_S3C2410_I2C if I2C
822 select HAVE_S3C_RTC if RTC_CLASS
823 select HAVE_S3C2410_WATCHDOG if WATCHDOG
824 select NEED_MACH_GPIO_H
825 select NEED_MACH_MEMORY_H
826 help
827 Samsung S5PV210/S5PC110 series based systems
829 config ARCH_EXYNOS
830 bool "SAMSUNG EXYNOS"
831 select CPU_V7
832 select ARCH_SPARSEMEM_ENABLE
833 select ARCH_HAS_HOLES_MEMORYMODEL
834 select GENERIC_GPIO
835 select HAVE_CLK
836 select CLKDEV_LOOKUP
837 select ARCH_HAS_CPUFREQ
838 select GENERIC_CLOCKEVENTS
839 select HAVE_S3C_RTC if RTC_CLASS
840 select HAVE_S3C2410_I2C if I2C
841 select HAVE_S3C2410_WATCHDOG if WATCHDOG
842 select NEED_MACH_GPIO_H
843 select NEED_MACH_MEMORY_H
844 help
845 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
847 config ARCH_SHARK
848 bool "Shark"
849 select CPU_SA110
850 select ISA
851 select ISA_DMA
852 select ZONE_DMA
853 select PCI
854 select ARCH_USES_GETTIMEOFFSET
855 select NEED_MACH_MEMORY_H
856 help
857 Support for the StrongARM based Digital DNARD machine, also known
858 as "Shark" (<http://www.shark-linux.de/shark.html>).
860 config ARCH_U300
861 bool "ST-Ericsson U300 Series"
862 depends on MMU
863 select CLKSRC_MMIO
864 select CPU_ARM926T
865 select HAVE_TCM
866 select ARM_AMBA
867 select ARM_PATCH_PHYS_VIRT
868 select ARM_VIC
869 select GENERIC_CLOCKEVENTS
870 select CLKDEV_LOOKUP
871 select COMMON_CLK
872 select GENERIC_GPIO
873 select ARCH_REQUIRE_GPIOLIB
874 select SPARSE_IRQ
875 help
876 Support for ST-Ericsson U300 series mobile platforms.
878 config ARCH_U8500
879 bool "ST-Ericsson U8500 Series"
880 depends on MMU
881 select CPU_V7
882 select ARM_AMBA
883 select GENERIC_CLOCKEVENTS
884 select CLKDEV_LOOKUP
885 select ARCH_REQUIRE_GPIOLIB
886 select ARCH_HAS_CPUFREQ
887 select HAVE_SMP
888 select MIGHT_HAVE_CACHE_L2X0
889 help
890 Support for ST-Ericsson's Ux500 architecture
892 config ARCH_NOMADIK
893 bool "STMicroelectronics Nomadik"
894 select ARM_AMBA
895 select ARM_VIC
896 select CPU_ARM926T
897 select COMMON_CLK
898 select GENERIC_CLOCKEVENTS
899 select PINCTRL
900 select PINCTRL_STN8815
901 select MIGHT_HAVE_CACHE_L2X0
902 select ARCH_REQUIRE_GPIOLIB
903 help
904 Support for the Nomadik platform by ST-Ericsson
906 config ARCH_DAVINCI
907 bool "TI DaVinci"
908 select GENERIC_CLOCKEVENTS
909 select ARCH_REQUIRE_GPIOLIB
910 select ZONE_DMA
911 select HAVE_IDE
912 select CLKDEV_LOOKUP
913 select GENERIC_ALLOCATOR
914 select GENERIC_IRQ_CHIP
915 select ARCH_HAS_HOLES_MEMORYMODEL
916 select NEED_MACH_GPIO_H
917 help
918 Support for TI's DaVinci platform.
920 config ARCH_OMAP
921 bool "TI OMAP"
922 depends on MMU
923 select HAVE_CLK
924 select ARCH_REQUIRE_GPIOLIB
925 select ARCH_HAS_CPUFREQ
926 select CLKSRC_MMIO
927 select GENERIC_CLOCKEVENTS
928 select ARCH_HAS_HOLES_MEMORYMODEL
929 select NEED_MACH_GPIO_H
930 help
931 Support for TI's OMAP platform (OMAP1/2/3/4).
933 config PLAT_SPEAR
934 bool "ST SPEAr"
935 select ARM_AMBA
936 select ARCH_REQUIRE_GPIOLIB
937 select CLKDEV_LOOKUP
938 select COMMON_CLK
939 select CLKSRC_MMIO
940 select GENERIC_CLOCKEVENTS
941 select HAVE_CLK
942 help
943 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
945 config ARCH_VT8500
946 bool "VIA/WonderMedia 85xx"
947 select CPU_ARM926T
948 select GENERIC_GPIO
949 select ARCH_HAS_CPUFREQ
950 select GENERIC_CLOCKEVENTS
951 select ARCH_REQUIRE_GPIOLIB
952 select USE_OF
953 select COMMON_CLK
954 select HAVE_CLK
955 select CLKDEV_LOOKUP
956 help
957 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
959 config ARCH_ZYNQ
960 bool "Xilinx Zynq ARM Cortex A9 Platform"
961 select CPU_V7
962 select GENERIC_CLOCKEVENTS
963 select CLKDEV_LOOKUP
964 select ARM_GIC
965 select ARM_AMBA
966 select ICST
967 select MIGHT_HAVE_CACHE_L2X0
968 select USE_OF
969 help
970 Support for Xilinx Zynq ARM Cortex A9 Platform
971 endchoice
973 menu "Multiple platform selection"
974 depends on ARCH_MULTIPLATFORM
976 comment "CPU Core family selection"
978 config ARCH_MULTI_V4
979 bool "ARMv4 based platforms (FA526, StrongARM)"
980 select ARCH_MULTI_V4_V5
981 depends on !ARCH_MULTI_V6_V7
983 config ARCH_MULTI_V4T
984 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
985 select ARCH_MULTI_V4_V5
986 depends on !ARCH_MULTI_V6_V7
988 config ARCH_MULTI_V5
989 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
990 select ARCH_MULTI_V4_V5
991 depends on !ARCH_MULTI_V6_V7
993 config ARCH_MULTI_V4_V5
994 bool
996 config ARCH_MULTI_V6
997 bool "ARMv6 based platforms (ARM11, Scorpion, ...)"
998 select CPU_V6
999 select ARCH_MULTI_V6_V7
1001 config ARCH_MULTI_V7
1002 bool "ARMv7 based platforms (Cortex-A, PJ4, Krait)"
1003 select CPU_V7
1004 select ARCH_VEXPRESS
1005 default y
1006 select ARCH_MULTI_V6_V7
1008 config ARCH_MULTI_V6_V7
1009 bool
1011 config ARCH_MULTI_CPU_AUTO
1012 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
1013 select ARCH_MULTI_V5
1015 endmenu
1017 #
1018 # This is sorted alphabetically by mach-* pathname. However, plat-*
1019 # Kconfigs may be included either alphabetically (according to the
1020 # plat- suffix) or along side the corresponding mach-* source.
1021 #
1022 source "arch/arm/mach-mvebu/Kconfig"
1024 source "arch/arm/mach-at91/Kconfig"
1026 source "arch/arm/mach-clps711x/Kconfig"
1028 source "arch/arm/mach-cns3xxx/Kconfig"
1030 source "arch/arm/mach-davinci/Kconfig"
1032 source "arch/arm/mach-dove/Kconfig"
1034 source "arch/arm/mach-ep93xx/Kconfig"
1036 source "arch/arm/mach-footbridge/Kconfig"
1038 source "arch/arm/mach-gemini/Kconfig"
1040 source "arch/arm/mach-h720x/Kconfig"
1042 source "arch/arm/mach-highbank/Kconfig"
1044 source "arch/arm/mach-integrator/Kconfig"
1046 source "arch/arm/mach-iop32x/Kconfig"
1048 source "arch/arm/mach-iop33x/Kconfig"
1050 source "arch/arm/mach-iop13xx/Kconfig"
1052 source "arch/arm/mach-ixp4xx/Kconfig"
1054 source "arch/arm/mach-kirkwood/Kconfig"
1056 source "arch/arm/mach-ks8695/Kconfig"
1058 source "arch/arm/mach-msm/Kconfig"
1060 source "arch/arm/mach-mv78xx0/Kconfig"
1062 source "arch/arm/plat-mxc/Kconfig"
1064 source "arch/arm/mach-mxs/Kconfig"
1066 source "arch/arm/mach-netx/Kconfig"
1068 source "arch/arm/mach-nomadik/Kconfig"
1069 source "arch/arm/plat-nomadik/Kconfig"
1071 source "arch/arm/plat-omap/Kconfig"
1073 source "arch/arm/mach-omap1/Kconfig"
1075 source "arch/arm/mach-omap2/Kconfig"
1077 source "arch/arm/mach-orion5x/Kconfig"
1079 source "arch/arm/mach-picoxcell/Kconfig"
1081 source "arch/arm/mach-pxa/Kconfig"
1082 source "arch/arm/plat-pxa/Kconfig"
1084 source "arch/arm/mach-mmp/Kconfig"
1086 source "arch/arm/mach-realview/Kconfig"
1088 source "arch/arm/mach-sa1100/Kconfig"
1090 source "arch/arm/plat-samsung/Kconfig"
1091 source "arch/arm/plat-s3c24xx/Kconfig"
1093 source "arch/arm/mach-socfpga/Kconfig"
1095 source "arch/arm/plat-spear/Kconfig"
1097 source "arch/arm/mach-s3c24xx/Kconfig"
1098 if ARCH_S3C24XX
1099 source "arch/arm/mach-s3c2412/Kconfig"
1100 source "arch/arm/mach-s3c2440/Kconfig"
1101 endif
1103 if ARCH_S3C64XX
1104 source "arch/arm/mach-s3c64xx/Kconfig"
1105 endif
1107 source "arch/arm/mach-s5p64x0/Kconfig"
1109 source "arch/arm/mach-s5pc100/Kconfig"
1111 source "arch/arm/mach-s5pv210/Kconfig"
1113 source "arch/arm/mach-exynos/Kconfig"
1115 source "arch/arm/mach-shmobile/Kconfig"
1117 source "arch/arm/mach-prima2/Kconfig"
1119 source "arch/arm/mach-tegra/Kconfig"
1121 source "arch/arm/mach-u300/Kconfig"
1123 source "arch/arm/mach-ux500/Kconfig"
1125 source "arch/arm/mach-versatile/Kconfig"
1127 source "arch/arm/mach-vexpress/Kconfig"
1128 source "arch/arm/plat-versatile/Kconfig"
1130 source "arch/arm/mach-w90x900/Kconfig"
1132 # Definitions to make life easier
1133 config ARCH_ACORN
1134 bool
1136 config PLAT_IOP
1137 bool
1138 select GENERIC_CLOCKEVENTS
1140 config PLAT_ORION
1141 bool
1142 select CLKSRC_MMIO
1143 select GENERIC_IRQ_CHIP
1144 select IRQ_DOMAIN
1145 select COMMON_CLK
1147 config PLAT_ORION_LEGACY
1148 bool
1149 select PLAT_ORION
1151 config PLAT_PXA
1152 bool
1154 config PLAT_VERSATILE
1155 bool
1157 config ARM_TIMER_SP804
1158 bool
1159 select CLKSRC_MMIO
1160 select HAVE_SCHED_CLOCK
1162 source arch/arm/mm/Kconfig
1164 config ARM_NR_BANKS
1165 int
1166 default 16 if ARCH_EP93XX
1167 default 8
1169 config IWMMXT
1170 bool "Enable iWMMXt support"
1171 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1172 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1173 help
1174 Enable support for iWMMXt context switching at run time if
1175 running on a CPU that supports it.
1177 config XSCALE_PMU
1178 bool
1179 depends on CPU_XSCALE
1180 default y
1182 config MULTI_IRQ_HANDLER
1183 bool
1184 help
1185 Allow each machine to specify it's own IRQ handler at run time.
1187 if !MMU
1188 source "arch/arm/Kconfig-nommu"
1189 endif
1191 config ARM_ERRATA_326103
1192 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1193 depends on CPU_V6
1194 help
1195 Executing a SWP instruction to read-only memory does not set bit 11
1196 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1197 treat the access as a read, preventing a COW from occurring and
1198 causing the faulting task to livelock.
1200 config ARM_ERRATA_411920
1201 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1202 depends on CPU_V6 || CPU_V6K
1203 help
1204 Invalidation of the Instruction Cache operation can
1205 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1206 It does not affect the MPCore. This option enables the ARM Ltd.
1207 recommended workaround.
1209 config ARM_ERRATA_430973
1210 bool "ARM errata: Stale prediction on replaced interworking branch"
1211 depends on CPU_V7
1212 help
1213 This option enables the workaround for the 430973 Cortex-A8
1214 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1215 interworking branch is replaced with another code sequence at the
1216 same virtual address, whether due to self-modifying code or virtual
1217 to physical address re-mapping, Cortex-A8 does not recover from the
1218 stale interworking branch prediction. This results in Cortex-A8
1219 executing the new code sequence in the incorrect ARM or Thumb state.
1220 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1221 and also flushes the branch target cache at every context switch.
1222 Note that setting specific bits in the ACTLR register may not be
1223 available in non-secure mode.
1225 config ARM_ERRATA_458693
1226 bool "ARM errata: Processor deadlock when a false hazard is created"
1227 depends on CPU_V7
1228 help
1229 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1230 erratum. For very specific sequences of memory operations, it is
1231 possible for a hazard condition intended for a cache line to instead
1232 be incorrectly associated with a different cache line. This false
1233 hazard might then cause a processor deadlock. The workaround enables
1234 the L1 caching of the NEON accesses and disables the PLD instruction
1235 in the ACTLR register. Note that setting specific bits in the ACTLR
1236 register may not be available in non-secure mode.
1238 config ARM_ERRATA_460075
1239 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1240 depends on CPU_V7
1241 help
1242 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1243 erratum. Any asynchronous access to the L2 cache may encounter a
1244 situation in which recent store transactions to the L2 cache are lost
1245 and overwritten with stale memory contents from external memory. The
1246 workaround disables the write-allocate mode for the L2 cache via the
1247 ACTLR register. Note that setting specific bits in the ACTLR register
1248 may not be available in non-secure mode.
1250 config ARM_ERRATA_742230
1251 bool "ARM errata: DMB operation may be faulty"
1252 depends on CPU_V7 && SMP
1253 help
1254 This option enables the workaround for the 742230 Cortex-A9
1255 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1256 between two write operations may not ensure the correct visibility
1257 ordering of the two writes. This workaround sets a specific bit in
1258 the diagnostic register of the Cortex-A9 which causes the DMB
1259 instruction to behave as a DSB, ensuring the correct behaviour of
1260 the two writes.
1262 config ARM_ERRATA_742231
1263 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1264 depends on CPU_V7 && SMP
1265 help
1266 This option enables the workaround for the 742231 Cortex-A9
1267 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1268 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1269 accessing some data located in the same cache line, may get corrupted
1270 data due to bad handling of the address hazard when the line gets
1271 replaced from one of the CPUs at the same time as another CPU is
1272 accessing it. This workaround sets specific bits in the diagnostic
1273 register of the Cortex-A9 which reduces the linefill issuing
1274 capabilities of the processor.
1276 config PL310_ERRATA_588369
1277 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1278 depends on CACHE_L2X0
1279 help
1280 The PL310 L2 cache controller implements three types of Clean &
1281 Invalidate maintenance operations: by Physical Address
1282 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1283 They are architecturally defined to behave as the execution of a
1284 clean operation followed immediately by an invalidate operation,
1285 both performing to the same memory location. This functionality
1286 is not correctly implemented in PL310 as clean lines are not
1287 invalidated as a result of these operations.
1289 config ARM_ERRATA_720789
1290 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1291 depends on CPU_V7
1292 help
1293 This option enables the workaround for the 720789 Cortex-A9 (prior to
1294 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1295 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1296 As a consequence of this erratum, some TLB entries which should be
1297 invalidated are not, resulting in an incoherency in the system page
1298 tables. The workaround changes the TLB flushing routines to invalidate
1299 entries regardless of the ASID.
1301 config PL310_ERRATA_727915
1302 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1303 depends on CACHE_L2X0
1304 help
1305 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1306 operation (offset 0x7FC). This operation runs in background so that
1307 PL310 can handle normal accesses while it is in progress. Under very
1308 rare circumstances, due to this erratum, write data can be lost when
1309 PL310 treats a cacheable write transaction during a Clean &
1310 Invalidate by Way operation.
1312 config ARM_ERRATA_743622
1313 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1314 depends on CPU_V7
1315 help
1316 This option enables the workaround for the 743622 Cortex-A9
1317 (r2p*) erratum. Under very rare conditions, a faulty
1318 optimisation in the Cortex-A9 Store Buffer may lead to data
1319 corruption. This workaround sets a specific bit in the diagnostic
1320 register of the Cortex-A9 which disables the Store Buffer
1321 optimisation, preventing the defect from occurring. This has no
1322 visible impact on the overall performance or power consumption of the
1323 processor.
1325 config ARM_ERRATA_751472
1326 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1327 depends on CPU_V7
1328 help
1329 This option enables the workaround for the 751472 Cortex-A9 (prior
1330 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1331 completion of a following broadcasted operation if the second
1332 operation is received by a CPU before the ICIALLUIS has completed,
1333 potentially leading to corrupted entries in the cache or TLB.
1335 config PL310_ERRATA_753970
1336 bool "PL310 errata: cache sync operation may be faulty"
1337 depends on CACHE_PL310
1338 help
1339 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1341 Under some condition the effect of cache sync operation on
1342 the store buffer still remains when the operation completes.
1343 This means that the store buffer is always asked to drain and
1344 this prevents it from merging any further writes. The workaround
1345 is to replace the normal offset of cache sync operation (0x730)
1346 by another offset targeting an unmapped PL310 register 0x740.
1347 This has the same effect as the cache sync operation: store buffer
1348 drain and waiting for all buffers empty.
1350 config ARM_ERRATA_754322
1351 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1352 depends on CPU_V7
1353 help
1354 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1355 r3p*) erratum. A speculative memory access may cause a page table walk
1356 which starts prior to an ASID switch but completes afterwards. This
1357 can populate the micro-TLB with a stale entry which may be hit with
1358 the new ASID. This workaround places two dsb instructions in the mm
1359 switching code so that no page table walks can cross the ASID switch.
1361 config ARM_ERRATA_754327
1362 bool "ARM errata: no automatic Store Buffer drain"
1363 depends on CPU_V7 && SMP
1364 help
1365 This option enables the workaround for the 754327 Cortex-A9 (prior to
1366 r2p0) erratum. The Store Buffer does not have any automatic draining
1367 mechanism and therefore a livelock may occur if an external agent
1368 continuously polls a memory location waiting to observe an update.
1369 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1370 written polling loops from denying visibility of updates to memory.
1372 config ARM_ERRATA_364296
1373 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1374 depends on CPU_V6 && !SMP
1375 help
1376 This options enables the workaround for the 364296 ARM1136
1377 r0p2 erratum (possible cache data corruption with
1378 hit-under-miss enabled). It sets the undocumented bit 31 in
1379 the auxiliary control register and the FI bit in the control
1380 register, thus disabling hit-under-miss without putting the
1381 processor into full low interrupt latency mode. ARM11MPCore
1382 is not affected.
1384 config ARM_ERRATA_764369
1385 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1386 depends on CPU_V7 && SMP
1387 help
1388 This option enables the workaround for erratum 764369
1389 affecting Cortex-A9 MPCore with two or more processors (all
1390 current revisions). Under certain timing circumstances, a data
1391 cache line maintenance operation by MVA targeting an Inner
1392 Shareable memory region may fail to proceed up to either the
1393 Point of Coherency or to the Point of Unification of the
1394 system. This workaround adds a DSB instruction before the
1395 relevant cache maintenance functions and sets a specific bit
1396 in the diagnostic control register of the SCU.
1398 config PL310_ERRATA_769419
1399 bool "PL310 errata: no automatic Store Buffer drain"
1400 depends on CACHE_L2X0
1401 help
1402 On revisions of the PL310 prior to r3p2, the Store Buffer does
1403 not automatically drain. This can cause normal, non-cacheable
1404 writes to be retained when the memory system is idle, leading
1405 to suboptimal I/O performance for drivers using coherent DMA.
1406 This option adds a write barrier to the cpu_idle loop so that,
1407 on systems with an outer cache, the store buffer is drained
1408 explicitly.
1410 config ARM_ERRATA_775420
1411 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1412 depends on CPU_V7
1413 help
1414 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1415 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1416 operation aborts with MMU exception, it might cause the processor
1417 to deadlock. This workaround puts DSB before executing ISB if
1418 an abort may occur on cache maintenance.
1420 endmenu
1422 source "arch/arm/common/Kconfig"
1424 menu "Bus support"
1426 config ARM_AMBA
1427 bool
1429 config ISA
1430 bool
1431 help
1432 Find out whether you have ISA slots on your motherboard. ISA is the
1433 name of a bus system, i.e. the way the CPU talks to the other stuff
1434 inside your box. Other bus systems are PCI, EISA, MicroChannel
1435 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1436 newer boards don't support it. If you have ISA, say Y, otherwise N.
1438 # Select ISA DMA controller support
1439 config ISA_DMA
1440 bool
1441 select ISA_DMA_API
1443 # Select ISA DMA interface
1444 config ISA_DMA_API
1445 bool
1447 config PCI
1448 bool "PCI support" if MIGHT_HAVE_PCI
1449 help
1450 Find out whether you have a PCI motherboard. PCI is the name of a
1451 bus system, i.e. the way the CPU talks to the other stuff inside
1452 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1453 VESA. If you have PCI, say Y, otherwise N.
1455 config PCI_DOMAINS
1456 bool
1457 depends on PCI
1459 config PCI_NANOENGINE
1460 bool "BSE nanoEngine PCI support"
1461 depends on SA1100_NANOENGINE
1462 help
1463 Enable PCI on the BSE nanoEngine board.
1465 config PCI_SYSCALL
1466 def_bool PCI
1468 # Select the host bridge type
1469 config PCI_HOST_VIA82C505
1470 bool
1471 depends on PCI && ARCH_SHARK
1472 default y
1474 config PCI_HOST_ITE8152
1475 bool
1476 depends on PCI && MACH_ARMCORE
1477 default y
1478 select DMABOUNCE
1480 source "drivers/pci/Kconfig"
1482 source "drivers/pcmcia/Kconfig"
1484 endmenu
1486 menu "Kernel Features"
1488 config HAVE_SMP
1489 bool
1490 help
1491 This option should be selected by machines which have an SMP-
1492 capable CPU.
1494 The only effect of this option is to make the SMP-related
1495 options available to the user for configuration.
1497 config SMP
1498 bool "Symmetric Multi-Processing"
1499 depends on CPU_V6K || CPU_V7
1500 depends on GENERIC_CLOCKEVENTS
1501 depends on HAVE_SMP
1502 depends on MMU
1503 select USE_GENERIC_SMP_HELPERS
1504 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1505 help
1506 This enables support for systems with more than one CPU. If you have
1507 a system with only one CPU, like most personal computers, say N. If
1508 you have a system with more than one CPU, say Y.
1510 If you say N here, the kernel will run on single and multiprocessor
1511 machines, but will use only one CPU of a multiprocessor machine. If
1512 you say Y here, the kernel will run on many, but not all, single
1513 processor machines. On a single processor machine, the kernel will
1514 run faster if you say N here.
1516 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1517 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1518 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1520 If you don't know what to do here, say N.
1522 config SMP_ON_UP
1523 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1524 depends on EXPERIMENTAL
1525 depends on SMP && !XIP_KERNEL
1526 default y
1527 help
1528 SMP kernels contain instructions which fail on non-SMP processors.
1529 Enabling this option allows the kernel to modify itself to make
1530 these instructions safe. Disabling it allows about 1K of space
1531 savings.
1533 If you don't know what to do here, say Y.
1535 config ARM_CPU_TOPOLOGY
1536 bool "Support cpu topology definition"
1537 depends on SMP && CPU_V7
1538 default y
1539 help
1540 Support ARM cpu topology definition. The MPIDR register defines
1541 affinity between processors which is then used to describe the cpu
1542 topology of an ARM System.
1544 config SCHED_MC
1545 bool "Multi-core scheduler support"
1546 depends on ARM_CPU_TOPOLOGY
1547 help
1548 Multi-core scheduler support improves the CPU scheduler's decision
1549 making when dealing with multi-core CPU chips at a cost of slightly
1550 increased overhead in some places. If unsure say N here.
1552 config SCHED_SMT
1553 bool "SMT scheduler support"
1554 depends on ARM_CPU_TOPOLOGY
1555 help
1556 Improves the CPU scheduler's decision making when dealing with
1557 MultiThreading at a cost of slightly increased overhead in some
1558 places. If unsure say N here.
1560 config HAVE_ARM_SCU
1561 bool
1562 help
1563 This option enables support for the ARM system coherency unit
1565 config ARM_ARCH_TIMER
1566 bool "Architected timer support"
1567 depends on CPU_V7
1568 help
1569 This option enables support for the ARM architected timer
1571 config HAVE_ARM_TWD
1572 bool
1573 depends on SMP
1574 help
1575 This options enables support for the ARM timer and watchdog unit
1577 choice
1578 prompt "Memory split"
1579 default VMSPLIT_3G
1580 help
1581 Select the desired split between kernel and user memory.
1583 If you are not absolutely sure what you are doing, leave this
1584 option alone!
1586 config VMSPLIT_3G
1587 bool "3G/1G user/kernel split"
1588 config VMSPLIT_2G
1589 bool "2G/2G user/kernel split"
1590 config VMSPLIT_1G
1591 bool "1G/3G user/kernel split"
1592 endchoice
1594 config PAGE_OFFSET
1595 hex
1596 default 0x40000000 if VMSPLIT_1G
1597 default 0x80000000 if VMSPLIT_2G
1598 default 0xC0000000
1600 config NR_CPUS
1601 int "Maximum number of CPUs (2-32)"
1602 range 2 32
1603 depends on SMP
1604 default "4"
1606 config HOTPLUG_CPU
1607 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1608 depends on SMP && HOTPLUG && EXPERIMENTAL
1609 help
1610 Say Y here to experiment with turning CPUs off and on. CPUs
1611 can be controlled through /sys/devices/system/cpu.
1613 config LOCAL_TIMERS
1614 bool "Use local timer interrupts"
1615 depends on SMP
1616 default y
1617 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1618 help
1619 Enable support for local timers on SMP platforms, rather then the
1620 legacy IPI broadcast method. Local timers allows the system
1621 accounting to be spread across the timer interval, preventing a
1622 "thundering herd" at every timer tick.
1624 config ARCH_NR_GPIO
1625 int
1626 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1627 default 355 if ARCH_U8500
1628 default 264 if MACH_H4700
1629 default 512 if SOC_OMAP5
1630 default 288 if ARCH_VT8500
1631 default 0
1632 help
1633 Maximum number of GPIOs in the system.
1635 If unsure, leave the default value.
1637 source kernel/Kconfig.preempt
1639 config HZ
1640 int
1641 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1642 ARCH_S5PV210 || ARCH_EXYNOS4
1643 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1644 default AT91_TIMER_HZ if ARCH_AT91
1645 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1646 default 100
1648 config THUMB2_KERNEL
1649 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1650 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1651 select AEABI
1652 select ARM_ASM_UNIFIED
1653 select ARM_UNWIND
1654 help
1655 By enabling this option, the kernel will be compiled in
1656 Thumb-2 mode. A compiler/assembler that understand the unified
1657 ARM-Thumb syntax is needed.
1659 If unsure, say N.
1661 config THUMB2_AVOID_R_ARM_THM_JUMP11
1662 bool "Work around buggy Thumb-2 short branch relocations in gas"
1663 depends on THUMB2_KERNEL && MODULES
1664 default y
1665 help
1666 Various binutils versions can resolve Thumb-2 branches to
1667 locally-defined, preemptible global symbols as short-range "b.n"
1668 branch instructions.
1670 This is a problem, because there's no guarantee the final
1671 destination of the symbol, or any candidate locations for a
1672 trampoline, are within range of the branch. For this reason, the
1673 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1674 relocation in modules at all, and it makes little sense to add
1675 support.
1677 The symptom is that the kernel fails with an "unsupported
1678 relocation" error when loading some modules.
1680 Until fixed tools are available, passing
1681 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1682 code which hits this problem, at the cost of a bit of extra runtime
1683 stack usage in some cases.
1685 The problem is described in more detail at:
1686 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1688 Only Thumb-2 kernels are affected.
1690 Unless you are sure your tools don't have this problem, say Y.
1692 config ARM_ASM_UNIFIED
1693 bool
1695 config AEABI
1696 bool "Use the ARM EABI to compile the kernel"
1697 help
1698 This option allows for the kernel to be compiled using the latest
1699 ARM ABI (aka EABI). This is only useful if you are using a user
1700 space environment that is also compiled with EABI.
1702 Since there are major incompatibilities between the legacy ABI and
1703 EABI, especially with regard to structure member alignment, this
1704 option also changes the kernel syscall calling convention to
1705 disambiguate both ABIs and allow for backward compatibility support
1706 (selected with CONFIG_OABI_COMPAT).
1708 To use this you need GCC version 4.0.0 or later.
1710 config OABI_COMPAT
1711 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1712 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1713 default y
1714 help
1715 This option preserves the old syscall interface along with the
1716 new (ARM EABI) one. It also provides a compatibility layer to
1717 intercept syscalls that have structure arguments which layout
1718 in memory differs between the legacy ABI and the new ARM EABI
1719 (only for non "thumb" binaries). This option adds a tiny
1720 overhead to all syscalls and produces a slightly larger kernel.
1721 If you know you'll be using only pure EABI user space then you
1722 can say N here. If this option is not selected and you attempt
1723 to execute a legacy ABI binary then the result will be
1724 UNPREDICTABLE (in fact it can be predicted that it won't work
1725 at all). If in doubt say Y.
1727 config ARCH_HAS_HOLES_MEMORYMODEL
1728 bool
1730 config ARCH_SPARSEMEM_ENABLE
1731 bool
1733 config ARCH_SPARSEMEM_DEFAULT
1734 def_bool ARCH_SPARSEMEM_ENABLE
1736 config ARCH_SELECT_MEMORY_MODEL
1737 def_bool ARCH_SPARSEMEM_ENABLE
1739 config HAVE_ARCH_PFN_VALID
1740 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1742 config HIGHMEM
1743 bool "High Memory Support"
1744 depends on MMU
1745 help
1746 The address space of ARM processors is only 4 Gigabytes large
1747 and it has to accommodate user address space, kernel address
1748 space as well as some memory mapped IO. That means that, if you
1749 have a large amount of physical memory and/or IO, not all of the
1750 memory can be "permanently mapped" by the kernel. The physical
1751 memory that is not permanently mapped is called "high memory".
1753 Depending on the selected kernel/user memory split, minimum
1754 vmalloc space and actual amount of RAM, you may not need this
1755 option which should result in a slightly faster kernel.
1757 If unsure, say n.
1759 config HIGHPTE
1760 bool "Allocate 2nd-level pagetables from highmem"
1761 depends on HIGHMEM
1763 config HW_PERF_EVENTS
1764 bool "Enable hardware performance counter support for perf events"
1765 depends on PERF_EVENTS
1766 default y
1767 help
1768 Enable hardware performance counter support for perf events. If
1769 disabled, perf events will use software events only.
1771 source "mm/Kconfig"
1773 config FORCE_MAX_ZONEORDER
1774 int "Maximum zone order" if ARCH_SHMOBILE
1775 range 11 64 if ARCH_SHMOBILE
1776 default "12" if SOC_AM33XX
1777 default "9" if SA1111
1778 default "11"
1779 help
1780 The kernel memory allocator divides physically contiguous memory
1781 blocks into "zones", where each zone is a power of two number of
1782 pages. This option selects the largest power of two that the kernel
1783 keeps in the memory allocator. If you need to allocate very large
1784 blocks of physically contiguous memory, then you may need to
1785 increase this value.
1787 This config option is actually maximum order plus one. For example,
1788 a value of 11 means that the largest free memory block is 2^10 pages.
1790 config ALIGNMENT_TRAP
1791 bool
1792 depends on CPU_CP15_MMU
1793 default y if !ARCH_EBSA110
1794 select HAVE_PROC_CPU if PROC_FS
1795 help
1796 ARM processors cannot fetch/store information which is not
1797 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1798 address divisible by 4. On 32-bit ARM processors, these non-aligned
1799 fetch/store instructions will be emulated in software if you say
1800 here, which has a severe performance impact. This is necessary for
1801 correct operation of some network protocols. With an IP-only
1802 configuration it is safe to say N, otherwise say Y.
1804 config UACCESS_WITH_MEMCPY
1805 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1806 depends on MMU
1807 default y if CPU_FEROCEON
1808 help
1809 Implement faster copy_to_user and clear_user methods for CPU
1810 cores where a 8-word STM instruction give significantly higher
1811 memory write throughput than a sequence of individual 32bit stores.
1813 A possible side effect is a slight increase in scheduling latency
1814 between threads sharing the same address space if they invoke
1815 such copy operations with large buffers.
1817 However, if the CPU data cache is using a write-allocate mode,
1818 this option is unlikely to provide any performance gain.
1820 config SECCOMP
1821 bool
1822 prompt "Enable seccomp to safely compute untrusted bytecode"
1823 ---help---
1824 This kernel feature is useful for number crunching applications
1825 that may need to compute untrusted bytecode during their
1826 execution. By using pipes or other transports made available to
1827 the process as file descriptors supporting the read/write
1828 syscalls, it's possible to isolate those applications in
1829 their own address space using seccomp. Once seccomp is
1830 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1831 and the task is only allowed to execute a few safe syscalls
1832 defined by each seccomp mode.
1834 config CC_STACKPROTECTOR
1835 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1836 depends on EXPERIMENTAL
1837 help
1838 This option turns on the -fstack-protector GCC feature. This
1839 feature puts, at the beginning of functions, a canary value on
1840 the stack just before the return address, and validates
1841 the value just before actually returning. Stack based buffer
1842 overflows (that need to overwrite this return address) now also
1843 overwrite the canary, which gets detected and the attack is then
1844 neutralized via a kernel panic.
1845 This feature requires gcc version 4.2 or above.
1847 config XEN_DOM0
1848 def_bool y
1849 depends on XEN
1851 config XEN
1852 bool "Xen guest support on ARM (EXPERIMENTAL)"
1853 depends on EXPERIMENTAL && ARM && OF
1854 help
1855 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1857 endmenu
1859 menu "Boot options"
1861 config USE_OF
1862 bool "Flattened Device Tree support"
1863 select OF
1864 select OF_EARLY_FLATTREE
1865 select IRQ_DOMAIN
1866 help
1867 Include support for flattened device tree machine descriptions.
1869 config ATAGS
1870 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1871 default y
1872 help
1873 This is the traditional way of passing data to the kernel at boot
1874 time. If you are solely relying on the flattened device tree (or
1875 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1876 to remove ATAGS support from your kernel binary. If unsure,
1877 leave this to y.
1879 config DEPRECATED_PARAM_STRUCT
1880 bool "Provide old way to pass kernel parameters"
1881 depends on ATAGS
1882 help
1883 This was deprecated in 2001 and announced to live on for 5 years.
1884 Some old boot loaders still use this way.
1886 # Compressed boot loader in ROM. Yes, we really want to ask about
1887 # TEXT and BSS so we preserve their values in the config files.
1888 config ZBOOT_ROM_TEXT
1889 hex "Compressed ROM boot loader base address"
1890 default "0"
1891 help
1892 The physical address at which the ROM-able zImage is to be
1893 placed in the target. Platforms which normally make use of
1894 ROM-able zImage formats normally set this to a suitable
1895 value in their defconfig file.
1897 If ZBOOT_ROM is not enabled, this has no effect.
1899 config ZBOOT_ROM_BSS
1900 hex "Compressed ROM boot loader BSS address"
1901 default "0"
1902 help
1903 The base address of an area of read/write memory in the target
1904 for the ROM-able zImage which must be available while the
1905 decompressor is running. It must be large enough to hold the
1906 entire decompressed kernel plus an additional 128 KiB.
1907 Platforms which normally make use of ROM-able zImage formats
1908 normally set this to a suitable value in their defconfig file.
1910 If ZBOOT_ROM is not enabled, this has no effect.
1912 config ZBOOT_ROM
1913 bool "Compressed boot loader in ROM/flash"
1914 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1915 help
1916 Say Y here if you intend to execute your compressed kernel image
1917 (zImage) directly from ROM or flash. If unsure, say N.
1919 choice
1920 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1921 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1922 default ZBOOT_ROM_NONE
1923 help
1924 Include experimental SD/MMC loading code in the ROM-able zImage.
1925 With this enabled it is possible to write the ROM-able zImage
1926 kernel image to an MMC or SD card and boot the kernel straight
1927 from the reset vector. At reset the processor Mask ROM will load
1928 the first part of the ROM-able zImage which in turn loads the
1929 rest the kernel image to RAM.
1931 config ZBOOT_ROM_NONE
1932 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1933 help
1934 Do not load image from SD or MMC
1936 config ZBOOT_ROM_MMCIF
1937 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1938 help
1939 Load image from MMCIF hardware block.
1941 config ZBOOT_ROM_SH_MOBILE_SDHI
1942 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1943 help
1944 Load image from SDHI hardware block
1946 endchoice
1948 config ARM_APPENDED_DTB
1949 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1950 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1951 help
1952 With this option, the boot code will look for a device tree binary
1953 (DTB) appended to zImage
1954 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1956 This is meant as a backward compatibility convenience for those
1957 systems with a bootloader that can't be upgraded to accommodate
1958 the documented boot protocol using a device tree.
1960 Beware that there is very little in terms of protection against
1961 this option being confused by leftover garbage in memory that might
1962 look like a DTB header after a reboot if no actual DTB is appended
1963 to zImage. Do not leave this option active in a production kernel
1964 if you don't intend to always append a DTB. Proper passing of the
1965 location into r2 of a bootloader provided DTB is always preferable
1966 to this option.
1968 config ARM_ATAG_DTB_COMPAT
1969 bool "Supplement the appended DTB with traditional ATAG information"
1970 depends on ARM_APPENDED_DTB
1971 help
1972 Some old bootloaders can't be updated to a DTB capable one, yet
1973 they provide ATAGs with memory configuration, the ramdisk address,
1974 the kernel cmdline string, etc. Such information is dynamically
1975 provided by the bootloader and can't always be stored in a static
1976 DTB. To allow a device tree enabled kernel to be used with such
1977 bootloaders, this option allows zImage to extract the information
1978 from the ATAG list and store it at run time into the appended DTB.
1980 choice
1981 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1982 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1984 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1985 bool "Use bootloader kernel arguments if available"
1986 help
1987 Uses the command-line options passed by the boot loader instead of
1988 the device tree bootargs property. If the boot loader doesn't provide
1989 any, the device tree bootargs property will be used.
1991 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1992 bool "Extend with bootloader kernel arguments"
1993 help
1994 The command-line arguments provided by the boot loader will be
1995 appended to the the device tree bootargs property.
1997 endchoice
1999 config CMDLINE
2000 string "Default kernel command string"
2001 default ""
2002 help
2003 On some architectures (EBSA110 and CATS), there is currently no way
2004 for the boot loader to pass arguments to the kernel. For these
2005 architectures, you should supply some command-line options at build
2006 time by entering them here. As a minimum, you should specify the
2007 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2009 choice
2010 prompt "Kernel command line type" if CMDLINE != ""
2011 default CMDLINE_FROM_BOOTLOADER
2012 depends on ATAGS
2014 config CMDLINE_FROM_BOOTLOADER
2015 bool "Use bootloader kernel arguments if available"
2016 help
2017 Uses the command-line options passed by the boot loader. If
2018 the boot loader doesn't provide any, the default kernel command
2019 string provided in CMDLINE will be used.
2021 config CMDLINE_EXTEND
2022 bool "Extend bootloader kernel arguments"
2023 help
2024 The command-line arguments provided by the boot loader will be
2025 appended to the default kernel command string.
2027 config CMDLINE_FORCE
2028 bool "Always use the default kernel command string"
2029 help
2030 Always use the default kernel command string, even if the boot
2031 loader passes other arguments to the kernel.
2032 This is useful if you cannot or don't want to change the
2033 command-line options your boot loader passes to the kernel.
2034 endchoice
2036 config XIP_KERNEL
2037 bool "Kernel Execute-In-Place from ROM"
2038 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2039 help
2040 Execute-In-Place allows the kernel to run from non-volatile storage
2041 directly addressable by the CPU, such as NOR flash. This saves RAM
2042 space since the text section of the kernel is not loaded from flash
2043 to RAM. Read-write sections, such as the data section and stack,
2044 are still copied to RAM. The XIP kernel is not compressed since
2045 it has to run directly from flash, so it will take more space to
2046 store it. The flash address used to link the kernel object files,
2047 and for storing it, is configuration dependent. Therefore, if you
2048 say Y here, you must know the proper physical address where to
2049 store the kernel image depending on your own flash memory usage.
2051 Also note that the make target becomes "make xipImage" rather than
2052 "make zImage" or "make Image". The final kernel binary to put in
2053 ROM memory will be arch/arm/boot/xipImage.
2055 If unsure, say N.
2057 config XIP_PHYS_ADDR
2058 hex "XIP Kernel Physical Location"
2059 depends on XIP_KERNEL
2060 default "0x00080000"
2061 help
2062 This is the physical address in your flash memory the kernel will
2063 be linked for and stored to. This address is dependent on your
2064 own flash usage.
2066 config KEXEC
2067 bool "Kexec system call (EXPERIMENTAL)"
2068 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2069 help
2070 kexec is a system call that implements the ability to shutdown your
2071 current kernel, and to start another kernel. It is like a reboot
2072 but it is independent of the system firmware. And like a reboot
2073 you can start any kernel with it, not just Linux.
2075 It is an ongoing process to be certain the hardware in a machine
2076 is properly shutdown, so do not be surprised if this code does not
2077 initially work for you. It may help to enable device hotplugging
2078 support.
2080 config ATAGS_PROC
2081 bool "Export atags in procfs"
2082 depends on ATAGS && KEXEC
2083 default y
2084 help
2085 Should the atags used to boot the kernel be exported in an "atags"
2086 file in procfs. Useful with kexec.
2088 config CRASH_DUMP
2089 bool "Build kdump crash kernel (EXPERIMENTAL)"
2090 depends on EXPERIMENTAL
2091 help
2092 Generate crash dump after being started by kexec. This should
2093 be normally only set in special crash dump kernels which are
2094 loaded in the main kernel with kexec-tools into a specially
2095 reserved region and then later executed after a crash by
2096 kdump/kexec. The crash dump kernel must be compiled to a
2097 memory address not used by the main kernel
2099 For more details see Documentation/kdump/kdump.txt
2101 config AUTO_ZRELADDR
2102 bool "Auto calculation of the decompressed kernel image address"
2103 depends on !ZBOOT_ROM && !ARCH_U300
2104 help
2105 ZRELADDR is the physical address where the decompressed kernel
2106 image will be placed. If AUTO_ZRELADDR is selected, the address
2107 will be determined at run-time by masking the current IP with
2108 0xf8000000. This assumes the zImage being placed in the first 128MB
2109 from start of memory.
2111 endmenu
2113 menu "CPU Power Management"
2115 if ARCH_HAS_CPUFREQ
2117 source "drivers/cpufreq/Kconfig"
2119 config CPU_FREQ_IMX
2120 tristate "CPUfreq driver for i.MX CPUs"
2121 depends on ARCH_MXC && CPU_FREQ
2122 select CPU_FREQ_TABLE
2123 help
2124 This enables the CPUfreq driver for i.MX CPUs.
2126 config CPU_FREQ_SA1100
2127 bool
2129 config CPU_FREQ_SA1110
2130 bool
2132 config CPU_FREQ_INTEGRATOR
2133 tristate "CPUfreq driver for ARM Integrator CPUs"
2134 depends on ARCH_INTEGRATOR && CPU_FREQ
2135 default y
2136 help
2137 This enables the CPUfreq driver for ARM Integrator CPUs.
2139 For details, take a look at <file:Documentation/cpu-freq>.
2141 If in doubt, say Y.
2143 config CPU_FREQ_PXA
2144 bool
2145 depends on CPU_FREQ && ARCH_PXA && PXA25x
2146 default y
2147 select CPU_FREQ_TABLE
2148 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2150 config CPU_FREQ_S3C
2151 bool
2152 help
2153 Internal configuration node for common cpufreq on Samsung SoC
2155 config CPU_FREQ_S3C24XX
2156 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2157 depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2158 select CPU_FREQ_S3C
2159 help
2160 This enables the CPUfreq driver for the Samsung S3C24XX family
2161 of CPUs.
2163 For details, take a look at <file:Documentation/cpu-freq>.
2165 If in doubt, say N.
2167 config CPU_FREQ_S3C24XX_PLL
2168 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2169 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2170 help
2171 Compile in support for changing the PLL frequency from the
2172 S3C24XX series CPUfreq driver. The PLL takes time to settle
2173 after a frequency change, so by default it is not enabled.
2175 This also means that the PLL tables for the selected CPU(s) will
2176 be built which may increase the size of the kernel image.
2178 config CPU_FREQ_S3C24XX_DEBUG
2179 bool "Debug CPUfreq Samsung driver core"
2180 depends on CPU_FREQ_S3C24XX
2181 help
2182 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2184 config CPU_FREQ_S3C24XX_IODEBUG
2185 bool "Debug CPUfreq Samsung driver IO timing"
2186 depends on CPU_FREQ_S3C24XX
2187 help
2188 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2190 config CPU_FREQ_S3C24XX_DEBUGFS
2191 bool "Export debugfs for CPUFreq"
2192 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2193 help
2194 Export status information via debugfs.
2196 endif
2198 source "drivers/cpuidle/Kconfig"
2200 endmenu
2202 menu "Floating point emulation"
2204 comment "At least one emulation must be selected"
2206 config FPE_NWFPE
2207 bool "NWFPE math emulation"
2208 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2209 ---help---
2210 Say Y to include the NWFPE floating point emulator in the kernel.
2211 This is necessary to run most binaries. Linux does not currently
2212 support floating point hardware so you need to say Y here even if
2213 your machine has an FPA or floating point co-processor podule.
2215 You may say N here if you are going to load the Acorn FPEmulator
2216 early in the bootup.
2218 config FPE_NWFPE_XP
2219 bool "Support extended precision"
2220 depends on FPE_NWFPE
2221 help
2222 Say Y to include 80-bit support in the kernel floating-point
2223 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2224 Note that gcc does not generate 80-bit operations by default,
2225 so in most cases this option only enlarges the size of the
2226 floating point emulator without any good reason.
2228 You almost surely want to say N here.
2230 config FPE_FASTFPE
2231 bool "FastFPE math emulation (EXPERIMENTAL)"
2232 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2233 ---help---
2234 Say Y here to include the FAST floating point emulator in the kernel.
2235 This is an experimental much faster emulator which now also has full
2236 precision for the mantissa. It does not support any exceptions.
2237 It is very simple, and approximately 3-6 times faster than NWFPE.
2239 It should be sufficient for most programs. It may be not suitable
2240 for scientific calculations, but you have to check this for yourself.
2241 If you do not feel you need a faster FP emulation you should better
2242 choose NWFPE.
2244 config VFP
2245 bool "VFP-format floating point maths"
2246 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2247 help
2248 Say Y to include VFP support code in the kernel. This is needed
2249 if your hardware includes a VFP unit.
2251 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2252 release notes and additional status information.
2254 Say N if your target does not have VFP hardware.
2256 config VFPv3
2257 bool
2258 depends on VFP
2259 default y if CPU_V7
2261 config NEON
2262 bool "Advanced SIMD (NEON) Extension support"
2263 depends on VFPv3 && CPU_V7
2264 help
2265 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2266 Extension.
2268 endmenu
2270 menu "Userspace binary formats"
2272 source "fs/Kconfig.binfmt"
2274 config ARTHUR
2275 tristate "RISC OS personality"
2276 depends on !AEABI
2277 help
2278 Say Y here to include the kernel code necessary if you want to run
2279 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2280 experimental; if this sounds frightening, say N and sleep in peace.
2281 You can also say M here to compile this support as a module (which
2282 will be called arthur).
2284 endmenu
2286 menu "Power management options"
2288 source "kernel/power/Kconfig"
2290 config ARCH_SUSPEND_POSSIBLE
2291 depends on !ARCH_S5PC100
2292 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2293 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2294 def_bool y
2296 config ARM_CPU_SUSPEND
2297 def_bool PM_SLEEP
2299 endmenu
2301 source "net/Kconfig"
2303 source "drivers/Kconfig"
2305 source "fs/Kconfig"
2307 source "arch/arm/Kconfig.debug"
2309 source "security/Kconfig"
2311 source "crypto/Kconfig"
2313 source "lib/Kconfig"