arch/arm/mach-integrator/integrator_ap.c

   1 /*
   2  *  linux/arch/arm/mach-integrator/integrator_ap.c
   3  *
   4  *  Copyright (C) 2000-2003 Deep Blue Solutions Ltd
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #include <linux/types.h>
  21 #include <linux/kernel.h>
  22 #include <linux/init.h>
  23 #include <linux/list.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/slab.h>
  26 #include <linux/string.h>
  27 #include <linux/sysdev.h>
  28 #include <linux/amba/bus.h>
  29 #include <linux/amba/kmi.h>
  30 #include <linux/clocksource.h>
  31 #include <linux/clockchips.h>
  32 #include <linux/interrupt.h>
  33 #include <linux/io.h>
  34 #include <linux/mtd/physmap.h>
  35
  36 #include <mach/hardware.h>
  37 #include <mach/platform.h>
  38 #include <asm/hardware/arm_timer.h>
  39 #include <asm/irq.h>
  40 #include <asm/setup.h>
  41 #include <asm/param.h>          /* HZ */
  42 #include <asm/mach-types.h>
  43
  44 #include <mach/lm.h>
  45
  46 #include <asm/mach/arch.h>
  47 #include <asm/mach/irq.h>
  48 #include <asm/mach/map.h>
  49 #include <asm/mach/time.h>
  50
  51 #include <plat/fpga-irq.h>
  52
  53 #include "common.h"
  54
  55 /*
  56  * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
  57  * is the (PA >> 12).
  58  *
  59  * Setup a VA for the Integrator interrupt controller (for header #0,
  60  * just for now).
  61  */
  62 #define VA_IC_BASE      __io_address(INTEGRATOR_IC_BASE)
  63 #define VA_SC_BASE      __io_address(INTEGRATOR_SC_BASE)
  64 #define VA_EBI_BASE     __io_address(INTEGRATOR_EBI_BASE)
  65 #define VA_CMIC_BASE    __io_address(INTEGRATOR_HDR_IC)
  66
  67 /*
  68  * Logical      Physical
  69  * e8000000     40000000        PCI memory              PHYS_PCI_MEM_BASE       (max 512M)
  70  * ec000000     61000000        PCI config space        PHYS_PCI_CONFIG_BASE    (max 16M)
  71  * ed000000     62000000        PCI V3 regs             PHYS_PCI_V3_BASE        (max 64k)
  72  * ee000000     60000000        PCI IO                  PHYS_PCI_IO_BASE        (max 16M)
  73  * ef000000                     Cache flush
  74  * f1000000     10000000        Core module registers
  75  * f1100000     11000000        System controller registers
  76  * f1200000     12000000        EBI registers
  77  * f1300000     13000000        Counter/Timer
  78  * f1400000     14000000        Interrupt controller
  79  * f1600000     16000000        UART 0
  80  * f1700000     17000000        UART 1
  81  * f1a00000     1a000000        Debug LEDs
  82  * f1b00000     1b000000        GPIO
  83  */
  84
  85 static struct map_desc ap_io_desc[] __initdata = {
  86         {
  87                 .virtual        = IO_ADDRESS(INTEGRATOR_HDR_BASE),
  88                 .pfn            = __phys_to_pfn(INTEGRATOR_HDR_BASE),
  89                 .length         = SZ_4K,
  90                 .type           = MT_DEVICE
  91         }, {
  92                 .virtual        = IO_ADDRESS(INTEGRATOR_SC_BASE),
  93                 .pfn            = __phys_to_pfn(INTEGRATOR_SC_BASE),
  94                 .length         = SZ_4K,
  95                 .type           = MT_DEVICE
  96         }, {
  97                 .virtual        = IO_ADDRESS(INTEGRATOR_EBI_BASE),
  98                 .pfn            = __phys_to_pfn(INTEGRATOR_EBI_BASE),
  99                 .length         = SZ_4K,
 100                 .type           = MT_DEVICE
 101         }, {
 102                 .virtual        = IO_ADDRESS(INTEGRATOR_CT_BASE),
 103                 .pfn            = __phys_to_pfn(INTEGRATOR_CT_BASE),
 104                 .length         = SZ_4K,
 105                 .type           = MT_DEVICE
 106         }, {
 107                 .virtual        = IO_ADDRESS(INTEGRATOR_IC_BASE),
 108                 .pfn            = __phys_to_pfn(INTEGRATOR_IC_BASE),
 109                 .length         = SZ_4K,
 110                 .type           = MT_DEVICE
 111         }, {
 112                 .virtual        = IO_ADDRESS(INTEGRATOR_UART0_BASE),
 113                 .pfn            = __phys_to_pfn(INTEGRATOR_UART0_BASE),
 114                 .length         = SZ_4K,
 115                 .type           = MT_DEVICE
 116         }, {
 117                 .virtual        = IO_ADDRESS(INTEGRATOR_UART1_BASE),
 118                 .pfn            = __phys_to_pfn(INTEGRATOR_UART1_BASE),
 119                 .length         = SZ_4K,
 120                 .type           = MT_DEVICE
 121         }, {
 122                 .virtual        = IO_ADDRESS(INTEGRATOR_DBG_BASE),
 123                 .pfn            = __phys_to_pfn(INTEGRATOR_DBG_BASE),
 124                 .length         = SZ_4K,
 125                 .type           = MT_DEVICE
 126         }, {
 127                 .virtual        = IO_ADDRESS(INTEGRATOR_AP_GPIO_BASE),
 128                 .pfn            = __phys_to_pfn(INTEGRATOR_AP_GPIO_BASE),
 129                 .length         = SZ_4K,
 130                 .type           = MT_DEVICE
 131         }, {
 132                 .virtual        = PCI_MEMORY_VADDR,
 133                 .pfn            = __phys_to_pfn(PHYS_PCI_MEM_BASE),
 134                 .length         = SZ_16M,
 135                 .type           = MT_DEVICE
 136         }, {
 137                 .virtual        = PCI_CONFIG_VADDR,
 138                 .pfn            = __phys_to_pfn(PHYS_PCI_CONFIG_BASE),
 139                 .length         = SZ_16M,
 140                 .type           = MT_DEVICE
 141         }, {
 142                 .virtual        = PCI_V3_VADDR,
 143                 .pfn            = __phys_to_pfn(PHYS_PCI_V3_BASE),
 144                 .length         = SZ_64K,
 145                 .type           = MT_DEVICE
 146         }, {
 147                 .virtual        = PCI_IO_VADDR,
 148                 .pfn            = __phys_to_pfn(PHYS_PCI_IO_BASE),
 149                 .length         = SZ_64K,
 150                 .type           = MT_DEVICE
 151         }
 152 };
 153
 154 static void __init ap_map_io(void)
 155 {
 156         iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
 157 }
 158
 159 #define INTEGRATOR_SC_VALID_INT 0x003fffff
 160
 161 static struct fpga_irq_data sc_irq_data = {
 162         .base           = VA_IC_BASE,
 163         .irq_start      = 0,
 164         .chip.name      = "SC",
 165 };
 166
 167 static void __init ap_init_irq(void)
 168 {
 169         /* Disable all interrupts initially. */
 170         /* Do the core module ones */
 171         writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
 172
 173         /* do the header card stuff next */
 174         writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
 175         writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
 176
 177         fpga_irq_init(-1, INTEGRATOR_SC_VALID_INT, &sc_irq_data);
 178 }
 179
 180 #ifdef CONFIG_PM
 181 static unsigned long ic_irq_enable;
 182
 183 static int irq_suspend(struct sys_device *dev, pm_message_t state)
 184 {
 185         ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE);
 186         return 0;
 187 }
 188
 189 static int irq_resume(struct sys_device *dev)
 190 {
 191         /* disable all irq sources */
 192         writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
 193         writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
 194         writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
 195
 196         writel(ic_irq_enable, VA_IC_BASE + IRQ_ENABLE_SET);
 197         return 0;
 198 }
 199 #else
 200 #define irq_suspend NULL
 201 #define irq_resume NULL
 202 #endif
 203
 204 static struct sysdev_class irq_class = {
 205         .name           = "irq",
 206         .suspend        = irq_suspend,
 207         .resume         = irq_resume,
 208 };
 209
 210 static struct sys_device irq_device = {
 211         .id     = 0,
 212         .cls    = &irq_class,
 213 };
 214
 215 static int __init irq_init_sysfs(void)
 216 {
 217         int ret = sysdev_class_register(&irq_class);
 218         if (ret == 0)
 219                 ret = sysdev_register(&irq_device);
 220         return ret;
 221 }
 222
 223 device_initcall(irq_init_sysfs);
 224
 225 /*
 226  * Flash handling.
 227  */
 228 #define SC_CTRLC (VA_SC_BASE + INTEGRATOR_SC_CTRLC_OFFSET)
 229 #define SC_CTRLS (VA_SC_BASE + INTEGRATOR_SC_CTRLS_OFFSET)
 230 #define EBI_CSR1 (VA_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET)
 231 #define EBI_LOCK (VA_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET)
 232
 233 static int ap_flash_init(struct platform_device *dev)
 234 {
 235         u32 tmp;
 236
 237         writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC);
 238
 239         tmp = readl(EBI_CSR1) | INTEGRATOR_EBI_WRITE_ENABLE;
 240         writel(tmp, EBI_CSR1);
 241
 242         if (!(readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE)) {
 243                 writel(0xa05f, EBI_LOCK);
 244                 writel(tmp, EBI_CSR1);
 245                 writel(0, EBI_LOCK);
 246         }
 247         return 0;
 248 }
 249
 250 static void ap_flash_exit(struct platform_device *dev)
 251 {
 252         u32 tmp;
 253
 254         writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC);
 255
 256         tmp = readl(EBI_CSR1) & ~INTEGRATOR_EBI_WRITE_ENABLE;
 257         writel(tmp, EBI_CSR1);
 258
 259         if (readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE) {
 260                 writel(0xa05f, EBI_LOCK);
 261                 writel(tmp, EBI_CSR1);
 262                 writel(0, EBI_LOCK);
 263         }
 264 }
 265
 266 static void ap_flash_set_vpp(struct platform_device *pdev, int on)
 267 {
 268         void __iomem *reg = on ? SC_CTRLS : SC_CTRLC;
 269
 270         writel(INTEGRATOR_SC_CTRL_nFLVPPEN, reg);
 271 }
 272
 273 static struct physmap_flash_data ap_flash_data = {
 274         .width          = 4,
 275         .init           = ap_flash_init,
 276         .exit           = ap_flash_exit,
 277         .set_vpp        = ap_flash_set_vpp,
 278 };
 279
 280 static struct resource cfi_flash_resource = {
 281         .start          = INTEGRATOR_FLASH_BASE,
 282         .end            = INTEGRATOR_FLASH_BASE + INTEGRATOR_FLASH_SIZE - 1,
 283         .flags          = IORESOURCE_MEM,
 284 };
 285
 286 static struct platform_device cfi_flash_device = {
 287         .name           = "physmap-flash",
 288         .id             = 0,
 289         .dev            = {
 290                 .platform_data  = &ap_flash_data,
 291         },
 292         .num_resources  = 1,
 293         .resource       = &cfi_flash_resource,
 294 };
 295
 296 static void __init ap_init(void)
 297 {
 298         unsigned long sc_dec;
 299         int i;
 300
 301         platform_device_register(&cfi_flash_device);
 302
 303         sc_dec = readl(VA_SC_BASE + INTEGRATOR_SC_DEC_OFFSET);
 304         for (i = 0; i < 4; i++) {
 305                 struct lm_device *lmdev;
 306
 307                 if ((sc_dec & (16 << i)) == 0)
 308                         continue;
 309
 310                 lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
 311                 if (!lmdev)
 312                         continue;
 313
 314                 lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
 315                 lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
 316                 lmdev->resource.flags = IORESOURCE_MEM;
 317                 lmdev->irq = IRQ_AP_EXPINT0 + i;
 318                 lmdev->id = i;
 319
 320                 lm_device_register(lmdev);
 321         }
 322 }
 323
 324 /*
 325  * Where is the timer (VA)?
 326  */
 327 #define TIMER0_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER0_BASE)
 328 #define TIMER1_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER1_BASE)
 329 #define TIMER2_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER2_BASE)
 330
 331 /*
 332  * How long is the timer interval?
 333  */
 334 #define TIMER_INTERVAL  (TICKS_PER_uSEC * mSEC_10)
 335 #if TIMER_INTERVAL >= 0x100000
 336 #define TICKS2USECS(x)  (256 * (x) / TICKS_PER_uSEC)
 337 #elif TIMER_INTERVAL >= 0x10000
 338 #define TICKS2USECS(x)  (16 * (x) / TICKS_PER_uSEC)
 339 #else
 340 #define TICKS2USECS(x)  ((x) / TICKS_PER_uSEC)
 341 #endif
 342
 343 static unsigned long timer_reload;
 344
 345 static void __iomem * const clksrc_base = (void __iomem *)TIMER2_VA_BASE;
 346
 347 static cycle_t timersp_read(struct clocksource *cs)
 348 {
 349         return ~(readl(clksrc_base + TIMER_VALUE) & 0xffff);
 350 }
 351
 352 static struct clocksource clocksource_timersp = {
 353         .name           = "timer2",
 354         .rating         = 200,
 355         .read           = timersp_read,
 356         .mask           = CLOCKSOURCE_MASK(16),
 357         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 358 };
 359
 360 static void integrator_clocksource_init(u32 khz)
 361 {
 362         struct clocksource *cs = &clocksource_timersp;
 363         void __iomem *base = clksrc_base;
 364         u32 ctrl = TIMER_CTRL_ENABLE;
 365
 366         if (khz >= 1500) {
 367                 khz /= 16;
 368                 ctrl = TIMER_CTRL_DIV16;
 369         }
 370
 371         writel(ctrl, base + TIMER_CTRL);
 372         writel(0xffff, base + TIMER_LOAD);
 373
 374         clocksource_register_khz(cs, khz);
 375 }
 376
 377 static void __iomem * const clkevt_base = (void __iomem *)TIMER1_VA_BASE;
 378
 379 /*
 380  * IRQ handler for the timer
 381  */
 382 static irqreturn_t integrator_timer_interrupt(int irq, void *dev_id)
 383 {
 384         struct clock_event_device *evt = dev_id;
 385
 386         /* clear the interrupt */
 387         writel(1, clkevt_base + TIMER_INTCLR);
 388
 389         evt->event_handler(evt);
 390
 391         return IRQ_HANDLED;
 392 }
 393
 394 static void clkevt_set_mode(enum clock_event_mode mode, struct clock_event_device *evt)
 395 {
 396         u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE;
 397
 398         BUG_ON(mode == CLOCK_EVT_MODE_ONESHOT);
 399
 400         if (mode == CLOCK_EVT_MODE_PERIODIC) {
 401                 writel(ctrl, clkevt_base + TIMER_CTRL);
 402                 writel(timer_reload, clkevt_base + TIMER_LOAD);
 403                 ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE;
 404         }
 405
 406         writel(ctrl, clkevt_base + TIMER_CTRL);
 407 }
 408
 409 static int clkevt_set_next_event(unsigned long next, struct clock_event_device *evt)
 410 {
 411         unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);
 412
 413         writel(ctrl & ~TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
 414         writel(next, clkevt_base + TIMER_LOAD);
 415         writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
 416
 417         return 0;
 418 }
 419
 420 static struct clock_event_device integrator_clockevent = {
 421         .name           = "timer1",
 422         .shift          = 34,
 423         .features       = CLOCK_EVT_FEAT_PERIODIC,
 424         .set_mode       = clkevt_set_mode,
 425         .set_next_event = clkevt_set_next_event,
 426         .rating         = 300,
 427         .cpumask        = cpu_all_mask,
 428 };
 429
 430 static struct irqaction integrator_timer_irq = {
 431         .name           = "timer",
 432         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 433         .handler        = integrator_timer_interrupt,
 434         .dev_id         = &integrator_clockevent,
 435 };
 436
 437 static void integrator_clockevent_init(u32 khz)
 438 {
 439         struct clock_event_device *evt = &integrator_clockevent;
 440         unsigned int ctrl = 0;
 441
 442         if (khz * 1000 > 0x100000 * HZ) {
 443                 khz /= 256;
 444                 ctrl |= TIMER_CTRL_DIV256;
 445         } else if (khz * 1000 > 0x10000 * HZ) {
 446                 khz /= 16;
 447                 ctrl |= TIMER_CTRL_DIV16;
 448         }
 449
 450         timer_reload = khz * 1000 / HZ;
 451         writel(ctrl, clkevt_base + TIMER_CTRL);
 452
 453         evt->irq = IRQ_TIMERINT1;
 454         evt->mult = div_sc(khz, NSEC_PER_MSEC, evt->shift);
 455         evt->max_delta_ns = clockevent_delta2ns(0xffff, evt);
 456         evt->min_delta_ns = clockevent_delta2ns(0xf, evt);
 457
 458         setup_irq(IRQ_TIMERINT1, &integrator_timer_irq);
 459         clockevents_register_device(evt);
 460 }
 461
 462 /*
 463  * Set up timer(s).
 464  */
 465 static void __init ap_init_timer(void)
 466 {
 467         u32 khz = TICKS_PER_uSEC * 1000;
 468
 469         writel(0, TIMER0_VA_BASE + TIMER_CTRL);
 470         writel(0, TIMER1_VA_BASE + TIMER_CTRL);
 471         writel(0, TIMER2_VA_BASE + TIMER_CTRL);
 472
 473         integrator_clocksource_init(khz);
 474         integrator_clockevent_init(khz);
 475 }
 476
 477 static struct sys_timer ap_timer = {
 478         .init           = ap_init_timer,
 479 };
 480
 481 MACHINE_START(INTEGRATOR, "ARM-Integrator")
 482         /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
 483         .boot_params    = 0x00000100,
 484         .reserve        = integrator_reserve,
 485         .map_io         = ap_map_io,
 486         .init_early     = integrator_init_early,
 487         .init_irq       = ap_init_irq,
 488         .timer          = &ap_timer,
 489         .init_machine   = ap_init,
 490 MACHINE_END