| blob | 20bb83fca873bcd0093ec2ffe30677a7db460757 |
1 config ARM
2 bool
3 default y
4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAVE_CUSTOM_GPIO_H
7 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
8 select ARCH_WANT_IPC_PARSE_VERSION
9 select BUILDTIME_EXTABLE_SORT if MMU
10 select CPU_PM if (SUSPEND || CPU_IDLE)
11 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
12 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
13 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
14 select GENERIC_IRQ_PROBE
15 select GENERIC_IRQ_SHOW
16 select GENERIC_PCI_IOMAP
17 select GENERIC_SMP_IDLE_THREAD
18 select GENERIC_IDLE_POLL_SETUP
19 select GENERIC_STRNCPY_FROM_USER
20 select GENERIC_STRNLEN_USER
21 select HARDIRQS_SW_RESEND
22 select HAVE_AOUT
23 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
24 select HAVE_ARCH_KGDB
25 select HAVE_ARCH_SECCOMP_FILTER
26 select HAVE_ARCH_TRACEHOOK
27 select HAVE_BPF_JIT
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_DEBUG_KMEMLEAK
30 select HAVE_DMA_API_DEBUG
31 select HAVE_DMA_ATTRS
32 select HAVE_DMA_CONTIGUOUS if MMU
33 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
34 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
35 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
36 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
37 select HAVE_GENERIC_DMA_COHERENT
38 select HAVE_GENERIC_HARDIRQS
39 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
40 select HAVE_IDE if PCI || ISA || PCMCIA
41 select HAVE_IRQ_TIME_ACCOUNTING
42 select HAVE_KERNEL_GZIP
43 select HAVE_KERNEL_LZMA
44 select HAVE_KERNEL_LZO
45 select HAVE_KERNEL_XZ
46 select HAVE_KPROBES if !XIP_KERNEL
47 select HAVE_KRETPROBES if (HAVE_KPROBES)
48 select HAVE_MEMBLOCK
49 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
50 select HAVE_PERF_EVENTS
51 select HAVE_REGS_AND_STACK_ACCESS_API
52 select HAVE_SYSCALL_TRACEPOINTS
53 select HAVE_UID16
54 select KTIME_SCALAR
55 select PERF_USE_VMALLOC
56 select RTC_LIB
57 select SYS_SUPPORTS_APM_EMULATION
58 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
59 select MODULES_USE_ELF_REL
60 select CLONE_BACKWARDS
61 select OLD_SIGSUSPEND3
62 select OLD_SIGACTION
63 select HAVE_CONTEXT_TRACKING
64 help
65 The ARM series is a line of low-power-consumption RISC chip designs
66 licensed by ARM Ltd and targeted at embedded applications and
67 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
68 manufactured, but legacy ARM-based PC hardware remains popular in
69 Europe. There is an ARM Linux project with a web page at
70 <http://www.arm.linux.org.uk/>.
72 config ARM_HAS_SG_CHAIN
73 bool
75 config NEED_SG_DMA_LENGTH
76 bool
78 config ARM_DMA_USE_IOMMU
79 bool
80 select ARM_HAS_SG_CHAIN
81 select NEED_SG_DMA_LENGTH
83 if ARM_DMA_USE_IOMMU
85 config ARM_DMA_IOMMU_ALIGNMENT
86 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
87 range 4 9
88 default 8
89 help
90 DMA mapping framework by default aligns all buffers to the smallest
91 PAGE_SIZE order which is greater than or equal to the requested buffer
92 size. This works well for buffers up to a few hundreds kilobytes, but
93 for larger buffers it just a waste of address space. Drivers which has
94 relatively small addressing window (like 64Mib) might run out of
95 virtual space with just a few allocations.
97 With this parameter you can specify the maximum PAGE_SIZE order for
98 DMA IOMMU buffers. Larger buffers will be aligned only to this
99 specified order. The order is expressed as a power of two multiplied
100 by the PAGE_SIZE.
102 endif
104 config HAVE_PWM
105 bool
107 config MIGHT_HAVE_PCI
108 bool
110 config SYS_SUPPORTS_APM_EMULATION
111 bool
113 config HAVE_TCM
114 bool
115 select GENERIC_ALLOCATOR
117 config HAVE_PROC_CPU
118 bool
120 config NO_IOPORT
121 bool
123 config EISA
124 bool
125 ---help---
126 The Extended Industry Standard Architecture (EISA) bus was
127 developed as an open alternative to the IBM MicroChannel bus.
129 The EISA bus provided some of the features of the IBM MicroChannel
130 bus while maintaining backward compatibility with cards made for
131 the older ISA bus. The EISA bus saw limited use between 1988 and
132 1995 when it was made obsolete by the PCI bus.
134 Say Y here if you are building a kernel for an EISA-based machine.
136 Otherwise, say N.
138 config SBUS
139 bool
141 config STACKTRACE_SUPPORT
142 bool
143 default y
145 config HAVE_LATENCYTOP_SUPPORT
146 bool
147 depends on !SMP
148 default y
150 config LOCKDEP_SUPPORT
151 bool
152 default y
154 config TRACE_IRQFLAGS_SUPPORT
155 bool
156 default y
158 config RWSEM_GENERIC_SPINLOCK
159 bool
160 default y
162 config RWSEM_XCHGADD_ALGORITHM
163 bool
165 config ARCH_HAS_ILOG2_U32
166 bool
168 config ARCH_HAS_ILOG2_U64
169 bool
171 config ARCH_HAS_CPUFREQ
172 bool
173 help
174 Internal node to signify that the ARCH has CPUFREQ support
175 and that the relevant menu configurations are displayed for
176 it.
178 config GENERIC_HWEIGHT
179 bool
180 default y
182 config GENERIC_CALIBRATE_DELAY
183 bool
184 default y
186 config ARCH_MAY_HAVE_PC_FDC
187 bool
189 config ZONE_DMA
190 bool
192 config NEED_DMA_MAP_STATE
193 def_bool y
195 config ARCH_HAS_DMA_SET_COHERENT_MASK
196 bool
198 config GENERIC_ISA_DMA
199 bool
201 config FIQ
202 bool
204 config NEED_RET_TO_USER
205 bool
207 config ARCH_MTD_XIP
208 bool
210 config VECTORS_BASE
211 hex
212 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
213 default DRAM_BASE if REMAP_VECTORS_TO_RAM
214 default 0x00000000
215 help
216 The base address of exception vectors.
218 config ARM_PATCH_PHYS_VIRT
219 bool "Patch physical to virtual translations at runtime" if EMBEDDED
220 default y
221 depends on !XIP_KERNEL && MMU
222 depends on !ARCH_REALVIEW || !SPARSEMEM
223 help
224 Patch phys-to-virt and virt-to-phys translation functions at
225 boot and module load time according to the position of the
226 kernel in system memory.
228 This can only be used with non-XIP MMU kernels where the base
229 of physical memory is at a 16MB boundary.
231 Only disable this option if you know that you do not require
232 this feature (eg, building a kernel for a single machine) and
233 you need to shrink the kernel to the minimal size.
235 config NEED_MACH_GPIO_H
236 bool
237 help
238 Select this when mach/gpio.h is required to provide special
239 definitions for this platform. The need for mach/gpio.h should
240 be avoided when possible.
242 config NEED_MACH_IO_H
243 bool
244 help
245 Select this when mach/io.h is required to provide special
246 definitions for this platform. The need for mach/io.h should
247 be avoided when possible.
249 config NEED_MACH_MEMORY_H
250 bool
251 help
252 Select this when mach/memory.h is required to provide special
253 definitions for this platform. The need for mach/memory.h should
254 be avoided when possible.
256 config PHYS_OFFSET
257 hex "Physical address of main memory" if MMU
258 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
259 default DRAM_BASE if !MMU
260 help
261 Please provide the physical address corresponding to the
262 location of main memory in your system.
264 config GENERIC_BUG
265 def_bool y
266 depends on BUG
268 source "init/Kconfig"
270 source "kernel/Kconfig.freezer"
272 menu "System Type"
274 config MMU
275 bool "MMU-based Paged Memory Management Support"
276 default y
277 help
278 Select if you want MMU-based virtualised addressing space
279 support by paged memory management. If unsure, say 'Y'.
281 #
282 # The "ARM system type" choice list is ordered alphabetically by option
283 # text. Please add new entries in the option alphabetic order.
284 #
285 choice
286 prompt "ARM system type"
287 default ARCH_VERSATILE if !MMU
288 default ARCH_MULTIPLATFORM if MMU
290 config ARCH_MULTIPLATFORM
291 bool "Allow multiple platforms to be selected"
292 depends on MMU
293 select ARM_PATCH_PHYS_VIRT
294 select AUTO_ZRELADDR
295 select COMMON_CLK
296 select MULTI_IRQ_HANDLER
297 select SPARSE_IRQ
298 select USE_OF
300 config ARCH_INTEGRATOR
301 bool "ARM Ltd. Integrator family"
302 select ARCH_HAS_CPUFREQ
303 select ARM_AMBA
304 select COMMON_CLK
305 select COMMON_CLK_VERSATILE
306 select GENERIC_CLOCKEVENTS
307 select HAVE_TCM
308 select ICST
309 select MULTI_IRQ_HANDLER
310 select NEED_MACH_MEMORY_H
311 select PLAT_VERSATILE
312 select SPARSE_IRQ
313 select VERSATILE_FPGA_IRQ
314 help
315 Support for ARM's Integrator platform.
317 config ARCH_REALVIEW
318 bool "ARM Ltd. RealView family"
319 select ARCH_WANT_OPTIONAL_GPIOLIB
320 select ARM_AMBA
321 select ARM_TIMER_SP804
322 select COMMON_CLK
323 select COMMON_CLK_VERSATILE
324 select GENERIC_CLOCKEVENTS
325 select GPIO_PL061 if GPIOLIB
326 select ICST
327 select NEED_MACH_MEMORY_H
328 select PLAT_VERSATILE
329 select PLAT_VERSATILE_CLCD
330 help
331 This enables support for ARM Ltd RealView boards.
333 config ARCH_VERSATILE
334 bool "ARM Ltd. Versatile family"
335 select ARCH_WANT_OPTIONAL_GPIOLIB
336 select ARM_AMBA
337 select ARM_TIMER_SP804
338 select ARM_VIC
339 select CLKDEV_LOOKUP
340 select GENERIC_CLOCKEVENTS
341 select HAVE_MACH_CLKDEV
342 select ICST
343 select PLAT_VERSATILE
344 select PLAT_VERSATILE_CLCD
345 select PLAT_VERSATILE_CLOCK
346 select VERSATILE_FPGA_IRQ
347 help
348 This enables support for ARM Ltd Versatile board.
350 config ARCH_AT91
351 bool "Atmel AT91"
352 select ARCH_REQUIRE_GPIOLIB
353 select CLKDEV_LOOKUP
354 select HAVE_CLK
355 select IRQ_DOMAIN
356 select NEED_MACH_GPIO_H
357 select NEED_MACH_IO_H if PCCARD
358 select PINCTRL
359 select PINCTRL_AT91 if USE_OF
360 help
361 This enables support for systems based on Atmel
362 AT91RM9200 and AT91SAM9* processors.
364 config ARCH_CLPS711X
365 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
366 select ARCH_REQUIRE_GPIOLIB
367 select AUTO_ZRELADDR
368 select CLKDEV_LOOKUP
369 select COMMON_CLK
370 select CPU_ARM720T
371 select GENERIC_CLOCKEVENTS
372 select MULTI_IRQ_HANDLER
373 select NEED_MACH_MEMORY_H
374 select SPARSE_IRQ
375 help
376 Support for Cirrus Logic 711x/721x/731x based boards.
378 config ARCH_GEMINI
379 bool "Cortina Systems Gemini"
380 select ARCH_REQUIRE_GPIOLIB
381 select ARCH_USES_GETTIMEOFFSET
382 select NEED_MACH_GPIO_H
383 select CPU_FA526
384 help
385 Support for the Cortina Systems Gemini family SoCs
387 config ARCH_EBSA110
388 bool "EBSA-110"
389 select ARCH_USES_GETTIMEOFFSET
390 select CPU_SA110
391 select ISA
392 select NEED_MACH_IO_H
393 select NEED_MACH_MEMORY_H
394 select NO_IOPORT
395 help
396 This is an evaluation board for the StrongARM processor available
397 from Digital. It has limited hardware on-board, including an
398 Ethernet interface, two PCMCIA sockets, two serial ports and a
399 parallel port.
401 config ARCH_EP93XX
402 bool "EP93xx-based"
403 select ARCH_HAS_HOLES_MEMORYMODEL
404 select ARCH_REQUIRE_GPIOLIB
405 select ARCH_USES_GETTIMEOFFSET
406 select ARM_AMBA
407 select ARM_VIC
408 select CLKDEV_LOOKUP
409 select CPU_ARM920T
410 select NEED_MACH_MEMORY_H
411 help
412 This enables support for the Cirrus EP93xx series of CPUs.
414 config ARCH_FOOTBRIDGE
415 bool "FootBridge"
416 select CPU_SA110
417 select FOOTBRIDGE
418 select GENERIC_CLOCKEVENTS
419 select HAVE_IDE
420 select NEED_MACH_IO_H if !MMU
421 select NEED_MACH_MEMORY_H
422 help
423 Support for systems based on the DC21285 companion chip
424 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
426 config ARCH_NETX
427 bool "Hilscher NetX based"
428 select ARM_VIC
429 select CLKSRC_MMIO
430 select CPU_ARM926T
431 select GENERIC_CLOCKEVENTS
432 help
433 This enables support for systems based on the Hilscher NetX Soc
435 config ARCH_IOP13XX
436 bool "IOP13xx-based"
437 depends on MMU
438 select ARCH_SUPPORTS_MSI
439 select CPU_XSC3
440 select NEED_MACH_MEMORY_H
441 select NEED_RET_TO_USER
442 select PCI
443 select PLAT_IOP
444 select VMSPLIT_1G
445 help
446 Support for Intel's IOP13XX (XScale) family of processors.
448 config ARCH_IOP32X
449 bool "IOP32x-based"
450 depends on MMU
451 select ARCH_REQUIRE_GPIOLIB
452 select CPU_XSCALE
453 select NEED_MACH_GPIO_H
454 select NEED_RET_TO_USER
455 select PCI
456 select PLAT_IOP
457 help
458 Support for Intel's 80219 and IOP32X (XScale) family of
459 processors.
461 config ARCH_IOP33X
462 bool "IOP33x-based"
463 depends on MMU
464 select ARCH_REQUIRE_GPIOLIB
465 select CPU_XSCALE
466 select NEED_MACH_GPIO_H
467 select NEED_RET_TO_USER
468 select PCI
469 select PLAT_IOP
470 help
471 Support for Intel's IOP33X (XScale) family of processors.
473 config ARCH_IXP4XX
474 bool "IXP4xx-based"
475 depends on MMU
476 select ARCH_HAS_DMA_SET_COHERENT_MASK
477 select ARCH_REQUIRE_GPIOLIB
478 select CLKSRC_MMIO
479 select CPU_XSCALE
480 select DMABOUNCE if PCI
481 select GENERIC_CLOCKEVENTS
482 select MIGHT_HAVE_PCI
483 select NEED_MACH_IO_H
484 select USB_EHCI_BIG_ENDIAN_MMIO
485 select USB_EHCI_BIG_ENDIAN_DESC
486 help
487 Support for Intel's IXP4XX (XScale) family of processors.
489 config ARCH_DOVE
490 bool "Marvell Dove"
491 select ARCH_REQUIRE_GPIOLIB
492 select CPU_PJ4
493 select GENERIC_CLOCKEVENTS
494 select MIGHT_HAVE_PCI
495 select PINCTRL
496 select PINCTRL_DOVE
497 select PLAT_ORION_LEGACY
498 select USB_ARCH_HAS_EHCI
499 select MVEBU_MBUS
500 help
501 Support for the Marvell Dove SoC 88AP510
503 config ARCH_KIRKWOOD
504 bool "Marvell Kirkwood"
505 select ARCH_HAS_CPUFREQ
506 select ARCH_REQUIRE_GPIOLIB
507 select CPU_FEROCEON
508 select GENERIC_CLOCKEVENTS
509 select PCI
510 select PCI_QUIRKS
511 select PINCTRL
512 select PINCTRL_KIRKWOOD
513 select PLAT_ORION_LEGACY
514 select MVEBU_MBUS
515 help
516 Support for the following Marvell Kirkwood series SoCs:
517 88F6180, 88F6192 and 88F6281.
519 config ARCH_MV78XX0
520 bool "Marvell MV78xx0"
521 select ARCH_REQUIRE_GPIOLIB
522 select CPU_FEROCEON
523 select GENERIC_CLOCKEVENTS
524 select PCI
525 select PLAT_ORION_LEGACY
526 select MVEBU_MBUS
527 help
528 Support for the following Marvell MV78xx0 series SoCs:
529 MV781x0, MV782x0.
531 config ARCH_ORION5X
532 bool "Marvell Orion"
533 depends on MMU
534 select ARCH_REQUIRE_GPIOLIB
535 select CPU_FEROCEON
536 select GENERIC_CLOCKEVENTS
537 select PCI
538 select PLAT_ORION_LEGACY
539 select MVEBU_MBUS
540 help
541 Support for the following Marvell Orion 5x series SoCs:
542 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
543 Orion-2 (5281), Orion-1-90 (6183).
545 config ARCH_MMP
546 bool "Marvell PXA168/910/MMP2"
547 depends on MMU
548 select ARCH_REQUIRE_GPIOLIB
549 select CLKDEV_LOOKUP
550 select GENERIC_ALLOCATOR
551 select GENERIC_CLOCKEVENTS
552 select GPIO_PXA
553 select IRQ_DOMAIN
554 select NEED_MACH_GPIO_H
555 select PINCTRL
556 select PLAT_PXA
557 select SPARSE_IRQ
558 help
559 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
561 config ARCH_KS8695
562 bool "Micrel/Kendin KS8695"
563 select ARCH_REQUIRE_GPIOLIB
564 select CLKSRC_MMIO
565 select CPU_ARM922T
566 select GENERIC_CLOCKEVENTS
567 select NEED_MACH_MEMORY_H
568 help
569 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
570 System-on-Chip devices.
572 config ARCH_W90X900
573 bool "Nuvoton W90X900 CPU"
574 select ARCH_REQUIRE_GPIOLIB
575 select CLKDEV_LOOKUP
576 select CLKSRC_MMIO
577 select CPU_ARM926T
578 select GENERIC_CLOCKEVENTS
579 help
580 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
581 At present, the w90x900 has been renamed nuc900, regarding
582 the ARM series product line, you can login the following
583 link address to know more.
585 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
586 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
588 config ARCH_LPC32XX
589 bool "NXP LPC32XX"
590 select ARCH_REQUIRE_GPIOLIB
591 select ARM_AMBA
592 select CLKDEV_LOOKUP
593 select CLKSRC_MMIO
594 select CPU_ARM926T
595 select GENERIC_CLOCKEVENTS
596 select HAVE_IDE
597 select HAVE_PWM
598 select USB_ARCH_HAS_OHCI
599 select USE_OF
600 help
601 Support for the NXP LPC32XX family of processors
603 config ARCH_PXA
604 bool "PXA2xx/PXA3xx-based"
605 depends on MMU
606 select ARCH_HAS_CPUFREQ
607 select ARCH_MTD_XIP
608 select ARCH_REQUIRE_GPIOLIB
609 select ARM_CPU_SUSPEND if PM
610 select AUTO_ZRELADDR
611 select CLKDEV_LOOKUP
612 select CLKSRC_MMIO
613 select GENERIC_CLOCKEVENTS
614 select GPIO_PXA
615 select HAVE_IDE
616 select MULTI_IRQ_HANDLER
617 select NEED_MACH_GPIO_H
618 select PLAT_PXA
619 select SPARSE_IRQ
620 help
621 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
623 config ARCH_MSM
624 bool "Qualcomm MSM"
625 select ARCH_REQUIRE_GPIOLIB
626 select CLKDEV_LOOKUP
627 select GENERIC_CLOCKEVENTS
628 select HAVE_CLK
629 help
630 Support for Qualcomm MSM/QSD based systems. This runs on the
631 apps processor of the MSM/QSD and depends on a shared memory
632 interface to the modem processor which runs the baseband
633 stack and controls some vital subsystems
634 (clock and power control, etc).
636 config ARCH_SHMOBILE
637 bool "Renesas SH-Mobile / R-Mobile"
638 select CLKDEV_LOOKUP
639 select GENERIC_CLOCKEVENTS
640 select HAVE_ARM_SCU if SMP
641 select HAVE_ARM_TWD if LOCAL_TIMERS
642 select HAVE_CLK
643 select HAVE_MACH_CLKDEV
644 select HAVE_SMP
645 select MIGHT_HAVE_CACHE_L2X0
646 select MULTI_IRQ_HANDLER
647 select NEED_MACH_MEMORY_H
648 select NO_IOPORT
649 select PINCTRL if ARCH_WANT_OPTIONAL_GPIOLIB
650 select PM_GENERIC_DOMAINS if PM
651 select SPARSE_IRQ
652 help
653 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
655 config ARCH_RPC
656 bool "RiscPC"
657 select ARCH_ACORN
658 select ARCH_MAY_HAVE_PC_FDC
659 select ARCH_SPARSEMEM_ENABLE
660 select ARCH_USES_GETTIMEOFFSET
661 select FIQ
662 select HAVE_IDE
663 select HAVE_PATA_PLATFORM
664 select ISA_DMA_API
665 select NEED_MACH_IO_H
666 select NEED_MACH_MEMORY_H
667 select NO_IOPORT
668 select VIRT_TO_BUS
669 help
670 On the Acorn Risc-PC, Linux can support the internal IDE disk and
671 CD-ROM interface, serial and parallel port, and the floppy drive.
673 config ARCH_SA1100
674 bool "SA1100-based"
675 select ARCH_HAS_CPUFREQ
676 select ARCH_MTD_XIP
677 select ARCH_REQUIRE_GPIOLIB
678 select ARCH_SPARSEMEM_ENABLE
679 select CLKDEV_LOOKUP
680 select CLKSRC_MMIO
681 select CPU_FREQ
682 select CPU_SA1100
683 select GENERIC_CLOCKEVENTS
684 select HAVE_IDE
685 select ISA
686 select NEED_MACH_GPIO_H
687 select NEED_MACH_MEMORY_H
688 select SPARSE_IRQ
689 help
690 Support for StrongARM 11x0 based boards.
692 config ARCH_S3C24XX
693 bool "Samsung S3C24XX SoCs"
694 select ARCH_HAS_CPUFREQ
695 select ARCH_REQUIRE_GPIOLIB
696 select CLKDEV_LOOKUP
697 select CLKSRC_MMIO
698 select GENERIC_CLOCKEVENTS
699 select HAVE_CLK
700 select HAVE_S3C2410_I2C if I2C
701 select HAVE_S3C2410_WATCHDOG if WATCHDOG
702 select HAVE_S3C_RTC if RTC_CLASS
703 select MULTI_IRQ_HANDLER
704 select NEED_MACH_GPIO_H
705 select NEED_MACH_IO_H
706 help
707 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
708 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
709 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
710 Samsung SMDK2410 development board (and derivatives).
712 config ARCH_S3C64XX
713 bool "Samsung S3C64XX"
714 select ARCH_HAS_CPUFREQ
715 select ARCH_REQUIRE_GPIOLIB
716 select ARM_VIC
717 select CLKDEV_LOOKUP
718 select CLKSRC_MMIO
719 select CPU_V6
720 select GENERIC_CLOCKEVENTS
721 select HAVE_CLK
722 select HAVE_S3C2410_I2C if I2C
723 select HAVE_S3C2410_WATCHDOG if WATCHDOG
724 select HAVE_TCM
725 select NEED_MACH_GPIO_H
726 select NO_IOPORT
727 select PLAT_SAMSUNG
728 select S3C_DEV_NAND
729 select S3C_GPIO_TRACK
730 select SAMSUNG_CLKSRC
731 select SAMSUNG_GPIOLIB_4BIT
732 select SAMSUNG_IRQ_VIC_TIMER
733 select USB_ARCH_HAS_OHCI
734 help
735 Samsung S3C64XX series based systems
737 config ARCH_S5P64X0
738 bool "Samsung S5P6440 S5P6450"
739 select CLKDEV_LOOKUP
740 select CLKSRC_MMIO
741 select CPU_V6
742 select GENERIC_CLOCKEVENTS
743 select HAVE_CLK
744 select HAVE_S3C2410_I2C if I2C
745 select HAVE_S3C2410_WATCHDOG if WATCHDOG
746 select HAVE_S3C_RTC if RTC_CLASS
747 select NEED_MACH_GPIO_H
748 help
749 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
750 SMDK6450.
752 config ARCH_S5PC100
753 bool "Samsung S5PC100"
754 select ARCH_REQUIRE_GPIOLIB
755 select CLKDEV_LOOKUP
756 select CLKSRC_MMIO
757 select CPU_V7
758 select GENERIC_CLOCKEVENTS
759 select HAVE_CLK
760 select HAVE_S3C2410_I2C if I2C
761 select HAVE_S3C2410_WATCHDOG if WATCHDOG
762 select HAVE_S3C_RTC if RTC_CLASS
763 select NEED_MACH_GPIO_H
764 help
765 Samsung S5PC100 series based systems
767 config ARCH_S5PV210
768 bool "Samsung S5PV210/S5PC110"
769 select ARCH_HAS_CPUFREQ
770 select ARCH_HAS_HOLES_MEMORYMODEL
771 select ARCH_SPARSEMEM_ENABLE
772 select CLKDEV_LOOKUP
773 select CLKSRC_MMIO
774 select CPU_V7
775 select GENERIC_CLOCKEVENTS
776 select HAVE_CLK
777 select HAVE_S3C2410_I2C if I2C
778 select HAVE_S3C2410_WATCHDOG if WATCHDOG
779 select HAVE_S3C_RTC if RTC_CLASS
780 select NEED_MACH_GPIO_H
781 select NEED_MACH_MEMORY_H
782 help
783 Samsung S5PV210/S5PC110 series based systems
785 config ARCH_EXYNOS
786 bool "Samsung EXYNOS"
787 select ARCH_HAS_CPUFREQ
788 select ARCH_HAS_HOLES_MEMORYMODEL
789 select ARCH_SPARSEMEM_ENABLE
790 select CLKDEV_LOOKUP
791 select COMMON_CLK
792 select CPU_V7
793 select GENERIC_CLOCKEVENTS
794 select HAVE_CLK
795 select HAVE_S3C2410_I2C if I2C
796 select HAVE_S3C2410_WATCHDOG if WATCHDOG
797 select HAVE_S3C_RTC if RTC_CLASS
798 select NEED_MACH_GPIO_H
799 select NEED_MACH_MEMORY_H
800 help
801 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
803 config ARCH_SHARK
804 bool "Shark"
805 select ARCH_USES_GETTIMEOFFSET
806 select CPU_SA110
807 select ISA
808 select ISA_DMA
809 select NEED_MACH_MEMORY_H
810 select PCI
811 select VIRT_TO_BUS
812 select ZONE_DMA
813 help
814 Support for the StrongARM based Digital DNARD machine, also known
815 as "Shark" (<http://www.shark-linux.de/shark.html>).
817 config ARCH_U300
818 bool "ST-Ericsson U300 Series"
819 depends on MMU
820 select ARCH_REQUIRE_GPIOLIB
821 select ARM_AMBA
822 select ARM_PATCH_PHYS_VIRT
823 select ARM_VIC
824 select CLKDEV_LOOKUP
825 select CLKSRC_MMIO
826 select COMMON_CLK
827 select CPU_ARM926T
828 select GENERIC_CLOCKEVENTS
829 select HAVE_TCM
830 select SPARSE_IRQ
831 help
832 Support for ST-Ericsson U300 series mobile platforms.
834 config ARCH_DAVINCI
835 bool "TI DaVinci"
836 select ARCH_HAS_HOLES_MEMORYMODEL
837 select ARCH_REQUIRE_GPIOLIB
838 select CLKDEV_LOOKUP
839 select GENERIC_ALLOCATOR
840 select GENERIC_CLOCKEVENTS
841 select GENERIC_IRQ_CHIP
842 select HAVE_IDE
843 select NEED_MACH_GPIO_H
844 select USE_OF
845 select ZONE_DMA
846 help
847 Support for TI's DaVinci platform.
849 config ARCH_OMAP1
850 bool "TI OMAP1"
851 depends on MMU
852 select ARCH_HAS_CPUFREQ
853 select ARCH_HAS_HOLES_MEMORYMODEL
854 select ARCH_OMAP
855 select ARCH_REQUIRE_GPIOLIB
856 select CLKDEV_LOOKUP
857 select CLKSRC_MMIO
858 select GENERIC_CLOCKEVENTS
859 select GENERIC_IRQ_CHIP
860 select HAVE_CLK
861 select HAVE_IDE
862 select IRQ_DOMAIN
863 select NEED_MACH_IO_H if PCCARD
864 select NEED_MACH_MEMORY_H
865 help
866 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
868 endchoice
870 menu "Multiple platform selection"
871 depends on ARCH_MULTIPLATFORM
873 comment "CPU Core family selection"
875 config ARCH_MULTI_V4
876 bool "ARMv4 based platforms (FA526, StrongARM)"
877 depends on !ARCH_MULTI_V6_V7
878 select ARCH_MULTI_V4_V5
880 config ARCH_MULTI_V4T
881 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
882 depends on !ARCH_MULTI_V6_V7
883 select ARCH_MULTI_V4_V5
885 config ARCH_MULTI_V5
886 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
887 depends on !ARCH_MULTI_V6_V7
888 select ARCH_MULTI_V4_V5
890 config ARCH_MULTI_V4_V5
891 bool
893 config ARCH_MULTI_V6
894 bool "ARMv6 based platforms (ARM11)"
895 select ARCH_MULTI_V6_V7
896 select CPU_V6
898 config ARCH_MULTI_V7
899 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
900 default y
901 select ARCH_MULTI_V6_V7
902 select CPU_V7
904 config ARCH_MULTI_V6_V7
905 bool
907 config ARCH_MULTI_CPU_AUTO
908 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
909 select ARCH_MULTI_V5
911 endmenu
913 #
914 # This is sorted alphabetically by mach-* pathname. However, plat-*
915 # Kconfigs may be included either alphabetically (according to the
916 # plat- suffix) or along side the corresponding mach-* source.
917 #
918 source "arch/arm/mach-mvebu/Kconfig"
920 source "arch/arm/mach-at91/Kconfig"
922 source "arch/arm/mach-bcm/Kconfig"
924 source "arch/arm/mach-bcm2835/Kconfig"
926 source "arch/arm/mach-clps711x/Kconfig"
928 source "arch/arm/mach-cns3xxx/Kconfig"
930 source "arch/arm/mach-davinci/Kconfig"
932 source "arch/arm/mach-dove/Kconfig"
934 source "arch/arm/mach-ep93xx/Kconfig"
936 source "arch/arm/mach-footbridge/Kconfig"
938 source "arch/arm/mach-gemini/Kconfig"
940 source "arch/arm/mach-highbank/Kconfig"
942 source "arch/arm/mach-integrator/Kconfig"
944 source "arch/arm/mach-iop32x/Kconfig"
946 source "arch/arm/mach-iop33x/Kconfig"
948 source "arch/arm/mach-iop13xx/Kconfig"
950 source "arch/arm/mach-ixp4xx/Kconfig"
952 source "arch/arm/mach-kirkwood/Kconfig"
954 source "arch/arm/mach-ks8695/Kconfig"
956 source "arch/arm/mach-msm/Kconfig"
958 source "arch/arm/mach-mv78xx0/Kconfig"
960 source "arch/arm/mach-imx/Kconfig"
962 source "arch/arm/mach-mxs/Kconfig"
964 source "arch/arm/mach-netx/Kconfig"
966 source "arch/arm/mach-nomadik/Kconfig"
968 source "arch/arm/plat-omap/Kconfig"
970 source "arch/arm/mach-omap1/Kconfig"
972 source "arch/arm/mach-omap2/Kconfig"
974 source "arch/arm/mach-orion5x/Kconfig"
976 source "arch/arm/mach-picoxcell/Kconfig"
978 source "arch/arm/mach-pxa/Kconfig"
979 source "arch/arm/plat-pxa/Kconfig"
981 source "arch/arm/mach-mmp/Kconfig"
983 source "arch/arm/mach-realview/Kconfig"
985 source "arch/arm/mach-sa1100/Kconfig"
987 source "arch/arm/plat-samsung/Kconfig"
989 source "arch/arm/mach-socfpga/Kconfig"
991 source "arch/arm/mach-spear/Kconfig"
993 source "arch/arm/mach-s3c24xx/Kconfig"
995 if ARCH_S3C64XX
996 source "arch/arm/mach-s3c64xx/Kconfig"
997 endif
999 source "arch/arm/mach-s5p64x0/Kconfig"
1001 source "arch/arm/mach-s5pc100/Kconfig"
1003 source "arch/arm/mach-s5pv210/Kconfig"
1005 source "arch/arm/mach-exynos/Kconfig"
1007 source "arch/arm/mach-shmobile/Kconfig"
1009 source "arch/arm/mach-sunxi/Kconfig"
1011 source "arch/arm/mach-prima2/Kconfig"
1013 source "arch/arm/mach-tegra/Kconfig"
1015 source "arch/arm/mach-u300/Kconfig"
1017 source "arch/arm/mach-ux500/Kconfig"
1019 source "arch/arm/mach-versatile/Kconfig"
1021 source "arch/arm/mach-vexpress/Kconfig"
1022 source "arch/arm/plat-versatile/Kconfig"
1024 source "arch/arm/mach-virt/Kconfig"
1026 source "arch/arm/mach-vt8500/Kconfig"
1028 source "arch/arm/mach-w90x900/Kconfig"
1030 source "arch/arm/mach-zynq/Kconfig"
1032 # Definitions to make life easier
1033 config ARCH_ACORN
1034 bool
1036 config PLAT_IOP
1037 bool
1038 select GENERIC_CLOCKEVENTS
1040 config PLAT_ORION
1041 bool
1042 select CLKSRC_MMIO
1043 select COMMON_CLK
1044 select GENERIC_IRQ_CHIP
1045 select IRQ_DOMAIN
1047 config PLAT_ORION_LEGACY
1048 bool
1049 select PLAT_ORION
1051 config PLAT_PXA
1052 bool
1054 config PLAT_VERSATILE
1055 bool
1057 config ARM_TIMER_SP804
1058 bool
1059 select CLKSRC_MMIO
1060 select CLKSRC_OF if OF
1062 source arch/arm/mm/Kconfig
1064 config ARM_NR_BANKS
1065 int
1066 default 16 if ARCH_EP93XX
1067 default 8
1069 config IWMMXT
1070 bool "Enable iWMMXt support" if !CPU_PJ4
1071 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1072 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
1073 help
1074 Enable support for iWMMXt context switching at run time if
1075 running on a CPU that supports it.
1077 config XSCALE_PMU
1078 bool
1079 depends on CPU_XSCALE
1080 default y
1082 config MULTI_IRQ_HANDLER
1083 bool
1084 help
1085 Allow each machine to specify it's own IRQ handler at run time.
1087 if !MMU
1088 source "arch/arm/Kconfig-nommu"
1089 endif
1091 config ARM_ERRATA_326103
1092 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1093 depends on CPU_V6
1094 help
1095 Executing a SWP instruction to read-only memory does not set bit 11
1096 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1097 treat the access as a read, preventing a COW from occurring and
1098 causing the faulting task to livelock.
1100 config ARM_ERRATA_411920
1101 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1102 depends on CPU_V6 || CPU_V6K
1103 help
1104 Invalidation of the Instruction Cache operation can
1105 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1106 It does not affect the MPCore. This option enables the ARM Ltd.
1107 recommended workaround.
1109 config ARM_ERRATA_430973
1110 bool "ARM errata: Stale prediction on replaced interworking branch"
1111 depends on CPU_V7
1112 help
1113 This option enables the workaround for the 430973 Cortex-A8
1114 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1115 interworking branch is replaced with another code sequence at the
1116 same virtual address, whether due to self-modifying code or virtual
1117 to physical address re-mapping, Cortex-A8 does not recover from the
1118 stale interworking branch prediction. This results in Cortex-A8
1119 executing the new code sequence in the incorrect ARM or Thumb state.
1120 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1121 and also flushes the branch target cache at every context switch.
1122 Note that setting specific bits in the ACTLR register may not be
1123 available in non-secure mode.
1125 config ARM_ERRATA_458693
1126 bool "ARM errata: Processor deadlock when a false hazard is created"
1127 depends on CPU_V7
1128 depends on !ARCH_MULTIPLATFORM
1129 help
1130 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1131 erratum. For very specific sequences of memory operations, it is
1132 possible for a hazard condition intended for a cache line to instead
1133 be incorrectly associated with a different cache line. This false
1134 hazard might then cause a processor deadlock. The workaround enables
1135 the L1 caching of the NEON accesses and disables the PLD instruction
1136 in the ACTLR register. Note that setting specific bits in the ACTLR
1137 register may not be available in non-secure mode.
1139 config ARM_ERRATA_460075
1140 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1141 depends on CPU_V7
1142 depends on !ARCH_MULTIPLATFORM
1143 help
1144 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1145 erratum. Any asynchronous access to the L2 cache may encounter a
1146 situation in which recent store transactions to the L2 cache are lost
1147 and overwritten with stale memory contents from external memory. The
1148 workaround disables the write-allocate mode for the L2 cache via the
1149 ACTLR register. Note that setting specific bits in the ACTLR register
1150 may not be available in non-secure mode.
1152 config ARM_ERRATA_742230
1153 bool "ARM errata: DMB operation may be faulty"
1154 depends on CPU_V7 && SMP
1155 depends on !ARCH_MULTIPLATFORM
1156 help
1157 This option enables the workaround for the 742230 Cortex-A9
1158 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1159 between two write operations may not ensure the correct visibility
1160 ordering of the two writes. This workaround sets a specific bit in
1161 the diagnostic register of the Cortex-A9 which causes the DMB
1162 instruction to behave as a DSB, ensuring the correct behaviour of
1163 the two writes.
1165 config ARM_ERRATA_742231
1166 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1167 depends on CPU_V7 && SMP
1168 depends on !ARCH_MULTIPLATFORM
1169 help
1170 This option enables the workaround for the 742231 Cortex-A9
1171 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1172 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1173 accessing some data located in the same cache line, may get corrupted
1174 data due to bad handling of the address hazard when the line gets
1175 replaced from one of the CPUs at the same time as another CPU is
1176 accessing it. This workaround sets specific bits in the diagnostic
1177 register of the Cortex-A9 which reduces the linefill issuing
1178 capabilities of the processor.
1180 config PL310_ERRATA_588369
1181 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1182 depends on CACHE_L2X0
1183 help
1184 The PL310 L2 cache controller implements three types of Clean &
1185 Invalidate maintenance operations: by Physical Address
1186 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1187 They are architecturally defined to behave as the execution of a
1188 clean operation followed immediately by an invalidate operation,
1189 both performing to the same memory location. This functionality
1190 is not correctly implemented in PL310 as clean lines are not
1191 invalidated as a result of these operations.
1193 config ARM_ERRATA_720789
1194 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1195 depends on CPU_V7
1196 help
1197 This option enables the workaround for the 720789 Cortex-A9 (prior to
1198 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1199 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1200 As a consequence of this erratum, some TLB entries which should be
1201 invalidated are not, resulting in an incoherency in the system page
1202 tables. The workaround changes the TLB flushing routines to invalidate
1203 entries regardless of the ASID.
1205 config PL310_ERRATA_727915
1206 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1207 depends on CACHE_L2X0
1208 help
1209 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1210 operation (offset 0x7FC). This operation runs in background so that
1211 PL310 can handle normal accesses while it is in progress. Under very
1212 rare circumstances, due to this erratum, write data can be lost when
1213 PL310 treats a cacheable write transaction during a Clean &
1214 Invalidate by Way operation.
1216 config ARM_ERRATA_743622
1217 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1218 depends on CPU_V7
1219 depends on !ARCH_MULTIPLATFORM
1220 help
1221 This option enables the workaround for the 743622 Cortex-A9
1222 (r2p*) erratum. Under very rare conditions, a faulty
1223 optimisation in the Cortex-A9 Store Buffer may lead to data
1224 corruption. This workaround sets a specific bit in the diagnostic
1225 register of the Cortex-A9 which disables the Store Buffer
1226 optimisation, preventing the defect from occurring. This has no
1227 visible impact on the overall performance or power consumption of the
1228 processor.
1230 config ARM_ERRATA_751472
1231 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1232 depends on CPU_V7
1233 depends on !ARCH_MULTIPLATFORM
1234 help
1235 This option enables the workaround for the 751472 Cortex-A9 (prior
1236 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1237 completion of a following broadcasted operation if the second
1238 operation is received by a CPU before the ICIALLUIS has completed,
1239 potentially leading to corrupted entries in the cache or TLB.
1241 config PL310_ERRATA_753970
1242 bool "PL310 errata: cache sync operation may be faulty"
1243 depends on CACHE_PL310
1244 help
1245 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1247 Under some condition the effect of cache sync operation on
1248 the store buffer still remains when the operation completes.
1249 This means that the store buffer is always asked to drain and
1250 this prevents it from merging any further writes. The workaround
1251 is to replace the normal offset of cache sync operation (0x730)
1252 by another offset targeting an unmapped PL310 register 0x740.
1253 This has the same effect as the cache sync operation: store buffer
1254 drain and waiting for all buffers empty.
1256 config ARM_ERRATA_754322
1257 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1258 depends on CPU_V7
1259 help
1260 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1261 r3p*) erratum. A speculative memory access may cause a page table walk
1262 which starts prior to an ASID switch but completes afterwards. This
1263 can populate the micro-TLB with a stale entry which may be hit with
1264 the new ASID. This workaround places two dsb instructions in the mm
1265 switching code so that no page table walks can cross the ASID switch.
1267 config ARM_ERRATA_754327
1268 bool "ARM errata: no automatic Store Buffer drain"
1269 depends on CPU_V7 && SMP
1270 help
1271 This option enables the workaround for the 754327 Cortex-A9 (prior to
1272 r2p0) erratum. The Store Buffer does not have any automatic draining
1273 mechanism and therefore a livelock may occur if an external agent
1274 continuously polls a memory location waiting to observe an update.
1275 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1276 written polling loops from denying visibility of updates to memory.
1278 config ARM_ERRATA_364296
1279 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1280 depends on CPU_V6 && !SMP
1281 help
1282 This options enables the workaround for the 364296 ARM1136
1283 r0p2 erratum (possible cache data corruption with
1284 hit-under-miss enabled). It sets the undocumented bit 31 in
1285 the auxiliary control register and the FI bit in the control
1286 register, thus disabling hit-under-miss without putting the
1287 processor into full low interrupt latency mode. ARM11MPCore
1288 is not affected.
1290 config ARM_ERRATA_764369
1291 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1292 depends on CPU_V7 && SMP
1293 help
1294 This option enables the workaround for erratum 764369
1295 affecting Cortex-A9 MPCore with two or more processors (all
1296 current revisions). Under certain timing circumstances, a data
1297 cache line maintenance operation by MVA targeting an Inner
1298 Shareable memory region may fail to proceed up to either the
1299 Point of Coherency or to the Point of Unification of the
1300 system. This workaround adds a DSB instruction before the
1301 relevant cache maintenance functions and sets a specific bit
1302 in the diagnostic control register of the SCU.
1304 config PL310_ERRATA_769419
1305 bool "PL310 errata: no automatic Store Buffer drain"
1306 depends on CACHE_L2X0
1307 help
1308 On revisions of the PL310 prior to r3p2, the Store Buffer does
1309 not automatically drain. This can cause normal, non-cacheable
1310 writes to be retained when the memory system is idle, leading
1311 to suboptimal I/O performance for drivers using coherent DMA.
1312 This option adds a write barrier to the cpu_idle loop so that,
1313 on systems with an outer cache, the store buffer is drained
1314 explicitly.
1316 config ARM_ERRATA_775420
1317 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1318 depends on CPU_V7
1319 help
1320 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1321 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1322 operation aborts with MMU exception, it might cause the processor
1323 to deadlock. This workaround puts DSB before executing ISB if
1324 an abort may occur on cache maintenance.
1326 config ARM_ERRATA_798181
1327 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1328 depends on CPU_V7 && SMP
1329 help
1330 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1331 adequately shooting down all use of the old entries. This
1332 option enables the Linux kernel workaround for this erratum
1333 which sends an IPI to the CPUs that are running the same ASID
1334 as the one being invalidated.
1336 endmenu
1338 source "arch/arm/common/Kconfig"
1340 menu "Bus support"
1342 config ARM_AMBA
1343 bool
1345 config ISA
1346 bool
1347 help
1348 Find out whether you have ISA slots on your motherboard. ISA is the
1349 name of a bus system, i.e. the way the CPU talks to the other stuff
1350 inside your box. Other bus systems are PCI, EISA, MicroChannel
1351 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1352 newer boards don't support it. If you have ISA, say Y, otherwise N.
1354 # Select ISA DMA controller support
1355 config ISA_DMA
1356 bool
1357 select ISA_DMA_API
1359 # Select ISA DMA interface
1360 config ISA_DMA_API
1361 bool
1363 config PCI
1364 bool "PCI support" if MIGHT_HAVE_PCI
1365 help
1366 Find out whether you have a PCI motherboard. PCI is the name of a
1367 bus system, i.e. the way the CPU talks to the other stuff inside
1368 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1369 VESA. If you have PCI, say Y, otherwise N.
1371 config PCI_DOMAINS
1372 bool
1373 depends on PCI
1375 config PCI_NANOENGINE
1376 bool "BSE nanoEngine PCI support"
1377 depends on SA1100_NANOENGINE
1378 help
1379 Enable PCI on the BSE nanoEngine board.
1381 config PCI_SYSCALL
1382 def_bool PCI
1384 # Select the host bridge type
1385 config PCI_HOST_VIA82C505
1386 bool
1387 depends on PCI && ARCH_SHARK
1388 default y
1390 config PCI_HOST_ITE8152
1391 bool
1392 depends on PCI && MACH_ARMCORE
1393 default y
1394 select DMABOUNCE
1396 source "drivers/pci/Kconfig"
1398 source "drivers/pcmcia/Kconfig"
1400 endmenu
1402 menu "Kernel Features"
1404 config HAVE_SMP
1405 bool
1406 help
1407 This option should be selected by machines which have an SMP-
1408 capable CPU.
1410 The only effect of this option is to make the SMP-related
1411 options available to the user for configuration.
1413 config SMP
1414 bool "Symmetric Multi-Processing"
1415 depends on CPU_V6K || CPU_V7
1416 depends on GENERIC_CLOCKEVENTS
1417 depends on HAVE_SMP
1418 depends on MMU
1419 select USE_GENERIC_SMP_HELPERS
1420 help
1421 This enables support for systems with more than one CPU. If you have
1422 a system with only one CPU, like most personal computers, say N. If
1423 you have a system with more than one CPU, say Y.
1425 If you say N here, the kernel will run on single and multiprocessor
1426 machines, but will use only one CPU of a multiprocessor machine. If
1427 you say Y here, the kernel will run on many, but not all, single
1428 processor machines. On a single processor machine, the kernel will
1429 run faster if you say N here.
1431 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1432 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1433 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1435 If you don't know what to do here, say N.
1437 config SMP_ON_UP
1438 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1439 depends on SMP && !XIP_KERNEL
1440 default y
1441 help
1442 SMP kernels contain instructions which fail on non-SMP processors.
1443 Enabling this option allows the kernel to modify itself to make
1444 these instructions safe. Disabling it allows about 1K of space
1445 savings.
1447 If you don't know what to do here, say Y.
1449 config ARM_CPU_TOPOLOGY
1450 bool "Support cpu topology definition"
1451 depends on SMP && CPU_V7
1452 default y
1453 help
1454 Support ARM cpu topology definition. The MPIDR register defines
1455 affinity between processors which is then used to describe the cpu
1456 topology of an ARM System.
1458 config SCHED_MC
1459 bool "Multi-core scheduler support"
1460 depends on ARM_CPU_TOPOLOGY
1461 help
1462 Multi-core scheduler support improves the CPU scheduler's decision
1463 making when dealing with multi-core CPU chips at a cost of slightly
1464 increased overhead in some places. If unsure say N here.
1466 config SCHED_SMT
1467 bool "SMT scheduler support"
1468 depends on ARM_CPU_TOPOLOGY
1469 help
1470 Improves the CPU scheduler's decision making when dealing with
1471 MultiThreading at a cost of slightly increased overhead in some
1472 places. If unsure say N here.
1474 config HAVE_ARM_SCU
1475 bool
1476 help
1477 This option enables support for the ARM system coherency unit
1479 config HAVE_ARM_ARCH_TIMER
1480 bool "Architected timer support"
1481 depends on CPU_V7
1482 select ARM_ARCH_TIMER
1483 help
1484 This option enables support for the ARM architected timer
1486 config HAVE_ARM_TWD
1487 bool
1488 depends on SMP
1489 select CLKSRC_OF if OF
1490 help
1491 This options enables support for the ARM timer and watchdog unit
1493 config MCPM
1494 bool "Multi-Cluster Power Management"
1495 depends on CPU_V7 && SMP
1496 help
1497 This option provides the common power management infrastructure
1498 for (multi-)cluster based systems, such as big.LITTLE based
1499 systems.
1501 choice
1502 prompt "Memory split"
1503 default VMSPLIT_3G
1504 help
1505 Select the desired split between kernel and user memory.
1507 If you are not absolutely sure what you are doing, leave this
1508 option alone!
1510 config VMSPLIT_3G
1511 bool "3G/1G user/kernel split"
1512 config VMSPLIT_2G
1513 bool "2G/2G user/kernel split"
1514 config VMSPLIT_1G
1515 bool "1G/3G user/kernel split"
1516 endchoice
1518 config PAGE_OFFSET
1519 hex
1520 default 0x40000000 if VMSPLIT_1G
1521 default 0x80000000 if VMSPLIT_2G
1522 default 0xC0000000
1524 config NR_CPUS
1525 int "Maximum number of CPUs (2-32)"
1526 range 2 32
1527 depends on SMP
1528 default "4"
1530 config HOTPLUG_CPU
1531 bool "Support for hot-pluggable CPUs"
1532 depends on SMP && HOTPLUG
1533 help
1534 Say Y here to experiment with turning CPUs off and on. CPUs
1535 can be controlled through /sys/devices/system/cpu.
1537 config ARM_PSCI
1538 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1539 depends on CPU_V7
1540 help
1541 Say Y here if you want Linux to communicate with system firmware
1542 implementing the PSCI specification for CPU-centric power
1543 management operations described in ARM document number ARM DEN
1544 0022A ("Power State Coordination Interface System Software on
1545 ARM processors").
1547 config LOCAL_TIMERS
1548 bool "Use local timer interrupts"
1549 depends on SMP
1550 default y
1551 help
1552 Enable support for local timers on SMP platforms, rather then the
1553 legacy IPI broadcast method. Local timers allows the system
1554 accounting to be spread across the timer interval, preventing a
1555 "thundering herd" at every timer tick.
1557 # The GPIO number here must be sorted by descending number. In case of
1558 # a multiplatform kernel, we just want the highest value required by the
1559 # selected platforms.
1560 config ARCH_NR_GPIO
1561 int
1562 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1563 default 512 if SOC_OMAP5
1564 default 392 if ARCH_U8500
1565 default 352 if ARCH_VT8500
1566 default 288 if ARCH_SUNXI
1567 default 264 if MACH_H4700
1568 default 0
1569 help
1570 Maximum number of GPIOs in the system.
1572 If unsure, leave the default value.
1574 source kernel/Kconfig.preempt
1576 config HZ
1577 int
1578 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1579 ARCH_S5PV210 || ARCH_EXYNOS4
1580 default AT91_TIMER_HZ if ARCH_AT91
1581 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1582 default 100
1584 config SCHED_HRTICK
1585 def_bool HIGH_RES_TIMERS
1587 config THUMB2_KERNEL
1588 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1589 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1590 default y if CPU_THUMBONLY
1591 select AEABI
1592 select ARM_ASM_UNIFIED
1593 select ARM_UNWIND
1594 help
1595 By enabling this option, the kernel will be compiled in
1596 Thumb-2 mode. A compiler/assembler that understand the unified
1597 ARM-Thumb syntax is needed.
1599 If unsure, say N.
1601 config THUMB2_AVOID_R_ARM_THM_JUMP11
1602 bool "Work around buggy Thumb-2 short branch relocations in gas"
1603 depends on THUMB2_KERNEL && MODULES
1604 default y
1605 help
1606 Various binutils versions can resolve Thumb-2 branches to
1607 locally-defined, preemptible global symbols as short-range "b.n"
1608 branch instructions.
1610 This is a problem, because there's no guarantee the final
1611 destination of the symbol, or any candidate locations for a
1612 trampoline, are within range of the branch. For this reason, the
1613 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1614 relocation in modules at all, and it makes little sense to add
1615 support.
1617 The symptom is that the kernel fails with an "unsupported
1618 relocation" error when loading some modules.
1620 Until fixed tools are available, passing
1621 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1622 code which hits this problem, at the cost of a bit of extra runtime
1623 stack usage in some cases.
1625 The problem is described in more detail at:
1626 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1628 Only Thumb-2 kernels are affected.
1630 Unless you are sure your tools don't have this problem, say Y.
1632 config ARM_ASM_UNIFIED
1633 bool
1635 config AEABI
1636 bool "Use the ARM EABI to compile the kernel"
1637 help
1638 This option allows for the kernel to be compiled using the latest
1639 ARM ABI (aka EABI). This is only useful if you are using a user
1640 space environment that is also compiled with EABI.
1642 Since there are major incompatibilities between the legacy ABI and
1643 EABI, especially with regard to structure member alignment, this
1644 option also changes the kernel syscall calling convention to
1645 disambiguate both ABIs and allow for backward compatibility support
1646 (selected with CONFIG_OABI_COMPAT).
1648 To use this you need GCC version 4.0.0 or later.
1650 config OABI_COMPAT
1651 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1652 depends on AEABI && !THUMB2_KERNEL
1653 default y
1654 help
1655 This option preserves the old syscall interface along with the
1656 new (ARM EABI) one. It also provides a compatibility layer to
1657 intercept syscalls that have structure arguments which layout
1658 in memory differs between the legacy ABI and the new ARM EABI
1659 (only for non "thumb" binaries). This option adds a tiny
1660 overhead to all syscalls and produces a slightly larger kernel.
1661 If you know you'll be using only pure EABI user space then you
1662 can say N here. If this option is not selected and you attempt
1663 to execute a legacy ABI binary then the result will be
1664 UNPREDICTABLE (in fact it can be predicted that it won't work
1665 at all). If in doubt say Y.
1667 config ARCH_HAS_HOLES_MEMORYMODEL
1668 bool
1670 config ARCH_SPARSEMEM_ENABLE
1671 bool
1673 config ARCH_SPARSEMEM_DEFAULT
1674 def_bool ARCH_SPARSEMEM_ENABLE
1676 config ARCH_SELECT_MEMORY_MODEL
1677 def_bool ARCH_SPARSEMEM_ENABLE
1679 config HAVE_ARCH_PFN_VALID
1680 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1682 config HIGHMEM
1683 bool "High Memory Support"
1684 depends on MMU
1685 help
1686 The address space of ARM processors is only 4 Gigabytes large
1687 and it has to accommodate user address space, kernel address
1688 space as well as some memory mapped IO. That means that, if you
1689 have a large amount of physical memory and/or IO, not all of the
1690 memory can be "permanently mapped" by the kernel. The physical
1691 memory that is not permanently mapped is called "high memory".
1693 Depending on the selected kernel/user memory split, minimum
1694 vmalloc space and actual amount of RAM, you may not need this
1695 option which should result in a slightly faster kernel.
1697 If unsure, say n.
1699 config HIGHPTE
1700 bool "Allocate 2nd-level pagetables from highmem"
1701 depends on HIGHMEM
1703 config HW_PERF_EVENTS
1704 bool "Enable hardware performance counter support for perf events"
1705 depends on PERF_EVENTS
1706 default y
1707 help
1708 Enable hardware performance counter support for perf events. If
1709 disabled, perf events will use software events only.
1711 source "mm/Kconfig"
1713 config FORCE_MAX_ZONEORDER
1714 int "Maximum zone order" if ARCH_SHMOBILE
1715 range 11 64 if ARCH_SHMOBILE
1716 default "12" if SOC_AM33XX
1717 default "9" if SA1111
1718 default "11"
1719 help
1720 The kernel memory allocator divides physically contiguous memory
1721 blocks into "zones", where each zone is a power of two number of
1722 pages. This option selects the largest power of two that the kernel
1723 keeps in the memory allocator. If you need to allocate very large
1724 blocks of physically contiguous memory, then you may need to
1725 increase this value.
1727 This config option is actually maximum order plus one. For example,
1728 a value of 11 means that the largest free memory block is 2^10 pages.
1730 config ALIGNMENT_TRAP
1731 bool
1732 depends on CPU_CP15_MMU
1733 default y if !ARCH_EBSA110
1734 select HAVE_PROC_CPU if PROC_FS
1735 help
1736 ARM processors cannot fetch/store information which is not
1737 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1738 address divisible by 4. On 32-bit ARM processors, these non-aligned
1739 fetch/store instructions will be emulated in software if you say
1740 here, which has a severe performance impact. This is necessary for
1741 correct operation of some network protocols. With an IP-only
1742 configuration it is safe to say N, otherwise say Y.
1744 config UACCESS_WITH_MEMCPY
1745 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1746 depends on MMU
1747 default y if CPU_FEROCEON
1748 help
1749 Implement faster copy_to_user and clear_user methods for CPU
1750 cores where a 8-word STM instruction give significantly higher
1751 memory write throughput than a sequence of individual 32bit stores.
1753 A possible side effect is a slight increase in scheduling latency
1754 between threads sharing the same address space if they invoke
1755 such copy operations with large buffers.
1757 However, if the CPU data cache is using a write-allocate mode,
1758 this option is unlikely to provide any performance gain.
1760 config SECCOMP
1761 bool
1762 prompt "Enable seccomp to safely compute untrusted bytecode"
1763 ---help---
1764 This kernel feature is useful for number crunching applications
1765 that may need to compute untrusted bytecode during their
1766 execution. By using pipes or other transports made available to
1767 the process as file descriptors supporting the read/write
1768 syscalls, it's possible to isolate those applications in
1769 their own address space using seccomp. Once seccomp is
1770 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1771 and the task is only allowed to execute a few safe syscalls
1772 defined by each seccomp mode.
1774 config CC_STACKPROTECTOR
1775 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1776 help
1777 This option turns on the -fstack-protector GCC feature. This
1778 feature puts, at the beginning of functions, a canary value on
1779 the stack just before the return address, and validates
1780 the value just before actually returning. Stack based buffer
1781 overflows (that need to overwrite this return address) now also
1782 overwrite the canary, which gets detected and the attack is then
1783 neutralized via a kernel panic.
1784 This feature requires gcc version 4.2 or above.
1786 config XEN_DOM0
1787 def_bool y
1788 depends on XEN
1790 config XEN
1791 bool "Xen guest support on ARM (EXPERIMENTAL)"
1792 depends on ARM && AEABI && OF
1793 depends on CPU_V7 && !CPU_V6
1794 depends on !GENERIC_ATOMIC64
1795 select ARM_PSCI
1796 help
1797 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1799 endmenu
1801 menu "Boot options"
1803 config USE_OF
1804 bool "Flattened Device Tree support"
1805 select IRQ_DOMAIN
1806 select OF
1807 select OF_EARLY_FLATTREE
1808 help
1809 Include support for flattened device tree machine descriptions.
1811 config ATAGS
1812 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1813 default y
1814 help
1815 This is the traditional way of passing data to the kernel at boot
1816 time. If you are solely relying on the flattened device tree (or
1817 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1818 to remove ATAGS support from your kernel binary. If unsure,
1819 leave this to y.
1821 config DEPRECATED_PARAM_STRUCT
1822 bool "Provide old way to pass kernel parameters"
1823 depends on ATAGS
1824 help
1825 This was deprecated in 2001 and announced to live on for 5 years.
1826 Some old boot loaders still use this way.
1828 # Compressed boot loader in ROM. Yes, we really want to ask about
1829 # TEXT and BSS so we preserve their values in the config files.
1830 config ZBOOT_ROM_TEXT
1831 hex "Compressed ROM boot loader base address"
1832 default "0"
1833 help
1834 The physical address at which the ROM-able zImage is to be
1835 placed in the target. Platforms which normally make use of
1836 ROM-able zImage formats normally set this to a suitable
1837 value in their defconfig file.
1839 If ZBOOT_ROM is not enabled, this has no effect.
1841 config ZBOOT_ROM_BSS
1842 hex "Compressed ROM boot loader BSS address"
1843 default "0"
1844 help
1845 The base address of an area of read/write memory in the target
1846 for the ROM-able zImage which must be available while the
1847 decompressor is running. It must be large enough to hold the
1848 entire decompressed kernel plus an additional 128 KiB.
1849 Platforms which normally make use of ROM-able zImage formats
1850 normally set this to a suitable value in their defconfig file.
1852 If ZBOOT_ROM is not enabled, this has no effect.
1854 config ZBOOT_ROM
1855 bool "Compressed boot loader in ROM/flash"
1856 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1857 help
1858 Say Y here if you intend to execute your compressed kernel image
1859 (zImage) directly from ROM or flash. If unsure, say N.
1861 choice
1862 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1863 depends on ZBOOT_ROM && ARCH_SH7372
1864 default ZBOOT_ROM_NONE
1865 help
1866 Include experimental SD/MMC loading code in the ROM-able zImage.
1867 With this enabled it is possible to write the ROM-able zImage
1868 kernel image to an MMC or SD card and boot the kernel straight
1869 from the reset vector. At reset the processor Mask ROM will load
1870 the first part of the ROM-able zImage which in turn loads the
1871 rest the kernel image to RAM.
1873 config ZBOOT_ROM_NONE
1874 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1875 help
1876 Do not load image from SD or MMC
1878 config ZBOOT_ROM_MMCIF
1879 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1880 help
1881 Load image from MMCIF hardware block.
1883 config ZBOOT_ROM_SH_MOBILE_SDHI
1884 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1885 help
1886 Load image from SDHI hardware block
1888 endchoice
1890 config ARM_APPENDED_DTB
1891 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1892 depends on OF && !ZBOOT_ROM
1893 help
1894 With this option, the boot code will look for a device tree binary
1895 (DTB) appended to zImage
1896 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1898 This is meant as a backward compatibility convenience for those
1899 systems with a bootloader that can't be upgraded to accommodate
1900 the documented boot protocol using a device tree.
1902 Beware that there is very little in terms of protection against
1903 this option being confused by leftover garbage in memory that might
1904 look like a DTB header after a reboot if no actual DTB is appended
1905 to zImage. Do not leave this option active in a production kernel
1906 if you don't intend to always append a DTB. Proper passing of the
1907 location into r2 of a bootloader provided DTB is always preferable
1908 to this option.
1910 config ARM_ATAG_DTB_COMPAT
1911 bool "Supplement the appended DTB with traditional ATAG information"
1912 depends on ARM_APPENDED_DTB
1913 help
1914 Some old bootloaders can't be updated to a DTB capable one, yet
1915 they provide ATAGs with memory configuration, the ramdisk address,
1916 the kernel cmdline string, etc. Such information is dynamically
1917 provided by the bootloader and can't always be stored in a static
1918 DTB. To allow a device tree enabled kernel to be used with such
1919 bootloaders, this option allows zImage to extract the information
1920 from the ATAG list and store it at run time into the appended DTB.
1922 choice
1923 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1924 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1926 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1927 bool "Use bootloader kernel arguments if available"
1928 help
1929 Uses the command-line options passed by the boot loader instead of
1930 the device tree bootargs property. If the boot loader doesn't provide
1931 any, the device tree bootargs property will be used.
1933 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1934 bool "Extend with bootloader kernel arguments"
1935 help
1936 The command-line arguments provided by the boot loader will be
1937 appended to the the device tree bootargs property.
1939 endchoice
1941 config CMDLINE
1942 string "Default kernel command string"
1943 default ""
1944 help
1945 On some architectures (EBSA110 and CATS), there is currently no way
1946 for the boot loader to pass arguments to the kernel. For these
1947 architectures, you should supply some command-line options at build
1948 time by entering them here. As a minimum, you should specify the
1949 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1951 choice
1952 prompt "Kernel command line type" if CMDLINE != ""
1953 default CMDLINE_FROM_BOOTLOADER
1954 depends on ATAGS
1956 config CMDLINE_FROM_BOOTLOADER
1957 bool "Use bootloader kernel arguments if available"
1958 help
1959 Uses the command-line options passed by the boot loader. If
1960 the boot loader doesn't provide any, the default kernel command
1961 string provided in CMDLINE will be used.
1963 config CMDLINE_EXTEND
1964 bool "Extend bootloader kernel arguments"
1965 help
1966 The command-line arguments provided by the boot loader will be
1967 appended to the default kernel command string.
1969 config CMDLINE_FORCE
1970 bool "Always use the default kernel command string"
1971 help
1972 Always use the default kernel command string, even if the boot
1973 loader passes other arguments to the kernel.
1974 This is useful if you cannot or don't want to change the
1975 command-line options your boot loader passes to the kernel.
1976 endchoice
1978 config XIP_KERNEL
1979 bool "Kernel Execute-In-Place from ROM"
1980 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
1981 help
1982 Execute-In-Place allows the kernel to run from non-volatile storage
1983 directly addressable by the CPU, such as NOR flash. This saves RAM
1984 space since the text section of the kernel is not loaded from flash
1985 to RAM. Read-write sections, such as the data section and stack,
1986 are still copied to RAM. The XIP kernel is not compressed since
1987 it has to run directly from flash, so it will take more space to
1988 store it. The flash address used to link the kernel object files,
1989 and for storing it, is configuration dependent. Therefore, if you
1990 say Y here, you must know the proper physical address where to
1991 store the kernel image depending on your own flash memory usage.
1993 Also note that the make target becomes "make xipImage" rather than
1994 "make zImage" or "make Image". The final kernel binary to put in
1995 ROM memory will be arch/arm/boot/xipImage.
1997 If unsure, say N.
1999 config XIP_PHYS_ADDR
2000 hex "XIP Kernel Physical Location"
2001 depends on XIP_KERNEL
2002 default "0x00080000"
2003 help
2004 This is the physical address in your flash memory the kernel will
2005 be linked for and stored to. This address is dependent on your
2006 own flash usage.
2008 config KEXEC
2009 bool "Kexec system call (EXPERIMENTAL)"
2010 depends on (!SMP || HOTPLUG_CPU)
2011 help
2012 kexec is a system call that implements the ability to shutdown your
2013 current kernel, and to start another kernel. It is like a reboot
2014 but it is independent of the system firmware. And like a reboot
2015 you can start any kernel with it, not just Linux.
2017 It is an ongoing process to be certain the hardware in a machine
2018 is properly shutdown, so do not be surprised if this code does not
2019 initially work for you. It may help to enable device hotplugging
2020 support.
2022 config ATAGS_PROC
2023 bool "Export atags in procfs"
2024 depends on ATAGS && KEXEC
2025 default y
2026 help
2027 Should the atags used to boot the kernel be exported in an "atags"
2028 file in procfs. Useful with kexec.
2030 config CRASH_DUMP
2031 bool "Build kdump crash kernel (EXPERIMENTAL)"
2032 help
2033 Generate crash dump after being started by kexec. This should
2034 be normally only set in special crash dump kernels which are
2035 loaded in the main kernel with kexec-tools into a specially
2036 reserved region and then later executed after a crash by
2037 kdump/kexec. The crash dump kernel must be compiled to a
2038 memory address not used by the main kernel
2040 For more details see Documentation/kdump/kdump.txt
2042 config AUTO_ZRELADDR
2043 bool "Auto calculation of the decompressed kernel image address"
2044 depends on !ZBOOT_ROM && !ARCH_U300
2045 help
2046 ZRELADDR is the physical address where the decompressed kernel
2047 image will be placed. If AUTO_ZRELADDR is selected, the address
2048 will be determined at run-time by masking the current IP with
2049 0xf8000000. This assumes the zImage being placed in the first 128MB
2050 from start of memory.
2052 endmenu
2054 menu "CPU Power Management"
2056 if ARCH_HAS_CPUFREQ
2057 source "drivers/cpufreq/Kconfig"
2059 config CPU_FREQ_S3C
2060 bool
2061 help
2062 Internal configuration node for common cpufreq on Samsung SoC
2064 config CPU_FREQ_S3C24XX
2065 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2066 depends on ARCH_S3C24XX && CPU_FREQ
2067 select CPU_FREQ_S3C
2068 help
2069 This enables the CPUfreq driver for the Samsung S3C24XX family
2070 of CPUs.
2072 For details, take a look at <file:Documentation/cpu-freq>.
2074 If in doubt, say N.
2076 config CPU_FREQ_S3C24XX_PLL
2077 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2078 depends on CPU_FREQ_S3C24XX
2079 help
2080 Compile in support for changing the PLL frequency from the
2081 S3C24XX series CPUfreq driver. The PLL takes time to settle
2082 after a frequency change, so by default it is not enabled.
2084 This also means that the PLL tables for the selected CPU(s) will
2085 be built which may increase the size of the kernel image.
2087 config CPU_FREQ_S3C24XX_DEBUG
2088 bool "Debug CPUfreq Samsung driver core"
2089 depends on CPU_FREQ_S3C24XX
2090 help
2091 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2093 config CPU_FREQ_S3C24XX_IODEBUG
2094 bool "Debug CPUfreq Samsung driver IO timing"
2095 depends on CPU_FREQ_S3C24XX
2096 help
2097 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2099 config CPU_FREQ_S3C24XX_DEBUGFS
2100 bool "Export debugfs for CPUFreq"
2101 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2102 help
2103 Export status information via debugfs.
2105 endif
2107 source "drivers/cpuidle/Kconfig"
2109 endmenu
2111 menu "Floating point emulation"
2113 comment "At least one emulation must be selected"
2115 config FPE_NWFPE
2116 bool "NWFPE math emulation"
2117 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2118 ---help---
2119 Say Y to include the NWFPE floating point emulator in the kernel.
2120 This is necessary to run most binaries. Linux does not currently
2121 support floating point hardware so you need to say Y here even if
2122 your machine has an FPA or floating point co-processor podule.
2124 You may say N here if you are going to load the Acorn FPEmulator
2125 early in the bootup.
2127 config FPE_NWFPE_XP
2128 bool "Support extended precision"
2129 depends on FPE_NWFPE
2130 help
2131 Say Y to include 80-bit support in the kernel floating-point
2132 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2133 Note that gcc does not generate 80-bit operations by default,
2134 so in most cases this option only enlarges the size of the
2135 floating point emulator without any good reason.
2137 You almost surely want to say N here.
2139 config FPE_FASTFPE
2140 bool "FastFPE math emulation (EXPERIMENTAL)"
2141 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2142 ---help---
2143 Say Y here to include the FAST floating point emulator in the kernel.
2144 This is an experimental much faster emulator which now also has full
2145 precision for the mantissa. It does not support any exceptions.
2146 It is very simple, and approximately 3-6 times faster than NWFPE.
2148 It should be sufficient for most programs. It may be not suitable
2149 for scientific calculations, but you have to check this for yourself.
2150 If you do not feel you need a faster FP emulation you should better
2151 choose NWFPE.
2153 config VFP
2154 bool "VFP-format floating point maths"
2155 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2156 help
2157 Say Y to include VFP support code in the kernel. This is needed
2158 if your hardware includes a VFP unit.
2160 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2161 release notes and additional status information.
2163 Say N if your target does not have VFP hardware.
2165 config VFPv3
2166 bool
2167 depends on VFP
2168 default y if CPU_V7
2170 config NEON
2171 bool "Advanced SIMD (NEON) Extension support"
2172 depends on VFPv3 && CPU_V7
2173 help
2174 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2175 Extension.
2177 endmenu
2179 menu "Userspace binary formats"
2181 source "fs/Kconfig.binfmt"
2183 config ARTHUR
2184 tristate "RISC OS personality"
2185 depends on !AEABI
2186 help
2187 Say Y here to include the kernel code necessary if you want to run
2188 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2189 experimental; if this sounds frightening, say N and sleep in peace.
2190 You can also say M here to compile this support as a module (which
2191 will be called arthur).
2193 endmenu
2195 menu "Power management options"
2197 source "kernel/power/Kconfig"
2199 config ARCH_SUSPEND_POSSIBLE
2200 depends on !ARCH_S5PC100
2201 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2202 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2203 def_bool y
2205 config ARM_CPU_SUSPEND
2206 def_bool PM_SLEEP
2208 endmenu
2210 source "net/Kconfig"
2212 source "drivers/Kconfig"
2214 source "fs/Kconfig"
2216 source "arch/arm/Kconfig.debug"
2218 source "security/Kconfig"
2220 source "crypto/Kconfig"
2222 source "lib/Kconfig"
2224 source "arch/arm/kvm/Kconfig"