1 /* linux/arch/arm/plat-s5p/sleep.S
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * S5PV210 power Manager (Suspend-To-RAM) support
7 * Based on S3C2410 sleep code by:
8 * Ben Dooks, (c) 2004 Simtec Electronics
10 * Based on PXA/SA1100 sleep code by:
11 * Nicolas Pitre, (c) 2002 Monta Vista Software Inc
12 * Cliff Brake, (c) 2001
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
29 #include <linux/linkage.h>
30 #include <asm/assembler.h>
31 #include <asm/memory.h>
38 * r0 = save address (virtual addr of s3c_sleep_save_phys)
43 stmfd sp!, { r3 - r12, lr }
45 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
46 mrc p15, 0, r5, c3, c0, 0 @ Domain ID
47 mrc p15, 0, r6, c2, c0, 0 @ Translation Table BASE0
48 mrc p15, 0, r7, c2, c0, 1 @ Translation Table BASE1
49 mrc p15, 0, r8, c2, c0, 2 @ Translation Table Control
50 mrc p15, 0, r9, c1, c0, 0 @ Control register
51 mrc p15, 0, r10, c1, c0, 1 @ Auxiliary control register
52 mrc p15, 0, r11, c1, c0, 2 @ Co-processor access controls
53 mrc p15, 0, r12, c10, c2, 0 @ Read PRRR
54 mrc p15, 0, r3, c10, c2, 1 @ READ NMRR
56 stmia r0, { r3 - r13 }
58 bl s3c_pm_cb_flushcache
66 * After MMU is turned on, restore the previous MMU table.
68 ldr r9 , =(PAGE_OFFSET - PHYS_OFFSET)
72 ldmfd sp!, { r3 - r12, pc }
78 .global s3c_sleep_save_phys
82 /* sleep magic, to allow the bootloader to check for an valid
83 * image to resume to. Must be the first word before the
84 * s3c_cpu_resume entry.
91 * resume code entry for bootloader to call
93 * we must put this code here in the data segment as we have no
94 * other way of restoring the stack pointer after sleep, and we
95 * must not write to the code segment (code is read-only)
99 mov r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE
103 mcr p15, 0, r1, c8, c7, 0 @ invalidate TLBs
104 mcr p15, 0, r1, c7, c5, 0 @ invalidate I Cache
106 ldr r0, s3c_sleep_save_phys @ address of restore block
107 ldmia r0, { r3 - r13 }
109 mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
110 mcr p15, 0, r5, c3, c0, 0 @ Domain ID
112 mcr p15, 0, r8, c2, c0, 2 @ Translation Table Control
113 mcr p15, 0, r7, c2, c0, 1 @ Translation Table BASE1
114 mcr p15, 0, r6, c2, c0, 0 @ Translation Table BASE0
116 mcr p15, 0, r10, c1, c0, 1 @ Auxiliary control register
119 mcr p15, 0, r0, c8, c7, 0 @ Invalidate I & D TLB
121 mov r0, #0 @ restore copro access
122 mcr p15, 0, r11, c1, c0, 2 @ Co-processor access
123 mcr p15, 0, r0, c7, c5, 4
125 mcr p15, 0, r12, c10, c2, 0 @ write PRRR
126 mcr p15, 0, r3, c10, c2, 1 @ write NMRR
129 * In Cortex-A8, when MMU is turned on, the pipeline is flushed.
130 * And there are no valid entries in the MMU table at this point.
131 * So before turning on the MMU, the MMU entry for the DRAM address
132 * range is added. After the MMU is turned on, the other entries
133 * in the MMU table will be restored.
136 /* r6 = Translation Table BASE0 */
141 /* Load address for adding to MMU table list */
142 ldr r11, =0xE010F000 @ INFORM0 reg.
144 mov r10, r10, LSR #18
148 /* Calculate MMU table entry */
149 mov r10, r10, LSL #18
153 /* Back up originally data */
156 /* Add calculated MMU table entry into MMU table list */
159 ldr r2, =resume_with_mmu
160 mcr p15, 0, r9, c1, c0, 0 @ turn on MMU, etc
166 nop @ second-to-last before mmu
168 mov pc, r2 @ go back to virtual address