drivers/net/wireless/ath/ath9k/hw.h

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #ifndef HW_H
  18 #define HW_H
  19
  20 #include <linux/if_ether.h>
  21 #include <linux/delay.h>
  22 #include <linux/io.h>
  23
  24 #include "mac.h"
  25 #include "ani.h"
  26 #include "eeprom.h"
  27 #include "calib.h"
  28 #include "reg.h"
  29 #include "phy.h"
  30 #include "btcoex.h"
  31
  32 #include "../regd.h"
  33 #include "../debug.h"
  34
  35 #define ATHEROS_VENDOR_ID       0x168c
  36 #define AR5416_DEVID_PCI        0x0023
  37 #define AR5416_DEVID_PCIE       0x0024
  38 #define AR9160_DEVID_PCI        0x0027
  39 #define AR9280_DEVID_PCI        0x0029
  40 #define AR9280_DEVID_PCIE       0x002a
  41 #define AR9285_DEVID_PCIE       0x002b
  42 #define AR5416_AR9100_DEVID     0x000b
  43 #define AR_SUBVENDOR_ID_NOG     0x0e11
  44 #define AR_SUBVENDOR_ID_NEW_A   0x7065
  45 #define AR5416_MAGIC            0x19641014
  46
  47 #define AR5416_DEVID_AR9287_PCI  0x002D
  48 #define AR5416_DEVID_AR9287_PCIE 0x002E
  49
  50 #define AR9280_COEX2WIRE_SUBSYSID       0x309b
  51 #define AT9285_COEX3WIRE_SA_SUBSYSID    0x30aa
  52 #define AT9285_COEX3WIRE_DA_SUBSYSID    0x30ab
  53
  54 #define ATH_AMPDU_LIMIT_MAX        (64 * 1024 - 1)
  55
  56 #define ATH_DEFAULT_NOISE_FLOOR -95
  57
  58 #define ATH9K_RSSI_BAD                  0x80
  59
  60 /* Register read/write primitives */
  61 #define REG_WRITE(_ah, _reg, _val) \
  62         ath9k_hw_common(_ah)->ops->write((_ah), (_val), (_reg))
  63
  64 #define REG_READ(_ah, _reg) \
  65         ath9k_hw_common(_ah)->ops->read((_ah), (_reg))
  66
  67 #define SM(_v, _f)  (((_v) << _f##_S) & _f)
  68 #define MS(_v, _f)  (((_v) & _f) >> _f##_S)
  69 #define REG_RMW(_a, _r, _set, _clr)    \
  70         REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
  71 #define REG_RMW_FIELD(_a, _r, _f, _v) \
  72         REG_WRITE(_a, _r, \
  73         (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
  74 #define REG_SET_BIT(_a, _r, _f) \
  75         REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
  76 #define REG_CLR_BIT(_a, _r, _f) \
  77         REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
  78
  79 #define DO_DELAY(x) do {                        \
  80                 if ((++(x) % 64) == 0)          \
  81                         udelay(1);              \
  82         } while (0)
  83
  84 #define REG_WRITE_ARRAY(iniarray, column, regWr) do {                   \
  85                 int r;                                                  \
  86                 for (r = 0; r < ((iniarray)->ia_rows); r++) {           \
  87                         REG_WRITE(ah, INI_RA((iniarray), (r), 0),       \
  88                                   INI_RA((iniarray), r, (column)));     \
  89                         DO_DELAY(regWr);                                \
  90                 }                                                       \
  91         } while (0)
  92
  93 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT             0
  94 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
  95 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED     2
  96 #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME           3
  97 #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL  4
  98 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED    5
  99 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED      6
 100
 101 #define AR_GPIOD_MASK               0x00001FFF
 102 #define AR_GPIO_BIT(_gpio)          (1 << (_gpio))
 103
 104 #define BASE_ACTIVATE_DELAY         100
 105 #define RTC_PLL_SETTLE_DELAY        100
 106 #define COEF_SCALE_S                24
 107 #define HT40_CHANNEL_CENTER_SHIFT   10
 108
 109 #define ATH9K_ANTENNA0_CHAINMASK    0x1
 110 #define ATH9K_ANTENNA1_CHAINMASK    0x2
 111
 112 #define ATH9K_NUM_DMA_DEBUG_REGS    8
 113 #define ATH9K_NUM_QUEUES            10
 114
 115 #define MAX_RATE_POWER              63
 116 #define AH_WAIT_TIMEOUT             100000 /* (us) */
 117 #define AH_TSF_WRITE_TIMEOUT        100    /* (us) */
 118 #define AH_TIME_QUANTUM             10
 119 #define AR_KEYTABLE_SIZE            128
 120 #define POWER_UP_TIME               10000
 121 #define SPUR_RSSI_THRESH            40
 122
 123 #define CAB_TIMEOUT_VAL             10
 124 #define BEACON_TIMEOUT_VAL          10
 125 #define MIN_BEACON_TIMEOUT_VAL      1
 126 #define SLEEP_SLOP                  3
 127
 128 #define INIT_CONFIG_STATUS          0x00000000
 129 #define INIT_RSSI_THR               0x00000700
 130 #define INIT_BCON_CNTRL_REG         0x00000000
 131
 132 #define TU_TO_USEC(_tu)             ((_tu) << 10)
 133
 134 enum wireless_mode {
 135         ATH9K_MODE_11A = 0,
 136         ATH9K_MODE_11G,
 137         ATH9K_MODE_11NA_HT20,
 138         ATH9K_MODE_11NG_HT20,
 139         ATH9K_MODE_11NA_HT40PLUS,
 140         ATH9K_MODE_11NA_HT40MINUS,
 141         ATH9K_MODE_11NG_HT40PLUS,
 142         ATH9K_MODE_11NG_HT40MINUS,
 143         ATH9K_MODE_MAX,
 144 };
 145
 146 enum ath9k_ant_setting {
 147         ATH9K_ANT_VARIABLE = 0,
 148         ATH9K_ANT_FIXED_A,
 149         ATH9K_ANT_FIXED_B
 150 };
 151
 152 enum ath9k_hw_caps {
 153         ATH9K_HW_CAP_MIC_AESCCM                 = BIT(0),
 154         ATH9K_HW_CAP_MIC_CKIP                   = BIT(1),
 155         ATH9K_HW_CAP_MIC_TKIP                   = BIT(2),
 156         ATH9K_HW_CAP_CIPHER_AESCCM              = BIT(3),
 157         ATH9K_HW_CAP_CIPHER_CKIP                = BIT(4),
 158         ATH9K_HW_CAP_CIPHER_TKIP                = BIT(5),
 159         ATH9K_HW_CAP_VEOL                       = BIT(6),
 160         ATH9K_HW_CAP_BSSIDMASK                  = BIT(7),
 161         ATH9K_HW_CAP_MCAST_KEYSEARCH            = BIT(8),
 162         ATH9K_HW_CAP_HT                         = BIT(9),
 163         ATH9K_HW_CAP_GTT                        = BIT(10),
 164         ATH9K_HW_CAP_FASTCC                     = BIT(11),
 165         ATH9K_HW_CAP_RFSILENT                   = BIT(12),
 166         ATH9K_HW_CAP_CST                        = BIT(13),
 167         ATH9K_HW_CAP_ENHANCEDPM                 = BIT(14),
 168         ATH9K_HW_CAP_AUTOSLEEP                  = BIT(15),
 169         ATH9K_HW_CAP_4KB_SPLITTRANS             = BIT(16),
 170 };
 171
 172 enum ath9k_capability_type {
 173         ATH9K_CAP_CIPHER = 0,
 174         ATH9K_CAP_TKIP_MIC,
 175         ATH9K_CAP_TKIP_SPLIT,
 176         ATH9K_CAP_DIVERSITY,
 177         ATH9K_CAP_TXPOW,
 178         ATH9K_CAP_MCAST_KEYSRCH,
 179         ATH9K_CAP_DS
 180 };
 181
 182 struct ath9k_hw_capabilities {
 183         u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
 184         DECLARE_BITMAP(wireless_modes, ATH9K_MODE_MAX); /* ATH9K_MODE_* */
 185         u16 total_queues;
 186         u16 keycache_size;
 187         u16 low_5ghz_chan, high_5ghz_chan;
 188         u16 low_2ghz_chan, high_2ghz_chan;
 189         u16 rts_aggr_limit;
 190         u8 tx_chainmask;
 191         u8 rx_chainmask;
 192         u16 tx_triglevel_max;
 193         u16 reg_cap;
 194         u8 num_gpio_pins;
 195         u8 num_antcfg_2ghz;
 196         u8 num_antcfg_5ghz;
 197 };
 198
 199 struct ath9k_ops_config {
 200         int dma_beacon_response_time;
 201         int sw_beacon_response_time;
 202         int additional_swba_backoff;
 203         int ack_6mb;
 204         int cwm_ignore_extcca;
 205         u8 pcie_powersave_enable;
 206         u8 pcie_clock_req;
 207         u32 pcie_waen;
 208         u8 analog_shiftreg;
 209         u8 ht_enable;
 210         u32 ofdm_trig_low;
 211         u32 ofdm_trig_high;
 212         u32 cck_trig_high;
 213         u32 cck_trig_low;
 214         u32 enable_ani;
 215         enum ath9k_ant_setting diversity_control;
 216         u16 antenna_switch_swap;
 217         int serialize_regmode;
 218         bool intr_mitigation;
 219 #define SPUR_DISABLE            0
 220 #define SPUR_ENABLE_IOCTL       1
 221 #define SPUR_ENABLE_EEPROM      2
 222 #define AR_EEPROM_MODAL_SPURS   5
 223 #define AR_SPUR_5413_1          1640
 224 #define AR_SPUR_5413_2          1200
 225 #define AR_NO_SPUR              0x8000
 226 #define AR_BASE_FREQ_2GHZ       2300
 227 #define AR_BASE_FREQ_5GHZ       4900
 228 #define AR_SPUR_FEEQ_BOUND_HT40 19
 229 #define AR_SPUR_FEEQ_BOUND_HT20 10
 230         int spurmode;
 231         u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
 232 };
 233
 234 enum ath9k_int {
 235         ATH9K_INT_RX = 0x00000001,
 236         ATH9K_INT_RXDESC = 0x00000002,
 237         ATH9K_INT_RXNOFRM = 0x00000008,
 238         ATH9K_INT_RXEOL = 0x00000010,
 239         ATH9K_INT_RXORN = 0x00000020,
 240         ATH9K_INT_TX = 0x00000040,
 241         ATH9K_INT_TXDESC = 0x00000080,
 242         ATH9K_INT_TIM_TIMER = 0x00000100,
 243         ATH9K_INT_TXURN = 0x00000800,
 244         ATH9K_INT_MIB = 0x00001000,
 245         ATH9K_INT_RXPHY = 0x00004000,
 246         ATH9K_INT_RXKCM = 0x00008000,
 247         ATH9K_INT_SWBA = 0x00010000,
 248         ATH9K_INT_BMISS = 0x00040000,
 249         ATH9K_INT_BNR = 0x00100000,
 250         ATH9K_INT_TIM = 0x00200000,
 251         ATH9K_INT_DTIM = 0x00400000,
 252         ATH9K_INT_DTIMSYNC = 0x00800000,
 253         ATH9K_INT_GPIO = 0x01000000,
 254         ATH9K_INT_CABEND = 0x02000000,
 255         ATH9K_INT_TSFOOR = 0x04000000,
 256         ATH9K_INT_GENTIMER = 0x08000000,
 257         ATH9K_INT_CST = 0x10000000,
 258         ATH9K_INT_GTT = 0x20000000,
 259         ATH9K_INT_FATAL = 0x40000000,
 260         ATH9K_INT_GLOBAL = 0x80000000,
 261         ATH9K_INT_BMISC = ATH9K_INT_TIM |
 262                 ATH9K_INT_DTIM |
 263                 ATH9K_INT_DTIMSYNC |
 264                 ATH9K_INT_TSFOOR |
 265                 ATH9K_INT_CABEND,
 266         ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
 267                 ATH9K_INT_RXDESC |
 268                 ATH9K_INT_RXEOL |
 269                 ATH9K_INT_RXORN |
 270                 ATH9K_INT_TXURN |
 271                 ATH9K_INT_TXDESC |
 272                 ATH9K_INT_MIB |
 273                 ATH9K_INT_RXPHY |
 274                 ATH9K_INT_RXKCM |
 275                 ATH9K_INT_SWBA |
 276                 ATH9K_INT_BMISS |
 277                 ATH9K_INT_GPIO,
 278         ATH9K_INT_NOCARD = 0xffffffff
 279 };
 280
 281 #define CHANNEL_CW_INT    0x00002
 282 #define CHANNEL_CCK       0x00020
 283 #define CHANNEL_OFDM      0x00040
 284 #define CHANNEL_2GHZ      0x00080
 285 #define CHANNEL_5GHZ      0x00100
 286 #define CHANNEL_PASSIVE   0x00200
 287 #define CHANNEL_DYN       0x00400
 288 #define CHANNEL_HALF      0x04000
 289 #define CHANNEL_QUARTER   0x08000
 290 #define CHANNEL_HT20      0x10000
 291 #define CHANNEL_HT40PLUS  0x20000
 292 #define CHANNEL_HT40MINUS 0x40000
 293
 294 #define CHANNEL_A           (CHANNEL_5GHZ|CHANNEL_OFDM)
 295 #define CHANNEL_B           (CHANNEL_2GHZ|CHANNEL_CCK)
 296 #define CHANNEL_G           (CHANNEL_2GHZ|CHANNEL_OFDM)
 297 #define CHANNEL_G_HT20      (CHANNEL_2GHZ|CHANNEL_HT20)
 298 #define CHANNEL_A_HT20      (CHANNEL_5GHZ|CHANNEL_HT20)
 299 #define CHANNEL_G_HT40PLUS  (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
 300 #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
 301 #define CHANNEL_A_HT40PLUS  (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
 302 #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
 303 #define CHANNEL_ALL                             \
 304         (CHANNEL_OFDM|                          \
 305          CHANNEL_CCK|                           \
 306          CHANNEL_2GHZ |                         \
 307          CHANNEL_5GHZ |                         \
 308          CHANNEL_HT20 |                         \
 309          CHANNEL_HT40PLUS |                     \
 310          CHANNEL_HT40MINUS)
 311
 312 struct ath9k_channel {
 313         struct ieee80211_channel *chan;
 314         u16 channel;
 315         u32 channelFlags;
 316         u32 chanmode;
 317         int32_t CalValid;
 318         bool oneTimeCalsDone;
 319         int8_t iCoff;
 320         int8_t qCoff;
 321         int16_t rawNoiseFloor;
 322 };
 323
 324 #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
 325        (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
 326        (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
 327        (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
 328 #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
 329 #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
 330 #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
 331 #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
 332 #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
 333 #define IS_CHAN_A_5MHZ_SPACED(_c)                       \
 334         ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) &&  \
 335          (((_c)->channel % 20) != 0) &&                 \
 336          (((_c)->channel % 10) != 0))
 337
 338 /* These macros check chanmode and not channelFlags */
 339 #define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
 340 #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
 341                           ((_c)->chanmode == CHANNEL_G_HT20))
 342 #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) ||     \
 343                           ((_c)->chanmode == CHANNEL_A_HT40MINUS) ||    \
 344                           ((_c)->chanmode == CHANNEL_G_HT40PLUS) ||     \
 345                           ((_c)->chanmode == CHANNEL_G_HT40MINUS))
 346 #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
 347
 348 enum ath9k_power_mode {
 349         ATH9K_PM_AWAKE = 0,
 350         ATH9K_PM_FULL_SLEEP,
 351         ATH9K_PM_NETWORK_SLEEP,
 352         ATH9K_PM_UNDEFINED
 353 };
 354
 355 enum ath9k_tp_scale {
 356         ATH9K_TP_SCALE_MAX = 0,
 357         ATH9K_TP_SCALE_50,
 358         ATH9K_TP_SCALE_25,
 359         ATH9K_TP_SCALE_12,
 360         ATH9K_TP_SCALE_MIN
 361 };
 362
 363 enum ser_reg_mode {
 364         SER_REG_MODE_OFF = 0,
 365         SER_REG_MODE_ON = 1,
 366         SER_REG_MODE_AUTO = 2,
 367 };
 368
 369 struct ath9k_beacon_state {
 370         u32 bs_nexttbtt;
 371         u32 bs_nextdtim;
 372         u32 bs_intval;
 373 #define ATH9K_BEACON_PERIOD       0x0000ffff
 374 #define ATH9K_BEACON_ENA          0x00800000
 375 #define ATH9K_BEACON_RESET_TSF    0x01000000
 376 #define ATH9K_TSFOOR_THRESHOLD    0x00004240 /* 16k us */
 377         u32 bs_dtimperiod;
 378         u16 bs_cfpperiod;
 379         u16 bs_cfpmaxduration;
 380         u32 bs_cfpnext;
 381         u16 bs_timoffset;
 382         u16 bs_bmissthreshold;
 383         u32 bs_sleepduration;
 384         u32 bs_tsfoor_threshold;
 385 };
 386
 387 struct chan_centers {
 388         u16 synth_center;
 389         u16 ctl_center;
 390         u16 ext_center;
 391 };
 392
 393 enum {
 394         ATH9K_RESET_POWER_ON,
 395         ATH9K_RESET_WARM,
 396         ATH9K_RESET_COLD,
 397 };
 398
 399 struct ath9k_hw_version {
 400         u32 magic;
 401         u16 devid;
 402         u16 subvendorid;
 403         u32 macVersion;
 404         u16 macRev;
 405         u16 phyRev;
 406         u16 analog5GhzRev;
 407         u16 analog2GhzRev;
 408         u16 subsysid;
 409 };
 410
 411 /* Generic TSF timer definitions */
 412
 413 #define ATH_MAX_GEN_TIMER       16
 414
 415 #define AR_GENTMR_BIT(_index)   (1 << (_index))
 416
 417 /*
 418  * Using de Bruijin sequence to to look up 1's index in a 32 bit number
 419  * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001
 420  */
 421 #define debruijn32 0x077CB531UL
 422
 423 struct ath_gen_timer_configuration {
 424         u32 next_addr;
 425         u32 period_addr;
 426         u32 mode_addr;
 427         u32 mode_mask;
 428 };
 429
 430 struct ath_gen_timer {
 431         void (*trigger)(void *arg);
 432         void (*overflow)(void *arg);
 433         void *arg;
 434         u8 index;
 435 };
 436
 437 struct ath_gen_timer_table {
 438         u32 gen_timer_index[32];
 439         struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER];
 440         union {
 441                 unsigned long timer_bits;
 442                 u16 val;
 443         } timer_mask;
 444 };
 445
 446 struct ath_hw {
 447         struct ieee80211_hw *hw;
 448         struct ath_softc *ah_sc;
 449         struct ath_common common;
 450         struct ath9k_hw_version hw_version;
 451         struct ath9k_ops_config config;
 452         struct ath9k_hw_capabilities caps;
 453         struct ath9k_channel channels[38];
 454         struct ath9k_channel *curchan;
 455
 456         union {
 457                 struct ar5416_eeprom_def def;
 458                 struct ar5416_eeprom_4k map4k;
 459                 struct ar9287_eeprom map9287;
 460         } eeprom;
 461         const struct eeprom_ops *eep_ops;
 462         enum ath9k_eep_map eep_map;
 463
 464         bool sw_mgmt_crypto;
 465         bool is_pciexpress;
 466         u16 tx_trig_level;
 467         u16 rfsilent;
 468         u32 rfkill_gpio;
 469         u32 rfkill_polarity;
 470         u32 ah_flags;
 471
 472         bool htc_reset_init;
 473
 474         enum nl80211_iftype opmode;
 475         enum ath9k_power_mode power_mode;
 476
 477         struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
 478         struct ath9k_pacal_info pacal_info;
 479         struct ar5416Stats stats;
 480         struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
 481
 482         int16_t curchan_rad_index;
 483         u32 mask_reg;
 484         u32 txok_interrupt_mask;
 485         u32 txerr_interrupt_mask;
 486         u32 txdesc_interrupt_mask;
 487         u32 txeol_interrupt_mask;
 488         u32 txurn_interrupt_mask;
 489         bool chip_fullsleep;
 490         u32 atim_window;
 491
 492         /* Calibration */
 493         enum ath9k_cal_types supp_cals;
 494         struct ath9k_cal_list iq_caldata;
 495         struct ath9k_cal_list adcgain_caldata;
 496         struct ath9k_cal_list adcdc_calinitdata;
 497         struct ath9k_cal_list adcdc_caldata;
 498         struct ath9k_cal_list *cal_list;
 499         struct ath9k_cal_list *cal_list_last;
 500         struct ath9k_cal_list *cal_list_curr;
 501 #define totalPowerMeasI meas0.unsign
 502 #define totalPowerMeasQ meas1.unsign
 503 #define totalIqCorrMeas meas2.sign
 504 #define totalAdcIOddPhase  meas0.unsign
 505 #define totalAdcIEvenPhase meas1.unsign
 506 #define totalAdcQOddPhase  meas2.unsign
 507 #define totalAdcQEvenPhase meas3.unsign
 508 #define totalAdcDcOffsetIOddPhase  meas0.sign
 509 #define totalAdcDcOffsetIEvenPhase meas1.sign
 510 #define totalAdcDcOffsetQOddPhase  meas2.sign
 511 #define totalAdcDcOffsetQEvenPhase meas3.sign
 512         union {
 513                 u32 unsign[AR5416_MAX_CHAINS];
 514                 int32_t sign[AR5416_MAX_CHAINS];
 515         } meas0;
 516         union {
 517                 u32 unsign[AR5416_MAX_CHAINS];
 518                 int32_t sign[AR5416_MAX_CHAINS];
 519         } meas1;
 520         union {
 521                 u32 unsign[AR5416_MAX_CHAINS];
 522                 int32_t sign[AR5416_MAX_CHAINS];
 523         } meas2;
 524         union {
 525                 u32 unsign[AR5416_MAX_CHAINS];
 526                 int32_t sign[AR5416_MAX_CHAINS];
 527         } meas3;
 528         u16 cal_samples;
 529
 530         u32 sta_id1_defaults;
 531         u32 misc_mode;
 532         enum {
 533                 AUTO_32KHZ,
 534                 USE_32KHZ,
 535                 DONT_USE_32KHZ,
 536         } enable_32kHz_clock;
 537
 538         /* RF */
 539         u32 *analogBank0Data;
 540         u32 *analogBank1Data;
 541         u32 *analogBank2Data;
 542         u32 *analogBank3Data;
 543         u32 *analogBank6Data;
 544         u32 *analogBank6TPCData;
 545         u32 *analogBank7Data;
 546         u32 *addac5416_21;
 547         u32 *bank6Temp;
 548
 549         int16_t txpower_indexoffset;
 550         u32 beacon_interval;
 551         u32 slottime;
 552         u32 acktimeout;
 553         u32 ctstimeout;
 554         u32 globaltxtimeout;
 555         u8 gbeacon_rate;
 556
 557         /* ANI */
 558         u32 proc_phyerr;
 559         u32 aniperiod;
 560         struct ar5416AniState *curani;
 561         struct ar5416AniState ani[255];
 562         int totalSizeDesired[5];
 563         int coarse_high[5];
 564         int coarse_low[5];
 565         int firpwr[5];
 566         enum ath9k_ani_cmd ani_function;
 567
 568         /* Bluetooth coexistance */
 569         struct ath_btcoex_hw btcoex_hw;
 570
 571         u32 intr_txqs;
 572         u8 txchainmask;
 573         u8 rxchainmask;
 574
 575         u32 originalGain[22];
 576         int initPDADC;
 577         int PDADCdelta;
 578         u8 led_pin;
 579
 580         struct ar5416IniArray iniModes;
 581         struct ar5416IniArray iniCommon;
 582         struct ar5416IniArray iniBank0;
 583         struct ar5416IniArray iniBB_RfGain;
 584         struct ar5416IniArray iniBank1;
 585         struct ar5416IniArray iniBank2;
 586         struct ar5416IniArray iniBank3;
 587         struct ar5416IniArray iniBank6;
 588         struct ar5416IniArray iniBank6TPC;
 589         struct ar5416IniArray iniBank7;
 590         struct ar5416IniArray iniAddac;
 591         struct ar5416IniArray iniPcieSerdes;
 592         struct ar5416IniArray iniModesAdditional;
 593         struct ar5416IniArray iniModesRxGain;
 594         struct ar5416IniArray iniModesTxGain;
 595         struct ar5416IniArray iniCckfirNormal;
 596         struct ar5416IniArray iniCckfirJapan2484;
 597
 598         u32 intr_gen_timer_trigger;
 599         u32 intr_gen_timer_thresh;
 600         struct ath_gen_timer_table hw_gen_timers;
 601 };
 602
 603 static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
 604 {
 605         return &ah->common;
 606 }
 607
 608 static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)
 609 {
 610         return &(ath9k_hw_common(ah)->regulatory);
 611 }
 612
 613 /* Initialization, Detach, Reset */
 614 const char *ath9k_hw_probe(u16 vendorid, u16 devid);
 615 void ath9k_hw_detach(struct ath_hw *ah);
 616 int ath9k_hw_init(struct ath_hw *ah);
 617 void ath9k_hw_rf_free(struct ath_hw *ah);
 618 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
 619                    bool bChannelChange);
 620 void ath9k_hw_fill_cap_info(struct ath_hw *ah);
 621 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
 622                             u32 capability, u32 *result);
 623 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
 624                             u32 capability, u32 setting, int *status);
 625
 626 /* Key Cache Management */
 627 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry);
 628 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac);
 629 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
 630                                  const struct ath9k_keyval *k,
 631                                  const u8 *mac);
 632 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry);
 633
 634 /* GPIO / RFKILL / Antennae */
 635 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio);
 636 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio);
 637 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
 638                          u32 ah_signal_type);
 639 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
 640 u32 ath9k_hw_getdefantenna(struct ath_hw *ah);
 641 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
 642 bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
 643                                enum ath9k_ant_setting settings,
 644                                struct ath9k_channel *chan,
 645                                u8 *tx_chainmask, u8 *rx_chainmask,
 646                                u8 *antenna_cfgd);
 647
 648 /* General Operation */
 649 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
 650 u32 ath9k_hw_reverse_bits(u32 val, u32 n);
 651 bool ath9k_get_channel_edges(struct ath_hw *ah, u16 flags, u16 *low, u16 *high);
 652 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
 653                            const struct ath_rate_table *rates,
 654                            u32 frameLen, u16 rateix, bool shortPreamble);
 655 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
 656                                   struct ath9k_channel *chan,
 657                                   struct chan_centers *centers);
 658 u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
 659 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
 660 bool ath9k_hw_phy_disable(struct ath_hw *ah);
 661 bool ath9k_hw_disable(struct ath_hw *ah);
 662 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit);
 663 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac);
 664 void ath9k_hw_setopmode(struct ath_hw *ah);
 665 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
 666 void ath9k_hw_setbssidmask(struct ath_hw *ah);
 667 void ath9k_hw_write_associd(struct ath_hw *ah);
 668 u64 ath9k_hw_gettsf64(struct ath_hw *ah);
 669 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
 670 void ath9k_hw_reset_tsf(struct ath_hw *ah);
 671 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting);
 672 bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us);
 673 void ath9k_hw_set11nmac2040(struct ath_hw *ah);
 674 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
 675 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
 676                                     const struct ath9k_beacon_state *bs);
 677
 678 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
 679
 680 void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off);
 681
 682 /* Interrupt Handling */
 683 bool ath9k_hw_intrpend(struct ath_hw *ah);
 684 bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked);
 685 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints);
 686
 687 /* Generic hw timer primitives */
 688 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
 689                                           void (*trigger)(void *),
 690                                           void (*overflow)(void *),
 691                                           void *arg,
 692                                           u8 timer_index);
 693 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
 694                               struct ath_gen_timer *timer,
 695                               u32 timer_next,
 696                               u32 timer_period);
 697 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer);
 698
 699 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer);
 700 void ath_gen_timer_isr(struct ath_hw *hw);
 701 u32 ath9k_hw_gettsf32(struct ath_hw *ah);
 702
 703 #define ATH_PCIE_CAP_LINK_CTRL  0x70
 704 #define ATH_PCIE_CAP_LINK_L0S   1
 705 #define ATH_PCIE_CAP_LINK_L1    2
 706
 707 #endif