| blob | 16773aa395130732cbdd7292bfdc0a7f315c3135 |
1 config ARM
2 bool
3 default y
4 select ARCH_HAVE_CUSTOM_GPIO_H
5 select HAVE_AOUT
6 select HAVE_DMA_API_DEBUG
7 select HAVE_IDE if PCI || ISA || PCMCIA
8 select HAVE_DMA_ATTRS
9 select HAVE_DMA_CONTIGUOUS if (CPU_V6 || CPU_V6K || CPU_V7)
10 select HAVE_MEMBLOCK
11 select RTC_LIB
12 select SYS_SUPPORTS_APM_EMULATION
13 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
14 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
15 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
16 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
17 select HAVE_ARCH_KGDB
18 select HAVE_ARCH_TRACEHOOK
19 select HAVE_KPROBES if !XIP_KERNEL
20 select HAVE_KRETPROBES if (HAVE_KPROBES)
21 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
22 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
23 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
24 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
25 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
26 select HAVE_GENERIC_DMA_COHERENT
27 select HAVE_KERNEL_GZIP
28 select HAVE_KERNEL_LZO
29 select HAVE_KERNEL_LZMA
30 select HAVE_KERNEL_XZ
31 select HAVE_IRQ_WORK
32 select HAVE_PERF_EVENTS
33 select PERF_USE_VMALLOC
34 select HAVE_REGS_AND_STACK_ACCESS_API
35 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
36 select HAVE_C_RECORDMCOUNT
37 select HAVE_GENERIC_HARDIRQS
38 select HARDIRQS_SW_RESEND
39 select GENERIC_IRQ_PROBE
40 select GENERIC_IRQ_SHOW
41 select ARCH_WANT_IPC_PARSE_VERSION
42 select HARDIRQS_SW_RESEND
43 select CPU_PM if (SUSPEND || CPU_IDLE)
44 select GENERIC_PCI_IOMAP
45 select HAVE_BPF_JIT
46 select GENERIC_SMP_IDLE_THREAD
47 select KTIME_SCALAR
48 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
49 select GENERIC_STRNCPY_FROM_USER
50 select GENERIC_STRNLEN_USER
51 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN
52 help
53 The ARM series is a line of low-power-consumption RISC chip designs
54 licensed by ARM Ltd and targeted at embedded applications and
55 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
56 manufactured, but legacy ARM-based PC hardware remains popular in
57 Europe. There is an ARM Linux project with a web page at
58 <http://www.arm.linux.org.uk/>.
60 config ARM_HAS_SG_CHAIN
61 bool
63 config NEED_SG_DMA_LENGTH
64 bool
66 config ARM_DMA_USE_IOMMU
67 select NEED_SG_DMA_LENGTH
68 select ARM_HAS_SG_CHAIN
69 bool
71 config HAVE_PWM
72 bool
74 config MIGHT_HAVE_PCI
75 bool
77 config SYS_SUPPORTS_APM_EMULATION
78 bool
80 config GENERIC_GPIO
81 bool
83 config HAVE_TCM
84 bool
85 select GENERIC_ALLOCATOR
87 config HAVE_PROC_CPU
88 bool
90 config NO_IOPORT
91 bool
93 config EISA
94 bool
95 ---help---
96 The Extended Industry Standard Architecture (EISA) bus was
97 developed as an open alternative to the IBM MicroChannel bus.
99 The EISA bus provided some of the features of the IBM MicroChannel
100 bus while maintaining backward compatibility with cards made for
101 the older ISA bus. The EISA bus saw limited use between 1988 and
102 1995 when it was made obsolete by the PCI bus.
104 Say Y here if you are building a kernel for an EISA-based machine.
106 Otherwise, say N.
108 config SBUS
109 bool
111 config STACKTRACE_SUPPORT
112 bool
113 default y
115 config HAVE_LATENCYTOP_SUPPORT
116 bool
117 depends on !SMP
118 default y
120 config LOCKDEP_SUPPORT
121 bool
122 default y
124 config TRACE_IRQFLAGS_SUPPORT
125 bool
126 default y
128 config RWSEM_GENERIC_SPINLOCK
129 bool
130 default y
132 config RWSEM_XCHGADD_ALGORITHM
133 bool
135 config ARCH_HAS_ILOG2_U32
136 bool
138 config ARCH_HAS_ILOG2_U64
139 bool
141 config ARCH_HAS_CPUFREQ
142 bool
143 help
144 Internal node to signify that the ARCH has CPUFREQ support
145 and that the relevant menu configurations are displayed for
146 it.
148 config GENERIC_HWEIGHT
149 bool
150 default y
152 config GENERIC_CALIBRATE_DELAY
153 bool
154 default y
156 config ARCH_MAY_HAVE_PC_FDC
157 bool
159 config ZONE_DMA
160 bool
162 config NEED_DMA_MAP_STATE
163 def_bool y
165 config ARCH_HAS_DMA_SET_COHERENT_MASK
166 bool
168 config GENERIC_ISA_DMA
169 bool
171 config FIQ
172 bool
174 config NEED_RET_TO_USER
175 bool
177 config ARCH_MTD_XIP
178 bool
180 config VECTORS_BASE
181 hex
182 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
183 default DRAM_BASE if REMAP_VECTORS_TO_RAM
184 default 0x00000000
185 help
186 The base address of exception vectors.
188 config ARM_PATCH_PHYS_VIRT
189 bool "Patch physical to virtual translations at runtime" if EMBEDDED
190 default y
191 depends on !XIP_KERNEL && MMU
192 depends on !ARCH_REALVIEW || !SPARSEMEM
193 help
194 Patch phys-to-virt and virt-to-phys translation functions at
195 boot and module load time according to the position of the
196 kernel in system memory.
198 This can only be used with non-XIP MMU kernels where the base
199 of physical memory is at a 16MB boundary.
201 Only disable this option if you know that you do not require
202 this feature (eg, building a kernel for a single machine) and
203 you need to shrink the kernel to the minimal size.
205 config NEED_MACH_GPIO_H
206 bool
207 help
208 Select this when mach/gpio.h is required to provide special
209 definitions for this platform. The need for mach/gpio.h should
210 be avoided when possible.
212 config NEED_MACH_IO_H
213 bool
214 help
215 Select this when mach/io.h is required to provide special
216 definitions for this platform. The need for mach/io.h should
217 be avoided when possible.
219 config NEED_MACH_MEMORY_H
220 bool
221 help
222 Select this when mach/memory.h is required to provide special
223 definitions for this platform. The need for mach/memory.h should
224 be avoided when possible.
226 config PHYS_OFFSET
227 hex "Physical address of main memory" if MMU
228 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
229 default DRAM_BASE if !MMU
230 help
231 Please provide the physical address corresponding to the
232 location of main memory in your system.
234 config GENERIC_BUG
235 def_bool y
236 depends on BUG
238 source "init/Kconfig"
240 source "kernel/Kconfig.freezer"
242 menu "System Type"
244 config MMU
245 bool "MMU-based Paged Memory Management Support"
246 default y
247 help
248 Select if you want MMU-based virtualised addressing space
249 support by paged memory management. If unsure, say 'Y'.
251 #
252 # The "ARM system type" choice list is ordered alphabetically by option
253 # text. Please add new entries in the option alphabetic order.
254 #
255 choice
256 prompt "ARM system type"
257 default ARCH_MULTIPLATFORM
259 config ARCH_MULTIPLATFORM
260 bool "Allow multiple platforms to be selected"
261 select ARM_PATCH_PHYS_VIRT
262 select AUTO_ZRELADDR
263 select COMMON_CLK
264 select MULTI_IRQ_HANDLER
265 select SPARSE_IRQ
266 select USE_OF
267 depends on MMU
269 config ARCH_INTEGRATOR
270 bool "ARM Ltd. Integrator family"
271 select ARM_AMBA
272 select ARCH_HAS_CPUFREQ
273 select COMMON_CLK
274 select CLK_VERSATILE
275 select HAVE_TCM
276 select ICST
277 select GENERIC_CLOCKEVENTS
278 select PLAT_VERSATILE
279 select PLAT_VERSATILE_FPGA_IRQ
280 select NEED_MACH_IO_H
281 select NEED_MACH_MEMORY_H
282 select SPARSE_IRQ
283 select MULTI_IRQ_HANDLER
284 help
285 Support for ARM's Integrator platform.
287 config ARCH_REALVIEW
288 bool "ARM Ltd. RealView family"
289 select ARM_AMBA
290 select CLKDEV_LOOKUP
291 select HAVE_MACH_CLKDEV
292 select ICST
293 select GENERIC_CLOCKEVENTS
294 select ARCH_WANT_OPTIONAL_GPIOLIB
295 select PLAT_VERSATILE
296 select PLAT_VERSATILE_CLOCK
297 select PLAT_VERSATILE_CLCD
298 select ARM_TIMER_SP804
299 select GPIO_PL061 if GPIOLIB
300 select NEED_MACH_MEMORY_H
301 help
302 This enables support for ARM Ltd RealView boards.
304 config ARCH_VERSATILE
305 bool "ARM Ltd. Versatile family"
306 select ARM_AMBA
307 select ARM_VIC
308 select CLKDEV_LOOKUP
309 select HAVE_MACH_CLKDEV
310 select ICST
311 select GENERIC_CLOCKEVENTS
312 select ARCH_WANT_OPTIONAL_GPIOLIB
313 select NEED_MACH_IO_H if PCI
314 select PLAT_VERSATILE
315 select PLAT_VERSATILE_CLOCK
316 select PLAT_VERSATILE_CLCD
317 select PLAT_VERSATILE_FPGA_IRQ
318 select ARM_TIMER_SP804
319 help
320 This enables support for ARM Ltd Versatile board.
322 config ARCH_AT91
323 bool "Atmel AT91"
324 select ARCH_REQUIRE_GPIOLIB
325 select HAVE_CLK
326 select CLKDEV_LOOKUP
327 select IRQ_DOMAIN
328 select NEED_MACH_GPIO_H
329 select NEED_MACH_IO_H if PCCARD
330 help
331 This enables support for systems based on Atmel
332 AT91RM9200 and AT91SAM9* processors.
334 config ARCH_BCMRING
335 bool "Broadcom BCMRING"
336 depends on MMU
337 select CPU_V6
338 select ARM_AMBA
339 select ARM_TIMER_SP804
340 select CLKDEV_LOOKUP
341 select GENERIC_CLOCKEVENTS
342 select ARCH_WANT_OPTIONAL_GPIOLIB
343 help
344 Support for Broadcom's BCMRing platform.
346 config ARCH_CLPS711X
347 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
348 select CPU_ARM720T
349 select ARCH_USES_GETTIMEOFFSET
350 select NEED_MACH_MEMORY_H
351 help
352 Support for Cirrus Logic 711x/721x/731x based boards.
354 config ARCH_CNS3XXX
355 bool "Cavium Networks CNS3XXX family"
356 select CPU_V6K
357 select GENERIC_CLOCKEVENTS
358 select ARM_GIC
359 select MIGHT_HAVE_CACHE_L2X0
360 select MIGHT_HAVE_PCI
361 select PCI_DOMAINS if PCI
362 help
363 Support for Cavium Networks CNS3XXX platform.
365 config ARCH_GEMINI
366 bool "Cortina Systems Gemini"
367 select CPU_FA526
368 select ARCH_REQUIRE_GPIOLIB
369 select ARCH_USES_GETTIMEOFFSET
370 help
371 Support for the Cortina Systems Gemini family SoCs
373 config ARCH_PRIMA2
374 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
375 select CPU_V7
376 select NO_IOPORT
377 select ARCH_REQUIRE_GPIOLIB
378 select GENERIC_CLOCKEVENTS
379 select CLKDEV_LOOKUP
380 select GENERIC_IRQ_CHIP
381 select MIGHT_HAVE_CACHE_L2X0
382 select PINCTRL
383 select PINCTRL_SIRF
384 select USE_OF
385 select ZONE_DMA
386 help
387 Support for CSR SiRFSoC ARM Cortex A9 Platform
389 config ARCH_EBSA110
390 bool "EBSA-110"
391 select CPU_SA110
392 select ISA
393 select NO_IOPORT
394 select ARCH_USES_GETTIMEOFFSET
395 select NEED_MACH_IO_H
396 select NEED_MACH_MEMORY_H
397 help
398 This is an evaluation board for the StrongARM processor available
399 from Digital. It has limited hardware on-board, including an
400 Ethernet interface, two PCMCIA sockets, two serial ports and a
401 parallel port.
403 config ARCH_EP93XX
404 bool "EP93xx-based"
405 select CPU_ARM920T
406 select ARM_AMBA
407 select ARM_VIC
408 select CLKDEV_LOOKUP
409 select ARCH_REQUIRE_GPIOLIB
410 select ARCH_HAS_HOLES_MEMORYMODEL
411 select ARCH_USES_GETTIMEOFFSET
412 select NEED_MACH_MEMORY_H
413 help
414 This enables support for the Cirrus EP93xx series of CPUs.
416 config ARCH_FOOTBRIDGE
417 bool "FootBridge"
418 select CPU_SA110
419 select FOOTBRIDGE
420 select GENERIC_CLOCKEVENTS
421 select HAVE_IDE
422 select NEED_MACH_IO_H
423 select NEED_MACH_MEMORY_H
424 help
425 Support for systems based on the DC21285 companion chip
426 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
428 config ARCH_MXC
429 bool "Freescale MXC/iMX-based"
430 select GENERIC_CLOCKEVENTS
431 select ARCH_REQUIRE_GPIOLIB
432 select CLKDEV_LOOKUP
433 select CLKSRC_MMIO
434 select GENERIC_IRQ_CHIP
435 select MULTI_IRQ_HANDLER
436 select SPARSE_IRQ
437 select USE_OF
438 help
439 Support for Freescale MXC/iMX-based family of processors
441 config ARCH_MXS
442 bool "Freescale MXS-based"
443 select GENERIC_CLOCKEVENTS
444 select ARCH_REQUIRE_GPIOLIB
445 select CLKDEV_LOOKUP
446 select CLKSRC_MMIO
447 select COMMON_CLK
448 select HAVE_CLK_PREPARE
449 select PINCTRL
450 select USE_OF
451 help
452 Support for Freescale MXS-based family of processors
454 config ARCH_NETX
455 bool "Hilscher NetX based"
456 select CLKSRC_MMIO
457 select CPU_ARM926T
458 select ARM_VIC
459 select GENERIC_CLOCKEVENTS
460 help
461 This enables support for systems based on the Hilscher NetX Soc
463 config ARCH_H720X
464 bool "Hynix HMS720x-based"
465 select CPU_ARM720T
466 select ISA_DMA_API
467 select ARCH_USES_GETTIMEOFFSET
468 help
469 This enables support for systems based on the Hynix HMS720x
471 config ARCH_IOP13XX
472 bool "IOP13xx-based"
473 depends on MMU
474 select CPU_XSC3
475 select PLAT_IOP
476 select PCI
477 select ARCH_SUPPORTS_MSI
478 select VMSPLIT_1G
479 select NEED_MACH_IO_H
480 select NEED_MACH_MEMORY_H
481 select NEED_RET_TO_USER
482 help
483 Support for Intel's IOP13XX (XScale) family of processors.
485 config ARCH_IOP32X
486 bool "IOP32x-based"
487 depends on MMU
488 select CPU_XSCALE
489 select NEED_MACH_GPIO_H
490 select NEED_MACH_IO_H
491 select NEED_RET_TO_USER
492 select PLAT_IOP
493 select PCI
494 select ARCH_REQUIRE_GPIOLIB
495 help
496 Support for Intel's 80219 and IOP32X (XScale) family of
497 processors.
499 config ARCH_IOP33X
500 bool "IOP33x-based"
501 depends on MMU
502 select CPU_XSCALE
503 select NEED_MACH_GPIO_H
504 select NEED_MACH_IO_H
505 select NEED_RET_TO_USER
506 select PLAT_IOP
507 select PCI
508 select ARCH_REQUIRE_GPIOLIB
509 help
510 Support for Intel's IOP33X (XScale) family of processors.
512 config ARCH_IXP4XX
513 bool "IXP4xx-based"
514 depends on MMU
515 select ARCH_HAS_DMA_SET_COHERENT_MASK
516 select CLKSRC_MMIO
517 select CPU_XSCALE
518 select ARCH_REQUIRE_GPIOLIB
519 select GENERIC_CLOCKEVENTS
520 select MIGHT_HAVE_PCI
521 select NEED_MACH_IO_H
522 select DMABOUNCE if PCI
523 help
524 Support for Intel's IXP4XX (XScale) family of processors.
526 config ARCH_DOVE
527 bool "Marvell Dove"
528 select CPU_V7
529 select PCI
530 select ARCH_REQUIRE_GPIOLIB
531 select GENERIC_CLOCKEVENTS
532 select NEED_MACH_IO_H
533 select PLAT_ORION
534 help
535 Support for the Marvell Dove SoC 88AP510
537 config ARCH_KIRKWOOD
538 bool "Marvell Kirkwood"
539 select CPU_FEROCEON
540 select PCI
541 select ARCH_REQUIRE_GPIOLIB
542 select GENERIC_CLOCKEVENTS
543 select NEED_MACH_IO_H
544 select PLAT_ORION
545 help
546 Support for the following Marvell Kirkwood series SoCs:
547 88F6180, 88F6192 and 88F6281.
549 config ARCH_LPC32XX
550 bool "NXP LPC32XX"
551 select CLKSRC_MMIO
552 select CPU_ARM926T
553 select ARCH_REQUIRE_GPIOLIB
554 select HAVE_IDE
555 select ARM_AMBA
556 select USB_ARCH_HAS_OHCI
557 select CLKDEV_LOOKUP
558 select GENERIC_CLOCKEVENTS
559 select USE_OF
560 select HAVE_PWM
561 help
562 Support for the NXP LPC32XX family of processors
564 config ARCH_MV78XX0
565 bool "Marvell MV78xx0"
566 select CPU_FEROCEON
567 select PCI
568 select ARCH_REQUIRE_GPIOLIB
569 select GENERIC_CLOCKEVENTS
570 select NEED_MACH_IO_H
571 select PLAT_ORION
572 help
573 Support for the following Marvell MV78xx0 series SoCs:
574 MV781x0, MV782x0.
576 config ARCH_ORION5X
577 bool "Marvell Orion"
578 depends on MMU
579 select CPU_FEROCEON
580 select PCI
581 select ARCH_REQUIRE_GPIOLIB
582 select GENERIC_CLOCKEVENTS
583 select NEED_MACH_IO_H
584 select PLAT_ORION
585 help
586 Support for the following Marvell Orion 5x series SoCs:
587 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
588 Orion-2 (5281), Orion-1-90 (6183).
590 config ARCH_MMP
591 bool "Marvell PXA168/910/MMP2"
592 depends on MMU
593 select ARCH_REQUIRE_GPIOLIB
594 select CLKDEV_LOOKUP
595 select GENERIC_CLOCKEVENTS
596 select GPIO_PXA
597 select IRQ_DOMAIN
598 select PLAT_PXA
599 select SPARSE_IRQ
600 select GENERIC_ALLOCATOR
601 select NEED_MACH_GPIO_H
602 help
603 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
605 config ARCH_KS8695
606 bool "Micrel/Kendin KS8695"
607 select CPU_ARM922T
608 select ARCH_REQUIRE_GPIOLIB
609 select ARCH_USES_GETTIMEOFFSET
610 select NEED_MACH_MEMORY_H
611 help
612 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
613 System-on-Chip devices.
615 config ARCH_W90X900
616 bool "Nuvoton W90X900 CPU"
617 select CPU_ARM926T
618 select ARCH_REQUIRE_GPIOLIB
619 select CLKDEV_LOOKUP
620 select CLKSRC_MMIO
621 select GENERIC_CLOCKEVENTS
622 help
623 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
624 At present, the w90x900 has been renamed nuc900, regarding
625 the ARM series product line, you can login the following
626 link address to know more.
628 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
629 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
631 config ARCH_TEGRA
632 bool "NVIDIA Tegra"
633 select CLKDEV_LOOKUP
634 select CLKSRC_MMIO
635 select GENERIC_CLOCKEVENTS
636 select GENERIC_GPIO
637 select HAVE_CLK
638 select HAVE_SMP
639 select MIGHT_HAVE_CACHE_L2X0
640 select NEED_MACH_IO_H if PCI
641 select ARCH_HAS_CPUFREQ
642 select USE_OF
643 help
644 This enables support for NVIDIA Tegra based systems (Tegra APX,
645 Tegra 6xx and Tegra 2 series).
647 config ARCH_PNX4008
648 bool "Philips Nexperia PNX4008 Mobile"
649 select CPU_ARM926T
650 select CLKDEV_LOOKUP
651 select ARCH_USES_GETTIMEOFFSET
652 help
653 This enables support for Philips PNX4008 mobile platform.
655 config ARCH_PXA
656 bool "PXA2xx/PXA3xx-based"
657 depends on MMU
658 select ARCH_MTD_XIP
659 select ARCH_HAS_CPUFREQ
660 select CLKDEV_LOOKUP
661 select CLKSRC_MMIO
662 select ARCH_REQUIRE_GPIOLIB
663 select GENERIC_CLOCKEVENTS
664 select GPIO_PXA
665 select PLAT_PXA
666 select SPARSE_IRQ
667 select AUTO_ZRELADDR
668 select MULTI_IRQ_HANDLER
669 select ARM_CPU_SUSPEND if PM
670 select HAVE_IDE
671 select NEED_MACH_GPIO_H
672 help
673 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
675 config ARCH_MSM
676 bool "Qualcomm MSM"
677 select HAVE_CLK
678 select GENERIC_CLOCKEVENTS
679 select ARCH_REQUIRE_GPIOLIB
680 select CLKDEV_LOOKUP
681 help
682 Support for Qualcomm MSM/QSD based systems. This runs on the
683 apps processor of the MSM/QSD and depends on a shared memory
684 interface to the modem processor which runs the baseband
685 stack and controls some vital subsystems
686 (clock and power control, etc).
688 config ARCH_SHMOBILE
689 bool "Renesas SH-Mobile / R-Mobile"
690 select HAVE_CLK
691 select CLKDEV_LOOKUP
692 select HAVE_MACH_CLKDEV
693 select HAVE_SMP
694 select GENERIC_CLOCKEVENTS
695 select MIGHT_HAVE_CACHE_L2X0
696 select NO_IOPORT
697 select SPARSE_IRQ
698 select MULTI_IRQ_HANDLER
699 select PM_GENERIC_DOMAINS if PM
700 select NEED_MACH_MEMORY_H
701 help
702 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
704 config ARCH_RPC
705 bool "RiscPC"
706 select ARCH_ACORN
707 select FIQ
708 select ARCH_MAY_HAVE_PC_FDC
709 select HAVE_PATA_PLATFORM
710 select ISA_DMA_API
711 select NO_IOPORT
712 select ARCH_SPARSEMEM_ENABLE
713 select ARCH_USES_GETTIMEOFFSET
714 select HAVE_IDE
715 select NEED_MACH_IO_H
716 select NEED_MACH_MEMORY_H
717 help
718 On the Acorn Risc-PC, Linux can support the internal IDE disk and
719 CD-ROM interface, serial and parallel port, and the floppy drive.
721 config ARCH_SA1100
722 bool "SA1100-based"
723 select CLKSRC_MMIO
724 select CPU_SA1100
725 select ISA
726 select ARCH_SPARSEMEM_ENABLE
727 select ARCH_MTD_XIP
728 select ARCH_HAS_CPUFREQ
729 select CPU_FREQ
730 select GENERIC_CLOCKEVENTS
731 select CLKDEV_LOOKUP
732 select ARCH_REQUIRE_GPIOLIB
733 select HAVE_IDE
734 select NEED_MACH_GPIO_H
735 select NEED_MACH_MEMORY_H
736 select SPARSE_IRQ
737 help
738 Support for StrongARM 11x0 based boards.
740 config ARCH_S3C24XX
741 bool "Samsung S3C24XX SoCs"
742 select GENERIC_GPIO
743 select ARCH_HAS_CPUFREQ
744 select HAVE_CLK
745 select CLKDEV_LOOKUP
746 select ARCH_USES_GETTIMEOFFSET
747 select HAVE_S3C2410_I2C if I2C
748 select HAVE_S3C_RTC if RTC_CLASS
749 select HAVE_S3C2410_WATCHDOG if WATCHDOG
750 select NEED_MACH_GPIO_H
751 select NEED_MACH_IO_H
752 help
753 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
754 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
755 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
756 Samsung SMDK2410 development board (and derivatives).
758 config ARCH_S3C64XX
759 bool "Samsung S3C64XX"
760 select PLAT_SAMSUNG
761 select CPU_V6
762 select ARM_VIC
763 select HAVE_CLK
764 select HAVE_TCM
765 select CLKDEV_LOOKUP
766 select NO_IOPORT
767 select ARCH_USES_GETTIMEOFFSET
768 select ARCH_HAS_CPUFREQ
769 select ARCH_REQUIRE_GPIOLIB
770 select SAMSUNG_CLKSRC
771 select SAMSUNG_IRQ_VIC_TIMER
772 select S3C_GPIO_TRACK
773 select S3C_DEV_NAND
774 select USB_ARCH_HAS_OHCI
775 select SAMSUNG_GPIOLIB_4BIT
776 select HAVE_S3C2410_I2C if I2C
777 select HAVE_S3C2410_WATCHDOG if WATCHDOG
778 select NEED_MACH_GPIO_H
779 help
780 Samsung S3C64XX series based systems
782 config ARCH_S5P64X0
783 bool "Samsung S5P6440 S5P6450"
784 select CPU_V6
785 select GENERIC_GPIO
786 select HAVE_CLK
787 select CLKDEV_LOOKUP
788 select CLKSRC_MMIO
789 select HAVE_S3C2410_WATCHDOG if WATCHDOG
790 select GENERIC_CLOCKEVENTS
791 select HAVE_S3C2410_I2C if I2C
792 select HAVE_S3C_RTC if RTC_CLASS
793 select NEED_MACH_GPIO_H
794 help
795 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
796 SMDK6450.
798 config ARCH_S5PC100
799 bool "Samsung S5PC100"
800 select GENERIC_GPIO
801 select HAVE_CLK
802 select CLKDEV_LOOKUP
803 select CPU_V7
804 select ARCH_USES_GETTIMEOFFSET
805 select HAVE_S3C2410_I2C if I2C
806 select HAVE_S3C_RTC if RTC_CLASS
807 select HAVE_S3C2410_WATCHDOG if WATCHDOG
808 select NEED_MACH_GPIO_H
809 help
810 Samsung S5PC100 series based systems
812 config ARCH_S5PV210
813 bool "Samsung S5PV210/S5PC110"
814 select CPU_V7
815 select ARCH_SPARSEMEM_ENABLE
816 select ARCH_HAS_HOLES_MEMORYMODEL
817 select GENERIC_GPIO
818 select HAVE_CLK
819 select CLKDEV_LOOKUP
820 select CLKSRC_MMIO
821 select ARCH_HAS_CPUFREQ
822 select GENERIC_CLOCKEVENTS
823 select HAVE_S3C2410_I2C if I2C
824 select HAVE_S3C_RTC if RTC_CLASS
825 select HAVE_S3C2410_WATCHDOG if WATCHDOG
826 select NEED_MACH_GPIO_H
827 select NEED_MACH_MEMORY_H
828 help
829 Samsung S5PV210/S5PC110 series based systems
831 config ARCH_EXYNOS
832 bool "SAMSUNG EXYNOS"
833 select CPU_V7
834 select ARCH_SPARSEMEM_ENABLE
835 select ARCH_HAS_HOLES_MEMORYMODEL
836 select GENERIC_GPIO
837 select HAVE_CLK
838 select CLKDEV_LOOKUP
839 select ARCH_HAS_CPUFREQ
840 select GENERIC_CLOCKEVENTS
841 select HAVE_S3C_RTC if RTC_CLASS
842 select HAVE_S3C2410_I2C if I2C
843 select HAVE_S3C2410_WATCHDOG if WATCHDOG
844 select NEED_MACH_GPIO_H
845 select NEED_MACH_MEMORY_H
846 help
847 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
849 config ARCH_SHARK
850 bool "Shark"
851 select CPU_SA110
852 select ISA
853 select ISA_DMA
854 select ZONE_DMA
855 select PCI
856 select ARCH_USES_GETTIMEOFFSET
857 select NEED_MACH_MEMORY_H
858 select NEED_MACH_IO_H
859 help
860 Support for the StrongARM based Digital DNARD machine, also known
861 as "Shark" (<http://www.shark-linux.de/shark.html>).
863 config ARCH_U300
864 bool "ST-Ericsson U300 Series"
865 depends on MMU
866 select CLKSRC_MMIO
867 select CPU_ARM926T
868 select HAVE_TCM
869 select ARM_AMBA
870 select ARM_PATCH_PHYS_VIRT
871 select ARM_VIC
872 select GENERIC_CLOCKEVENTS
873 select CLKDEV_LOOKUP
874 select COMMON_CLK
875 select GENERIC_GPIO
876 select ARCH_REQUIRE_GPIOLIB
877 help
878 Support for ST-Ericsson U300 series mobile platforms.
880 config ARCH_U8500
881 bool "ST-Ericsson U8500 Series"
882 depends on MMU
883 select CPU_V7
884 select ARM_AMBA
885 select GENERIC_CLOCKEVENTS
886 select CLKDEV_LOOKUP
887 select ARCH_REQUIRE_GPIOLIB
888 select ARCH_HAS_CPUFREQ
889 select HAVE_SMP
890 select MIGHT_HAVE_CACHE_L2X0
891 help
892 Support for ST-Ericsson's Ux500 architecture
894 config ARCH_NOMADIK
895 bool "STMicroelectronics Nomadik"
896 select ARM_AMBA
897 select ARM_VIC
898 select CPU_ARM926T
899 select COMMON_CLK
900 select GENERIC_CLOCKEVENTS
901 select PINCTRL
902 select MIGHT_HAVE_CACHE_L2X0
903 select ARCH_REQUIRE_GPIOLIB
904 help
905 Support for the Nomadik platform by ST-Ericsson
907 config ARCH_DAVINCI
908 bool "TI DaVinci"
909 select GENERIC_CLOCKEVENTS
910 select ARCH_REQUIRE_GPIOLIB
911 select ZONE_DMA
912 select HAVE_IDE
913 select CLKDEV_LOOKUP
914 select GENERIC_ALLOCATOR
915 select GENERIC_IRQ_CHIP
916 select ARCH_HAS_HOLES_MEMORYMODEL
917 select NEED_MACH_GPIO_H
918 help
919 Support for TI's DaVinci platform.
921 config ARCH_OMAP
922 bool "TI OMAP"
923 depends on MMU
924 select HAVE_CLK
925 select ARCH_REQUIRE_GPIOLIB
926 select ARCH_HAS_CPUFREQ
927 select CLKSRC_MMIO
928 select GENERIC_CLOCKEVENTS
929 select ARCH_HAS_HOLES_MEMORYMODEL
930 select NEED_MACH_GPIO_H
931 help
932 Support for TI's OMAP platform (OMAP1/2/3/4).
934 config PLAT_SPEAR
935 bool "ST SPEAr"
936 select ARM_AMBA
937 select ARCH_REQUIRE_GPIOLIB
938 select CLKDEV_LOOKUP
939 select COMMON_CLK
940 select CLKSRC_MMIO
941 select GENERIC_CLOCKEVENTS
942 select HAVE_CLK
943 help
944 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
946 config ARCH_VT8500
947 bool "VIA/WonderMedia 85xx"
948 select CPU_ARM926T
949 select GENERIC_GPIO
950 select ARCH_HAS_CPUFREQ
951 select GENERIC_CLOCKEVENTS
952 select ARCH_REQUIRE_GPIOLIB
953 help
954 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
956 config ARCH_ZYNQ
957 bool "Xilinx Zynq ARM Cortex A9 Platform"
958 select CPU_V7
959 select GENERIC_CLOCKEVENTS
960 select CLKDEV_LOOKUP
961 select ARM_GIC
962 select ARM_AMBA
963 select ICST
964 select MIGHT_HAVE_CACHE_L2X0
965 select USE_OF
966 help
967 Support for Xilinx Zynq ARM Cortex A9 Platform
968 endchoice
970 menu "Multiple platform selection"
971 depends on ARCH_MULTIPLATFORM
973 comment "CPU Core family selection"
975 config ARCH_MULTI_V4
976 bool "ARMv4 based platforms (FA526, StrongARM)"
977 select ARCH_MULTI_V4_V5
978 depends on !ARCH_MULTI_V6_V7
980 config ARCH_MULTI_V4T
981 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
982 select ARCH_MULTI_V4_V5
983 depends on !ARCH_MULTI_V6_V7
985 config ARCH_MULTI_V5
986 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
987 select ARCH_MULTI_V4_V5
988 depends on !ARCH_MULTI_V6_V7
990 config ARCH_MULTI_V4_V5
991 bool
993 config ARCH_MULTI_V6
994 bool "ARMv6 based platforms (ARM11, Scorpion, ...)"
995 select CPU_V6
996 select ARCH_MULTI_V6_V7
998 config ARCH_MULTI_V7
999 bool "ARMv7 based platforms (Cortex-A, PJ4, Krait)"
1000 select CPU_V7
1001 select ARCH_VEXPRESS
1002 default y
1003 select ARCH_MULTI_V6_V7
1005 config ARCH_MULTI_V6_V7
1006 bool
1008 config ARCH_MULTI_CPU_AUTO
1009 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
1010 select ARCH_MULTI_V5
1012 endmenu
1014 #
1015 # This is sorted alphabetically by mach-* pathname. However, plat-*
1016 # Kconfigs may be included either alphabetically (according to the
1017 # plat- suffix) or along side the corresponding mach-* source.
1018 #
1019 source "arch/arm/mach-mvebu/Kconfig"
1021 source "arch/arm/mach-at91/Kconfig"
1023 source "arch/arm/mach-bcmring/Kconfig"
1025 source "arch/arm/mach-clps711x/Kconfig"
1027 source "arch/arm/mach-cns3xxx/Kconfig"
1029 source "arch/arm/mach-davinci/Kconfig"
1031 source "arch/arm/mach-dove/Kconfig"
1033 source "arch/arm/mach-ep93xx/Kconfig"
1035 source "arch/arm/mach-footbridge/Kconfig"
1037 source "arch/arm/mach-gemini/Kconfig"
1039 source "arch/arm/mach-h720x/Kconfig"
1041 source "arch/arm/mach-highbank/Kconfig"
1043 source "arch/arm/mach-integrator/Kconfig"
1045 source "arch/arm/mach-iop32x/Kconfig"
1047 source "arch/arm/mach-iop33x/Kconfig"
1049 source "arch/arm/mach-iop13xx/Kconfig"
1051 source "arch/arm/mach-ixp4xx/Kconfig"
1053 source "arch/arm/mach-kirkwood/Kconfig"
1055 source "arch/arm/mach-ks8695/Kconfig"
1057 source "arch/arm/mach-msm/Kconfig"
1059 source "arch/arm/mach-mv78xx0/Kconfig"
1061 source "arch/arm/plat-mxc/Kconfig"
1063 source "arch/arm/mach-mxs/Kconfig"
1065 source "arch/arm/mach-netx/Kconfig"
1067 source "arch/arm/mach-nomadik/Kconfig"
1068 source "arch/arm/plat-nomadik/Kconfig"
1070 source "arch/arm/plat-omap/Kconfig"
1072 source "arch/arm/mach-omap1/Kconfig"
1074 source "arch/arm/mach-omap2/Kconfig"
1076 source "arch/arm/mach-orion5x/Kconfig"
1078 source "arch/arm/mach-picoxcell/Kconfig"
1080 source "arch/arm/mach-pxa/Kconfig"
1081 source "arch/arm/plat-pxa/Kconfig"
1083 source "arch/arm/mach-mmp/Kconfig"
1085 source "arch/arm/mach-realview/Kconfig"
1087 source "arch/arm/mach-sa1100/Kconfig"
1089 source "arch/arm/plat-samsung/Kconfig"
1090 source "arch/arm/plat-s3c24xx/Kconfig"
1092 source "arch/arm/mach-socfpga/Kconfig"
1094 source "arch/arm/plat-spear/Kconfig"
1096 source "arch/arm/mach-s3c24xx/Kconfig"
1097 if ARCH_S3C24XX
1098 source "arch/arm/mach-s3c2412/Kconfig"
1099 source "arch/arm/mach-s3c2440/Kconfig"
1100 endif
1102 if ARCH_S3C64XX
1103 source "arch/arm/mach-s3c64xx/Kconfig"
1104 endif
1106 source "arch/arm/mach-s5p64x0/Kconfig"
1108 source "arch/arm/mach-s5pc100/Kconfig"
1110 source "arch/arm/mach-s5pv210/Kconfig"
1112 source "arch/arm/mach-exynos/Kconfig"
1114 source "arch/arm/mach-shmobile/Kconfig"
1116 source "arch/arm/mach-tegra/Kconfig"
1118 source "arch/arm/mach-u300/Kconfig"
1120 source "arch/arm/mach-ux500/Kconfig"
1122 source "arch/arm/mach-versatile/Kconfig"
1124 source "arch/arm/mach-vexpress/Kconfig"
1125 source "arch/arm/plat-versatile/Kconfig"
1127 source "arch/arm/mach-vt8500/Kconfig"
1129 source "arch/arm/mach-w90x900/Kconfig"
1131 # Definitions to make life easier
1132 config ARCH_ACORN
1133 bool
1135 config PLAT_IOP
1136 bool
1137 select GENERIC_CLOCKEVENTS
1139 config PLAT_ORION
1140 bool
1141 select CLKSRC_MMIO
1142 select GENERIC_IRQ_CHIP
1143 select IRQ_DOMAIN
1144 select COMMON_CLK
1146 config PLAT_PXA
1147 bool
1149 config PLAT_VERSATILE
1150 bool
1152 config ARM_TIMER_SP804
1153 bool
1154 select CLKSRC_MMIO
1155 select HAVE_SCHED_CLOCK
1157 source arch/arm/mm/Kconfig
1159 config ARM_NR_BANKS
1160 int
1161 default 16 if ARCH_EP93XX
1162 default 8
1164 config IWMMXT
1165 bool "Enable iWMMXt support"
1166 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1167 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1168 help
1169 Enable support for iWMMXt context switching at run time if
1170 running on a CPU that supports it.
1172 config XSCALE_PMU
1173 bool
1174 depends on CPU_XSCALE
1175 default y
1177 config CPU_HAS_PMU
1178 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1179 (!ARCH_OMAP3 || OMAP3_EMU)
1180 default y
1181 bool
1183 config MULTI_IRQ_HANDLER
1184 bool
1185 help
1186 Allow each machine to specify it's own IRQ handler at run time.
1188 if !MMU
1189 source "arch/arm/Kconfig-nommu"
1190 endif
1192 config ARM_ERRATA_326103
1193 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1194 depends on CPU_V6
1195 help
1196 Executing a SWP instruction to read-only memory does not set bit 11
1197 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1198 treat the access as a read, preventing a COW from occurring and
1199 causing the faulting task to livelock.
1201 config ARM_ERRATA_411920
1202 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1203 depends on CPU_V6 || CPU_V6K
1204 help
1205 Invalidation of the Instruction Cache operation can
1206 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1207 It does not affect the MPCore. This option enables the ARM Ltd.
1208 recommended workaround.
1210 config ARM_ERRATA_430973
1211 bool "ARM errata: Stale prediction on replaced interworking branch"
1212 depends on CPU_V7
1213 help
1214 This option enables the workaround for the 430973 Cortex-A8
1215 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1216 interworking branch is replaced with another code sequence at the
1217 same virtual address, whether due to self-modifying code or virtual
1218 to physical address re-mapping, Cortex-A8 does not recover from the
1219 stale interworking branch prediction. This results in Cortex-A8
1220 executing the new code sequence in the incorrect ARM or Thumb state.
1221 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1222 and also flushes the branch target cache at every context switch.
1223 Note that setting specific bits in the ACTLR register may not be
1224 available in non-secure mode.
1226 config ARM_ERRATA_458693
1227 bool "ARM errata: Processor deadlock when a false hazard is created"
1228 depends on CPU_V7
1229 help
1230 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1231 erratum. For very specific sequences of memory operations, it is
1232 possible for a hazard condition intended for a cache line to instead
1233 be incorrectly associated with a different cache line. This false
1234 hazard might then cause a processor deadlock. The workaround enables
1235 the L1 caching of the NEON accesses and disables the PLD instruction
1236 in the ACTLR register. Note that setting specific bits in the ACTLR
1237 register may not be available in non-secure mode.
1239 config ARM_ERRATA_460075
1240 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1241 depends on CPU_V7
1242 help
1243 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1244 erratum. Any asynchronous access to the L2 cache may encounter a
1245 situation in which recent store transactions to the L2 cache are lost
1246 and overwritten with stale memory contents from external memory. The
1247 workaround disables the write-allocate mode for the L2 cache via the
1248 ACTLR register. Note that setting specific bits in the ACTLR register
1249 may not be available in non-secure mode.
1251 config ARM_ERRATA_742230
1252 bool "ARM errata: DMB operation may be faulty"
1253 depends on CPU_V7 && SMP
1254 help
1255 This option enables the workaround for the 742230 Cortex-A9
1256 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1257 between two write operations may not ensure the correct visibility
1258 ordering of the two writes. This workaround sets a specific bit in
1259 the diagnostic register of the Cortex-A9 which causes the DMB
1260 instruction to behave as a DSB, ensuring the correct behaviour of
1261 the two writes.
1263 config ARM_ERRATA_742231
1264 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1265 depends on CPU_V7 && SMP
1266 help
1267 This option enables the workaround for the 742231 Cortex-A9
1268 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1269 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1270 accessing some data located in the same cache line, may get corrupted
1271 data due to bad handling of the address hazard when the line gets
1272 replaced from one of the CPUs at the same time as another CPU is
1273 accessing it. This workaround sets specific bits in the diagnostic
1274 register of the Cortex-A9 which reduces the linefill issuing
1275 capabilities of the processor.
1277 config PL310_ERRATA_588369
1278 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1279 depends on CACHE_L2X0
1280 help
1281 The PL310 L2 cache controller implements three types of Clean &
1282 Invalidate maintenance operations: by Physical Address
1283 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1284 They are architecturally defined to behave as the execution of a
1285 clean operation followed immediately by an invalidate operation,
1286 both performing to the same memory location. This functionality
1287 is not correctly implemented in PL310 as clean lines are not
1288 invalidated as a result of these operations.
1290 config ARM_ERRATA_720789
1291 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1292 depends on CPU_V7
1293 help
1294 This option enables the workaround for the 720789 Cortex-A9 (prior to
1295 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1296 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1297 As a consequence of this erratum, some TLB entries which should be
1298 invalidated are not, resulting in an incoherency in the system page
1299 tables. The workaround changes the TLB flushing routines to invalidate
1300 entries regardless of the ASID.
1302 config PL310_ERRATA_727915
1303 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1304 depends on CACHE_L2X0
1305 help
1306 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1307 operation (offset 0x7FC). This operation runs in background so that
1308 PL310 can handle normal accesses while it is in progress. Under very
1309 rare circumstances, due to this erratum, write data can be lost when
1310 PL310 treats a cacheable write transaction during a Clean &
1311 Invalidate by Way operation.
1313 config ARM_ERRATA_743622
1314 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1315 depends on CPU_V7
1316 help
1317 This option enables the workaround for the 743622 Cortex-A9
1318 (r2p*) erratum. Under very rare conditions, a faulty
1319 optimisation in the Cortex-A9 Store Buffer may lead to data
1320 corruption. This workaround sets a specific bit in the diagnostic
1321 register of the Cortex-A9 which disables the Store Buffer
1322 optimisation, preventing the defect from occurring. This has no
1323 visible impact on the overall performance or power consumption of the
1324 processor.
1326 config ARM_ERRATA_751472
1327 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1328 depends on CPU_V7
1329 help
1330 This option enables the workaround for the 751472 Cortex-A9 (prior
1331 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1332 completion of a following broadcasted operation if the second
1333 operation is received by a CPU before the ICIALLUIS has completed,
1334 potentially leading to corrupted entries in the cache or TLB.
1336 config PL310_ERRATA_753970
1337 bool "PL310 errata: cache sync operation may be faulty"
1338 depends on CACHE_PL310
1339 help
1340 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1342 Under some condition the effect of cache sync operation on
1343 the store buffer still remains when the operation completes.
1344 This means that the store buffer is always asked to drain and
1345 this prevents it from merging any further writes. The workaround
1346 is to replace the normal offset of cache sync operation (0x730)
1347 by another offset targeting an unmapped PL310 register 0x740.
1348 This has the same effect as the cache sync operation: store buffer
1349 drain and waiting for all buffers empty.
1351 config ARM_ERRATA_754322
1352 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1353 depends on CPU_V7
1354 help
1355 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1356 r3p*) erratum. A speculative memory access may cause a page table walk
1357 which starts prior to an ASID switch but completes afterwards. This
1358 can populate the micro-TLB with a stale entry which may be hit with
1359 the new ASID. This workaround places two dsb instructions in the mm
1360 switching code so that no page table walks can cross the ASID switch.
1362 config ARM_ERRATA_754327
1363 bool "ARM errata: no automatic Store Buffer drain"
1364 depends on CPU_V7 && SMP
1365 help
1366 This option enables the workaround for the 754327 Cortex-A9 (prior to
1367 r2p0) erratum. The Store Buffer does not have any automatic draining
1368 mechanism and therefore a livelock may occur if an external agent
1369 continuously polls a memory location waiting to observe an update.
1370 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1371 written polling loops from denying visibility of updates to memory.
1373 config ARM_ERRATA_364296
1374 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1375 depends on CPU_V6 && !SMP
1376 help
1377 This options enables the workaround for the 364296 ARM1136
1378 r0p2 erratum (possible cache data corruption with
1379 hit-under-miss enabled). It sets the undocumented bit 31 in
1380 the auxiliary control register and the FI bit in the control
1381 register, thus disabling hit-under-miss without putting the
1382 processor into full low interrupt latency mode. ARM11MPCore
1383 is not affected.
1385 config ARM_ERRATA_764369
1386 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1387 depends on CPU_V7 && SMP
1388 help
1389 This option enables the workaround for erratum 764369
1390 affecting Cortex-A9 MPCore with two or more processors (all
1391 current revisions). Under certain timing circumstances, a data
1392 cache line maintenance operation by MVA targeting an Inner
1393 Shareable memory region may fail to proceed up to either the
1394 Point of Coherency or to the Point of Unification of the
1395 system. This workaround adds a DSB instruction before the
1396 relevant cache maintenance functions and sets a specific bit
1397 in the diagnostic control register of the SCU.
1399 config PL310_ERRATA_769419
1400 bool "PL310 errata: no automatic Store Buffer drain"
1401 depends on CACHE_L2X0
1402 help
1403 On revisions of the PL310 prior to r3p2, the Store Buffer does
1404 not automatically drain. This can cause normal, non-cacheable
1405 writes to be retained when the memory system is idle, leading
1406 to suboptimal I/O performance for drivers using coherent DMA.
1407 This option adds a write barrier to the cpu_idle loop so that,
1408 on systems with an outer cache, the store buffer is drained
1409 explicitly.
1411 endmenu
1413 source "arch/arm/common/Kconfig"
1415 menu "Bus support"
1417 config ARM_AMBA
1418 bool
1420 config ISA
1421 bool
1422 help
1423 Find out whether you have ISA slots on your motherboard. ISA is the
1424 name of a bus system, i.e. the way the CPU talks to the other stuff
1425 inside your box. Other bus systems are PCI, EISA, MicroChannel
1426 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1427 newer boards don't support it. If you have ISA, say Y, otherwise N.
1429 # Select ISA DMA controller support
1430 config ISA_DMA
1431 bool
1432 select ISA_DMA_API
1434 # Select ISA DMA interface
1435 config ISA_DMA_API
1436 bool
1438 config PCI
1439 bool "PCI support" if MIGHT_HAVE_PCI
1440 help
1441 Find out whether you have a PCI motherboard. PCI is the name of a
1442 bus system, i.e. the way the CPU talks to the other stuff inside
1443 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1444 VESA. If you have PCI, say Y, otherwise N.
1446 config PCI_DOMAINS
1447 bool
1448 depends on PCI
1450 config PCI_NANOENGINE
1451 bool "BSE nanoEngine PCI support"
1452 depends on SA1100_NANOENGINE
1453 help
1454 Enable PCI on the BSE nanoEngine board.
1456 config PCI_SYSCALL
1457 def_bool PCI
1459 # Select the host bridge type
1460 config PCI_HOST_VIA82C505
1461 bool
1462 depends on PCI && ARCH_SHARK
1463 default y
1465 config PCI_HOST_ITE8152
1466 bool
1467 depends on PCI && MACH_ARMCORE
1468 default y
1469 select DMABOUNCE
1471 source "drivers/pci/Kconfig"
1473 source "drivers/pcmcia/Kconfig"
1475 endmenu
1477 menu "Kernel Features"
1479 config HAVE_SMP
1480 bool
1481 help
1482 This option should be selected by machines which have an SMP-
1483 capable CPU.
1485 The only effect of this option is to make the SMP-related
1486 options available to the user for configuration.
1488 config SMP
1489 bool "Symmetric Multi-Processing"
1490 depends on CPU_V6K || CPU_V7
1491 depends on GENERIC_CLOCKEVENTS
1492 depends on HAVE_SMP
1493 depends on MMU
1494 select USE_GENERIC_SMP_HELPERS
1495 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1496 help
1497 This enables support for systems with more than one CPU. If you have
1498 a system with only one CPU, like most personal computers, say N. If
1499 you have a system with more than one CPU, say Y.
1501 If you say N here, the kernel will run on single and multiprocessor
1502 machines, but will use only one CPU of a multiprocessor machine. If
1503 you say Y here, the kernel will run on many, but not all, single
1504 processor machines. On a single processor machine, the kernel will
1505 run faster if you say N here.
1507 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1508 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1509 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1511 If you don't know what to do here, say N.
1513 config SMP_ON_UP
1514 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1515 depends on EXPERIMENTAL
1516 depends on SMP && !XIP_KERNEL
1517 default y
1518 help
1519 SMP kernels contain instructions which fail on non-SMP processors.
1520 Enabling this option allows the kernel to modify itself to make
1521 these instructions safe. Disabling it allows about 1K of space
1522 savings.
1524 If you don't know what to do here, say Y.
1526 config ARM_CPU_TOPOLOGY
1527 bool "Support cpu topology definition"
1528 depends on SMP && CPU_V7
1529 default y
1530 help
1531 Support ARM cpu topology definition. The MPIDR register defines
1532 affinity between processors which is then used to describe the cpu
1533 topology of an ARM System.
1535 config SCHED_MC
1536 bool "Multi-core scheduler support"
1537 depends on ARM_CPU_TOPOLOGY
1538 help
1539 Multi-core scheduler support improves the CPU scheduler's decision
1540 making when dealing with multi-core CPU chips at a cost of slightly
1541 increased overhead in some places. If unsure say N here.
1543 config SCHED_SMT
1544 bool "SMT scheduler support"
1545 depends on ARM_CPU_TOPOLOGY
1546 help
1547 Improves the CPU scheduler's decision making when dealing with
1548 MultiThreading at a cost of slightly increased overhead in some
1549 places. If unsure say N here.
1551 config HAVE_ARM_SCU
1552 bool
1553 help
1554 This option enables support for the ARM system coherency unit
1556 config ARM_ARCH_TIMER
1557 bool "Architected timer support"
1558 depends on CPU_V7
1559 help
1560 This option enables support for the ARM architected timer
1562 config HAVE_ARM_TWD
1563 bool
1564 depends on SMP
1565 help
1566 This options enables support for the ARM timer and watchdog unit
1568 choice
1569 prompt "Memory split"
1570 default VMSPLIT_3G
1571 help
1572 Select the desired split between kernel and user memory.
1574 If you are not absolutely sure what you are doing, leave this
1575 option alone!
1577 config VMSPLIT_3G
1578 bool "3G/1G user/kernel split"
1579 config VMSPLIT_2G
1580 bool "2G/2G user/kernel split"
1581 config VMSPLIT_1G
1582 bool "1G/3G user/kernel split"
1583 endchoice
1585 config PAGE_OFFSET
1586 hex
1587 default 0x40000000 if VMSPLIT_1G
1588 default 0x80000000 if VMSPLIT_2G
1589 default 0xC0000000
1591 config NR_CPUS
1592 int "Maximum number of CPUs (2-32)"
1593 range 2 32
1594 depends on SMP
1595 default "4"
1597 config HOTPLUG_CPU
1598 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1599 depends on SMP && HOTPLUG && EXPERIMENTAL
1600 help
1601 Say Y here to experiment with turning CPUs off and on. CPUs
1602 can be controlled through /sys/devices/system/cpu.
1604 config LOCAL_TIMERS
1605 bool "Use local timer interrupts"
1606 depends on SMP
1607 default y
1608 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1609 help
1610 Enable support for local timers on SMP platforms, rather then the
1611 legacy IPI broadcast method. Local timers allows the system
1612 accounting to be spread across the timer interval, preventing a
1613 "thundering herd" at every timer tick.
1615 config ARCH_NR_GPIO
1616 int
1617 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1618 default 355 if ARCH_U8500
1619 default 264 if MACH_H4700
1620 default 512 if SOC_OMAP5
1621 default 0
1622 help
1623 Maximum number of GPIOs in the system.
1625 If unsure, leave the default value.
1627 source kernel/Kconfig.preempt
1629 config HZ
1630 int
1631 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1632 ARCH_S5PV210 || ARCH_EXYNOS4
1633 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1634 default AT91_TIMER_HZ if ARCH_AT91
1635 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1636 default 100
1638 config THUMB2_KERNEL
1639 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1640 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1641 select AEABI
1642 select ARM_ASM_UNIFIED
1643 select ARM_UNWIND
1644 help
1645 By enabling this option, the kernel will be compiled in
1646 Thumb-2 mode. A compiler/assembler that understand the unified
1647 ARM-Thumb syntax is needed.
1649 If unsure, say N.
1651 config THUMB2_AVOID_R_ARM_THM_JUMP11
1652 bool "Work around buggy Thumb-2 short branch relocations in gas"
1653 depends on THUMB2_KERNEL && MODULES
1654 default y
1655 help
1656 Various binutils versions can resolve Thumb-2 branches to
1657 locally-defined, preemptible global symbols as short-range "b.n"
1658 branch instructions.
1660 This is a problem, because there's no guarantee the final
1661 destination of the symbol, or any candidate locations for a
1662 trampoline, are within range of the branch. For this reason, the
1663 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1664 relocation in modules at all, and it makes little sense to add
1665 support.
1667 The symptom is that the kernel fails with an "unsupported
1668 relocation" error when loading some modules.
1670 Until fixed tools are available, passing
1671 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1672 code which hits this problem, at the cost of a bit of extra runtime
1673 stack usage in some cases.
1675 The problem is described in more detail at:
1676 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1678 Only Thumb-2 kernels are affected.
1680 Unless you are sure your tools don't have this problem, say Y.
1682 config ARM_ASM_UNIFIED
1683 bool
1685 config AEABI
1686 bool "Use the ARM EABI to compile the kernel"
1687 help
1688 This option allows for the kernel to be compiled using the latest
1689 ARM ABI (aka EABI). This is only useful if you are using a user
1690 space environment that is also compiled with EABI.
1692 Since there are major incompatibilities between the legacy ABI and
1693 EABI, especially with regard to structure member alignment, this
1694 option also changes the kernel syscall calling convention to
1695 disambiguate both ABIs and allow for backward compatibility support
1696 (selected with CONFIG_OABI_COMPAT).
1698 To use this you need GCC version 4.0.0 or later.
1700 config OABI_COMPAT
1701 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1702 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1703 default y
1704 help
1705 This option preserves the old syscall interface along with the
1706 new (ARM EABI) one. It also provides a compatibility layer to
1707 intercept syscalls that have structure arguments which layout
1708 in memory differs between the legacy ABI and the new ARM EABI
1709 (only for non "thumb" binaries). This option adds a tiny
1710 overhead to all syscalls and produces a slightly larger kernel.
1711 If you know you'll be using only pure EABI user space then you
1712 can say N here. If this option is not selected and you attempt
1713 to execute a legacy ABI binary then the result will be
1714 UNPREDICTABLE (in fact it can be predicted that it won't work
1715 at all). If in doubt say Y.
1717 config ARCH_HAS_HOLES_MEMORYMODEL
1718 bool
1720 config ARCH_SPARSEMEM_ENABLE
1721 bool
1723 config ARCH_SPARSEMEM_DEFAULT
1724 def_bool ARCH_SPARSEMEM_ENABLE
1726 config ARCH_SELECT_MEMORY_MODEL
1727 def_bool ARCH_SPARSEMEM_ENABLE
1729 config HAVE_ARCH_PFN_VALID
1730 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1732 config HIGHMEM
1733 bool "High Memory Support"
1734 depends on MMU
1735 help
1736 The address space of ARM processors is only 4 Gigabytes large
1737 and it has to accommodate user address space, kernel address
1738 space as well as some memory mapped IO. That means that, if you
1739 have a large amount of physical memory and/or IO, not all of the
1740 memory can be "permanently mapped" by the kernel. The physical
1741 memory that is not permanently mapped is called "high memory".
1743 Depending on the selected kernel/user memory split, minimum
1744 vmalloc space and actual amount of RAM, you may not need this
1745 option which should result in a slightly faster kernel.
1747 If unsure, say n.
1749 config HIGHPTE
1750 bool "Allocate 2nd-level pagetables from highmem"
1751 depends on HIGHMEM
1753 config HW_PERF_EVENTS
1754 bool "Enable hardware performance counter support for perf events"
1755 depends on PERF_EVENTS && CPU_HAS_PMU
1756 default y
1757 help
1758 Enable hardware performance counter support for perf events. If
1759 disabled, perf events will use software events only.
1761 source "mm/Kconfig"
1763 config FORCE_MAX_ZONEORDER
1764 int "Maximum zone order" if ARCH_SHMOBILE
1765 range 11 64 if ARCH_SHMOBILE
1766 default "9" if SA1111
1767 default "11"
1768 help
1769 The kernel memory allocator divides physically contiguous memory
1770 blocks into "zones", where each zone is a power of two number of
1771 pages. This option selects the largest power of two that the kernel
1772 keeps in the memory allocator. If you need to allocate very large
1773 blocks of physically contiguous memory, then you may need to
1774 increase this value.
1776 This config option is actually maximum order plus one. For example,
1777 a value of 11 means that the largest free memory block is 2^10 pages.
1779 config LEDS
1780 bool "Timer and CPU usage LEDs"
1781 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1782 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1783 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1784 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1785 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1786 ARCH_AT91 || ARCH_DAVINCI || \
1787 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1788 help
1789 If you say Y here, the LEDs on your machine will be used
1790 to provide useful information about your current system status.
1792 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1793 be able to select which LEDs are active using the options below. If
1794 you are compiling a kernel for the EBSA-110 or the LART however, the
1795 red LED will simply flash regularly to indicate that the system is
1796 still functional. It is safe to say Y here if you have a CATS
1797 system, but the driver will do nothing.
1799 config LEDS_TIMER
1800 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1801 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1802 || MACH_OMAP_PERSEUS2
1803 depends on LEDS
1804 depends on !GENERIC_CLOCKEVENTS
1805 default y if ARCH_EBSA110
1806 help
1807 If you say Y here, one of the system LEDs (the green one on the
1808 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1809 will flash regularly to indicate that the system is still
1810 operational. This is mainly useful to kernel hackers who are
1811 debugging unstable kernels.
1813 The LART uses the same LED for both Timer LED and CPU usage LED
1814 functions. You may choose to use both, but the Timer LED function
1815 will overrule the CPU usage LED.
1817 config LEDS_CPU
1818 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1819 !ARCH_OMAP) \
1820 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1821 || MACH_OMAP_PERSEUS2
1822 depends on LEDS
1823 help
1824 If you say Y here, the red LED will be used to give a good real
1825 time indication of CPU usage, by lighting whenever the idle task
1826 is not currently executing.
1828 The LART uses the same LED for both Timer LED and CPU usage LED
1829 functions. You may choose to use both, but the Timer LED function
1830 will overrule the CPU usage LED.
1832 config ALIGNMENT_TRAP
1833 bool
1834 depends on CPU_CP15_MMU
1835 default y if !ARCH_EBSA110
1836 select HAVE_PROC_CPU if PROC_FS
1837 help
1838 ARM processors cannot fetch/store information which is not
1839 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1840 address divisible by 4. On 32-bit ARM processors, these non-aligned
1841 fetch/store instructions will be emulated in software if you say
1842 here, which has a severe performance impact. This is necessary for
1843 correct operation of some network protocols. With an IP-only
1844 configuration it is safe to say N, otherwise say Y.
1846 config UACCESS_WITH_MEMCPY
1847 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1848 depends on MMU && EXPERIMENTAL
1849 default y if CPU_FEROCEON
1850 help
1851 Implement faster copy_to_user and clear_user methods for CPU
1852 cores where a 8-word STM instruction give significantly higher
1853 memory write throughput than a sequence of individual 32bit stores.
1855 A possible side effect is a slight increase in scheduling latency
1856 between threads sharing the same address space if they invoke
1857 such copy operations with large buffers.
1859 However, if the CPU data cache is using a write-allocate mode,
1860 this option is unlikely to provide any performance gain.
1862 config SECCOMP
1863 bool
1864 prompt "Enable seccomp to safely compute untrusted bytecode"
1865 ---help---
1866 This kernel feature is useful for number crunching applications
1867 that may need to compute untrusted bytecode during their
1868 execution. By using pipes or other transports made available to
1869 the process as file descriptors supporting the read/write
1870 syscalls, it's possible to isolate those applications in
1871 their own address space using seccomp. Once seccomp is
1872 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1873 and the task is only allowed to execute a few safe syscalls
1874 defined by each seccomp mode.
1876 config CC_STACKPROTECTOR
1877 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1878 depends on EXPERIMENTAL
1879 help
1880 This option turns on the -fstack-protector GCC feature. This
1881 feature puts, at the beginning of functions, a canary value on
1882 the stack just before the return address, and validates
1883 the value just before actually returning. Stack based buffer
1884 overflows (that need to overwrite this return address) now also
1885 overwrite the canary, which gets detected and the attack is then
1886 neutralized via a kernel panic.
1887 This feature requires gcc version 4.2 or above.
1889 config DEPRECATED_PARAM_STRUCT
1890 bool "Provide old way to pass kernel parameters"
1891 help
1892 This was deprecated in 2001 and announced to live on for 5 years.
1893 Some old boot loaders still use this way.
1895 endmenu
1897 menu "Boot options"
1899 config USE_OF
1900 bool "Flattened Device Tree support"
1901 select OF
1902 select OF_EARLY_FLATTREE
1903 select IRQ_DOMAIN
1904 help
1905 Include support for flattened device tree machine descriptions.
1907 # Compressed boot loader in ROM. Yes, we really want to ask about
1908 # TEXT and BSS so we preserve their values in the config files.
1909 config ZBOOT_ROM_TEXT
1910 hex "Compressed ROM boot loader base address"
1911 default "0"
1912 help
1913 The physical address at which the ROM-able zImage is to be
1914 placed in the target. Platforms which normally make use of
1915 ROM-able zImage formats normally set this to a suitable
1916 value in their defconfig file.
1918 If ZBOOT_ROM is not enabled, this has no effect.
1920 config ZBOOT_ROM_BSS
1921 hex "Compressed ROM boot loader BSS address"
1922 default "0"
1923 help
1924 The base address of an area of read/write memory in the target
1925 for the ROM-able zImage which must be available while the
1926 decompressor is running. It must be large enough to hold the
1927 entire decompressed kernel plus an additional 128 KiB.
1928 Platforms which normally make use of ROM-able zImage formats
1929 normally set this to a suitable value in their defconfig file.
1931 If ZBOOT_ROM is not enabled, this has no effect.
1933 config ZBOOT_ROM
1934 bool "Compressed boot loader in ROM/flash"
1935 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1936 help
1937 Say Y here if you intend to execute your compressed kernel image
1938 (zImage) directly from ROM or flash. If unsure, say N.
1940 choice
1941 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1942 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1943 default ZBOOT_ROM_NONE
1944 help
1945 Include experimental SD/MMC loading code in the ROM-able zImage.
1946 With this enabled it is possible to write the ROM-able zImage
1947 kernel image to an MMC or SD card and boot the kernel straight
1948 from the reset vector. At reset the processor Mask ROM will load
1949 the first part of the ROM-able zImage which in turn loads the
1950 rest the kernel image to RAM.
1952 config ZBOOT_ROM_NONE
1953 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1954 help
1955 Do not load image from SD or MMC
1957 config ZBOOT_ROM_MMCIF
1958 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1959 help
1960 Load image from MMCIF hardware block.
1962 config ZBOOT_ROM_SH_MOBILE_SDHI
1963 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1964 help
1965 Load image from SDHI hardware block
1967 endchoice
1969 config ARM_APPENDED_DTB
1970 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1971 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1972 help
1973 With this option, the boot code will look for a device tree binary
1974 (DTB) appended to zImage
1975 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1977 This is meant as a backward compatibility convenience for those
1978 systems with a bootloader that can't be upgraded to accommodate
1979 the documented boot protocol using a device tree.
1981 Beware that there is very little in terms of protection against
1982 this option being confused by leftover garbage in memory that might
1983 look like a DTB header after a reboot if no actual DTB is appended
1984 to zImage. Do not leave this option active in a production kernel
1985 if you don't intend to always append a DTB. Proper passing of the
1986 location into r2 of a bootloader provided DTB is always preferable
1987 to this option.
1989 config ARM_ATAG_DTB_COMPAT
1990 bool "Supplement the appended DTB with traditional ATAG information"
1991 depends on ARM_APPENDED_DTB
1992 help
1993 Some old bootloaders can't be updated to a DTB capable one, yet
1994 they provide ATAGs with memory configuration, the ramdisk address,
1995 the kernel cmdline string, etc. Such information is dynamically
1996 provided by the bootloader and can't always be stored in a static
1997 DTB. To allow a device tree enabled kernel to be used with such
1998 bootloaders, this option allows zImage to extract the information
1999 from the ATAG list and store it at run time into the appended DTB.
2001 choice
2002 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2003 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2005 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2006 bool "Use bootloader kernel arguments if available"
2007 help
2008 Uses the command-line options passed by the boot loader instead of
2009 the device tree bootargs property. If the boot loader doesn't provide
2010 any, the device tree bootargs property will be used.
2012 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2013 bool "Extend with bootloader kernel arguments"
2014 help
2015 The command-line arguments provided by the boot loader will be
2016 appended to the the device tree bootargs property.
2018 endchoice
2020 config CMDLINE
2021 string "Default kernel command string"
2022 default ""
2023 help
2024 On some architectures (EBSA110 and CATS), there is currently no way
2025 for the boot loader to pass arguments to the kernel. For these
2026 architectures, you should supply some command-line options at build
2027 time by entering them here. As a minimum, you should specify the
2028 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2030 choice
2031 prompt "Kernel command line type" if CMDLINE != ""
2032 default CMDLINE_FROM_BOOTLOADER
2034 config CMDLINE_FROM_BOOTLOADER
2035 bool "Use bootloader kernel arguments if available"
2036 help
2037 Uses the command-line options passed by the boot loader. If
2038 the boot loader doesn't provide any, the default kernel command
2039 string provided in CMDLINE will be used.
2041 config CMDLINE_EXTEND
2042 bool "Extend bootloader kernel arguments"
2043 help
2044 The command-line arguments provided by the boot loader will be
2045 appended to the default kernel command string.
2047 config CMDLINE_FORCE
2048 bool "Always use the default kernel command string"
2049 help
2050 Always use the default kernel command string, even if the boot
2051 loader passes other arguments to the kernel.
2052 This is useful if you cannot or don't want to change the
2053 command-line options your boot loader passes to the kernel.
2054 endchoice
2056 config XIP_KERNEL
2057 bool "Kernel Execute-In-Place from ROM"
2058 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2059 help
2060 Execute-In-Place allows the kernel to run from non-volatile storage
2061 directly addressable by the CPU, such as NOR flash. This saves RAM
2062 space since the text section of the kernel is not loaded from flash
2063 to RAM. Read-write sections, such as the data section and stack,
2064 are still copied to RAM. The XIP kernel is not compressed since
2065 it has to run directly from flash, so it will take more space to
2066 store it. The flash address used to link the kernel object files,
2067 and for storing it, is configuration dependent. Therefore, if you
2068 say Y here, you must know the proper physical address where to
2069 store the kernel image depending on your own flash memory usage.
2071 Also note that the make target becomes "make xipImage" rather than
2072 "make zImage" or "make Image". The final kernel binary to put in
2073 ROM memory will be arch/arm/boot/xipImage.
2075 If unsure, say N.
2077 config XIP_PHYS_ADDR
2078 hex "XIP Kernel Physical Location"
2079 depends on XIP_KERNEL
2080 default "0x00080000"
2081 help
2082 This is the physical address in your flash memory the kernel will
2083 be linked for and stored to. This address is dependent on your
2084 own flash usage.
2086 config KEXEC
2087 bool "Kexec system call (EXPERIMENTAL)"
2088 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2089 help
2090 kexec is a system call that implements the ability to shutdown your
2091 current kernel, and to start another kernel. It is like a reboot
2092 but it is independent of the system firmware. And like a reboot
2093 you can start any kernel with it, not just Linux.
2095 It is an ongoing process to be certain the hardware in a machine
2096 is properly shutdown, so do not be surprised if this code does not
2097 initially work for you. It may help to enable device hotplugging
2098 support.
2100 config ATAGS_PROC
2101 bool "Export atags in procfs"
2102 depends on KEXEC
2103 default y
2104 help
2105 Should the atags used to boot the kernel be exported in an "atags"
2106 file in procfs. Useful with kexec.
2108 config CRASH_DUMP
2109 bool "Build kdump crash kernel (EXPERIMENTAL)"
2110 depends on EXPERIMENTAL
2111 help
2112 Generate crash dump after being started by kexec. This should
2113 be normally only set in special crash dump kernels which are
2114 loaded in the main kernel with kexec-tools into a specially
2115 reserved region and then later executed after a crash by
2116 kdump/kexec. The crash dump kernel must be compiled to a
2117 memory address not used by the main kernel
2119 For more details see Documentation/kdump/kdump.txt
2121 config AUTO_ZRELADDR
2122 bool "Auto calculation of the decompressed kernel image address"
2123 depends on !ZBOOT_ROM && !ARCH_U300
2124 help
2125 ZRELADDR is the physical address where the decompressed kernel
2126 image will be placed. If AUTO_ZRELADDR is selected, the address
2127 will be determined at run-time by masking the current IP with
2128 0xf8000000. This assumes the zImage being placed in the first 128MB
2129 from start of memory.
2131 endmenu
2133 menu "CPU Power Management"
2135 if ARCH_HAS_CPUFREQ
2137 source "drivers/cpufreq/Kconfig"
2139 config CPU_FREQ_IMX
2140 tristate "CPUfreq driver for i.MX CPUs"
2141 depends on ARCH_MXC && CPU_FREQ
2142 select CPU_FREQ_TABLE
2143 help
2144 This enables the CPUfreq driver for i.MX CPUs.
2146 config CPU_FREQ_SA1100
2147 bool
2149 config CPU_FREQ_SA1110
2150 bool
2152 config CPU_FREQ_INTEGRATOR
2153 tristate "CPUfreq driver for ARM Integrator CPUs"
2154 depends on ARCH_INTEGRATOR && CPU_FREQ
2155 default y
2156 help
2157 This enables the CPUfreq driver for ARM Integrator CPUs.
2159 For details, take a look at <file:Documentation/cpu-freq>.
2161 If in doubt, say Y.
2163 config CPU_FREQ_PXA
2164 bool
2165 depends on CPU_FREQ && ARCH_PXA && PXA25x
2166 default y
2167 select CPU_FREQ_TABLE
2168 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2170 config CPU_FREQ_S3C
2171 bool
2172 help
2173 Internal configuration node for common cpufreq on Samsung SoC
2175 config CPU_FREQ_S3C24XX
2176 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2177 depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2178 select CPU_FREQ_S3C
2179 help
2180 This enables the CPUfreq driver for the Samsung S3C24XX family
2181 of CPUs.
2183 For details, take a look at <file:Documentation/cpu-freq>.
2185 If in doubt, say N.
2187 config CPU_FREQ_S3C24XX_PLL
2188 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2189 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2190 help
2191 Compile in support for changing the PLL frequency from the
2192 S3C24XX series CPUfreq driver. The PLL takes time to settle
2193 after a frequency change, so by default it is not enabled.
2195 This also means that the PLL tables for the selected CPU(s) will
2196 be built which may increase the size of the kernel image.
2198 config CPU_FREQ_S3C24XX_DEBUG
2199 bool "Debug CPUfreq Samsung driver core"
2200 depends on CPU_FREQ_S3C24XX
2201 help
2202 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2204 config CPU_FREQ_S3C24XX_IODEBUG
2205 bool "Debug CPUfreq Samsung driver IO timing"
2206 depends on CPU_FREQ_S3C24XX
2207 help
2208 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2210 config CPU_FREQ_S3C24XX_DEBUGFS
2211 bool "Export debugfs for CPUFreq"
2212 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2213 help
2214 Export status information via debugfs.
2216 endif
2218 source "drivers/cpuidle/Kconfig"
2220 endmenu
2222 menu "Floating point emulation"
2224 comment "At least one emulation must be selected"
2226 config FPE_NWFPE
2227 bool "NWFPE math emulation"
2228 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2229 ---help---
2230 Say Y to include the NWFPE floating point emulator in the kernel.
2231 This is necessary to run most binaries. Linux does not currently
2232 support floating point hardware so you need to say Y here even if
2233 your machine has an FPA or floating point co-processor podule.
2235 You may say N here if you are going to load the Acorn FPEmulator
2236 early in the bootup.
2238 config FPE_NWFPE_XP
2239 bool "Support extended precision"
2240 depends on FPE_NWFPE
2241 help
2242 Say Y to include 80-bit support in the kernel floating-point
2243 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2244 Note that gcc does not generate 80-bit operations by default,
2245 so in most cases this option only enlarges the size of the
2246 floating point emulator without any good reason.
2248 You almost surely want to say N here.
2250 config FPE_FASTFPE
2251 bool "FastFPE math emulation (EXPERIMENTAL)"
2252 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2253 ---help---
2254 Say Y here to include the FAST floating point emulator in the kernel.
2255 This is an experimental much faster emulator which now also has full
2256 precision for the mantissa. It does not support any exceptions.
2257 It is very simple, and approximately 3-6 times faster than NWFPE.
2259 It should be sufficient for most programs. It may be not suitable
2260 for scientific calculations, but you have to check this for yourself.
2261 If you do not feel you need a faster FP emulation you should better
2262 choose NWFPE.
2264 config VFP
2265 bool "VFP-format floating point maths"
2266 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2267 help
2268 Say Y to include VFP support code in the kernel. This is needed
2269 if your hardware includes a VFP unit.
2271 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2272 release notes and additional status information.
2274 Say N if your target does not have VFP hardware.
2276 config VFPv3
2277 bool
2278 depends on VFP
2279 default y if CPU_V7
2281 config NEON
2282 bool "Advanced SIMD (NEON) Extension support"
2283 depends on VFPv3 && CPU_V7
2284 help
2285 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2286 Extension.
2288 endmenu
2290 menu "Userspace binary formats"
2292 source "fs/Kconfig.binfmt"
2294 config ARTHUR
2295 tristate "RISC OS personality"
2296 depends on !AEABI
2297 help
2298 Say Y here to include the kernel code necessary if you want to run
2299 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2300 experimental; if this sounds frightening, say N and sleep in peace.
2301 You can also say M here to compile this support as a module (which
2302 will be called arthur).
2304 endmenu
2306 menu "Power management options"
2308 source "kernel/power/Kconfig"
2310 config ARCH_SUSPEND_POSSIBLE
2311 depends on !ARCH_S5PC100 && !ARCH_TEGRA
2312 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2313 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2314 def_bool y
2316 config ARM_CPU_SUSPEND
2317 def_bool PM_SLEEP
2319 endmenu
2321 source "net/Kconfig"
2323 source "drivers/Kconfig"
2325 source "fs/Kconfig"
2327 source "arch/arm/Kconfig.debug"
2329 source "security/Kconfig"
2331 source "crypto/Kconfig"
2333 source "lib/Kconfig"