include/asm-powerpc/system.h

   1 /*
   2  * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
   3  */
   4 #ifndef _ASM_POWERPC_SYSTEM_H
   5 #define _ASM_POWERPC_SYSTEM_H
   6
   7 #include <linux/kernel.h>
   8 #include <linux/irqflags.h>
   9
  10 #include <asm/hw_irq.h>
  11
  12 /*
  13  * Memory barrier.
  14  * The sync instruction guarantees that all memory accesses initiated
  15  * by this processor have been performed (with respect to all other
  16  * mechanisms that access memory).  The eieio instruction is a barrier
  17  * providing an ordering (separately) for (a) cacheable stores and (b)
  18  * loads and stores to non-cacheable memory (e.g. I/O devices).
  19  *
  20  * mb() prevents loads and stores being reordered across this point.
  21  * rmb() prevents loads being reordered across this point.
  22  * wmb() prevents stores being reordered across this point.
  23  * read_barrier_depends() prevents data-dependent loads being reordered
  24  *      across this point (nop on PPC).
  25  *
  26  * We have to use the sync instructions for mb(), since lwsync doesn't
  27  * order loads with respect to previous stores.  Lwsync is fine for
  28  * rmb(), though. Note that rmb() actually uses a sync on 32-bit
  29  * architectures.
  30  *
  31  * For wmb(), we use sync since wmb is used in drivers to order
  32  * stores to system memory with respect to writes to the device.
  33  * However, smp_wmb() can be a lighter-weight lwsync or eieio barrier
  34  * on SMP since it is only used to order updates to system memory.
  35  */
  36 #define mb()   __asm__ __volatile__ ("sync" : : : "memory")
  37 #define rmb()  __asm__ __volatile__ ("sync" : : : "memory")
  38 #define wmb()  __asm__ __volatile__ ("sync" : : : "memory")
  39 #define read_barrier_depends()  do { } while(0)
  40
  41 #define set_mb(var, value)      do { var = value; mb(); } while (0)
  42
  43 #ifdef __KERNEL__
  44 #define AT_VECTOR_SIZE_ARCH 6 /* entries in ARCH_DLINFO */
  45 #ifdef CONFIG_SMP
  46
  47 #ifdef __SUBARCH_HAS_LWSYNC
  48 #    define SMPWMB      lwsync
  49 #else
  50 #    define SMPWMB      eieio
  51 #endif
  52
  53 #define smp_mb()        mb()
  54 #define smp_rmb()       rmb()
  55 #define smp_wmb()       __asm__ __volatile__ (__stringify(SMPWMB) : : :"memory")
  56 #define smp_read_barrier_depends()      read_barrier_depends()
  57 #else
  58 #define smp_mb()        barrier()
  59 #define smp_rmb()       barrier()
  60 #define smp_wmb()       barrier()
  61 #define smp_read_barrier_depends()      do { } while(0)
  62 #endif /* CONFIG_SMP */
  63
  64 /*
  65  * This is a barrier which prevents following instructions from being
  66  * started until the value of the argument x is known.  For example, if
  67  * x is a variable loaded from memory, this prevents following
  68  * instructions from being executed until the load has been performed.
  69  */
  70 #define data_barrier(x) \
  71         asm volatile("twi 0,%0,0; isync" : : "r" (x) : "memory");
  72
  73 struct task_struct;
  74 struct pt_regs;
  75
  76 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
  77
  78 extern int (*__debugger)(struct pt_regs *regs);
  79 extern int (*__debugger_ipi)(struct pt_regs *regs);
  80 extern int (*__debugger_bpt)(struct pt_regs *regs);
  81 extern int (*__debugger_sstep)(struct pt_regs *regs);
  82 extern int (*__debugger_iabr_match)(struct pt_regs *regs);
  83 extern int (*__debugger_dabr_match)(struct pt_regs *regs);
  84 extern int (*__debugger_fault_handler)(struct pt_regs *regs);
  85
  86 #define DEBUGGER_BOILERPLATE(__NAME) \
  87 static inline int __NAME(struct pt_regs *regs) \
  88 { \
  89         if (unlikely(__ ## __NAME)) \
  90                 return __ ## __NAME(regs); \
  91         return 0; \
  92 }
  93
  94 DEBUGGER_BOILERPLATE(debugger)
  95 DEBUGGER_BOILERPLATE(debugger_ipi)
  96 DEBUGGER_BOILERPLATE(debugger_bpt)
  97 DEBUGGER_BOILERPLATE(debugger_sstep)
  98 DEBUGGER_BOILERPLATE(debugger_iabr_match)
  99 DEBUGGER_BOILERPLATE(debugger_dabr_match)
 100 DEBUGGER_BOILERPLATE(debugger_fault_handler)
 101
 102 #else
 103 static inline int debugger(struct pt_regs *regs) { return 0; }
 104 static inline int debugger_ipi(struct pt_regs *regs) { return 0; }
 105 static inline int debugger_bpt(struct pt_regs *regs) { return 0; }
 106 static inline int debugger_sstep(struct pt_regs *regs) { return 0; }
 107 static inline int debugger_iabr_match(struct pt_regs *regs) { return 0; }
 108 static inline int debugger_dabr_match(struct pt_regs *regs) { return 0; }
 109 static inline int debugger_fault_handler(struct pt_regs *regs) { return 0; }
 110 #endif
 111
 112 extern int set_dabr(unsigned long dabr);
 113 extern void print_backtrace(unsigned long *);
 114 extern void show_regs(struct pt_regs * regs);
 115 extern void flush_instruction_cache(void);
 116 extern void hard_reset_now(void);
 117 extern void poweroff_now(void);
 118
 119 #ifdef CONFIG_6xx
 120 extern long _get_L2CR(void);
 121 extern long _get_L3CR(void);
 122 extern void _set_L2CR(unsigned long);
 123 extern void _set_L3CR(unsigned long);
 124 #else
 125 #define _get_L2CR()     0L
 126 #define _get_L3CR()     0L
 127 #define _set_L2CR(val)  do { } while(0)
 128 #define _set_L3CR(val)  do { } while(0)
 129 #endif
 130
 131 extern void via_cuda_init(void);
 132 extern void read_rtc_time(void);
 133 extern void pmac_find_display(void);
 134 extern void giveup_fpu(struct task_struct *);
 135 extern void disable_kernel_fp(void);
 136 extern void enable_kernel_fp(void);
 137 extern void flush_fp_to_thread(struct task_struct *);
 138 extern void enable_kernel_altivec(void);
 139 extern void giveup_altivec(struct task_struct *);
 140 extern void load_up_altivec(struct task_struct *);
 141 extern int emulate_altivec(struct pt_regs *);
 142 extern void __giveup_vsx(struct task_struct *);
 143 extern void giveup_vsx(struct task_struct *);
 144 extern void enable_kernel_spe(void);
 145 extern void giveup_spe(struct task_struct *);
 146 extern void load_up_spe(struct task_struct *);
 147 extern int fix_alignment(struct pt_regs *);
 148 extern void cvt_fd(float *from, double *to, struct thread_struct *thread);
 149 extern void cvt_df(double *from, float *to, struct thread_struct *thread);
 150
 151 #ifndef CONFIG_SMP
 152 extern void discard_lazy_cpu_state(void);
 153 #else
 154 static inline void discard_lazy_cpu_state(void)
 155 {
 156 }
 157 #endif
 158
 159 #ifdef CONFIG_ALTIVEC
 160 extern void flush_altivec_to_thread(struct task_struct *);
 161 #else
 162 static inline void flush_altivec_to_thread(struct task_struct *t)
 163 {
 164 }
 165 #endif
 166
 167 #ifdef CONFIG_VSX
 168 extern void flush_vsx_to_thread(struct task_struct *);
 169 #else
 170 static inline void flush_vsx_to_thread(struct task_struct *t)
 171 {
 172 }
 173 #endif
 174
 175 #ifdef CONFIG_SPE
 176 extern void flush_spe_to_thread(struct task_struct *);
 177 #else
 178 static inline void flush_spe_to_thread(struct task_struct *t)
 179 {
 180 }
 181 #endif
 182
 183 extern int call_rtas(const char *, int, int, unsigned long *, ...);
 184 extern void cacheable_memzero(void *p, unsigned int nb);
 185 extern void *cacheable_memcpy(void *, const void *, unsigned int);
 186 extern int do_page_fault(struct pt_regs *, unsigned long, unsigned long);
 187 extern void bad_page_fault(struct pt_regs *, unsigned long, int);
 188 extern int die(const char *, struct pt_regs *, long);
 189 extern void _exception(int, struct pt_regs *, int, unsigned long);
 190 extern void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
 191
 192 #ifdef CONFIG_BOOKE_WDT
 193 extern u32 booke_wdt_enabled;
 194 extern u32 booke_wdt_period;
 195 #endif /* CONFIG_BOOKE_WDT */
 196
 197 struct device_node;
 198 extern void note_scsi_host(struct device_node *, void *);
 199
 200 extern struct task_struct *__switch_to(struct task_struct *,
 201         struct task_struct *);
 202 #define switch_to(prev, next, last)     ((last) = __switch_to((prev), (next)))
 203
 204 struct thread_struct;
 205 extern struct task_struct *_switch(struct thread_struct *prev,
 206                                    struct thread_struct *next);
 207
 208 extern unsigned int rtas_data;
 209 extern int mem_init_done;       /* set on boot once kmalloc can be called */
 210 extern int init_bootmem_done;   /* set on !NUMA once bootmem is available */
 211 extern unsigned long memory_limit;
 212 extern unsigned long klimit;
 213
 214 extern void *alloc_maybe_bootmem(size_t size, gfp_t mask);
 215 extern void *zalloc_maybe_bootmem(size_t size, gfp_t mask);
 216
 217 extern int powersave_nap;       /* set if nap mode can be used in idle loop */
 218
 219 /*
 220  * Atomic exchange
 221  *
 222  * Changes the memory location '*ptr' to be val and returns
 223  * the previous value stored there.
 224  */
 225 static __always_inline unsigned long
 226 __xchg_u32(volatile void *p, unsigned long val)
 227 {
 228         unsigned long prev;
 229
 230         __asm__ __volatile__(
 231         LWSYNC_ON_SMP
 232 "1:     lwarx   %0,0,%2 \n"
 233         PPC405_ERR77(0,%2)
 234 "       stwcx.  %3,0,%2 \n\
 235         bne-    1b"
 236         ISYNC_ON_SMP
 237         : "=&r" (prev), "+m" (*(volatile unsigned int *)p)
 238         : "r" (p), "r" (val)
 239         : "cc", "memory");
 240
 241         return prev;
 242 }
 243
 244 /*
 245  * Atomic exchange
 246  *
 247  * Changes the memory location '*ptr' to be val and returns
 248  * the previous value stored there.
 249  */
 250 static __always_inline unsigned long
 251 __xchg_u32_local(volatile void *p, unsigned long val)
 252 {
 253         unsigned long prev;
 254
 255         __asm__ __volatile__(
 256 "1:     lwarx   %0,0,%2 \n"
 257         PPC405_ERR77(0,%2)
 258 "       stwcx.  %3,0,%2 \n\
 259         bne-    1b"
 260         : "=&r" (prev), "+m" (*(volatile unsigned int *)p)
 261         : "r" (p), "r" (val)
 262         : "cc", "memory");
 263
 264         return prev;
 265 }
 266
 267 #ifdef CONFIG_PPC64
 268 static __always_inline unsigned long
 269 __xchg_u64(volatile void *p, unsigned long val)
 270 {
 271         unsigned long prev;
 272
 273         __asm__ __volatile__(
 274         LWSYNC_ON_SMP
 275 "1:     ldarx   %0,0,%2 \n"
 276         PPC405_ERR77(0,%2)
 277 "       stdcx.  %3,0,%2 \n\
 278         bne-    1b"
 279         ISYNC_ON_SMP
 280         : "=&r" (prev), "+m" (*(volatile unsigned long *)p)
 281         : "r" (p), "r" (val)
 282         : "cc", "memory");
 283
 284         return prev;
 285 }
 286
 287 static __always_inline unsigned long
 288 __xchg_u64_local(volatile void *p, unsigned long val)
 289 {
 290         unsigned long prev;
 291
 292         __asm__ __volatile__(
 293 "1:     ldarx   %0,0,%2 \n"
 294         PPC405_ERR77(0,%2)
 295 "       stdcx.  %3,0,%2 \n\
 296         bne-    1b"
 297         : "=&r" (prev), "+m" (*(volatile unsigned long *)p)
 298         : "r" (p), "r" (val)
 299         : "cc", "memory");
 300
 301         return prev;
 302 }
 303 #endif
 304
 305 /*
 306  * This function doesn't exist, so you'll get a linker error
 307  * if something tries to do an invalid xchg().
 308  */
 309 extern void __xchg_called_with_bad_pointer(void);
 310
 311 static __always_inline unsigned long
 312 __xchg(volatile void *ptr, unsigned long x, unsigned int size)
 313 {
 314         switch (size) {
 315         case 4:
 316                 return __xchg_u32(ptr, x);
 317 #ifdef CONFIG_PPC64
 318         case 8:
 319                 return __xchg_u64(ptr, x);
 320 #endif
 321         }
 322         __xchg_called_with_bad_pointer();
 323         return x;
 324 }
 325
 326 static __always_inline unsigned long
 327 __xchg_local(volatile void *ptr, unsigned long x, unsigned int size)
 328 {
 329         switch (size) {
 330         case 4:
 331                 return __xchg_u32_local(ptr, x);
 332 #ifdef CONFIG_PPC64
 333         case 8:
 334                 return __xchg_u64_local(ptr, x);
 335 #endif
 336         }
 337         __xchg_called_with_bad_pointer();
 338         return x;
 339 }
 340 #define xchg(ptr,x)                                                          \
 341   ({                                                                         \
 342      __typeof__(*(ptr)) _x_ = (x);                                           \
 343      (__typeof__(*(ptr))) __xchg((ptr), (unsigned long)_x_, sizeof(*(ptr))); \
 344   })
 345
 346 #define xchg_local(ptr,x)                                                    \
 347   ({                                                                         \
 348      __typeof__(*(ptr)) _x_ = (x);                                           \
 349      (__typeof__(*(ptr))) __xchg_local((ptr),                                \
 350                 (unsigned long)_x_, sizeof(*(ptr)));                         \
 351   })
 352
 353 /*
 354  * Compare and exchange - if *p == old, set it to new,
 355  * and return the old value of *p.
 356  */
 357 #define __HAVE_ARCH_CMPXCHG     1
 358
 359 static __always_inline unsigned long
 360 __cmpxchg_u32(volatile unsigned int *p, unsigned long old, unsigned long new)
 361 {
 362         unsigned int prev;
 363
 364         __asm__ __volatile__ (
 365         LWSYNC_ON_SMP
 366 "1:     lwarx   %0,0,%2         # __cmpxchg_u32\n\
 367         cmpw    0,%0,%3\n\
 368         bne-    2f\n"
 369         PPC405_ERR77(0,%2)
 370 "       stwcx.  %4,0,%2\n\
 371         bne-    1b"
 372         ISYNC_ON_SMP
 373         "\n\
 374 2:"
 375         : "=&r" (prev), "+m" (*p)
 376         : "r" (p), "r" (old), "r" (new)
 377         : "cc", "memory");
 378
 379         return prev;
 380 }
 381
 382 static __always_inline unsigned long
 383 __cmpxchg_u32_local(volatile unsigned int *p, unsigned long old,
 384                         unsigned long new)
 385 {
 386         unsigned int prev;
 387
 388         __asm__ __volatile__ (
 389 "1:     lwarx   %0,0,%2         # __cmpxchg_u32\n\
 390         cmpw    0,%0,%3\n\
 391         bne-    2f\n"
 392         PPC405_ERR77(0,%2)
 393 "       stwcx.  %4,0,%2\n\
 394         bne-    1b"
 395         "\n\
 396 2:"
 397         : "=&r" (prev), "+m" (*p)
 398         : "r" (p), "r" (old), "r" (new)
 399         : "cc", "memory");
 400
 401         return prev;
 402 }
 403
 404 #ifdef CONFIG_PPC64
 405 static __always_inline unsigned long
 406 __cmpxchg_u64(volatile unsigned long *p, unsigned long old, unsigned long new)
 407 {
 408         unsigned long prev;
 409
 410         __asm__ __volatile__ (
 411         LWSYNC_ON_SMP
 412 "1:     ldarx   %0,0,%2         # __cmpxchg_u64\n\
 413         cmpd    0,%0,%3\n\
 414         bne-    2f\n\
 415         stdcx.  %4,0,%2\n\
 416         bne-    1b"
 417         ISYNC_ON_SMP
 418         "\n\
 419 2:"
 420         : "=&r" (prev), "+m" (*p)
 421         : "r" (p), "r" (old), "r" (new)
 422         : "cc", "memory");
 423
 424         return prev;
 425 }
 426
 427 static __always_inline unsigned long
 428 __cmpxchg_u64_local(volatile unsigned long *p, unsigned long old,
 429                         unsigned long new)
 430 {
 431         unsigned long prev;
 432
 433         __asm__ __volatile__ (
 434 "1:     ldarx   %0,0,%2         # __cmpxchg_u64\n\
 435         cmpd    0,%0,%3\n\
 436         bne-    2f\n\
 437         stdcx.  %4,0,%2\n\
 438         bne-    1b"
 439         "\n\
 440 2:"
 441         : "=&r" (prev), "+m" (*p)
 442         : "r" (p), "r" (old), "r" (new)
 443         : "cc", "memory");
 444
 445         return prev;
 446 }
 447 #endif
 448
 449 /* This function doesn't exist, so you'll get a linker error
 450    if something tries to do an invalid cmpxchg().  */
 451 extern void __cmpxchg_called_with_bad_pointer(void);
 452
 453 static __always_inline unsigned long
 454 __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new,
 455           unsigned int size)
 456 {
 457         switch (size) {
 458         case 4:
 459                 return __cmpxchg_u32(ptr, old, new);
 460 #ifdef CONFIG_PPC64
 461         case 8:
 462                 return __cmpxchg_u64(ptr, old, new);
 463 #endif
 464         }
 465         __cmpxchg_called_with_bad_pointer();
 466         return old;
 467 }
 468
 469 static __always_inline unsigned long
 470 __cmpxchg_local(volatile void *ptr, unsigned long old, unsigned long new,
 471           unsigned int size)
 472 {
 473         switch (size) {
 474         case 4:
 475                 return __cmpxchg_u32_local(ptr, old, new);
 476 #ifdef CONFIG_PPC64
 477         case 8:
 478                 return __cmpxchg_u64_local(ptr, old, new);
 479 #endif
 480         }
 481         __cmpxchg_called_with_bad_pointer();
 482         return old;
 483 }
 484
 485 #define cmpxchg(ptr, o, n)                                               \
 486   ({                                                                     \
 487      __typeof__(*(ptr)) _o_ = (o);                                       \
 488      __typeof__(*(ptr)) _n_ = (n);                                       \
 489      (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_,           \
 490                                     (unsigned long)_n_, sizeof(*(ptr))); \
 491   })
 492
 493
 494 #define cmpxchg_local(ptr, o, n)                                         \
 495   ({                                                                     \
 496      __typeof__(*(ptr)) _o_ = (o);                                       \
 497      __typeof__(*(ptr)) _n_ = (n);                                       \
 498      (__typeof__(*(ptr))) __cmpxchg_local((ptr), (unsigned long)_o_,     \
 499                                     (unsigned long)_n_, sizeof(*(ptr))); \
 500   })
 501
 502 #ifdef CONFIG_PPC64
 503 /*
 504  * We handle most unaligned accesses in hardware. On the other hand
 505  * unaligned DMA can be very expensive on some ppc64 IO chips (it does
 506  * powers of 2 writes until it reaches sufficient alignment).
 507  *
 508  * Based on this we disable the IP header alignment in network drivers.
 509  * We also modify NET_SKB_PAD to be a cacheline in size, thus maintaining
 510  * cacheline alignment of buffers.
 511  */
 512 #define NET_IP_ALIGN    0
 513 #define NET_SKB_PAD     L1_CACHE_BYTES
 514
 515 #define cmpxchg64(ptr, o, n)                                            \
 516   ({                                                                    \
 517         BUILD_BUG_ON(sizeof(*(ptr)) != 8);                              \
 518         cmpxchg((ptr), (o), (n));                                       \
 519   })
 520 #define cmpxchg64_local(ptr, o, n)                                      \
 521   ({                                                                    \
 522         BUILD_BUG_ON(sizeof(*(ptr)) != 8);                              \
 523         cmpxchg_local((ptr), (o), (n));                                 \
 524   })
 525 #else
 526 #include <asm-generic/cmpxchg-local.h>
 527 #define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
 528 #endif
 529
 530 #define arch_align_stack(x) (x)
 531
 532 /* Used in very early kernel initialization. */
 533 extern unsigned long reloc_offset(void);
 534 extern unsigned long add_reloc_offset(unsigned long);
 535 extern void reloc_got2(unsigned long);
 536
 537 #define PTRRELOC(x)     ((typeof(x)) add_reloc_offset((unsigned long)(x)))
 538
 539 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
 540 extern void account_system_vtime(struct task_struct *);
 541 #endif
 542
 543 extern struct dentry *powerpc_debugfs_root;
 544
 545 #endif /* __KERNEL__ */
 546 #endif /* _ASM_POWERPC_SYSTEM_H */