arch/frv/mb93090-mb00/pci-frv.c

   1 /* pci-frv.c: low-level PCI access routines
   2  *
   3  * Copyright (C) 2003-5 Red Hat, Inc. All Rights Reserved.
   4  * Written by David Howells (dhowells@redhat.com)
   5  * - Derived from the i386 equivalent stuff
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * as published by the Free Software Foundation; either version
  10  * 2 of the License, or (at your option) any later version.
  11  */
  12
  13 #include <linux/types.h>
  14 #include <linux/kernel.h>
  15 #include <linux/pci.h>
  16 #include <linux/init.h>
  17 #include <linux/ioport.h>
  18 #include <linux/errno.h>
  19
  20 #include "pci-frv.h"
  21
  22 /*
  23  * We need to avoid collisions with `mirrored' VGA ports
  24  * and other strange ISA hardware, so we always want the
  25  * addresses to be allocated in the 0x000-0x0ff region
  26  * modulo 0x400.
  27  *
  28  * Why? Because some silly external IO cards only decode
  29  * the low 10 bits of the IO address. The 0x00-0xff region
  30  * is reserved for motherboard devices that decode all 16
  31  * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
  32  * but we want to try to avoid allocating at 0x2900-0x2bff
  33  * which might have be mirrored at 0x0100-0x03ff..
  34  */
  35 void
  36 pcibios_align_resource(void *data, struct resource *res,
  37                        resource_size_t size, resource_size_t align)
  38 {
  39         if (res->flags & IORESOURCE_IO) {
  40                 resource_size_t start = res->start;
  41
  42                 if (start & 0x300) {
  43                         start = (start + 0x3ff) & ~0x3ff;
  44                         res->start = start;
  45                 }
  46         }
  47 }
  48
  49
  50 /*
  51  *  Handle resources of PCI devices.  If the world were perfect, we could
  52  *  just allocate all the resource regions and do nothing more.  It isn't.
  53  *  On the other hand, we cannot just re-allocate all devices, as it would
  54  *  require us to know lots of host bridge internals.  So we attempt to
  55  *  keep as much of the original configuration as possible, but tweak it
  56  *  when it's found to be wrong.
  57  *
  58  *  Known BIOS problems we have to work around:
  59  *      - I/O or memory regions not configured
  60  *      - regions configured, but not enabled in the command register
  61  *      - bogus I/O addresses above 64K used
  62  *      - expansion ROMs left enabled (this may sound harmless, but given
  63  *        the fact the PCI specs explicitly allow address decoders to be
  64  *        shared between expansion ROMs and other resource regions, it's
  65  *        at least dangerous)
  66  *
  67  *  Our solution:
  68  *      (1) Allocate resources for all buses behind PCI-to-PCI bridges.
  69  *          This gives us fixed barriers on where we can allocate.
  70  *      (2) Allocate resources for all enabled devices.  If there is
  71  *          a collision, just mark the resource as unallocated. Also
  72  *          disable expansion ROMs during this step.
  73  *      (3) Try to allocate resources for disabled devices.  If the
  74  *          resources were assigned correctly, everything goes well,
  75  *          if they weren't, they won't disturb allocation of other
  76  *          resources.
  77  *      (4) Assign new addresses to resources which were either
  78  *          not configured at all or misconfigured.  If explicitly
  79  *          requested by the user, configure expansion ROM address
  80  *          as well.
  81  */
  82
  83 static void __init pcibios_allocate_bus_resources(struct list_head *bus_list)
  84 {
  85         struct list_head *ln;
  86         struct pci_bus *bus;
  87         struct pci_dev *dev;
  88         int idx;
  89         struct resource *r, *pr;
  90
  91         /* Depth-First Search on bus tree */
  92         for (ln=bus_list->next; ln != bus_list; ln=ln->next) {
  93                 bus = pci_bus_b(ln);
  94                 if ((dev = bus->self)) {
  95                         for (idx = PCI_BRIDGE_RESOURCES; idx < PCI_NUM_RESOURCES; idx++) {
  96                                 r = &dev->resource[idx];
  97                                 if (!r->start)
  98                                         continue;
  99                                 pr = pci_find_parent_resource(dev, r);
 100                                 if (!pr || request_resource(pr, r) < 0)
 101                                         printk(KERN_ERR "PCI: Cannot allocate resource region %d of bridge %s\n", idx, pci_name(dev));
 102                         }
 103                 }
 104                 pcibios_allocate_bus_resources(&bus->children);
 105         }
 106 }
 107
 108 static void __init pcibios_allocate_resources(int pass)
 109 {
 110         struct pci_dev *dev = NULL;
 111         int idx, disabled;
 112         u16 command;
 113         struct resource *r, *pr;
 114
 115         for_each_pci_dev(dev) {
 116                 pci_read_config_word(dev, PCI_COMMAND, &command);
 117                 for(idx = 0; idx < 6; idx++) {
 118                         r = &dev->resource[idx];
 119                         if (r->parent)          /* Already allocated */
 120                                 continue;
 121                         if (!r->start)          /* Address not assigned at all */
 122                                 continue;
 123                         if (r->flags & IORESOURCE_IO)
 124                                 disabled = !(command & PCI_COMMAND_IO);
 125                         else
 126                                 disabled = !(command & PCI_COMMAND_MEMORY);
 127                         if (pass == disabled) {
 128                                 DBG("PCI: Resource %08lx-%08lx (f=%lx, d=%d, p=%d)\n",
 129                                     r->start, r->end, r->flags, disabled, pass);
 130                                 pr = pci_find_parent_resource(dev, r);
 131                                 if (!pr || request_resource(pr, r) < 0) {
 132                                         printk(KERN_ERR "PCI: Cannot allocate resource region %d of device %s\n", idx, pci_name(dev));
 133                                         /* We'll assign a new address later */
 134                                         r->end -= r->start;
 135                                         r->start = 0;
 136                                 }
 137                         }
 138                 }
 139                 if (!pass) {
 140                         r = &dev->resource[PCI_ROM_RESOURCE];
 141                         if (r->flags & IORESOURCE_ROM_ENABLE) {
 142                                 /* Turn the ROM off, leave the resource region, but keep it unregistered. */
 143                                 u32 reg;
 144                                 DBG("PCI: Switching off ROM of %s\n", pci_name(dev));
 145                                 r->flags &= ~IORESOURCE_ROM_ENABLE;
 146                                 pci_read_config_dword(dev, dev->rom_base_reg, &reg);
 147                                 pci_write_config_dword(dev, dev->rom_base_reg, reg & ~PCI_ROM_ADDRESS_ENABLE);
 148                         }
 149                 }
 150         }
 151 }
 152
 153 static void __init pcibios_assign_resources(void)
 154 {
 155         struct pci_dev *dev = NULL;
 156         int idx;
 157         struct resource *r;
 158
 159         for_each_pci_dev(dev) {
 160                 int class = dev->class >> 8;
 161
 162                 /* Don't touch classless devices and host bridges */
 163                 if (!class || class == PCI_CLASS_BRIDGE_HOST)
 164                         continue;
 165
 166                 for(idx=0; idx<6; idx++) {
 167                         r = &dev->resource[idx];
 168
 169                         /*
 170                          *  Don't touch IDE controllers and I/O ports of video cards!
 171                          */
 172                         if ((class == PCI_CLASS_STORAGE_IDE && idx < 4) ||
 173                             (class == PCI_CLASS_DISPLAY_VGA && (r->flags & IORESOURCE_IO)))
 174                                 continue;
 175
 176                         /*
 177                          *  We shall assign a new address to this resource, either because
 178                          *  the BIOS forgot to do so or because we have decided the old
 179                          *  address was unusable for some reason.
 180                          */
 181                         if (!r->start && r->end)
 182                                 pci_assign_resource(dev, idx);
 183                 }
 184
 185                 if (pci_probe & PCI_ASSIGN_ROMS) {
 186                         r = &dev->resource[PCI_ROM_RESOURCE];
 187                         r->end -= r->start;
 188                         r->start = 0;
 189                         if (r->end)
 190                                 pci_assign_resource(dev, PCI_ROM_RESOURCE);
 191                 }
 192         }
 193 }
 194
 195 void __init pcibios_resource_survey(void)
 196 {
 197         DBG("PCI: Allocating resources\n");
 198         pcibios_allocate_bus_resources(&pci_root_buses);
 199         pcibios_allocate_resources(0);
 200         pcibios_allocate_resources(1);
 201         pcibios_assign_resources();
 202 }
 203
 204 /*
 205  *  If we set up a device for bus mastering, we need to check the latency
 206  *  timer as certain crappy BIOSes forget to set it properly.
 207  */
 208 unsigned int pcibios_max_latency = 255;
 209
 210 void pcibios_set_master(struct pci_dev *dev)
 211 {
 212         u8 lat;
 213         pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
 214         if (lat < 16)
 215                 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
 216         else if (lat > pcibios_max_latency)
 217                 lat = pcibios_max_latency;
 218         else
 219                 return;
 220         printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n", pci_name(dev), lat);
 221         pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
 222 }