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[SCSI] qla4xxx: Use polling mode for disable interrupt mailbox completion
[linux-2.6.git] / drivers / scsi / ipr.h
blob13f425fb8851f5206f74be7a3c0615dea0b0ca8d
1 /*
2 * ipr.h -- driver for IBM Power Linux RAID adapters
3 *
4 * Written By: Brian King <brking@us.ibm.com>, IBM Corporation
5 *
6 * Copyright (C) 2003, 2004 IBM Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 * Alan Cox <alan@lxorguk.ukuu.org.uk> - Removed several careless u32/dma_addr_t errors
23 * that broke 64bit platforms.
24 */
25
26 #ifndef _IPR_H
27 #define _IPR_H
28
29 #include <asm/unaligned.h>
30 #include <linux/types.h>
31 #include <linux/completion.h>
32 #include <linux/libata.h>
33 #include <linux/list.h>
34 #include <linux/kref.h>
35 #include <scsi/scsi.h>
36 #include <scsi/scsi_cmnd.h>
37
38 /*
39 * Literals
40 */
41 #define IPR_DRIVER_VERSION "2.5.1"
42 #define IPR_DRIVER_DATE "(August 10, 2010)"
43
44 /*
45 * IPR_MAX_CMD_PER_LUN: This defines the maximum number of outstanding
46 * ops per device for devices not running tagged command queuing.
47 * This can be adjusted at runtime through sysfs device attributes.
48 */
49 #define IPR_MAX_CMD_PER_LUN 6
50 #define IPR_MAX_CMD_PER_ATA_LUN 1
51
52 /*
53 * IPR_NUM_BASE_CMD_BLKS: This defines the maximum number of
54 * ops the mid-layer can send to the adapter.
55 */
56 #define IPR_NUM_BASE_CMD_BLKS 100
57
58 #define PCI_DEVICE_ID_IBM_OBSIDIAN_E 0x0339
59
60 #define PCI_DEVICE_ID_IBM_CROC_FPGA_E2 0x033D
61 #define PCI_DEVICE_ID_IBM_CROC_ASIC_E2 0x034A
62
63 #define IPR_SUBS_DEV_ID_2780 0x0264
64 #define IPR_SUBS_DEV_ID_5702 0x0266
65 #define IPR_SUBS_DEV_ID_5703 0x0278
66 #define IPR_SUBS_DEV_ID_572E 0x028D
67 #define IPR_SUBS_DEV_ID_573E 0x02D3
68 #define IPR_SUBS_DEV_ID_573D 0x02D4
69 #define IPR_SUBS_DEV_ID_571A 0x02C0
70 #define IPR_SUBS_DEV_ID_571B 0x02BE
71 #define IPR_SUBS_DEV_ID_571E 0x02BF
72 #define IPR_SUBS_DEV_ID_571F 0x02D5
73 #define IPR_SUBS_DEV_ID_572A 0x02C1
74 #define IPR_SUBS_DEV_ID_572B 0x02C2
75 #define IPR_SUBS_DEV_ID_572F 0x02C3
76 #define IPR_SUBS_DEV_ID_574E 0x030A
77 #define IPR_SUBS_DEV_ID_575B 0x030D
78 #define IPR_SUBS_DEV_ID_575C 0x0338
79 #define IPR_SUBS_DEV_ID_57B3 0x033A
80 #define IPR_SUBS_DEV_ID_57B7 0x0360
81 #define IPR_SUBS_DEV_ID_57B8 0x02C2
82
83 #define IPR_SUBS_DEV_ID_57B4 0x033B
84 #define IPR_SUBS_DEV_ID_57B2 0x035F
85 #define IPR_SUBS_DEV_ID_57C4 0x0354
86 #define IPR_SUBS_DEV_ID_57C6 0x0357
87 #define IPR_SUBS_DEV_ID_57CC 0x035C
88
89 #define IPR_SUBS_DEV_ID_57B5 0x033C
90 #define IPR_SUBS_DEV_ID_57CE 0x035E
91 #define IPR_SUBS_DEV_ID_57B1 0x0355
92
93 #define IPR_SUBS_DEV_ID_574D 0x0356
94 #define IPR_SUBS_DEV_ID_575D 0x035D
95
96 #define IPR_NAME "ipr"
97
98 /*
99 * Return codes
100 */
101 #define IPR_RC_JOB_CONTINUE 1
102 #define IPR_RC_JOB_RETURN 2
103
104 /*
105 * IOASCs
106 */
107 #define IPR_IOASC_NR_INIT_CMD_REQUIRED 0x02040200
108 #define IPR_IOASC_NR_IOA_RESET_REQUIRED 0x02048000
109 #define IPR_IOASC_SYNC_REQUIRED 0x023f0000
110 #define IPR_IOASC_MED_DO_NOT_REALLOC 0x03110C00
111 #define IPR_IOASC_HW_SEL_TIMEOUT 0x04050000
112 #define IPR_IOASC_HW_DEV_BUS_STATUS 0x04448500
113 #define IPR_IOASC_IOASC_MASK 0xFFFFFF00
114 #define IPR_IOASC_SCSI_STATUS_MASK 0x000000FF
115 #define IPR_IOASC_IR_INVALID_REQ_TYPE_OR_PKT 0x05240000
116 #define IPR_IOASC_IR_RESOURCE_HANDLE 0x05250000
117 #define IPR_IOASC_IR_NO_CMDS_TO_2ND_IOA 0x05258100
118 #define IPR_IOASA_IR_DUAL_IOA_DISABLED 0x052C8000
119 #define IPR_IOASC_BUS_WAS_RESET 0x06290000
120 #define IPR_IOASC_BUS_WAS_RESET_BY_OTHER 0x06298000
121 #define IPR_IOASC_ABORTED_CMD_TERM_BY_HOST 0x0B5A0000
122
123 #define IPR_FIRST_DRIVER_IOASC 0x10000000
124 #define IPR_IOASC_IOA_WAS_RESET 0x10000001
125 #define IPR_IOASC_PCI_ACCESS_ERROR 0x10000002
126
127 /* Driver data flags */
128 #define IPR_USE_LONG_TRANSOP_TIMEOUT 0x00000001
129 #define IPR_USE_PCI_WARM_RESET 0x00000002
130
131 #define IPR_DEFAULT_MAX_ERROR_DUMP 984
132 #define IPR_NUM_LOG_HCAMS 2
133 #define IPR_NUM_CFG_CHG_HCAMS 2
134 #define IPR_NUM_HCAMS (IPR_NUM_LOG_HCAMS + IPR_NUM_CFG_CHG_HCAMS)
135
136 #define IPR_MAX_SIS64_TARGETS_PER_BUS 1024
137 #define IPR_MAX_SIS64_LUNS_PER_TARGET 0xffffffff
138
139 #define IPR_MAX_NUM_TARGETS_PER_BUS 256
140 #define IPR_MAX_NUM_LUNS_PER_TARGET 256
141 #define IPR_MAX_NUM_VSET_LUNS_PER_TARGET 8
142 #define IPR_VSET_BUS 0xff
143 #define IPR_IOA_BUS 0xff
144 #define IPR_IOA_TARGET 0xff
145 #define IPR_IOA_LUN 0xff
146 #define IPR_MAX_NUM_BUSES 16
147 #define IPR_MAX_BUS_TO_SCAN IPR_MAX_NUM_BUSES
148
149 #define IPR_NUM_RESET_RELOAD_RETRIES 3
150
151 /* We need resources for HCAMS, IOA reset, IOA bringdown, and ERP */
152 #define IPR_NUM_INTERNAL_CMD_BLKS (IPR_NUM_HCAMS + \
153 ((IPR_NUM_RESET_RELOAD_RETRIES + 1) * 2) + 4)
154
155 #define IPR_MAX_COMMANDS IPR_NUM_BASE_CMD_BLKS
156 #define IPR_NUM_CMD_BLKS (IPR_NUM_BASE_CMD_BLKS + \
157 IPR_NUM_INTERNAL_CMD_BLKS)
158
159 #define IPR_MAX_PHYSICAL_DEVS 192
160 #define IPR_DEFAULT_SIS64_DEVS 1024
161 #define IPR_MAX_SIS64_DEVS 4096
162
163 #define IPR_MAX_SGLIST 64
164 #define IPR_IOA_MAX_SECTORS 32767
165 #define IPR_VSET_MAX_SECTORS 512
166 #define IPR_MAX_CDB_LEN 16
167 #define IPR_MAX_HRRQ_RETRIES 3
168
169 #define IPR_DEFAULT_BUS_WIDTH 16
170 #define IPR_80MBs_SCSI_RATE ((80 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
171 #define IPR_U160_SCSI_RATE ((160 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
172 #define IPR_U320_SCSI_RATE ((320 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
173 #define IPR_MAX_SCSI_RATE(width) ((320 * 10) / ((width) / 8))
174
175 #define IPR_IOA_RES_HANDLE 0xffffffff
176 #define IPR_INVALID_RES_HANDLE 0
177 #define IPR_IOA_RES_ADDR 0x00ffffff
178
179 /*
180 * Adapter Commands
181 */
182 #define IPR_QUERY_RSRC_STATE 0xC2
183 #define IPR_RESET_DEVICE 0xC3
184 #define IPR_RESET_TYPE_SELECT 0x80
185 #define IPR_LUN_RESET 0x40
186 #define IPR_TARGET_RESET 0x20
187 #define IPR_BUS_RESET 0x10
188 #define IPR_ATA_PHY_RESET 0x80
189 #define IPR_ID_HOST_RR_Q 0xC4
190 #define IPR_QUERY_IOA_CONFIG 0xC5
191 #define IPR_CANCEL_ALL_REQUESTS 0xCE
192 #define IPR_HOST_CONTROLLED_ASYNC 0xCF
193 #define IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE 0x01
194 #define IPR_HCAM_CDB_OP_CODE_LOG_DATA 0x02
195 #define IPR_SET_SUPPORTED_DEVICES 0xFB
196 #define IPR_SET_ALL_SUPPORTED_DEVICES 0x80
197 #define IPR_IOA_SHUTDOWN 0xF7
198 #define IPR_WR_BUF_DOWNLOAD_AND_SAVE 0x05
199
200 /*
201 * Timeouts
202 */
203 #define IPR_SHUTDOWN_TIMEOUT (ipr_fastfail ? 60 * HZ : 10 * 60 * HZ)
204 #define IPR_VSET_RW_TIMEOUT (ipr_fastfail ? 30 * HZ : 2 * 60 * HZ)
205 #define IPR_ABBREV_SHUTDOWN_TIMEOUT (10 * HZ)
206 #define IPR_DUAL_IOA_ABBR_SHUTDOWN_TO (2 * 60 * HZ)
207 #define IPR_DEVICE_RESET_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
208 #define IPR_CANCEL_ALL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
209 #define IPR_ABORT_TASK_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
210 #define IPR_INTERNAL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
211 #define IPR_WRITE_BUFFER_TIMEOUT (10 * 60 * HZ)
212 #define IPR_SET_SUP_DEVICE_TIMEOUT (2 * 60 * HZ)
213 #define IPR_REQUEST_SENSE_TIMEOUT (10 * HZ)
214 #define IPR_OPERATIONAL_TIMEOUT (5 * 60)
215 #define IPR_LONG_OPERATIONAL_TIMEOUT (12 * 60)
216 #define IPR_WAIT_FOR_RESET_TIMEOUT (2 * HZ)
217 #define IPR_CHECK_FOR_RESET_TIMEOUT (HZ / 10)
218 #define IPR_WAIT_FOR_BIST_TIMEOUT (2 * HZ)
219 #define IPR_PCI_RESET_TIMEOUT (HZ / 2)
220 #define IPR_DUMP_TIMEOUT (15 * HZ)
221 #define IPR_DUMP_DELAY_SECONDS 4
222 #define IPR_DUMP_DELAY_TIMEOUT (IPR_DUMP_DELAY_SECONDS * HZ)
223
224 /*
225 * SCSI Literals
226 */
227 #define IPR_VENDOR_ID_LEN 8
228 #define IPR_PROD_ID_LEN 16
229 #define IPR_SERIAL_NUM_LEN 8
230
231 /*
232 * Hardware literals
233 */
234 #define IPR_FMT2_MBX_ADDR_MASK 0x0fffffff
235 #define IPR_FMT2_MBX_BAR_SEL_MASK 0xf0000000
236 #define IPR_FMT2_MKR_BAR_SEL_SHIFT 28
237 #define IPR_GET_FMT2_BAR_SEL(mbx) \
238 (((mbx) & IPR_FMT2_MBX_BAR_SEL_MASK) >> IPR_FMT2_MKR_BAR_SEL_SHIFT)
239 #define IPR_SDT_FMT2_BAR0_SEL 0x0
240 #define IPR_SDT_FMT2_BAR1_SEL 0x1
241 #define IPR_SDT_FMT2_BAR2_SEL 0x2
242 #define IPR_SDT_FMT2_BAR3_SEL 0x3
243 #define IPR_SDT_FMT2_BAR4_SEL 0x4
244 #define IPR_SDT_FMT2_BAR5_SEL 0x5
245 #define IPR_SDT_FMT2_EXP_ROM_SEL 0x8
246 #define IPR_FMT2_SDT_READY_TO_USE 0xC4D4E3F2
247 #define IPR_FMT3_SDT_READY_TO_USE 0xC4D4E3F3
248 #define IPR_DOORBELL 0x82800000
249 #define IPR_RUNTIME_RESET 0x40000000
250
251 #define IPR_IPL_INIT_MIN_STAGE_TIME 5
252 #define IPR_IPL_INIT_DEFAULT_STAGE_TIME 15
253 #define IPR_IPL_INIT_STAGE_UNKNOWN 0x0
254 #define IPR_IPL_INIT_STAGE_TRANSOP 0xB0000000
255 #define IPR_IPL_INIT_STAGE_MASK 0xff000000
256 #define IPR_IPL_INIT_STAGE_TIME_MASK 0x0000ffff
257 #define IPR_PCII_IPL_STAGE_CHANGE (0x80000000 >> 0)
258
259 #define IPR_PCII_IOA_TRANS_TO_OPER (0x80000000 >> 0)
260 #define IPR_PCII_IOARCB_XFER_FAILED (0x80000000 >> 3)
261 #define IPR_PCII_IOA_UNIT_CHECKED (0x80000000 >> 4)
262 #define IPR_PCII_NO_HOST_RRQ (0x80000000 >> 5)
263 #define IPR_PCII_CRITICAL_OPERATION (0x80000000 >> 6)
264 #define IPR_PCII_IO_DEBUG_ACKNOWLEDGE (0x80000000 >> 7)
265 #define IPR_PCII_IOARRIN_LOST (0x80000000 >> 27)
266 #define IPR_PCII_MMIO_ERROR (0x80000000 >> 28)
267 #define IPR_PCII_PROC_ERR_STATE (0x80000000 >> 29)
268 #define IPR_PCII_HRRQ_UPDATED (0x80000000 >> 30)
269 #define IPR_PCII_CORE_ISSUED_RST_REQ (0x80000000 >> 31)
270
271 #define IPR_PCII_ERROR_INTERRUPTS \
272 (IPR_PCII_IOARCB_XFER_FAILED | IPR_PCII_IOA_UNIT_CHECKED | \
273 IPR_PCII_NO_HOST_RRQ | IPR_PCII_IOARRIN_LOST | IPR_PCII_MMIO_ERROR)
274
275 #define IPR_PCII_OPER_INTERRUPTS \
276 (IPR_PCII_ERROR_INTERRUPTS | IPR_PCII_HRRQ_UPDATED | IPR_PCII_IOA_TRANS_TO_OPER)
277
278 #define IPR_UPROCI_RESET_ALERT (0x80000000 >> 7)
279 #define IPR_UPROCI_IO_DEBUG_ALERT (0x80000000 >> 9)
280 #define IPR_UPROCI_SIS64_START_BIST (0x80000000 >> 23)
281
282 #define IPR_LDUMP_MAX_LONG_ACK_DELAY_IN_USEC 200000 /* 200 ms */
283 #define IPR_LDUMP_MAX_SHORT_ACK_DELAY_IN_USEC 200000 /* 200 ms */
284
285 /*
286 * Dump literals
287 */
288 #define IPR_MAX_IOA_DUMP_SIZE (4 * 1024 * 1024)
289 #define IPR_NUM_SDT_ENTRIES 511
290 #define IPR_MAX_NUM_DUMP_PAGES ((IPR_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1)
291
292 /*
293 * Misc literals
294 */
295 #define IPR_NUM_IOADL_ENTRIES IPR_MAX_SGLIST
296
297 /*
298 * Adapter interface types
299 */
300
301 struct ipr_res_addr {
302 u8 reserved;
303 u8 bus;
304 u8 target;
305 u8 lun;
306 #define IPR_GET_PHYS_LOC(res_addr) \
307 (((res_addr).bus << 16) | ((res_addr).target << 8) | (res_addr).lun)
308 }__attribute__((packed, aligned (4)));
309
310 struct ipr_std_inq_vpids {
311 u8 vendor_id[IPR_VENDOR_ID_LEN];
312 u8 product_id[IPR_PROD_ID_LEN];
313 }__attribute__((packed));
314
315 struct ipr_vpd {
316 struct ipr_std_inq_vpids vpids;
317 u8 sn[IPR_SERIAL_NUM_LEN];
318 }__attribute__((packed));
319
320 struct ipr_ext_vpd {
321 struct ipr_vpd vpd;
322 __be32 wwid[2];
323 }__attribute__((packed));
324
325 struct ipr_ext_vpd64 {
326 struct ipr_vpd vpd;
327 __be32 wwid[4];
328 }__attribute__((packed));
329
330 struct ipr_std_inq_data {
331 u8 peri_qual_dev_type;
332 #define IPR_STD_INQ_PERI_QUAL(peri) ((peri) >> 5)
333 #define IPR_STD_INQ_PERI_DEV_TYPE(peri) ((peri) & 0x1F)
334
335 u8 removeable_medium_rsvd;
336 #define IPR_STD_INQ_REMOVEABLE_MEDIUM 0x80
337
338 #define IPR_IS_DASD_DEVICE(std_inq) \
339 ((IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_DISK) && \
340 !(((std_inq).removeable_medium_rsvd) & IPR_STD_INQ_REMOVEABLE_MEDIUM))
341
342 #define IPR_IS_SES_DEVICE(std_inq) \
343 (IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_ENCLOSURE)
344
345 u8 version;
346 u8 aen_naca_fmt;
347 u8 additional_len;
348 u8 sccs_rsvd;
349 u8 bq_enc_multi;
350 u8 sync_cmdq_flags;
351
352 struct ipr_std_inq_vpids vpids;
353
354 u8 ros_rsvd_ram_rsvd[4];
355
356 u8 serial_num[IPR_SERIAL_NUM_LEN];
357 }__attribute__ ((packed));
358
359 #define IPR_RES_TYPE_AF_DASD 0x00
360 #define IPR_RES_TYPE_GENERIC_SCSI 0x01
361 #define IPR_RES_TYPE_VOLUME_SET 0x02
362 #define IPR_RES_TYPE_REMOTE_AF_DASD 0x03
363 #define IPR_RES_TYPE_GENERIC_ATA 0x04
364 #define IPR_RES_TYPE_ARRAY 0x05
365 #define IPR_RES_TYPE_IOAFP 0xff
366
367 struct ipr_config_table_entry {
368 u8 proto;
369 #define IPR_PROTO_SATA 0x02
370 #define IPR_PROTO_SATA_ATAPI 0x03
371 #define IPR_PROTO_SAS_STP 0x06
372 #define IPR_PROTO_SAS_STP_ATAPI 0x07
373 u8 array_id;
374 u8 flags;
375 #define IPR_IS_IOA_RESOURCE 0x80
376 u8 rsvd_subtype;
377
378 #define IPR_QUEUEING_MODEL(res) ((((res)->flags) & 0x70) >> 4)
379 #define IPR_QUEUE_FROZEN_MODEL 0
380 #define IPR_QUEUE_NACA_MODEL 1
381
382 struct ipr_res_addr res_addr;
383 __be32 res_handle;
384 __be32 lun_wwn[2];
385 struct ipr_std_inq_data std_inq_data;
386 }__attribute__ ((packed, aligned (4)));
387
388 struct ipr_config_table_entry64 {
389 u8 res_type;
390 u8 proto;
391 u8 vset_num;
392 u8 array_id;
393 __be16 flags;
394 __be16 res_flags;
395 #define IPR_QUEUEING_MODEL64(res) ((((res)->res_flags) & 0x7000) >> 12)
396 __be32 res_handle;
397 u8 dev_id_type;
398 u8 reserved[3];
399 __be64 dev_id;
400 __be64 lun;
401 __be64 lun_wwn[2];
402 #define IPR_MAX_RES_PATH_LENGTH 24
403 __be64 res_path;
404 struct ipr_std_inq_data std_inq_data;
405 u8 reserved2[4];
406 __be64 reserved3[2];
407 u8 reserved4[8];
408 }__attribute__ ((packed, aligned (8)));
409
410 struct ipr_config_table_hdr {
411 u8 num_entries;
412 u8 flags;
413 #define IPR_UCODE_DOWNLOAD_REQ 0x10
414 __be16 reserved;
415 }__attribute__((packed, aligned (4)));
416
417 struct ipr_config_table_hdr64 {
418 __be16 num_entries;
419 __be16 reserved;
420 u8 flags;
421 u8 reserved2[11];
422 }__attribute__((packed, aligned (4)));
423
424 struct ipr_config_table {
425 struct ipr_config_table_hdr hdr;
426 struct ipr_config_table_entry dev[0];
427 }__attribute__((packed, aligned (4)));
428
429 struct ipr_config_table64 {
430 struct ipr_config_table_hdr64 hdr64;
431 struct ipr_config_table_entry64 dev[0];
432 }__attribute__((packed, aligned (8)));
433
434 struct ipr_config_table_entry_wrapper {
435 union {
436 struct ipr_config_table_entry *cfgte;
437 struct ipr_config_table_entry64 *cfgte64;
438 } u;
439 };
440
441 struct ipr_hostrcb_cfg_ch_not {
442 union {
443 struct ipr_config_table_entry cfgte;
444 struct ipr_config_table_entry64 cfgte64;
445 } u;
446 u8 reserved[936];
447 }__attribute__((packed, aligned (4)));
448
449 struct ipr_supported_device {
450 __be16 data_length;
451 u8 reserved;
452 u8 num_records;
453 struct ipr_std_inq_vpids vpids;
454 u8 reserved2[16];
455 }__attribute__((packed, aligned (4)));
456
457 /* Command packet structure */
458 struct ipr_cmd_pkt {
459 __be16 reserved; /* Reserved by IOA */
460 u8 request_type;
461 #define IPR_RQTYPE_SCSICDB 0x00
462 #define IPR_RQTYPE_IOACMD 0x01
463 #define IPR_RQTYPE_HCAM 0x02
464 #define IPR_RQTYPE_ATA_PASSTHRU 0x04
465
466 u8 reserved2;
467
468 u8 flags_hi;
469 #define IPR_FLAGS_HI_WRITE_NOT_READ 0x80
470 #define IPR_FLAGS_HI_NO_ULEN_CHK 0x20
471 #define IPR_FLAGS_HI_SYNC_OVERRIDE 0x10
472 #define IPR_FLAGS_HI_SYNC_COMPLETE 0x08
473 #define IPR_FLAGS_HI_NO_LINK_DESC 0x04
474
475 u8 flags_lo;
476 #define IPR_FLAGS_LO_ALIGNED_BFR 0x20
477 #define IPR_FLAGS_LO_DELAY_AFTER_RST 0x10
478 #define IPR_FLAGS_LO_UNTAGGED_TASK 0x00
479 #define IPR_FLAGS_LO_SIMPLE_TASK 0x02
480 #define IPR_FLAGS_LO_ORDERED_TASK 0x04
481 #define IPR_FLAGS_LO_HEAD_OF_Q_TASK 0x06
482 #define IPR_FLAGS_LO_ACA_TASK 0x08
483
484 u8 cdb[16];
485 __be16 timeout;
486 }__attribute__ ((packed, aligned(4)));
487
488 struct ipr_ioarcb_ata_regs { /* 22 bytes */
489 u8 flags;
490 #define IPR_ATA_FLAG_PACKET_CMD 0x80
491 #define IPR_ATA_FLAG_XFER_TYPE_DMA 0x40
492 #define IPR_ATA_FLAG_STATUS_ON_GOOD_COMPLETION 0x20
493 u8 reserved[3];
494
495 __be16 data;
496 u8 feature;
497 u8 nsect;
498 u8 lbal;
499 u8 lbam;
500 u8 lbah;
501 u8 device;
502 u8 command;
503 u8 reserved2[3];
504 u8 hob_feature;
505 u8 hob_nsect;
506 u8 hob_lbal;
507 u8 hob_lbam;
508 u8 hob_lbah;
509 u8 ctl;
510 }__attribute__ ((packed, aligned(4)));
511
512 struct ipr_ioadl_desc {
513 __be32 flags_and_data_len;
514 #define IPR_IOADL_FLAGS_MASK 0xff000000
515 #define IPR_IOADL_GET_FLAGS(x) (be32_to_cpu(x) & IPR_IOADL_FLAGS_MASK)
516 #define IPR_IOADL_DATA_LEN_MASK 0x00ffffff
517 #define IPR_IOADL_GET_DATA_LEN(x) (be32_to_cpu(x) & IPR_IOADL_DATA_LEN_MASK)
518 #define IPR_IOADL_FLAGS_READ 0x48000000
519 #define IPR_IOADL_FLAGS_READ_LAST 0x49000000
520 #define IPR_IOADL_FLAGS_WRITE 0x68000000
521 #define IPR_IOADL_FLAGS_WRITE_LAST 0x69000000
522 #define IPR_IOADL_FLAGS_LAST 0x01000000
523
524 __be32 address;
525 }__attribute__((packed, aligned (8)));
526
527 struct ipr_ioadl64_desc {
528 __be32 flags;
529 __be32 data_len;
530 __be64 address;
531 }__attribute__((packed, aligned (16)));
532
533 struct ipr_ata64_ioadl {
534 struct ipr_ioarcb_ata_regs regs;
535 u16 reserved[5];
536 struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES];
537 }__attribute__((packed, aligned (16)));
538
539 struct ipr_ioarcb_add_data {
540 union {
541 struct ipr_ioarcb_ata_regs regs;
542 struct ipr_ioadl_desc ioadl[5];
543 __be32 add_cmd_parms[10];
544 } u;
545 }__attribute__ ((packed, aligned (4)));
546
547 struct ipr_ioarcb_sis64_add_addr_ecb {
548 __be64 ioasa_host_pci_addr;
549 __be64 data_ioadl_addr;
550 __be64 reserved;
551 __be32 ext_control_buf[4];
552 }__attribute__((packed, aligned (8)));
553
554 /* IOA Request Control Block 128 bytes */
555 struct ipr_ioarcb {
556 union {
557 __be32 ioarcb_host_pci_addr;
558 __be64 ioarcb_host_pci_addr64;
559 } a;
560 __be32 res_handle;
561 __be32 host_response_handle;
562 __be32 reserved1;
563 __be32 reserved2;
564 __be32 reserved3;
565
566 __be32 data_transfer_length;
567 __be32 read_data_transfer_length;
568 __be32 write_ioadl_addr;
569 __be32 ioadl_len;
570 __be32 read_ioadl_addr;
571 __be32 read_ioadl_len;
572
573 __be32 ioasa_host_pci_addr;
574 __be16 ioasa_len;
575 __be16 reserved4;
576
577 struct ipr_cmd_pkt cmd_pkt;
578
579 __be16 add_cmd_parms_offset;
580 __be16 add_cmd_parms_len;
581
582 union {
583 struct ipr_ioarcb_add_data add_data;
584 struct ipr_ioarcb_sis64_add_addr_ecb sis64_addr_data;
585 } u;
586
587 }__attribute__((packed, aligned (4)));
588
589 struct ipr_ioasa_vset {
590 __be32 failing_lba_hi;
591 __be32 failing_lba_lo;
592 __be32 reserved;
593 }__attribute__((packed, aligned (4)));
594
595 struct ipr_ioasa_af_dasd {
596 __be32 failing_lba;
597 __be32 reserved[2];
598 }__attribute__((packed, aligned (4)));
599
600 struct ipr_ioasa_gpdd {
601 u8 end_state;
602 u8 bus_phase;
603 __be16 reserved;
604 __be32 ioa_data[2];
605 }__attribute__((packed, aligned (4)));
606
607 struct ipr_ioasa_gata {
608 u8 error;
609 u8 nsect; /* Interrupt reason */
610 u8 lbal;
611 u8 lbam;
612 u8 lbah;
613 u8 device;
614 u8 status;
615 u8 alt_status; /* ATA CTL */
616 u8 hob_nsect;
617 u8 hob_lbal;
618 u8 hob_lbam;
619 u8 hob_lbah;
620 }__attribute__((packed, aligned (4)));
621
622 struct ipr_auto_sense {
623 __be16 auto_sense_len;
624 __be16 ioa_data_len;
625 __be32 data[SCSI_SENSE_BUFFERSIZE/sizeof(__be32)];
626 };
627
628 struct ipr_ioasa_hdr {
629 __be32 ioasc;
630 #define IPR_IOASC_SENSE_KEY(ioasc) ((ioasc) >> 24)
631 #define IPR_IOASC_SENSE_CODE(ioasc) (((ioasc) & 0x00ff0000) >> 16)
632 #define IPR_IOASC_SENSE_QUAL(ioasc) (((ioasc) & 0x0000ff00) >> 8)
633 #define IPR_IOASC_SENSE_STATUS(ioasc) ((ioasc) & 0x000000ff)
634
635 __be16 ret_stat_len; /* Length of the returned IOASA */
636
637 __be16 avail_stat_len; /* Total Length of status available. */
638
639 __be32 residual_data_len; /* number of bytes in the host data */
640 /* buffers that were not used by the IOARCB command. */
641
642 __be32 ilid;
643 #define IPR_NO_ILID 0
644 #define IPR_DRIVER_ILID 0xffffffff
645
646 __be32 fd_ioasc;
647
648 __be32 fd_phys_locator;
649
650 __be32 fd_res_handle;
651
652 __be32 ioasc_specific; /* status code specific field */
653 #define IPR_ADDITIONAL_STATUS_FMT 0x80000000
654 #define IPR_AUTOSENSE_VALID 0x40000000
655 #define IPR_ATA_DEVICE_WAS_RESET 0x20000000
656 #define IPR_IOASC_SPECIFIC_MASK 0x00ffffff
657 #define IPR_FIELD_POINTER_VALID (0x80000000 >> 8)
658 #define IPR_FIELD_POINTER_MASK 0x0000ffff
659
660 }__attribute__((packed, aligned (4)));
661
662 struct ipr_ioasa {
663 struct ipr_ioasa_hdr hdr;
664
665 union {
666 struct ipr_ioasa_vset vset;
667 struct ipr_ioasa_af_dasd dasd;
668 struct ipr_ioasa_gpdd gpdd;
669 struct ipr_ioasa_gata gata;
670 } u;
671
672 struct ipr_auto_sense auto_sense;
673 }__attribute__((packed, aligned (4)));
674
675 struct ipr_ioasa64 {
676 struct ipr_ioasa_hdr hdr;
677 u8 fd_res_path[8];
678
679 union {
680 struct ipr_ioasa_vset vset;
681 struct ipr_ioasa_af_dasd dasd;
682 struct ipr_ioasa_gpdd gpdd;
683 struct ipr_ioasa_gata gata;
684 } u;
685
686 struct ipr_auto_sense auto_sense;
687 }__attribute__((packed, aligned (4)));
688
689 struct ipr_mode_parm_hdr {
690 u8 length;
691 u8 medium_type;
692 u8 device_spec_parms;
693 u8 block_desc_len;
694 }__attribute__((packed));
695
696 struct ipr_mode_pages {
697 struct ipr_mode_parm_hdr hdr;
698 u8 data[255 - sizeof(struct ipr_mode_parm_hdr)];
699 }__attribute__((packed));
700
701 struct ipr_mode_page_hdr {
702 u8 ps_page_code;
703 #define IPR_MODE_PAGE_PS 0x80
704 #define IPR_GET_MODE_PAGE_CODE(hdr) ((hdr)->ps_page_code & 0x3F)
705 u8 page_length;
706 }__attribute__ ((packed));
707
708 struct ipr_dev_bus_entry {
709 struct ipr_res_addr res_addr;
710 u8 flags;
711 #define IPR_SCSI_ATTR_ENABLE_QAS 0x80
712 #define IPR_SCSI_ATTR_DISABLE_QAS 0x40
713 #define IPR_SCSI_ATTR_QAS_MASK 0xC0
714 #define IPR_SCSI_ATTR_ENABLE_TM 0x20
715 #define IPR_SCSI_ATTR_NO_TERM_PWR 0x10
716 #define IPR_SCSI_ATTR_TM_SUPPORTED 0x08
717 #define IPR_SCSI_ATTR_LVD_TO_SE_NOT_ALLOWED 0x04
718
719 u8 scsi_id;
720 u8 bus_width;
721 u8 extended_reset_delay;
722 #define IPR_EXTENDED_RESET_DELAY 7
723
724 __be32 max_xfer_rate;
725
726 u8 spinup_delay;
727 u8 reserved3;
728 __be16 reserved4;
729 }__attribute__((packed, aligned (4)));
730
731 struct ipr_mode_page28 {
732 struct ipr_mode_page_hdr hdr;
733 u8 num_entries;
734 u8 entry_length;
735 struct ipr_dev_bus_entry bus[0];
736 }__attribute__((packed));
737
738 struct ipr_mode_page24 {
739 struct ipr_mode_page_hdr hdr;
740 u8 flags;
741 #define IPR_ENABLE_DUAL_IOA_AF 0x80
742 }__attribute__((packed));
743
744 struct ipr_ioa_vpd {
745 struct ipr_std_inq_data std_inq_data;
746 u8 ascii_part_num[12];
747 u8 reserved[40];
748 u8 ascii_plant_code[4];
749 }__attribute__((packed));
750
751 struct ipr_inquiry_page3 {
752 u8 peri_qual_dev_type;
753 u8 page_code;
754 u8 reserved1;
755 u8 page_length;
756 u8 ascii_len;
757 u8 reserved2[3];
758 u8 load_id[4];
759 u8 major_release;
760 u8 card_type;
761 u8 minor_release[2];
762 u8 ptf_number[4];
763 u8 patch_number[4];
764 }__attribute__((packed));
765
766 struct ipr_inquiry_cap {
767 u8 peri_qual_dev_type;
768 u8 page_code;
769 u8 reserved1;
770 u8 page_length;
771 u8 ascii_len;
772 u8 reserved2;
773 u8 sis_version[2];
774 u8 cap;
775 #define IPR_CAP_DUAL_IOA_RAID 0x80
776 u8 reserved3[15];
777 }__attribute__((packed));
778
779 #define IPR_INQUIRY_PAGE0_ENTRIES 20
780 struct ipr_inquiry_page0 {
781 u8 peri_qual_dev_type;
782 u8 page_code;
783 u8 reserved1;
784 u8 len;
785 u8 page[IPR_INQUIRY_PAGE0_ENTRIES];
786 }__attribute__((packed));
787
788 struct ipr_hostrcb_device_data_entry {
789 struct ipr_vpd vpd;
790 struct ipr_res_addr dev_res_addr;
791 struct ipr_vpd new_vpd;
792 struct ipr_vpd ioa_last_with_dev_vpd;
793 struct ipr_vpd cfc_last_with_dev_vpd;
794 __be32 ioa_data[5];
795 }__attribute__((packed, aligned (4)));
796
797 struct ipr_hostrcb_device_data_entry_enhanced {
798 struct ipr_ext_vpd vpd;
799 u8 ccin[4];
800 struct ipr_res_addr dev_res_addr;
801 struct ipr_ext_vpd new_vpd;
802 u8 new_ccin[4];
803 struct ipr_ext_vpd ioa_last_with_dev_vpd;
804 struct ipr_ext_vpd cfc_last_with_dev_vpd;
805 }__attribute__((packed, aligned (4)));
806
807 struct ipr_hostrcb64_device_data_entry_enhanced {
808 struct ipr_ext_vpd vpd;
809 u8 ccin[4];
810 u8 res_path[8];
811 struct ipr_ext_vpd new_vpd;
812 u8 new_ccin[4];
813 struct ipr_ext_vpd ioa_last_with_dev_vpd;
814 struct ipr_ext_vpd cfc_last_with_dev_vpd;
815 }__attribute__((packed, aligned (4)));
816
817 struct ipr_hostrcb_array_data_entry {
818 struct ipr_vpd vpd;
819 struct ipr_res_addr expected_dev_res_addr;
820 struct ipr_res_addr dev_res_addr;
821 }__attribute__((packed, aligned (4)));
822
823 struct ipr_hostrcb64_array_data_entry {
824 struct ipr_ext_vpd vpd;
825 u8 ccin[4];
826 u8 expected_res_path[8];
827 u8 res_path[8];
828 }__attribute__((packed, aligned (4)));
829
830 struct ipr_hostrcb_array_data_entry_enhanced {
831 struct ipr_ext_vpd vpd;
832 u8 ccin[4];
833 struct ipr_res_addr expected_dev_res_addr;
834 struct ipr_res_addr dev_res_addr;
835 }__attribute__((packed, aligned (4)));
836
837 struct ipr_hostrcb_type_ff_error {
838 __be32 ioa_data[758];
839 }__attribute__((packed, aligned (4)));
840
841 struct ipr_hostrcb_type_01_error {
842 __be32 seek_counter;
843 __be32 read_counter;
844 u8 sense_data[32];
845 __be32 ioa_data[236];
846 }__attribute__((packed, aligned (4)));
847
848 struct ipr_hostrcb_type_02_error {
849 struct ipr_vpd ioa_vpd;
850 struct ipr_vpd cfc_vpd;
851 struct ipr_vpd ioa_last_attached_to_cfc_vpd;
852 struct ipr_vpd cfc_last_attached_to_ioa_vpd;
853 __be32 ioa_data[3];
854 }__attribute__((packed, aligned (4)));
855
856 struct ipr_hostrcb_type_12_error {
857 struct ipr_ext_vpd ioa_vpd;
858 struct ipr_ext_vpd cfc_vpd;
859 struct ipr_ext_vpd ioa_last_attached_to_cfc_vpd;
860 struct ipr_ext_vpd cfc_last_attached_to_ioa_vpd;
861 __be32 ioa_data[3];
862 }__attribute__((packed, aligned (4)));
863
864 struct ipr_hostrcb_type_03_error {
865 struct ipr_vpd ioa_vpd;
866 struct ipr_vpd cfc_vpd;
867 __be32 errors_detected;
868 __be32 errors_logged;
869 u8 ioa_data[12];
870 struct ipr_hostrcb_device_data_entry dev[3];
871 }__attribute__((packed, aligned (4)));
872
873 struct ipr_hostrcb_type_13_error {
874 struct ipr_ext_vpd ioa_vpd;
875 struct ipr_ext_vpd cfc_vpd;
876 __be32 errors_detected;
877 __be32 errors_logged;
878 struct ipr_hostrcb_device_data_entry_enhanced dev[3];
879 }__attribute__((packed, aligned (4)));
880
881 struct ipr_hostrcb_type_23_error {
882 struct ipr_ext_vpd ioa_vpd;
883 struct ipr_ext_vpd cfc_vpd;
884 __be32 errors_detected;
885 __be32 errors_logged;
886 struct ipr_hostrcb64_device_data_entry_enhanced dev[3];
887 }__attribute__((packed, aligned (4)));
888
889 struct ipr_hostrcb_type_04_error {
890 struct ipr_vpd ioa_vpd;
891 struct ipr_vpd cfc_vpd;
892 u8 ioa_data[12];
893 struct ipr_hostrcb_array_data_entry array_member[10];
894 __be32 exposed_mode_adn;
895 __be32 array_id;
896 struct ipr_vpd incomp_dev_vpd;
897 __be32 ioa_data2;
898 struct ipr_hostrcb_array_data_entry array_member2[8];
899 struct ipr_res_addr last_func_vset_res_addr;
900 u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
901 u8 protection_level[8];
902 }__attribute__((packed, aligned (4)));
903
904 struct ipr_hostrcb_type_14_error {
905 struct ipr_ext_vpd ioa_vpd;
906 struct ipr_ext_vpd cfc_vpd;
907 __be32 exposed_mode_adn;
908 __be32 array_id;
909 struct ipr_res_addr last_func_vset_res_addr;
910 u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
911 u8 protection_level[8];
912 __be32 num_entries;
913 struct ipr_hostrcb_array_data_entry_enhanced array_member[18];
914 }__attribute__((packed, aligned (4)));
915
916 struct ipr_hostrcb_type_24_error {
917 struct ipr_ext_vpd ioa_vpd;
918 struct ipr_ext_vpd cfc_vpd;
919 u8 reserved[2];
920 u8 exposed_mode_adn;
921 #define IPR_INVALID_ARRAY_DEV_NUM 0xff
922 u8 array_id;
923 u8 last_res_path[8];
924 u8 protection_level[8];
925 struct ipr_ext_vpd64 array_vpd;
926 u8 description[16];
927 u8 reserved2[3];
928 u8 num_entries;
929 struct ipr_hostrcb64_array_data_entry array_member[32];
930 }__attribute__((packed, aligned (4)));
931
932 struct ipr_hostrcb_type_07_error {
933 u8 failure_reason[64];
934 struct ipr_vpd vpd;
935 u32 data[222];
936 }__attribute__((packed, aligned (4)));
937
938 struct ipr_hostrcb_type_17_error {
939 u8 failure_reason[64];
940 struct ipr_ext_vpd vpd;
941 u32 data[476];
942 }__attribute__((packed, aligned (4)));
943
944 struct ipr_hostrcb_config_element {
945 u8 type_status;
946 #define IPR_PATH_CFG_TYPE_MASK 0xF0
947 #define IPR_PATH_CFG_NOT_EXIST 0x00
948 #define IPR_PATH_CFG_IOA_PORT 0x10
949 #define IPR_PATH_CFG_EXP_PORT 0x20
950 #define IPR_PATH_CFG_DEVICE_PORT 0x30
951 #define IPR_PATH_CFG_DEVICE_LUN 0x40
952
953 #define IPR_PATH_CFG_STATUS_MASK 0x0F
954 #define IPR_PATH_CFG_NO_PROB 0x00
955 #define IPR_PATH_CFG_DEGRADED 0x01
956 #define IPR_PATH_CFG_FAILED 0x02
957 #define IPR_PATH_CFG_SUSPECT 0x03
958 #define IPR_PATH_NOT_DETECTED 0x04
959 #define IPR_PATH_INCORRECT_CONN 0x05
960
961 u8 cascaded_expander;
962 u8 phy;
963 u8 link_rate;
964 #define IPR_PHY_LINK_RATE_MASK 0x0F
965
966 __be32 wwid[2];
967 }__attribute__((packed, aligned (4)));
968
969 struct ipr_hostrcb64_config_element {
970 __be16 length;
971 u8 descriptor_id;
972 #define IPR_DESCRIPTOR_MASK 0xC0
973 #define IPR_DESCRIPTOR_SIS64 0x00
974
975 u8 reserved;
976 u8 type_status;
977
978 u8 reserved2[2];
979 u8 link_rate;
980
981 u8 res_path[8];
982 __be32 wwid[2];
983 }__attribute__((packed, aligned (8)));
984
985 struct ipr_hostrcb_fabric_desc {
986 __be16 length;
987 u8 ioa_port;
988 u8 cascaded_expander;
989 u8 phy;
990 u8 path_state;
991 #define IPR_PATH_ACTIVE_MASK 0xC0
992 #define IPR_PATH_NO_INFO 0x00
993 #define IPR_PATH_ACTIVE 0x40
994 #define IPR_PATH_NOT_ACTIVE 0x80
995
996 #define IPR_PATH_STATE_MASK 0x0F
997 #define IPR_PATH_STATE_NO_INFO 0x00
998 #define IPR_PATH_HEALTHY 0x01
999 #define IPR_PATH_DEGRADED 0x02
1000 #define IPR_PATH_FAILED 0x03
1001
1002 __be16 num_entries;
1003 struct ipr_hostrcb_config_element elem[1];
1004 }__attribute__((packed, aligned (4)));
1005
1006 struct ipr_hostrcb64_fabric_desc {
1007 __be16 length;
1008 u8 descriptor_id;
1009
1010 u8 reserved[2];
1011 u8 path_state;
1012
1013 u8 reserved2[2];
1014 u8 res_path[8];
1015 u8 reserved3[6];
1016 __be16 num_entries;
1017 struct ipr_hostrcb64_config_element elem[1];
1018 }__attribute__((packed, aligned (8)));
1019
1020 #define for_each_fabric_cfg(fabric, cfg) \
1021 for (cfg = (fabric)->elem; \
1022 cfg < ((fabric)->elem + be16_to_cpu((fabric)->num_entries)); \
1023 cfg++)
1024
1025 struct ipr_hostrcb_type_20_error {
1026 u8 failure_reason[64];
1027 u8 reserved[3];
1028 u8 num_entries;
1029 struct ipr_hostrcb_fabric_desc desc[1];
1030 }__attribute__((packed, aligned (4)));
1031
1032 struct ipr_hostrcb_type_30_error {
1033 u8 failure_reason[64];
1034 u8 reserved[3];
1035 u8 num_entries;
1036 struct ipr_hostrcb64_fabric_desc desc[1];
1037 }__attribute__((packed, aligned (4)));
1038
1039 struct ipr_hostrcb_error {
1040 __be32 fd_ioasc;
1041 struct ipr_res_addr fd_res_addr;
1042 __be32 fd_res_handle;
1043 __be32 prc;
1044 union {
1045 struct ipr_hostrcb_type_ff_error type_ff_error;
1046 struct ipr_hostrcb_type_01_error type_01_error;
1047 struct ipr_hostrcb_type_02_error type_02_error;
1048 struct ipr_hostrcb_type_03_error type_03_error;
1049 struct ipr_hostrcb_type_04_error type_04_error;
1050 struct ipr_hostrcb_type_07_error type_07_error;
1051 struct ipr_hostrcb_type_12_error type_12_error;
1052 struct ipr_hostrcb_type_13_error type_13_error;
1053 struct ipr_hostrcb_type_14_error type_14_error;
1054 struct ipr_hostrcb_type_17_error type_17_error;
1055 struct ipr_hostrcb_type_20_error type_20_error;
1056 } u;
1057 }__attribute__((packed, aligned (4)));
1058
1059 struct ipr_hostrcb64_error {
1060 __be32 fd_ioasc;
1061 __be32 ioa_fw_level;
1062 __be32 fd_res_handle;
1063 __be32 prc;
1064 __be64 fd_dev_id;
1065 __be64 fd_lun;
1066 u8 fd_res_path[8];
1067 __be64 time_stamp;
1068 u8 reserved[16];
1069 union {
1070 struct ipr_hostrcb_type_ff_error type_ff_error;
1071 struct ipr_hostrcb_type_12_error type_12_error;
1072 struct ipr_hostrcb_type_17_error type_17_error;
1073 struct ipr_hostrcb_type_23_error type_23_error;
1074 struct ipr_hostrcb_type_24_error type_24_error;
1075 struct ipr_hostrcb_type_30_error type_30_error;
1076 } u;
1077 }__attribute__((packed, aligned (8)));
1078
1079 struct ipr_hostrcb_raw {
1080 __be32 data[sizeof(struct ipr_hostrcb_error)/sizeof(__be32)];
1081 }__attribute__((packed, aligned (4)));
1082
1083 struct ipr_hcam {
1084 u8 op_code;
1085 #define IPR_HOST_RCB_OP_CODE_CONFIG_CHANGE 0xE1
1086 #define IPR_HOST_RCB_OP_CODE_LOG_DATA 0xE2
1087
1088 u8 notify_type;
1089 #define IPR_HOST_RCB_NOTIF_TYPE_EXISTING_CHANGED 0x00
1090 #define IPR_HOST_RCB_NOTIF_TYPE_NEW_ENTRY 0x01
1091 #define IPR_HOST_RCB_NOTIF_TYPE_REM_ENTRY 0x02
1092 #define IPR_HOST_RCB_NOTIF_TYPE_ERROR_LOG_ENTRY 0x10
1093 #define IPR_HOST_RCB_NOTIF_TYPE_INFORMATION_ENTRY 0x11
1094
1095 u8 notifications_lost;
1096 #define IPR_HOST_RCB_NO_NOTIFICATIONS_LOST 0
1097 #define IPR_HOST_RCB_NOTIFICATIONS_LOST 0x80
1098
1099 u8 flags;
1100 #define IPR_HOSTRCB_INTERNAL_OPER 0x80
1101 #define IPR_HOSTRCB_ERR_RESP_SENT 0x40
1102
1103 u8 overlay_id;
1104 #define IPR_HOST_RCB_OVERLAY_ID_1 0x01
1105 #define IPR_HOST_RCB_OVERLAY_ID_2 0x02
1106 #define IPR_HOST_RCB_OVERLAY_ID_3 0x03
1107 #define IPR_HOST_RCB_OVERLAY_ID_4 0x04
1108 #define IPR_HOST_RCB_OVERLAY_ID_6 0x06
1109 #define IPR_HOST_RCB_OVERLAY_ID_7 0x07
1110 #define IPR_HOST_RCB_OVERLAY_ID_12 0x12
1111 #define IPR_HOST_RCB_OVERLAY_ID_13 0x13
1112 #define IPR_HOST_RCB_OVERLAY_ID_14 0x14
1113 #define IPR_HOST_RCB_OVERLAY_ID_16 0x16
1114 #define IPR_HOST_RCB_OVERLAY_ID_17 0x17
1115 #define IPR_HOST_RCB_OVERLAY_ID_20 0x20
1116 #define IPR_HOST_RCB_OVERLAY_ID_23 0x23
1117 #define IPR_HOST_RCB_OVERLAY_ID_24 0x24
1118 #define IPR_HOST_RCB_OVERLAY_ID_26 0x26
1119 #define IPR_HOST_RCB_OVERLAY_ID_30 0x30
1120 #define IPR_HOST_RCB_OVERLAY_ID_DEFAULT 0xFF
1121
1122 u8 reserved1[3];
1123 __be32 ilid;
1124 __be32 time_since_last_ioa_reset;
1125 __be32 reserved2;
1126 __be32 length;
1127
1128 union {
1129 struct ipr_hostrcb_error error;
1130 struct ipr_hostrcb64_error error64;
1131 struct ipr_hostrcb_cfg_ch_not ccn;
1132 struct ipr_hostrcb_raw raw;
1133 } u;
1134 }__attribute__((packed, aligned (4)));
1135
1136 struct ipr_hostrcb {
1137 struct ipr_hcam hcam;
1138 dma_addr_t hostrcb_dma;
1139 struct list_head queue;
1140 struct ipr_ioa_cfg *ioa_cfg;
1141 char rp_buffer[IPR_MAX_RES_PATH_LENGTH];
1142 };
1143
1144 /* IPR smart dump table structures */
1145 struct ipr_sdt_entry {
1146 __be32 start_token;
1147 __be32 end_token;
1148 u8 reserved[4];
1149
1150 u8 flags;
1151 #define IPR_SDT_ENDIAN 0x80
1152 #define IPR_SDT_VALID_ENTRY 0x20
1153
1154 u8 resv;
1155 __be16 priority;
1156 }__attribute__((packed, aligned (4)));
1157
1158 struct ipr_sdt_header {
1159 __be32 state;
1160 __be32 num_entries;
1161 __be32 num_entries_used;
1162 __be32 dump_size;
1163 }__attribute__((packed, aligned (4)));
1164
1165 struct ipr_sdt {
1166 struct ipr_sdt_header hdr;
1167 struct ipr_sdt_entry entry[IPR_NUM_SDT_ENTRIES];
1168 }__attribute__((packed, aligned (4)));
1169
1170 struct ipr_uc_sdt {
1171 struct ipr_sdt_header hdr;
1172 struct ipr_sdt_entry entry[1];
1173 }__attribute__((packed, aligned (4)));
1174
1175 /*
1176 * Driver types
1177 */
1178 struct ipr_bus_attributes {
1179 u8 bus;
1180 u8 qas_enabled;
1181 u8 bus_width;
1182 u8 reserved;
1183 u32 max_xfer_rate;
1184 };
1185
1186 struct ipr_sata_port {
1187 struct ipr_ioa_cfg *ioa_cfg;
1188 struct ata_port *ap;
1189 struct ipr_resource_entry *res;
1190 struct ipr_ioasa_gata ioasa;
1191 };
1192
1193 struct ipr_resource_entry {
1194 u8 needs_sync_complete:1;
1195 u8 in_erp:1;
1196 u8 add_to_ml:1;
1197 u8 del_from_ml:1;
1198 u8 resetting_device:1;
1199
1200 u32 bus; /* AKA channel */
1201 u32 target; /* AKA id */
1202 u32 lun;
1203 #define IPR_ARRAY_VIRTUAL_BUS 0x1
1204 #define IPR_VSET_VIRTUAL_BUS 0x2
1205 #define IPR_IOAFP_VIRTUAL_BUS 0x3
1206
1207 #define IPR_GET_RES_PHYS_LOC(res) \
1208 (((res)->bus << 24) | ((res)->target << 8) | (res)->lun)
1209
1210 u8 ata_class;
1211
1212 u8 flags;
1213 __be16 res_flags;
1214
1215 u8 type;
1216
1217 u8 qmodel;
1218 struct ipr_std_inq_data std_inq_data;
1219
1220 __be32 res_handle;
1221 __be64 dev_id;
1222 __be64 lun_wwn;
1223 struct scsi_lun dev_lun;
1224 u8 res_path[8];
1225
1226 struct ipr_ioa_cfg *ioa_cfg;
1227 struct scsi_device *sdev;
1228 struct ipr_sata_port *sata_port;
1229 struct list_head queue;
1230 }; /* struct ipr_resource_entry */
1231
1232 struct ipr_resource_hdr {
1233 u16 num_entries;
1234 u16 reserved;
1235 };
1236
1237 struct ipr_misc_cbs {
1238 struct ipr_ioa_vpd ioa_vpd;
1239 struct ipr_inquiry_page0 page0_data;
1240 struct ipr_inquiry_page3 page3_data;
1241 struct ipr_inquiry_cap cap;
1242 struct ipr_mode_pages mode_pages;
1243 struct ipr_supported_device supp_dev;
1244 };
1245
1246 struct ipr_interrupt_offsets {
1247 unsigned long set_interrupt_mask_reg;
1248 unsigned long clr_interrupt_mask_reg;
1249 unsigned long clr_interrupt_mask_reg32;
1250 unsigned long sense_interrupt_mask_reg;
1251 unsigned long sense_interrupt_mask_reg32;
1252 unsigned long clr_interrupt_reg;
1253 unsigned long clr_interrupt_reg32;
1254
1255 unsigned long sense_interrupt_reg;
1256 unsigned long sense_interrupt_reg32;
1257 unsigned long ioarrin_reg;
1258 unsigned long sense_uproc_interrupt_reg;
1259 unsigned long sense_uproc_interrupt_reg32;
1260 unsigned long set_uproc_interrupt_reg;
1261 unsigned long set_uproc_interrupt_reg32;
1262 unsigned long clr_uproc_interrupt_reg;
1263 unsigned long clr_uproc_interrupt_reg32;
1264
1265 unsigned long init_feedback_reg;
1266
1267 unsigned long dump_addr_reg;
1268 unsigned long dump_data_reg;
1269
1270 #define IPR_ENDIAN_SWAP_KEY 0x00080800
1271 unsigned long endian_swap_reg;
1272 };
1273
1274 struct ipr_interrupts {
1275 void __iomem *set_interrupt_mask_reg;
1276 void __iomem *clr_interrupt_mask_reg;
1277 void __iomem *clr_interrupt_mask_reg32;
1278 void __iomem *sense_interrupt_mask_reg;
1279 void __iomem *sense_interrupt_mask_reg32;
1280 void __iomem *clr_interrupt_reg;
1281 void __iomem *clr_interrupt_reg32;
1282
1283 void __iomem *sense_interrupt_reg;
1284 void __iomem *sense_interrupt_reg32;
1285 void __iomem *ioarrin_reg;
1286 void __iomem *sense_uproc_interrupt_reg;
1287 void __iomem *sense_uproc_interrupt_reg32;
1288 void __iomem *set_uproc_interrupt_reg;
1289 void __iomem *set_uproc_interrupt_reg32;
1290 void __iomem *clr_uproc_interrupt_reg;
1291 void __iomem *clr_uproc_interrupt_reg32;
1292
1293 void __iomem *init_feedback_reg;
1294
1295 void __iomem *dump_addr_reg;
1296 void __iomem *dump_data_reg;
1297
1298 void __iomem *endian_swap_reg;
1299 };
1300
1301 struct ipr_chip_cfg_t {
1302 u32 mailbox;
1303 u8 cache_line_size;
1304 struct ipr_interrupt_offsets regs;
1305 };
1306
1307 struct ipr_chip_t {
1308 u16 vendor;
1309 u16 device;
1310 u16 intr_type;
1311 #define IPR_USE_LSI 0x00
1312 #define IPR_USE_MSI 0x01
1313 u16 sis_type;
1314 #define IPR_SIS32 0x00
1315 #define IPR_SIS64 0x01
1316 u16 bist_method;
1317 #define IPR_PCI_CFG 0x00
1318 #define IPR_MMIO 0x01
1319 const struct ipr_chip_cfg_t *cfg;
1320 };
1321
1322 enum ipr_shutdown_type {
1323 IPR_SHUTDOWN_NORMAL = 0x00,
1324 IPR_SHUTDOWN_PREPARE_FOR_NORMAL = 0x40,
1325 IPR_SHUTDOWN_ABBREV = 0x80,
1326 IPR_SHUTDOWN_NONE = 0x100
1327 };
1328
1329 struct ipr_trace_entry {
1330 u32 time;
1331
1332 u8 op_code;
1333 u8 ata_op_code;
1334 u8 type;
1335 #define IPR_TRACE_START 0x00
1336 #define IPR_TRACE_FINISH 0xff
1337 u8 cmd_index;
1338
1339 __be32 res_handle;
1340 union {
1341 u32 ioasc;
1342 u32 add_data;
1343 u32 res_addr;
1344 } u;
1345 };
1346
1347 struct ipr_sglist {
1348 u32 order;
1349 u32 num_sg;
1350 u32 num_dma_sg;
1351 u32 buffer_len;
1352 struct scatterlist scatterlist[1];
1353 };
1354
1355 enum ipr_sdt_state {
1356 INACTIVE,
1357 WAIT_FOR_DUMP,
1358 GET_DUMP,
1359 ABORT_DUMP,
1360 DUMP_OBTAINED
1361 };
1362
1363 /* Per-controller data */
1364 struct ipr_ioa_cfg {
1365 char eye_catcher[8];
1366 #define IPR_EYECATCHER "iprcfg"
1367
1368 struct list_head queue;
1369
1370 u8 allow_interrupts:1;
1371 u8 in_reset_reload:1;
1372 u8 in_ioa_bringdown:1;
1373 u8 ioa_unit_checked:1;
1374 u8 ioa_is_dead:1;
1375 u8 dump_taken:1;
1376 u8 allow_cmds:1;
1377 u8 allow_ml_add_del:1;
1378 u8 needs_hard_reset:1;
1379 u8 dual_raid:1;
1380 u8 needs_warm_reset:1;
1381 u8 msi_received:1;
1382 u8 sis64:1;
1383
1384 u8 revid;
1385
1386 /*
1387 * Bitmaps for SIS64 generated target values
1388 */
1389 unsigned long *target_ids;
1390 unsigned long *array_ids;
1391 unsigned long *vset_ids;
1392
1393 u16 type; /* CCIN of the card */
1394
1395 u8 log_level;
1396 #define IPR_MAX_LOG_LEVEL 4
1397 #define IPR_DEFAULT_LOG_LEVEL 2
1398
1399 #define IPR_NUM_TRACE_INDEX_BITS 8
1400 #define IPR_NUM_TRACE_ENTRIES (1 << IPR_NUM_TRACE_INDEX_BITS)
1401 #define IPR_TRACE_SIZE (sizeof(struct ipr_trace_entry) * IPR_NUM_TRACE_ENTRIES)
1402 char trace_start[8];
1403 #define IPR_TRACE_START_LABEL "trace"
1404 struct ipr_trace_entry *trace;
1405 u32 trace_index:IPR_NUM_TRACE_INDEX_BITS;
1406
1407 /*
1408 * Queue for free command blocks
1409 */
1410 char ipr_free_label[8];
1411 #define IPR_FREEQ_LABEL "free-q"
1412 struct list_head free_q;
1413
1414 /*
1415 * Queue for command blocks outstanding to the adapter
1416 */
1417 char ipr_pending_label[8];
1418 #define IPR_PENDQ_LABEL "pend-q"
1419 struct list_head pending_q;
1420
1421 char cfg_table_start[8];
1422 #define IPR_CFG_TBL_START "cfg"
1423 union {
1424 struct ipr_config_table *cfg_table;
1425 struct ipr_config_table64 *cfg_table64;
1426 } u;
1427 dma_addr_t cfg_table_dma;
1428 u32 cfg_table_size;
1429 u32 max_devs_supported;
1430
1431 char resource_table_label[8];
1432 #define IPR_RES_TABLE_LABEL "res_tbl"
1433 struct ipr_resource_entry *res_entries;
1434 struct list_head free_res_q;
1435 struct list_head used_res_q;
1436
1437 char ipr_hcam_label[8];
1438 #define IPR_HCAM_LABEL "hcams"
1439 struct ipr_hostrcb *hostrcb[IPR_NUM_HCAMS];
1440 dma_addr_t hostrcb_dma[IPR_NUM_HCAMS];
1441 struct list_head hostrcb_free_q;
1442 struct list_head hostrcb_pending_q;
1443
1444 __be32 *host_rrq;
1445 dma_addr_t host_rrq_dma;
1446 #define IPR_HRRQ_REQ_RESP_HANDLE_MASK 0xfffffffc
1447 #define IPR_HRRQ_RESP_BIT_SET 0x00000002
1448 #define IPR_HRRQ_TOGGLE_BIT 0x00000001
1449 #define IPR_HRRQ_REQ_RESP_HANDLE_SHIFT 2
1450 volatile __be32 *hrrq_start;
1451 volatile __be32 *hrrq_end;
1452 volatile __be32 *hrrq_curr;
1453 volatile u32 toggle_bit;
1454
1455 struct ipr_bus_attributes bus_attr[IPR_MAX_NUM_BUSES];
1456
1457 unsigned int transop_timeout;
1458 const struct ipr_chip_cfg_t *chip_cfg;
1459 const struct ipr_chip_t *ipr_chip;
1460
1461 void __iomem *hdw_dma_regs; /* iomapped PCI memory space */
1462 unsigned long hdw_dma_regs_pci; /* raw PCI memory space */
1463 void __iomem *ioa_mailbox;
1464 struct ipr_interrupts regs;
1465
1466 u16 saved_pcix_cmd_reg;
1467 u16 reset_retries;
1468
1469 u32 errors_logged;
1470 u32 doorbell;
1471
1472 struct Scsi_Host *host;
1473 struct pci_dev *pdev;
1474 struct ipr_sglist *ucode_sglist;
1475 u8 saved_mode_page_len;
1476
1477 struct work_struct work_q;
1478
1479 wait_queue_head_t reset_wait_q;
1480 wait_queue_head_t msi_wait_q;
1481
1482 struct ipr_dump *dump;
1483 enum ipr_sdt_state sdt_state;
1484
1485 struct ipr_misc_cbs *vpd_cbs;
1486 dma_addr_t vpd_cbs_dma;
1487
1488 struct pci_pool *ipr_cmd_pool;
1489
1490 struct ipr_cmnd *reset_cmd;
1491 int (*reset) (struct ipr_cmnd *);
1492
1493 struct ata_host ata_host;
1494 char ipr_cmd_label[8];
1495 #define IPR_CMD_LABEL "ipr_cmd"
1496 struct ipr_cmnd *ipr_cmnd_list[IPR_NUM_CMD_BLKS];
1497 dma_addr_t ipr_cmnd_list_dma[IPR_NUM_CMD_BLKS];
1498 }; /* struct ipr_ioa_cfg */
1499
1500 struct ipr_cmnd {
1501 struct ipr_ioarcb ioarcb;
1502 union {
1503 struct ipr_ioadl_desc ioadl[IPR_NUM_IOADL_ENTRIES];
1504 struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES];
1505 struct ipr_ata64_ioadl ata_ioadl;
1506 } i;
1507 union {
1508 struct ipr_ioasa ioasa;
1509 struct ipr_ioasa64 ioasa64;
1510 } s;
1511 struct list_head queue;
1512 struct scsi_cmnd *scsi_cmd;
1513 struct ata_queued_cmd *qc;
1514 struct completion completion;
1515 struct timer_list timer;
1516 void (*done) (struct ipr_cmnd *);
1517 int (*job_step) (struct ipr_cmnd *);
1518 int (*job_step_failed) (struct ipr_cmnd *);
1519 u16 cmd_index;
1520 u8 sense_buffer[SCSI_SENSE_BUFFERSIZE];
1521 dma_addr_t sense_buffer_dma;
1522 unsigned short dma_use_sg;
1523 dma_addr_t dma_addr;
1524 struct ipr_cmnd *sibling;
1525 union {
1526 enum ipr_shutdown_type shutdown_type;
1527 struct ipr_hostrcb *hostrcb;
1528 unsigned long time_left;
1529 unsigned long scratch;
1530 struct ipr_resource_entry *res;
1531 struct scsi_device *sdev;
1532 } u;
1533
1534 struct ipr_ioa_cfg *ioa_cfg;
1535 };
1536
1537 struct ipr_ses_table_entry {
1538 char product_id[17];
1539 char compare_product_id_byte[17];
1540 u32 max_bus_speed_limit; /* MB/sec limit for this backplane */
1541 };
1542
1543 struct ipr_dump_header {
1544 u32 eye_catcher;
1545 #define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2
1546 u32 len;
1547 u32 num_entries;
1548 u32 first_entry_offset;
1549 u32 status;
1550 #define IPR_DUMP_STATUS_SUCCESS 0
1551 #define IPR_DUMP_STATUS_QUAL_SUCCESS 2
1552 #define IPR_DUMP_STATUS_FAILED 0xffffffff
1553 u32 os;
1554 #define IPR_DUMP_OS_LINUX 0x4C4E5558
1555 u32 driver_name;
1556 #define IPR_DUMP_DRIVER_NAME 0x49505232
1557 }__attribute__((packed, aligned (4)));
1558
1559 struct ipr_dump_entry_header {
1560 u32 eye_catcher;
1561 #define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2
1562 u32 len;
1563 u32 num_elems;
1564 u32 offset;
1565 u32 data_type;
1566 #define IPR_DUMP_DATA_TYPE_ASCII 0x41534349
1567 #define IPR_DUMP_DATA_TYPE_BINARY 0x42494E41
1568 u32 id;
1569 #define IPR_DUMP_IOA_DUMP_ID 0x494F4131
1570 #define IPR_DUMP_LOCATION_ID 0x4C4F4341
1571 #define IPR_DUMP_TRACE_ID 0x54524143
1572 #define IPR_DUMP_DRIVER_VERSION_ID 0x44525652
1573 #define IPR_DUMP_DRIVER_TYPE_ID 0x54595045
1574 #define IPR_DUMP_IOA_CTRL_BLK 0x494F4342
1575 #define IPR_DUMP_PEND_OPS 0x414F5053
1576 u32 status;
1577 }__attribute__((packed, aligned (4)));
1578
1579 struct ipr_dump_location_entry {
1580 struct ipr_dump_entry_header hdr;
1581 u8 location[20];
1582 }__attribute__((packed));
1583
1584 struct ipr_dump_trace_entry {
1585 struct ipr_dump_entry_header hdr;
1586 u32 trace[IPR_TRACE_SIZE / sizeof(u32)];
1587 }__attribute__((packed, aligned (4)));
1588
1589 struct ipr_dump_version_entry {
1590 struct ipr_dump_entry_header hdr;
1591 u8 version[sizeof(IPR_DRIVER_VERSION)];
1592 };
1593
1594 struct ipr_dump_ioa_type_entry {
1595 struct ipr_dump_entry_header hdr;
1596 u32 type;
1597 u32 fw_version;
1598 };
1599
1600 struct ipr_driver_dump {
1601 struct ipr_dump_header hdr;
1602 struct ipr_dump_version_entry version_entry;
1603 struct ipr_dump_location_entry location_entry;
1604 struct ipr_dump_ioa_type_entry ioa_type_entry;
1605 struct ipr_dump_trace_entry trace_entry;
1606 }__attribute__((packed));
1607
1608 struct ipr_ioa_dump {
1609 struct ipr_dump_entry_header hdr;
1610 struct ipr_sdt sdt;
1611 __be32 *ioa_data[IPR_MAX_NUM_DUMP_PAGES];
1612 u32 reserved;
1613 u32 next_page_index;
1614 u32 page_offset;
1615 u32 format;
1616 }__attribute__((packed, aligned (4)));
1617
1618 struct ipr_dump {
1619 struct kref kref;
1620 struct ipr_ioa_cfg *ioa_cfg;
1621 struct ipr_driver_dump driver_dump;
1622 struct ipr_ioa_dump ioa_dump;
1623 };
1624
1625 struct ipr_error_table_t {
1626 u32 ioasc;
1627 int log_ioasa;
1628 int log_hcam;
1629 char *error;
1630 };
1631
1632 struct ipr_software_inq_lid_info {
1633 __be32 load_id;
1634 __be32 timestamp[3];
1635 }__attribute__((packed, aligned (4)));
1636
1637 struct ipr_ucode_image_header {
1638 __be32 header_length;
1639 __be32 lid_table_offset;
1640 u8 major_release;
1641 u8 card_type;
1642 u8 minor_release[2];
1643 u8 reserved[20];
1644 char eyecatcher[16];
1645 __be32 num_lids;
1646 struct ipr_software_inq_lid_info lid[1];
1647 }__attribute__((packed, aligned (4)));
1648
1649 /*
1650 * Macros
1651 */
1652 #define IPR_DBG_CMD(CMD) if (ipr_debug) { CMD; }
1653
1654 #ifdef CONFIG_SCSI_IPR_TRACE
1655 #define ipr_create_trace_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1656 #define ipr_remove_trace_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1657 #else
1658 #define ipr_create_trace_file(kobj, attr) 0
1659 #define ipr_remove_trace_file(kobj, attr) do { } while(0)
1660 #endif
1661
1662 #ifdef CONFIG_SCSI_IPR_DUMP
1663 #define ipr_create_dump_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1664 #define ipr_remove_dump_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1665 #else
1666 #define ipr_create_dump_file(kobj, attr) 0
1667 #define ipr_remove_dump_file(kobj, attr) do { } while(0)
1668 #endif
1669
1670 /*
1671 * Error logging macros
1672 */
1673 #define ipr_err(...) printk(KERN_ERR IPR_NAME ": "__VA_ARGS__)
1674 #define ipr_info(...) printk(KERN_INFO IPR_NAME ": "__VA_ARGS__)
1675 #define ipr_dbg(...) IPR_DBG_CMD(printk(KERN_INFO IPR_NAME ": "__VA_ARGS__))
1676
1677 #define ipr_res_printk(level, ioa_cfg, bus, target, lun, fmt, ...) \
1678 printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
1679 bus, target, lun, ##__VA_ARGS__)
1680
1681 #define ipr_res_err(ioa_cfg, res, fmt, ...) \
1682 ipr_res_printk(KERN_ERR, ioa_cfg, (res)->bus, (res)->target, (res)->lun, fmt, ##__VA_ARGS__)
1683
1684 #define ipr_ra_printk(level, ioa_cfg, ra, fmt, ...) \
1685 printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
1686 (ra).bus, (ra).target, (ra).lun, ##__VA_ARGS__)
1687
1688 #define ipr_ra_err(ioa_cfg, ra, fmt, ...) \
1689 ipr_ra_printk(KERN_ERR, ioa_cfg, ra, fmt, ##__VA_ARGS__)
1690
1691 #define ipr_phys_res_err(ioa_cfg, res, fmt, ...) \
1692 { \
1693 if ((res).bus >= IPR_MAX_NUM_BUSES) { \
1694 ipr_err(fmt": unknown\n", ##__VA_ARGS__); \
1695 } else { \
1696 ipr_err(fmt": %d:%d:%d:%d\n", \
1697 ##__VA_ARGS__, (ioa_cfg)->host->host_no, \
1698 (res).bus, (res).target, (res).lun); \
1699 } \
1700 }
1701
1702 #define ipr_hcam_err(hostrcb, fmt, ...) \
1703 { \
1704 if (ipr_is_device(hostrcb)) { \
1705 if ((hostrcb)->ioa_cfg->sis64) { \
1706 printk(KERN_ERR IPR_NAME ": %s: " fmt, \
1707 ipr_format_res_path(hostrcb->hcam.u.error64.fd_res_path, \
1708 hostrcb->rp_buffer, \
1709 sizeof(hostrcb->rp_buffer)), \
1710 __VA_ARGS__); \
1711 } else { \
1712 ipr_ra_err((hostrcb)->ioa_cfg, \
1713 (hostrcb)->hcam.u.error.fd_res_addr, \
1714 fmt, __VA_ARGS__); \
1715 } \
1716 } else { \
1717 dev_err(&(hostrcb)->ioa_cfg->pdev->dev, fmt, __VA_ARGS__); \
1718 } \
1719 }
1720
1721 #define ipr_trace ipr_dbg("%s: %s: Line: %d\n",\
1722 __FILE__, __func__, __LINE__)
1723
1724 #define ENTER IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Entering %s\n", __func__))
1725 #define LEAVE IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Leaving %s\n", __func__))
1726
1727 #define ipr_err_separator \
1728 ipr_err("----------------------------------------------------------\n")
1729
1730
1731 /*
1732 * Inlines
1733 */
1734
1735 /**
1736 * ipr_is_ioa_resource - Determine if a resource is the IOA
1737 * @res: resource entry struct
1738 *
1739 * Return value:
1740 * 1 if IOA / 0 if not IOA
1741 **/
1742 static inline int ipr_is_ioa_resource(struct ipr_resource_entry *res)
1743 {
1744 return res->type == IPR_RES_TYPE_IOAFP;
1745 }
1746
1747 /**
1748 * ipr_is_af_dasd_device - Determine if a resource is an AF DASD
1749 * @res: resource entry struct
1750 *
1751 * Return value:
1752 * 1 if AF DASD / 0 if not AF DASD
1753 **/
1754 static inline int ipr_is_af_dasd_device(struct ipr_resource_entry *res)
1755 {
1756 return res->type == IPR_RES_TYPE_AF_DASD ||
1757 res->type == IPR_RES_TYPE_REMOTE_AF_DASD;
1758 }
1759
1760 /**
1761 * ipr_is_vset_device - Determine if a resource is a VSET
1762 * @res: resource entry struct
1763 *
1764 * Return value:
1765 * 1 if VSET / 0 if not VSET
1766 **/
1767 static inline int ipr_is_vset_device(struct ipr_resource_entry *res)
1768 {
1769 return res->type == IPR_RES_TYPE_VOLUME_SET;
1770 }
1771
1772 /**
1773 * ipr_is_gscsi - Determine if a resource is a generic scsi resource
1774 * @res: resource entry struct
1775 *
1776 * Return value:
1777 * 1 if GSCSI / 0 if not GSCSI
1778 **/
1779 static inline int ipr_is_gscsi(struct ipr_resource_entry *res)
1780 {
1781 return res->type == IPR_RES_TYPE_GENERIC_SCSI;
1782 }
1783
1784 /**
1785 * ipr_is_scsi_disk - Determine if a resource is a SCSI disk
1786 * @res: resource entry struct
1787 *
1788 * Return value:
1789 * 1 if SCSI disk / 0 if not SCSI disk
1790 **/
1791 static inline int ipr_is_scsi_disk(struct ipr_resource_entry *res)
1792 {
1793 if (ipr_is_af_dasd_device(res) ||
1794 (ipr_is_gscsi(res) && IPR_IS_DASD_DEVICE(res->std_inq_data)))
1795 return 1;
1796 else
1797 return 0;
1798 }
1799
1800 /**
1801 * ipr_is_gata - Determine if a resource is a generic ATA resource
1802 * @res: resource entry struct
1803 *
1804 * Return value:
1805 * 1 if GATA / 0 if not GATA
1806 **/
1807 static inline int ipr_is_gata(struct ipr_resource_entry *res)
1808 {
1809 return res->type == IPR_RES_TYPE_GENERIC_ATA;
1810 }
1811
1812 /**
1813 * ipr_is_naca_model - Determine if a resource is using NACA queueing model
1814 * @res: resource entry struct
1815 *
1816 * Return value:
1817 * 1 if NACA queueing model / 0 if not NACA queueing model
1818 **/
1819 static inline int ipr_is_naca_model(struct ipr_resource_entry *res)
1820 {
1821 if (ipr_is_gscsi(res) && res->qmodel == IPR_QUEUE_NACA_MODEL)
1822 return 1;
1823 return 0;
1824 }
1825
1826 /**
1827 * ipr_is_device - Determine if the hostrcb structure is related to a device
1828 * @hostrcb: host resource control blocks struct
1829 *
1830 * Return value:
1831 * 1 if AF / 0 if not AF
1832 **/
1833 static inline int ipr_is_device(struct ipr_hostrcb *hostrcb)
1834 {
1835 struct ipr_res_addr *res_addr;
1836 u8 *res_path;
1837
1838 if (hostrcb->ioa_cfg->sis64) {
1839 res_path = &hostrcb->hcam.u.error64.fd_res_path[0];
1840 if ((res_path[0] == 0x00 || res_path[0] == 0x80 ||
1841 res_path[0] == 0x81) && res_path[2] != 0xFF)
1842 return 1;
1843 } else {
1844 res_addr = &hostrcb->hcam.u.error.fd_res_addr;
1845
1846 if ((res_addr->bus < IPR_MAX_NUM_BUSES) &&
1847 (res_addr->target < (IPR_MAX_NUM_TARGETS_PER_BUS - 1)))
1848 return 1;
1849 }
1850 return 0;
1851 }
1852
1853 /**
1854 * ipr_sdt_is_fmt2 - Determine if a SDT address is in format 2
1855 * @sdt_word: SDT address
1856 *
1857 * Return value:
1858 * 1 if format 2 / 0 if not
1859 **/
1860 static inline int ipr_sdt_is_fmt2(u32 sdt_word)
1861 {
1862 u32 bar_sel = IPR_GET_FMT2_BAR_SEL(sdt_word);
1863
1864 switch (bar_sel) {
1865 case IPR_SDT_FMT2_BAR0_SEL:
1866 case IPR_SDT_FMT2_BAR1_SEL:
1867 case IPR_SDT_FMT2_BAR2_SEL:
1868 case IPR_SDT_FMT2_BAR3_SEL:
1869 case IPR_SDT_FMT2_BAR4_SEL:
1870 case IPR_SDT_FMT2_BAR5_SEL:
1871 case IPR_SDT_FMT2_EXP_ROM_SEL:
1872 return 1;
1873 };
1874
1875 return 0;
1876 }
1877
1878 #ifndef writeq
1879 static inline void writeq(u64 val, void __iomem *addr)
1880 {
1881 writel(((u32) (val >> 32)), addr);
1882 writel(((u32) (val)), (addr + 4));
1883 }
1884 #endif
1885
1886 #endif /* _IPR_H */
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