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sky2: rx allocation threshold change
[linux-2.6.git] / drivers / net / sky2.c
blobc177e87182f4293f531ce468554e9c672e1652d8
1 /*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/version.h>
28 #include <linux/module.h>
29 #include <linux/netdevice.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/pci.h>
34 #include <linux/ip.h>
35 #include <net/ip.h>
36 #include <linux/tcp.h>
37 #include <linux/in.h>
38 #include <linux/delay.h>
39 #include <linux/workqueue.h>
40 #include <linux/if_vlan.h>
41 #include <linux/prefetch.h>
42 #include <linux/debugfs.h>
43 #include <linux/mii.h>
44
45 #include <asm/irq.h>
46
47 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48 #define SKY2_VLAN_TAG_USED 1
49 #endif
50
51 #include "sky2.h"
52
53 #define DRV_NAME "sky2"
54 #define DRV_VERSION "1.20"
55 #define PFX DRV_NAME " "
56
57 /*
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
60 * similar to Tigon3.
61 */
62
63 #define RX_LE_SIZE 1024
64 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
65 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
66 #define RX_DEF_PENDING RX_MAX_PENDING
67
68 #define TX_RING_SIZE 512
69 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
70 #define TX_MIN_PENDING 64
71 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
72
73 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
74 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
75 #define TX_WATCHDOG (5 * HZ)
76 #define NAPI_WEIGHT 64
77 #define PHY_RETRIES 1000
78
79 #define SKY2_EEPROM_MAGIC 0x9955aabb
80
81
82 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
83
84 static const u32 default_msg =
85 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
86 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
87 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
88
89 static int debug = -1; /* defaults above */
90 module_param(debug, int, 0);
91 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
92
93 static int copybreak __read_mostly = 128;
94 module_param(copybreak, int, 0);
95 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
96
97 static int disable_msi = 0;
98 module_param(disable_msi, int, 0);
99 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
100
101 static const struct pci_device_id sky2_id_table[] = {
102 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
104 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
137 { 0 }
138 };
139
140 MODULE_DEVICE_TABLE(pci, sky2_id_table);
141
142 /* Avoid conditionals by using array */
143 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
144 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
145 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
146
147 /* This driver supports yukon2 chipset only */
148 static const char *yukon2_name[] = {
149 "XL", /* 0xb3 */
150 "EC Ultra", /* 0xb4 */
151 "Extreme", /* 0xb5 */
152 "EC", /* 0xb6 */
153 "FE", /* 0xb7 */
154 "FE+", /* 0xb8 */
155 };
156
157 static void sky2_set_multicast(struct net_device *dev);
158
159 /* Access to PHY via serial interconnect */
160 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
161 {
162 int i;
163
164 gma_write16(hw, port, GM_SMI_DATA, val);
165 gma_write16(hw, port, GM_SMI_CTRL,
166 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
167
168 for (i = 0; i < PHY_RETRIES; i++) {
169 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
170 if (ctrl == 0xffff)
171 goto io_error;
172
173 if (!(ctrl & GM_SMI_CT_BUSY))
174 return 0;
175
176 udelay(10);
177 }
178
179 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
180 return -ETIMEDOUT;
181
182 io_error:
183 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
184 return -EIO;
185 }
186
187 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
188 {
189 int i;
190
191 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
192 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
193
194 for (i = 0; i < PHY_RETRIES; i++) {
195 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
196 if (ctrl == 0xffff)
197 goto io_error;
198
199 if (ctrl & GM_SMI_CT_RD_VAL) {
200 *val = gma_read16(hw, port, GM_SMI_DATA);
201 return 0;
202 }
203
204 udelay(10);
205 }
206
207 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
208 return -ETIMEDOUT;
209 io_error:
210 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
211 return -EIO;
212 }
213
214 static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
215 {
216 u16 v;
217 __gm_phy_read(hw, port, reg, &v);
218 return v;
219 }
220
221
222 static void sky2_power_on(struct sky2_hw *hw)
223 {
224 /* switch power to VCC (WA for VAUX problem) */
225 sky2_write8(hw, B0_POWER_CTRL,
226 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
227
228 /* disable Core Clock Division, */
229 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
230
231 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
232 /* enable bits are inverted */
233 sky2_write8(hw, B2_Y2_CLK_GATE,
234 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
235 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
236 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
237 else
238 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
239
240 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
241 u32 reg;
242
243 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
244
245 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
246 /* set all bits to 0 except bits 15..12 and 8 */
247 reg &= P_ASPM_CONTROL_MSK;
248 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
249
250 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
251 /* set all bits to 0 except bits 28 & 27 */
252 reg &= P_CTL_TIM_VMAIN_AV_MSK;
253 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
254
255 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
256
257 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
258 reg = sky2_read32(hw, B2_GP_IO);
259 reg |= GLB_GPIO_STAT_RACE_DIS;
260 sky2_write32(hw, B2_GP_IO, reg);
261
262 sky2_read32(hw, B2_GP_IO);
263 }
264 }
265
266 static void sky2_power_aux(struct sky2_hw *hw)
267 {
268 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
269 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
270 else
271 /* enable bits are inverted */
272 sky2_write8(hw, B2_Y2_CLK_GATE,
273 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
274 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
275 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
276
277 /* switch power to VAUX */
278 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
279 sky2_write8(hw, B0_POWER_CTRL,
280 (PC_VAUX_ENA | PC_VCC_ENA |
281 PC_VAUX_ON | PC_VCC_OFF));
282 }
283
284 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
285 {
286 u16 reg;
287
288 /* disable all GMAC IRQ's */
289 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
290
291 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
292 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
293 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
294 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
295
296 reg = gma_read16(hw, port, GM_RX_CTRL);
297 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
298 gma_write16(hw, port, GM_RX_CTRL, reg);
299 }
300
301 /* flow control to advertise bits */
302 static const u16 copper_fc_adv[] = {
303 [FC_NONE] = 0,
304 [FC_TX] = PHY_M_AN_ASP,
305 [FC_RX] = PHY_M_AN_PC,
306 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
307 };
308
309 /* flow control to advertise bits when using 1000BaseX */
310 static const u16 fiber_fc_adv[] = {
311 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
312 [FC_TX] = PHY_M_P_ASYM_MD_X,
313 [FC_RX] = PHY_M_P_SYM_MD_X,
314 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
315 };
316
317 /* flow control to GMA disable bits */
318 static const u16 gm_fc_disable[] = {
319 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
320 [FC_TX] = GM_GPCR_FC_RX_DIS,
321 [FC_RX] = GM_GPCR_FC_TX_DIS,
322 [FC_BOTH] = 0,
323 };
324
325
326 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
327 {
328 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
329 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
330
331 if (sky2->autoneg == AUTONEG_ENABLE &&
332 !(hw->flags & SKY2_HW_NEWER_PHY)) {
333 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
334
335 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
336 PHY_M_EC_MAC_S_MSK);
337 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
338
339 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
340 if (hw->chip_id == CHIP_ID_YUKON_EC)
341 /* set downshift counter to 3x and enable downshift */
342 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
343 else
344 /* set master & slave downshift counter to 1x */
345 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
346
347 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
348 }
349
350 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
351 if (sky2_is_copper(hw)) {
352 if (!(hw->flags & SKY2_HW_GIGABIT)) {
353 /* enable automatic crossover */
354 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
355
356 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
357 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
358 u16 spec;
359
360 /* Enable Class A driver for FE+ A0 */
361 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
362 spec |= PHY_M_FESC_SEL_CL_A;
363 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
364 }
365 } else {
366 /* disable energy detect */
367 ctrl &= ~PHY_M_PC_EN_DET_MSK;
368
369 /* enable automatic crossover */
370 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
371
372 /* downshift on PHY 88E1112 and 88E1149 is changed */
373 if (sky2->autoneg == AUTONEG_ENABLE
374 && (hw->flags & SKY2_HW_NEWER_PHY)) {
375 /* set downshift counter to 3x and enable downshift */
376 ctrl &= ~PHY_M_PC_DSC_MSK;
377 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
378 }
379 }
380 } else {
381 /* workaround for deviation #4.88 (CRC errors) */
382 /* disable Automatic Crossover */
383
384 ctrl &= ~PHY_M_PC_MDIX_MSK;
385 }
386
387 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
388
389 /* special setup for PHY 88E1112 Fiber */
390 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
391 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
392
393 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
394 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
395 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
396 ctrl &= ~PHY_M_MAC_MD_MSK;
397 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
398 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
399
400 if (hw->pmd_type == 'P') {
401 /* select page 1 to access Fiber registers */
402 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
403
404 /* for SFP-module set SIGDET polarity to low */
405 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
406 ctrl |= PHY_M_FIB_SIGD_POL;
407 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
408 }
409
410 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
411 }
412
413 ctrl = PHY_CT_RESET;
414 ct1000 = 0;
415 adv = PHY_AN_CSMA;
416 reg = 0;
417
418 if (sky2->autoneg == AUTONEG_ENABLE) {
419 if (sky2_is_copper(hw)) {
420 if (sky2->advertising & ADVERTISED_1000baseT_Full)
421 ct1000 |= PHY_M_1000C_AFD;
422 if (sky2->advertising & ADVERTISED_1000baseT_Half)
423 ct1000 |= PHY_M_1000C_AHD;
424 if (sky2->advertising & ADVERTISED_100baseT_Full)
425 adv |= PHY_M_AN_100_FD;
426 if (sky2->advertising & ADVERTISED_100baseT_Half)
427 adv |= PHY_M_AN_100_HD;
428 if (sky2->advertising & ADVERTISED_10baseT_Full)
429 adv |= PHY_M_AN_10_FD;
430 if (sky2->advertising & ADVERTISED_10baseT_Half)
431 adv |= PHY_M_AN_10_HD;
432
433 adv |= copper_fc_adv[sky2->flow_mode];
434 } else { /* special defines for FIBER (88E1040S only) */
435 if (sky2->advertising & ADVERTISED_1000baseT_Full)
436 adv |= PHY_M_AN_1000X_AFD;
437 if (sky2->advertising & ADVERTISED_1000baseT_Half)
438 adv |= PHY_M_AN_1000X_AHD;
439
440 adv |= fiber_fc_adv[sky2->flow_mode];
441 }
442
443 /* Restart Auto-negotiation */
444 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
445 } else {
446 /* forced speed/duplex settings */
447 ct1000 = PHY_M_1000C_MSE;
448
449 /* Disable auto update for duplex flow control and speed */
450 reg |= GM_GPCR_AU_ALL_DIS;
451
452 switch (sky2->speed) {
453 case SPEED_1000:
454 ctrl |= PHY_CT_SP1000;
455 reg |= GM_GPCR_SPEED_1000;
456 break;
457 case SPEED_100:
458 ctrl |= PHY_CT_SP100;
459 reg |= GM_GPCR_SPEED_100;
460 break;
461 }
462
463 if (sky2->duplex == DUPLEX_FULL) {
464 reg |= GM_GPCR_DUP_FULL;
465 ctrl |= PHY_CT_DUP_MD;
466 } else if (sky2->speed < SPEED_1000)
467 sky2->flow_mode = FC_NONE;
468
469
470 reg |= gm_fc_disable[sky2->flow_mode];
471
472 /* Forward pause packets to GMAC? */
473 if (sky2->flow_mode & FC_RX)
474 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
475 else
476 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
477 }
478
479 gma_write16(hw, port, GM_GP_CTRL, reg);
480
481 if (hw->flags & SKY2_HW_GIGABIT)
482 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
483
484 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
485 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
486
487 /* Setup Phy LED's */
488 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
489 ledover = 0;
490
491 switch (hw->chip_id) {
492 case CHIP_ID_YUKON_FE:
493 /* on 88E3082 these bits are at 11..9 (shifted left) */
494 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
495
496 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
497
498 /* delete ACT LED control bits */
499 ctrl &= ~PHY_M_FELP_LED1_MSK;
500 /* change ACT LED control to blink mode */
501 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
502 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
503 break;
504
505 case CHIP_ID_YUKON_FE_P:
506 /* Enable Link Partner Next Page */
507 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
508 ctrl |= PHY_M_PC_ENA_LIP_NP;
509
510 /* disable Energy Detect and enable scrambler */
511 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
512 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
513
514 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
515 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
516 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
517 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
518
519 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
520 break;
521
522 case CHIP_ID_YUKON_XL:
523 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
524
525 /* select page 3 to access LED control register */
526 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
527
528 /* set LED Function Control register */
529 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
530 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
531 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
532 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
533 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
534
535 /* set Polarity Control register */
536 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
537 (PHY_M_POLC_LS1_P_MIX(4) |
538 PHY_M_POLC_IS0_P_MIX(4) |
539 PHY_M_POLC_LOS_CTRL(2) |
540 PHY_M_POLC_INIT_CTRL(2) |
541 PHY_M_POLC_STA1_CTRL(2) |
542 PHY_M_POLC_STA0_CTRL(2)));
543
544 /* restore page register */
545 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
546 break;
547
548 case CHIP_ID_YUKON_EC_U:
549 case CHIP_ID_YUKON_EX:
550 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
551
552 /* select page 3 to access LED control register */
553 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
554
555 /* set LED Function Control register */
556 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
557 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
558 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
559 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
560 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
561
562 /* set Blink Rate in LED Timer Control Register */
563 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
564 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
565 /* restore page register */
566 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
567 break;
568
569 default:
570 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
571 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
572 /* turn off the Rx LED (LED_RX) */
573 ledover &= ~PHY_M_LED_MO_RX;
574 }
575
576 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
577 hw->chip_rev == CHIP_REV_YU_EC_U_A1) {
578 /* apply fixes in PHY AFE */
579 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
580
581 /* increase differential signal amplitude in 10BASE-T */
582 gm_phy_write(hw, port, 0x18, 0xaa99);
583 gm_phy_write(hw, port, 0x17, 0x2011);
584
585 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
586 gm_phy_write(hw, port, 0x18, 0xa204);
587 gm_phy_write(hw, port, 0x17, 0x2002);
588
589 /* set page register to 0 */
590 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
591 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
592 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
593 /* apply workaround for integrated resistors calibration */
594 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
595 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
596 } else if (hw->chip_id != CHIP_ID_YUKON_EX) {
597 /* no effect on Yukon-XL */
598 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
599
600 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
601 /* turn on 100 Mbps LED (LED_LINK100) */
602 ledover |= PHY_M_LED_MO_100;
603 }
604
605 if (ledover)
606 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
607
608 }
609
610 /* Enable phy interrupt on auto-negotiation complete (or link up) */
611 if (sky2->autoneg == AUTONEG_ENABLE)
612 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
613 else
614 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
615 }
616
617 static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
618 {
619 u32 reg1;
620 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
621 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
622
623 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
624 /* Turn on/off phy power saving */
625 if (onoff)
626 reg1 &= ~phy_power[port];
627 else
628 reg1 |= phy_power[port];
629
630 if (onoff && hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
631 reg1 |= coma_mode[port];
632
633 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
634 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
635
636 udelay(100);
637 }
638
639 /* Force a renegotiation */
640 static void sky2_phy_reinit(struct sky2_port *sky2)
641 {
642 spin_lock_bh(&sky2->phy_lock);
643 sky2_phy_init(sky2->hw, sky2->port);
644 spin_unlock_bh(&sky2->phy_lock);
645 }
646
647 /* Put device in state to listen for Wake On Lan */
648 static void sky2_wol_init(struct sky2_port *sky2)
649 {
650 struct sky2_hw *hw = sky2->hw;
651 unsigned port = sky2->port;
652 enum flow_control save_mode;
653 u16 ctrl;
654 u32 reg1;
655
656 /* Bring hardware out of reset */
657 sky2_write16(hw, B0_CTST, CS_RST_CLR);
658 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
659
660 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
661 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
662
663 /* Force to 10/100
664 * sky2_reset will re-enable on resume
665 */
666 save_mode = sky2->flow_mode;
667 ctrl = sky2->advertising;
668
669 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
670 sky2->flow_mode = FC_NONE;
671 sky2_phy_power(hw, port, 1);
672 sky2_phy_reinit(sky2);
673
674 sky2->flow_mode = save_mode;
675 sky2->advertising = ctrl;
676
677 /* Set GMAC to no flow control and auto update for speed/duplex */
678 gma_write16(hw, port, GM_GP_CTRL,
679 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
680 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
681
682 /* Set WOL address */
683 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
684 sky2->netdev->dev_addr, ETH_ALEN);
685
686 /* Turn on appropriate WOL control bits */
687 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
688 ctrl = 0;
689 if (sky2->wol & WAKE_PHY)
690 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
691 else
692 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
693
694 if (sky2->wol & WAKE_MAGIC)
695 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
696 else
697 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
698
699 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
700 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
701
702 /* Turn on legacy PCI-Express PME mode */
703 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
704 reg1 |= PCI_Y2_PME_LEGACY;
705 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
706
707 /* block receiver */
708 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
709
710 }
711
712 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
713 {
714 struct net_device *dev = hw->dev[port];
715
716 if (dev->mtu <= ETH_DATA_LEN)
717 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
718 TX_JUMBO_DIS | TX_STFW_ENA);
719
720 else if (hw->chip_id != CHIP_ID_YUKON_EC_U)
721 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
722 TX_STFW_ENA | TX_JUMBO_ENA);
723 else {
724 /* set Tx GMAC FIFO Almost Empty Threshold */
725 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
726 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
727
728 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
729 TX_JUMBO_ENA | TX_STFW_DIS);
730
731 /* Can't do offload because of lack of store/forward */
732 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
733 }
734 }
735
736 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
737 {
738 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
739 u16 reg;
740 u32 rx_reg;
741 int i;
742 const u8 *addr = hw->dev[port]->dev_addr;
743
744 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
745 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
746
747 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
748
749 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
750 /* WA DEV_472 -- looks like crossed wires on port 2 */
751 /* clear GMAC 1 Control reset */
752 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
753 do {
754 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
755 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
756 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
757 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
758 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
759 }
760
761 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
762
763 /* Enable Transmit FIFO Underrun */
764 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
765
766 spin_lock_bh(&sky2->phy_lock);
767 sky2_phy_init(hw, port);
768 spin_unlock_bh(&sky2->phy_lock);
769
770 /* MIB clear */
771 reg = gma_read16(hw, port, GM_PHY_ADDR);
772 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
773
774 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
775 gma_read16(hw, port, i);
776 gma_write16(hw, port, GM_PHY_ADDR, reg);
777
778 /* transmit control */
779 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
780
781 /* receive control reg: unicast + multicast + no FCS */
782 gma_write16(hw, port, GM_RX_CTRL,
783 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
784
785 /* transmit flow control */
786 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
787
788 /* transmit parameter */
789 gma_write16(hw, port, GM_TX_PARAM,
790 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
791 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
792 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
793 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
794
795 /* serial mode register */
796 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
797 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
798
799 if (hw->dev[port]->mtu > ETH_DATA_LEN)
800 reg |= GM_SMOD_JUMBO_ENA;
801
802 gma_write16(hw, port, GM_SERIAL_MODE, reg);
803
804 /* virtual address for data */
805 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
806
807 /* physical address: used for pause frames */
808 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
809
810 /* ignore counter overflows */
811 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
812 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
813 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
814
815 /* Configure Rx MAC FIFO */
816 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
817 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
818 if (hw->chip_id == CHIP_ID_YUKON_EX ||
819 hw->chip_id == CHIP_ID_YUKON_FE_P)
820 rx_reg |= GMF_RX_OVER_ON;
821
822 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
823
824 if (hw->chip_id == CHIP_ID_YUKON_XL) {
825 /* Hardware errata - clear flush mask */
826 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
827 } else {
828 /* Flush Rx MAC FIFO on any flow control or error */
829 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
830 }
831
832 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
833 reg = RX_GMF_FL_THR_DEF + 1;
834 /* Another magic mystery workaround from sk98lin */
835 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
836 hw->chip_rev == CHIP_REV_YU_FE2_A0)
837 reg = 0x178;
838 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
839
840 /* Configure Tx MAC FIFO */
841 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
842 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
843
844 /* On chips without ram buffer, pause is controled by MAC level */
845 if (sky2_read8(hw, B2_E_0) == 0) {
846 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
847 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
848
849 sky2_set_tx_stfwd(hw, port);
850 }
851
852 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
853 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
854 /* disable dynamic watermark */
855 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
856 reg &= ~TX_DYN_WM_ENA;
857 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
858 }
859 }
860
861 /* Assign Ram Buffer allocation to queue */
862 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
863 {
864 u32 end;
865
866 /* convert from K bytes to qwords used for hw register */
867 start *= 1024/8;
868 space *= 1024/8;
869 end = start + space - 1;
870
871 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
872 sky2_write32(hw, RB_ADDR(q, RB_START), start);
873 sky2_write32(hw, RB_ADDR(q, RB_END), end);
874 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
875 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
876
877 if (q == Q_R1 || q == Q_R2) {
878 u32 tp = space - space/4;
879
880 /* On receive queue's set the thresholds
881 * give receiver priority when > 3/4 full
882 * send pause when down to 2K
883 */
884 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
885 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
886
887 tp = space - 2048/8;
888 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
889 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
890 } else {
891 /* Enable store & forward on Tx queue's because
892 * Tx FIFO is only 1K on Yukon
893 */
894 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
895 }
896
897 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
898 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
899 }
900
901 /* Setup Bus Memory Interface */
902 static void sky2_qset(struct sky2_hw *hw, u16 q)
903 {
904 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
905 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
906 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
907 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
908 }
909
910 /* Setup prefetch unit registers. This is the interface between
911 * hardware and driver list elements
912 */
913 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
914 u64 addr, u32 last)
915 {
916 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
917 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
918 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
919 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
920 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
921 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
922
923 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
924 }
925
926 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
927 {
928 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
929
930 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
931 le->ctrl = 0;
932 return le;
933 }
934
935 static void tx_init(struct sky2_port *sky2)
936 {
937 struct sky2_tx_le *le;
938
939 sky2->tx_prod = sky2->tx_cons = 0;
940 sky2->tx_tcpsum = 0;
941 sky2->tx_last_mss = 0;
942
943 le = get_tx_le(sky2);
944 le->addr = 0;
945 le->opcode = OP_ADDR64 | HW_OWNER;
946 }
947
948 static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
949 struct sky2_tx_le *le)
950 {
951 return sky2->tx_ring + (le - sky2->tx_le);
952 }
953
954 /* Update chip's next pointer */
955 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
956 {
957 /* Make sure write' to descriptors are complete before we tell hardware */
958 wmb();
959 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
960
961 /* Synchronize I/O on since next processor may write to tail */
962 mmiowb();
963 }
964
965
966 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
967 {
968 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
969 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
970 le->ctrl = 0;
971 return le;
972 }
973
974 /* Build description to hardware for one receive segment */
975 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
976 dma_addr_t map, unsigned len)
977 {
978 struct sky2_rx_le *le;
979
980 if (sizeof(dma_addr_t) > sizeof(u32)) {
981 le = sky2_next_rx(sky2);
982 le->addr = cpu_to_le32(upper_32_bits(map));
983 le->opcode = OP_ADDR64 | HW_OWNER;
984 }
985
986 le = sky2_next_rx(sky2);
987 le->addr = cpu_to_le32((u32) map);
988 le->length = cpu_to_le16(len);
989 le->opcode = op | HW_OWNER;
990 }
991
992 /* Build description to hardware for one possibly fragmented skb */
993 static void sky2_rx_submit(struct sky2_port *sky2,
994 const struct rx_ring_info *re)
995 {
996 int i;
997
998 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
999
1000 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1001 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1002 }
1003
1004
1005 static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
1006 unsigned size)
1007 {
1008 struct sk_buff *skb = re->skb;
1009 int i;
1010
1011 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
1012 pci_unmap_len_set(re, data_size, size);
1013
1014 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1015 re->frag_addr[i] = pci_map_page(pdev,
1016 skb_shinfo(skb)->frags[i].page,
1017 skb_shinfo(skb)->frags[i].page_offset,
1018 skb_shinfo(skb)->frags[i].size,
1019 PCI_DMA_FROMDEVICE);
1020 }
1021
1022 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1023 {
1024 struct sk_buff *skb = re->skb;
1025 int i;
1026
1027 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1028 PCI_DMA_FROMDEVICE);
1029
1030 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1031 pci_unmap_page(pdev, re->frag_addr[i],
1032 skb_shinfo(skb)->frags[i].size,
1033 PCI_DMA_FROMDEVICE);
1034 }
1035
1036 /* Tell chip where to start receive checksum.
1037 * Actually has two checksums, but set both same to avoid possible byte
1038 * order problems.
1039 */
1040 static void rx_set_checksum(struct sky2_port *sky2)
1041 {
1042 struct sky2_rx_le *le = sky2_next_rx(sky2);
1043
1044 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1045 le->ctrl = 0;
1046 le->opcode = OP_TCPSTART | HW_OWNER;
1047
1048 sky2_write32(sky2->hw,
1049 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1050 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
1051 }
1052
1053 /*
1054 * The RX Stop command will not work for Yukon-2 if the BMU does not
1055 * reach the end of packet and since we can't make sure that we have
1056 * incoming data, we must reset the BMU while it is not doing a DMA
1057 * transfer. Since it is possible that the RX path is still active,
1058 * the RX RAM buffer will be stopped first, so any possible incoming
1059 * data will not trigger a DMA. After the RAM buffer is stopped, the
1060 * BMU is polled until any DMA in progress is ended and only then it
1061 * will be reset.
1062 */
1063 static void sky2_rx_stop(struct sky2_port *sky2)
1064 {
1065 struct sky2_hw *hw = sky2->hw;
1066 unsigned rxq = rxqaddr[sky2->port];
1067 int i;
1068
1069 /* disable the RAM Buffer receive queue */
1070 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1071
1072 for (i = 0; i < 0xffff; i++)
1073 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1074 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1075 goto stopped;
1076
1077 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1078 sky2->netdev->name);
1079 stopped:
1080 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1081
1082 /* reset the Rx prefetch unit */
1083 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1084 mmiowb();
1085 }
1086
1087 /* Clean out receive buffer area, assumes receiver hardware stopped */
1088 static void sky2_rx_clean(struct sky2_port *sky2)
1089 {
1090 unsigned i;
1091
1092 memset(sky2->rx_le, 0, RX_LE_BYTES);
1093 for (i = 0; i < sky2->rx_pending; i++) {
1094 struct rx_ring_info *re = sky2->rx_ring + i;
1095
1096 if (re->skb) {
1097 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1098 kfree_skb(re->skb);
1099 re->skb = NULL;
1100 }
1101 }
1102 }
1103
1104 /* Basic MII support */
1105 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1106 {
1107 struct mii_ioctl_data *data = if_mii(ifr);
1108 struct sky2_port *sky2 = netdev_priv(dev);
1109 struct sky2_hw *hw = sky2->hw;
1110 int err = -EOPNOTSUPP;
1111
1112 if (!netif_running(dev))
1113 return -ENODEV; /* Phy still in reset */
1114
1115 switch (cmd) {
1116 case SIOCGMIIPHY:
1117 data->phy_id = PHY_ADDR_MARV;
1118
1119 /* fallthru */
1120 case SIOCGMIIREG: {
1121 u16 val = 0;
1122
1123 spin_lock_bh(&sky2->phy_lock);
1124 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1125 spin_unlock_bh(&sky2->phy_lock);
1126
1127 data->val_out = val;
1128 break;
1129 }
1130
1131 case SIOCSMIIREG:
1132 if (!capable(CAP_NET_ADMIN))
1133 return -EPERM;
1134
1135 spin_lock_bh(&sky2->phy_lock);
1136 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1137 data->val_in);
1138 spin_unlock_bh(&sky2->phy_lock);
1139 break;
1140 }
1141 return err;
1142 }
1143
1144 #ifdef SKY2_VLAN_TAG_USED
1145 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1146 {
1147 struct sky2_port *sky2 = netdev_priv(dev);
1148 struct sky2_hw *hw = sky2->hw;
1149 u16 port = sky2->port;
1150
1151 netif_tx_lock_bh(dev);
1152 napi_disable(&hw->napi);
1153
1154 sky2->vlgrp = grp;
1155 if (grp) {
1156 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1157 RX_VLAN_STRIP_ON);
1158 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1159 TX_VLAN_TAG_ON);
1160 } else {
1161 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1162 RX_VLAN_STRIP_OFF);
1163 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1164 TX_VLAN_TAG_OFF);
1165 }
1166
1167 sky2_read32(hw, B0_Y2_SP_LISR);
1168 napi_enable(&hw->napi);
1169 netif_tx_unlock_bh(dev);
1170 }
1171 #endif
1172
1173 /*
1174 * Allocate an skb for receiving. If the MTU is large enough
1175 * make the skb non-linear with a fragment list of pages.
1176 */
1177 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
1178 {
1179 struct sk_buff *skb;
1180 int i;
1181
1182 if (sky2->hw->flags & SKY2_HW_FIFO_HANG_CHECK) {
1183 unsigned char *start;
1184 /*
1185 * Workaround for a bug in FIFO that cause hang
1186 * if the FIFO if the receive buffer is not 64 byte aligned.
1187 * The buffer returned from netdev_alloc_skb is
1188 * aligned except if slab debugging is enabled.
1189 */
1190 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + 8);
1191 if (!skb)
1192 goto nomem;
1193 start = PTR_ALIGN(skb->data, 8);
1194 skb_reserve(skb, start - skb->data);
1195 } else {
1196 skb = netdev_alloc_skb(sky2->netdev,
1197 sky2->rx_data_size + NET_IP_ALIGN);
1198 if (!skb)
1199 goto nomem;
1200 skb_reserve(skb, NET_IP_ALIGN);
1201 }
1202
1203 for (i = 0; i < sky2->rx_nfrags; i++) {
1204 struct page *page = alloc_page(GFP_ATOMIC);
1205
1206 if (!page)
1207 goto free_partial;
1208 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1209 }
1210
1211 return skb;
1212 free_partial:
1213 kfree_skb(skb);
1214 nomem:
1215 return NULL;
1216 }
1217
1218 static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1219 {
1220 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1221 }
1222
1223 /*
1224 * Allocate and setup receiver buffer pool.
1225 * Normal case this ends up creating one list element for skb
1226 * in the receive ring. Worst case if using large MTU and each
1227 * allocation falls on a different 64 bit region, that results
1228 * in 6 list elements per ring entry.
1229 * One element is used for checksum enable/disable, and one
1230 * extra to avoid wrap.
1231 */
1232 static int sky2_rx_start(struct sky2_port *sky2)
1233 {
1234 struct sky2_hw *hw = sky2->hw;
1235 struct rx_ring_info *re;
1236 unsigned rxq = rxqaddr[sky2->port];
1237 unsigned i, size, thresh;
1238
1239 sky2->rx_put = sky2->rx_next = 0;
1240 sky2_qset(hw, rxq);
1241
1242 /* On PCI express lowering the watermark gives better performance */
1243 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1244 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1245
1246 /* These chips have no ram buffer?
1247 * MAC Rx RAM Read is controlled by hardware */
1248 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1249 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1250 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
1251 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
1252
1253 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1254
1255 if (!(hw->flags & SKY2_HW_NEW_LE))
1256 rx_set_checksum(sky2);
1257
1258 /* Space needed for frame data + headers rounded up */
1259 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1260
1261 /* Stopping point for hardware truncation */
1262 thresh = (size - 8) / sizeof(u32);
1263
1264 sky2->rx_nfrags = size >> PAGE_SHIFT;
1265 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1266
1267 /* Compute residue after pages */
1268 size -= sky2->rx_nfrags << PAGE_SHIFT;
1269
1270 /* Optimize to handle small packets and headers */
1271 if (size < copybreak)
1272 size = copybreak;
1273 if (size < ETH_HLEN)
1274 size = ETH_HLEN;
1275
1276 sky2->rx_data_size = size;
1277
1278 /* Fill Rx ring */
1279 for (i = 0; i < sky2->rx_pending; i++) {
1280 re = sky2->rx_ring + i;
1281
1282 re->skb = sky2_rx_alloc(sky2);
1283 if (!re->skb)
1284 goto nomem;
1285
1286 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1287 sky2_rx_submit(sky2, re);
1288 }
1289
1290 /*
1291 * The receiver hangs if it receives frames larger than the
1292 * packet buffer. As a workaround, truncate oversize frames, but
1293 * the register is limited to 9 bits, so if you do frames > 2052
1294 * you better get the MTU right!
1295 */
1296 if (thresh > 0x1ff)
1297 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1298 else {
1299 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1300 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1301 }
1302
1303 /* Tell chip about available buffers */
1304 sky2_rx_update(sky2, rxq);
1305 return 0;
1306 nomem:
1307 sky2_rx_clean(sky2);
1308 return -ENOMEM;
1309 }
1310
1311 /* Bring up network interface. */
1312 static int sky2_up(struct net_device *dev)
1313 {
1314 struct sky2_port *sky2 = netdev_priv(dev);
1315 struct sky2_hw *hw = sky2->hw;
1316 unsigned port = sky2->port;
1317 u32 imask, ramsize;
1318 int cap, err = -ENOMEM;
1319 struct net_device *otherdev = hw->dev[sky2->port^1];
1320
1321 /*
1322 * On dual port PCI-X card, there is an problem where status
1323 * can be received out of order due to split transactions
1324 */
1325 if (otherdev && netif_running(otherdev) &&
1326 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1327 u16 cmd;
1328
1329 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1330 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1331 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1332
1333 }
1334
1335 if (netif_msg_ifup(sky2))
1336 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1337
1338 netif_carrier_off(dev);
1339
1340 /* must be power of 2 */
1341 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1342 TX_RING_SIZE *
1343 sizeof(struct sky2_tx_le),
1344 &sky2->tx_le_map);
1345 if (!sky2->tx_le)
1346 goto err_out;
1347
1348 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
1349 GFP_KERNEL);
1350 if (!sky2->tx_ring)
1351 goto err_out;
1352
1353 tx_init(sky2);
1354
1355 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1356 &sky2->rx_le_map);
1357 if (!sky2->rx_le)
1358 goto err_out;
1359 memset(sky2->rx_le, 0, RX_LE_BYTES);
1360
1361 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1362 GFP_KERNEL);
1363 if (!sky2->rx_ring)
1364 goto err_out;
1365
1366 sky2_phy_power(hw, port, 1);
1367
1368 sky2_mac_init(hw, port);
1369
1370 /* Register is number of 4K blocks on internal RAM buffer. */
1371 ramsize = sky2_read8(hw, B2_E_0) * 4;
1372 if (ramsize > 0) {
1373 u32 rxspace;
1374
1375 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1376 if (ramsize < 16)
1377 rxspace = ramsize / 2;
1378 else
1379 rxspace = 8 + (2*(ramsize - 16))/3;
1380
1381 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1382 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1383
1384 /* Make sure SyncQ is disabled */
1385 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1386 RB_RST_SET);
1387 }
1388
1389 sky2_qset(hw, txqaddr[port]);
1390
1391 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1392 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1393 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1394
1395 /* Set almost empty threshold */
1396 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1397 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1398 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
1399
1400 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1401 TX_RING_SIZE - 1);
1402
1403 err = sky2_rx_start(sky2);
1404 if (err)
1405 goto err_out;
1406
1407 /* Enable interrupts from phy/mac for port */
1408 imask = sky2_read32(hw, B0_IMSK);
1409 imask |= portirq_msk[port];
1410 sky2_write32(hw, B0_IMSK, imask);
1411
1412 return 0;
1413
1414 err_out:
1415 if (sky2->rx_le) {
1416 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1417 sky2->rx_le, sky2->rx_le_map);
1418 sky2->rx_le = NULL;
1419 }
1420 if (sky2->tx_le) {
1421 pci_free_consistent(hw->pdev,
1422 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1423 sky2->tx_le, sky2->tx_le_map);
1424 sky2->tx_le = NULL;
1425 }
1426 kfree(sky2->tx_ring);
1427 kfree(sky2->rx_ring);
1428
1429 sky2->tx_ring = NULL;
1430 sky2->rx_ring = NULL;
1431 return err;
1432 }
1433
1434 /* Modular subtraction in ring */
1435 static inline int tx_dist(unsigned tail, unsigned head)
1436 {
1437 return (head - tail) & (TX_RING_SIZE - 1);
1438 }
1439
1440 /* Number of list elements available for next tx */
1441 static inline int tx_avail(const struct sky2_port *sky2)
1442 {
1443 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1444 }
1445
1446 /* Estimate of number of transmit list elements required */
1447 static unsigned tx_le_req(const struct sk_buff *skb)
1448 {
1449 unsigned count;
1450
1451 count = sizeof(dma_addr_t) / sizeof(u32);
1452 count += skb_shinfo(skb)->nr_frags * count;
1453
1454 if (skb_is_gso(skb))
1455 ++count;
1456
1457 if (skb->ip_summed == CHECKSUM_PARTIAL)
1458 ++count;
1459
1460 return count;
1461 }
1462
1463 /*
1464 * Put one packet in ring for transmit.
1465 * A single packet can generate multiple list elements, and
1466 * the number of ring elements will probably be less than the number
1467 * of list elements used.
1468 */
1469 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1470 {
1471 struct sky2_port *sky2 = netdev_priv(dev);
1472 struct sky2_hw *hw = sky2->hw;
1473 struct sky2_tx_le *le = NULL;
1474 struct tx_ring_info *re;
1475 unsigned i, len;
1476 dma_addr_t mapping;
1477 u16 mss;
1478 u8 ctrl;
1479
1480 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1481 return NETDEV_TX_BUSY;
1482
1483 if (unlikely(netif_msg_tx_queued(sky2)))
1484 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1485 dev->name, sky2->tx_prod, skb->len);
1486
1487 len = skb_headlen(skb);
1488 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1489
1490 /* Send high bits if needed */
1491 if (sizeof(dma_addr_t) > sizeof(u32)) {
1492 le = get_tx_le(sky2);
1493 le->addr = cpu_to_le32(upper_32_bits(mapping));
1494 le->opcode = OP_ADDR64 | HW_OWNER;
1495 }
1496
1497 /* Check for TCP Segmentation Offload */
1498 mss = skb_shinfo(skb)->gso_size;
1499 if (mss != 0) {
1500
1501 if (!(hw->flags & SKY2_HW_NEW_LE))
1502 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1503
1504 if (mss != sky2->tx_last_mss) {
1505 le = get_tx_le(sky2);
1506 le->addr = cpu_to_le32(mss);
1507
1508 if (hw->flags & SKY2_HW_NEW_LE)
1509 le->opcode = OP_MSS | HW_OWNER;
1510 else
1511 le->opcode = OP_LRGLEN | HW_OWNER;
1512 sky2->tx_last_mss = mss;
1513 }
1514 }
1515
1516 ctrl = 0;
1517 #ifdef SKY2_VLAN_TAG_USED
1518 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1519 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1520 if (!le) {
1521 le = get_tx_le(sky2);
1522 le->addr = 0;
1523 le->opcode = OP_VLAN|HW_OWNER;
1524 } else
1525 le->opcode |= OP_VLAN;
1526 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1527 ctrl |= INS_VLAN;
1528 }
1529 #endif
1530
1531 /* Handle TCP checksum offload */
1532 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1533 /* On Yukon EX (some versions) encoding change. */
1534 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
1535 ctrl |= CALSUM; /* auto checksum */
1536 else {
1537 const unsigned offset = skb_transport_offset(skb);
1538 u32 tcpsum;
1539
1540 tcpsum = offset << 16; /* sum start */
1541 tcpsum |= offset + skb->csum_offset; /* sum write */
1542
1543 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1544 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1545 ctrl |= UDPTCP;
1546
1547 if (tcpsum != sky2->tx_tcpsum) {
1548 sky2->tx_tcpsum = tcpsum;
1549
1550 le = get_tx_le(sky2);
1551 le->addr = cpu_to_le32(tcpsum);
1552 le->length = 0; /* initial checksum value */
1553 le->ctrl = 1; /* one packet */
1554 le->opcode = OP_TCPLISW | HW_OWNER;
1555 }
1556 }
1557 }
1558
1559 le = get_tx_le(sky2);
1560 le->addr = cpu_to_le32((u32) mapping);
1561 le->length = cpu_to_le16(len);
1562 le->ctrl = ctrl;
1563 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1564
1565 re = tx_le_re(sky2, le);
1566 re->skb = skb;
1567 pci_unmap_addr_set(re, mapaddr, mapping);
1568 pci_unmap_len_set(re, maplen, len);
1569
1570 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1571 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1572
1573 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1574 frag->size, PCI_DMA_TODEVICE);
1575
1576 if (sizeof(dma_addr_t) > sizeof(u32)) {
1577 le = get_tx_le(sky2);
1578 le->addr = cpu_to_le32(upper_32_bits(mapping));
1579 le->ctrl = 0;
1580 le->opcode = OP_ADDR64 | HW_OWNER;
1581 }
1582
1583 le = get_tx_le(sky2);
1584 le->addr = cpu_to_le32((u32) mapping);
1585 le->length = cpu_to_le16(frag->size);
1586 le->ctrl = ctrl;
1587 le->opcode = OP_BUFFER | HW_OWNER;
1588
1589 re = tx_le_re(sky2, le);
1590 re->skb = skb;
1591 pci_unmap_addr_set(re, mapaddr, mapping);
1592 pci_unmap_len_set(re, maplen, frag->size);
1593 }
1594
1595 le->ctrl |= EOP;
1596
1597 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1598 netif_stop_queue(dev);
1599
1600 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1601
1602 dev->trans_start = jiffies;
1603 return NETDEV_TX_OK;
1604 }
1605
1606 /*
1607 * Free ring elements from starting at tx_cons until "done"
1608 *
1609 * NB: the hardware will tell us about partial completion of multi-part
1610 * buffers so make sure not to free skb to early.
1611 */
1612 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1613 {
1614 struct net_device *dev = sky2->netdev;
1615 struct pci_dev *pdev = sky2->hw->pdev;
1616 unsigned idx;
1617
1618 BUG_ON(done >= TX_RING_SIZE);
1619
1620 for (idx = sky2->tx_cons; idx != done;
1621 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1622 struct sky2_tx_le *le = sky2->tx_le + idx;
1623 struct tx_ring_info *re = sky2->tx_ring + idx;
1624
1625 switch(le->opcode & ~HW_OWNER) {
1626 case OP_LARGESEND:
1627 case OP_PACKET:
1628 pci_unmap_single(pdev,
1629 pci_unmap_addr(re, mapaddr),
1630 pci_unmap_len(re, maplen),
1631 PCI_DMA_TODEVICE);
1632 break;
1633 case OP_BUFFER:
1634 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1635 pci_unmap_len(re, maplen),
1636 PCI_DMA_TODEVICE);
1637 break;
1638 }
1639
1640 if (le->ctrl & EOP) {
1641 if (unlikely(netif_msg_tx_done(sky2)))
1642 printk(KERN_DEBUG "%s: tx done %u\n",
1643 dev->name, idx);
1644
1645 dev->stats.tx_packets++;
1646 dev->stats.tx_bytes += re->skb->len;
1647
1648 dev_kfree_skb_any(re->skb);
1649 sky2->tx_next = RING_NEXT(idx, TX_RING_SIZE);
1650 }
1651 }
1652
1653 sky2->tx_cons = idx;
1654 smp_mb();
1655
1656 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
1657 netif_wake_queue(dev);
1658 }
1659
1660 /* Cleanup all untransmitted buffers, assume transmitter not running */
1661 static void sky2_tx_clean(struct net_device *dev)
1662 {
1663 struct sky2_port *sky2 = netdev_priv(dev);
1664
1665 netif_tx_lock_bh(dev);
1666 sky2_tx_complete(sky2, sky2->tx_prod);
1667 netif_tx_unlock_bh(dev);
1668 }
1669
1670 /* Network shutdown */
1671 static int sky2_down(struct net_device *dev)
1672 {
1673 struct sky2_port *sky2 = netdev_priv(dev);
1674 struct sky2_hw *hw = sky2->hw;
1675 unsigned port = sky2->port;
1676 u16 ctrl;
1677 u32 imask;
1678
1679 /* Never really got started! */
1680 if (!sky2->tx_le)
1681 return 0;
1682
1683 if (netif_msg_ifdown(sky2))
1684 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1685
1686 /* Stop more packets from being queued */
1687 netif_stop_queue(dev);
1688
1689 /* Disable port IRQ */
1690 imask = sky2_read32(hw, B0_IMSK);
1691 imask &= ~portirq_msk[port];
1692 sky2_write32(hw, B0_IMSK, imask);
1693
1694 synchronize_irq(hw->pdev->irq);
1695
1696 sky2_gmac_reset(hw, port);
1697
1698 /* Stop transmitter */
1699 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1700 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1701
1702 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1703 RB_RST_SET | RB_DIS_OP_MD);
1704
1705 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1706 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1707 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1708
1709 /* Make sure no packets are pending */
1710 napi_synchronize(&hw->napi);
1711
1712 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1713
1714 /* Workaround shared GMAC reset */
1715 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1716 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1717 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1718
1719 /* Disable Force Sync bit and Enable Alloc bit */
1720 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1721 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1722
1723 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1724 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1725 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1726
1727 /* Reset the PCI FIFO of the async Tx queue */
1728 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1729 BMU_RST_SET | BMU_FIFO_RST);
1730
1731 /* Reset the Tx prefetch units */
1732 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1733 PREF_UNIT_RST_SET);
1734
1735 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1736
1737 sky2_rx_stop(sky2);
1738
1739 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1740 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1741
1742 sky2_phy_power(hw, port, 0);
1743
1744 netif_carrier_off(dev);
1745
1746 /* turn off LED's */
1747 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1748
1749 sky2_tx_clean(dev);
1750 sky2_rx_clean(sky2);
1751
1752 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1753 sky2->rx_le, sky2->rx_le_map);
1754 kfree(sky2->rx_ring);
1755
1756 pci_free_consistent(hw->pdev,
1757 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1758 sky2->tx_le, sky2->tx_le_map);
1759 kfree(sky2->tx_ring);
1760
1761 sky2->tx_le = NULL;
1762 sky2->rx_le = NULL;
1763
1764 sky2->rx_ring = NULL;
1765 sky2->tx_ring = NULL;
1766
1767 return 0;
1768 }
1769
1770 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1771 {
1772 if (hw->flags & SKY2_HW_FIBRE_PHY)
1773 return SPEED_1000;
1774
1775 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1776 if (aux & PHY_M_PS_SPEED_100)
1777 return SPEED_100;
1778 else
1779 return SPEED_10;
1780 }
1781
1782 switch (aux & PHY_M_PS_SPEED_MSK) {
1783 case PHY_M_PS_SPEED_1000:
1784 return SPEED_1000;
1785 case PHY_M_PS_SPEED_100:
1786 return SPEED_100;
1787 default:
1788 return SPEED_10;
1789 }
1790 }
1791
1792 static void sky2_link_up(struct sky2_port *sky2)
1793 {
1794 struct sky2_hw *hw = sky2->hw;
1795 unsigned port = sky2->port;
1796 u16 reg;
1797 static const char *fc_name[] = {
1798 [FC_NONE] = "none",
1799 [FC_TX] = "tx",
1800 [FC_RX] = "rx",
1801 [FC_BOTH] = "both",
1802 };
1803
1804 /* enable Rx/Tx */
1805 reg = gma_read16(hw, port, GM_GP_CTRL);
1806 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1807 gma_write16(hw, port, GM_GP_CTRL, reg);
1808
1809 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1810
1811 netif_carrier_on(sky2->netdev);
1812
1813 mod_timer(&hw->watchdog_timer, jiffies + 1);
1814
1815 /* Turn on link LED */
1816 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1817 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1818
1819 if (netif_msg_link(sky2))
1820 printk(KERN_INFO PFX
1821 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1822 sky2->netdev->name, sky2->speed,
1823 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1824 fc_name[sky2->flow_status]);
1825 }
1826
1827 static void sky2_link_down(struct sky2_port *sky2)
1828 {
1829 struct sky2_hw *hw = sky2->hw;
1830 unsigned port = sky2->port;
1831 u16 reg;
1832
1833 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1834
1835 reg = gma_read16(hw, port, GM_GP_CTRL);
1836 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1837 gma_write16(hw, port, GM_GP_CTRL, reg);
1838
1839 netif_carrier_off(sky2->netdev);
1840
1841 /* Turn on link LED */
1842 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1843
1844 if (netif_msg_link(sky2))
1845 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1846
1847 sky2_phy_init(hw, port);
1848 }
1849
1850 static enum flow_control sky2_flow(int rx, int tx)
1851 {
1852 if (rx)
1853 return tx ? FC_BOTH : FC_RX;
1854 else
1855 return tx ? FC_TX : FC_NONE;
1856 }
1857
1858 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1859 {
1860 struct sky2_hw *hw = sky2->hw;
1861 unsigned port = sky2->port;
1862 u16 advert, lpa;
1863
1864 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
1865 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1866 if (lpa & PHY_M_AN_RF) {
1867 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1868 return -1;
1869 }
1870
1871 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1872 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1873 sky2->netdev->name);
1874 return -1;
1875 }
1876
1877 sky2->speed = sky2_phy_speed(hw, aux);
1878 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1879
1880 /* Since the pause result bits seem to in different positions on
1881 * different chips. look at registers.
1882 */
1883 if (hw->flags & SKY2_HW_FIBRE_PHY) {
1884 /* Shift for bits in fiber PHY */
1885 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
1886 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
1887
1888 if (advert & ADVERTISE_1000XPAUSE)
1889 advert |= ADVERTISE_PAUSE_CAP;
1890 if (advert & ADVERTISE_1000XPSE_ASYM)
1891 advert |= ADVERTISE_PAUSE_ASYM;
1892 if (lpa & LPA_1000XPAUSE)
1893 lpa |= LPA_PAUSE_CAP;
1894 if (lpa & LPA_1000XPAUSE_ASYM)
1895 lpa |= LPA_PAUSE_ASYM;
1896 }
1897
1898 sky2->flow_status = FC_NONE;
1899 if (advert & ADVERTISE_PAUSE_CAP) {
1900 if (lpa & LPA_PAUSE_CAP)
1901 sky2->flow_status = FC_BOTH;
1902 else if (advert & ADVERTISE_PAUSE_ASYM)
1903 sky2->flow_status = FC_RX;
1904 } else if (advert & ADVERTISE_PAUSE_ASYM) {
1905 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
1906 sky2->flow_status = FC_TX;
1907 }
1908
1909 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
1910 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
1911 sky2->flow_status = FC_NONE;
1912
1913 if (sky2->flow_status & FC_TX)
1914 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1915 else
1916 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1917
1918 return 0;
1919 }
1920
1921 /* Interrupt from PHY */
1922 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
1923 {
1924 struct net_device *dev = hw->dev[port];
1925 struct sky2_port *sky2 = netdev_priv(dev);
1926 u16 istatus, phystat;
1927
1928 if (!netif_running(dev))
1929 return;
1930
1931 spin_lock(&sky2->phy_lock);
1932 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1933 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1934
1935 if (netif_msg_intr(sky2))
1936 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1937 sky2->netdev->name, istatus, phystat);
1938
1939 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
1940 if (sky2_autoneg_done(sky2, phystat) == 0)
1941 sky2_link_up(sky2);
1942 goto out;
1943 }
1944
1945 if (istatus & PHY_M_IS_LSP_CHANGE)
1946 sky2->speed = sky2_phy_speed(hw, phystat);
1947
1948 if (istatus & PHY_M_IS_DUP_CHANGE)
1949 sky2->duplex =
1950 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1951
1952 if (istatus & PHY_M_IS_LST_CHANGE) {
1953 if (phystat & PHY_M_PS_LINK_UP)
1954 sky2_link_up(sky2);
1955 else
1956 sky2_link_down(sky2);
1957 }
1958 out:
1959 spin_unlock(&sky2->phy_lock);
1960 }
1961
1962 /* Transmit timeout is only called if we are running, carrier is up
1963 * and tx queue is full (stopped).
1964 */
1965 static void sky2_tx_timeout(struct net_device *dev)
1966 {
1967 struct sky2_port *sky2 = netdev_priv(dev);
1968 struct sky2_hw *hw = sky2->hw;
1969
1970 if (netif_msg_timer(sky2))
1971 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1972
1973 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
1974 dev->name, sky2->tx_cons, sky2->tx_prod,
1975 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
1976 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
1977
1978 /* can't restart safely under softirq */
1979 schedule_work(&hw->restart_work);
1980 }
1981
1982 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1983 {
1984 struct sky2_port *sky2 = netdev_priv(dev);
1985 struct sky2_hw *hw = sky2->hw;
1986 unsigned port = sky2->port;
1987 int err;
1988 u16 ctl, mode;
1989 u32 imask;
1990
1991 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1992 return -EINVAL;
1993
1994 if (new_mtu > ETH_DATA_LEN &&
1995 (hw->chip_id == CHIP_ID_YUKON_FE ||
1996 hw->chip_id == CHIP_ID_YUKON_FE_P))
1997 return -EINVAL;
1998
1999 if (!netif_running(dev)) {
2000 dev->mtu = new_mtu;
2001 return 0;
2002 }
2003
2004 imask = sky2_read32(hw, B0_IMSK);
2005 sky2_write32(hw, B0_IMSK, 0);
2006
2007 dev->trans_start = jiffies; /* prevent tx timeout */
2008 netif_stop_queue(dev);
2009 napi_disable(&hw->napi);
2010
2011 synchronize_irq(hw->pdev->irq);
2012
2013 if (sky2_read8(hw, B2_E_0) == 0)
2014 sky2_set_tx_stfwd(hw, port);
2015
2016 ctl = gma_read16(hw, port, GM_GP_CTRL);
2017 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
2018 sky2_rx_stop(sky2);
2019 sky2_rx_clean(sky2);
2020
2021 dev->mtu = new_mtu;
2022
2023 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2024 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2025
2026 if (dev->mtu > ETH_DATA_LEN)
2027 mode |= GM_SMOD_JUMBO_ENA;
2028
2029 gma_write16(hw, port, GM_SERIAL_MODE, mode);
2030
2031 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
2032
2033 err = sky2_rx_start(sky2);
2034 sky2_write32(hw, B0_IMSK, imask);
2035
2036 sky2_read32(hw, B0_Y2_SP_LISR);
2037 napi_enable(&hw->napi);
2038
2039 if (err)
2040 dev_close(dev);
2041 else {
2042 gma_write16(hw, port, GM_GP_CTRL, ctl);
2043
2044 netif_wake_queue(dev);
2045 }
2046
2047 return err;
2048 }
2049
2050 /* For small just reuse existing skb for next receive */
2051 static struct sk_buff *receive_copy(struct sky2_port *sky2,
2052 const struct rx_ring_info *re,
2053 unsigned length)
2054 {
2055 struct sk_buff *skb;
2056
2057 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2058 if (likely(skb)) {
2059 skb_reserve(skb, 2);
2060 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2061 length, PCI_DMA_FROMDEVICE);
2062 skb_copy_from_linear_data(re->skb, skb->data, length);
2063 skb->ip_summed = re->skb->ip_summed;
2064 skb->csum = re->skb->csum;
2065 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2066 length, PCI_DMA_FROMDEVICE);
2067 re->skb->ip_summed = CHECKSUM_NONE;
2068 skb_put(skb, length);
2069 }
2070 return skb;
2071 }
2072
2073 /* Adjust length of skb with fragments to match received data */
2074 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2075 unsigned int length)
2076 {
2077 int i, num_frags;
2078 unsigned int size;
2079
2080 /* put header into skb */
2081 size = min(length, hdr_space);
2082 skb->tail += size;
2083 skb->len += size;
2084 length -= size;
2085
2086 num_frags = skb_shinfo(skb)->nr_frags;
2087 for (i = 0; i < num_frags; i++) {
2088 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2089
2090 if (length == 0) {
2091 /* don't need this page */
2092 __free_page(frag->page);
2093 --skb_shinfo(skb)->nr_frags;
2094 } else {
2095 size = min(length, (unsigned) PAGE_SIZE);
2096
2097 frag->size = size;
2098 skb->data_len += size;
2099 skb->truesize += size;
2100 skb->len += size;
2101 length -= size;
2102 }
2103 }
2104 }
2105
2106 /* Normal packet - take skb from ring element and put in a new one */
2107 static struct sk_buff *receive_new(struct sky2_port *sky2,
2108 struct rx_ring_info *re,
2109 unsigned int length)
2110 {
2111 struct sk_buff *skb, *nskb;
2112 unsigned hdr_space = sky2->rx_data_size;
2113
2114 /* Don't be tricky about reusing pages (yet) */
2115 nskb = sky2_rx_alloc(sky2);
2116 if (unlikely(!nskb))
2117 return NULL;
2118
2119 skb = re->skb;
2120 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2121
2122 prefetch(skb->data);
2123 re->skb = nskb;
2124 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2125
2126 if (skb_shinfo(skb)->nr_frags)
2127 skb_put_frags(skb, hdr_space, length);
2128 else
2129 skb_put(skb, length);
2130 return skb;
2131 }
2132
2133 /*
2134 * Receive one packet.
2135 * For larger packets, get new buffer.
2136 */
2137 static struct sk_buff *sky2_receive(struct net_device *dev,
2138 u16 length, u32 status)
2139 {
2140 struct sky2_port *sky2 = netdev_priv(dev);
2141 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2142 struct sk_buff *skb = NULL;
2143 u16 count = (status & GMR_FS_LEN) >> 16;
2144
2145 #ifdef SKY2_VLAN_TAG_USED
2146 /* Account for vlan tag */
2147 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2148 count -= VLAN_HLEN;
2149 #endif
2150
2151 if (unlikely(netif_msg_rx_status(sky2)))
2152 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
2153 dev->name, sky2->rx_next, status, length);
2154
2155 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2156 prefetch(sky2->rx_ring + sky2->rx_next);
2157
2158 /* This chip has hardware problems that generates bogus status.
2159 * So do only marginal checking and expect higher level protocols
2160 * to handle crap frames.
2161 */
2162 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2163 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2164 length != count)
2165 goto okay;
2166
2167 if (status & GMR_FS_ANY_ERR)
2168 goto error;
2169
2170 if (!(status & GMR_FS_RX_OK))
2171 goto resubmit;
2172
2173 /* if length reported by DMA does not match PHY, packet was truncated */
2174 if (length != count)
2175 goto len_error;
2176
2177 okay:
2178 if (length < copybreak)
2179 skb = receive_copy(sky2, re, length);
2180 else
2181 skb = receive_new(sky2, re, length);
2182 resubmit:
2183 sky2_rx_submit(sky2, re);
2184
2185 return skb;
2186
2187 len_error:
2188 /* Truncation of overlength packets
2189 causes PHY length to not match MAC length */
2190 ++dev->stats.rx_length_errors;
2191 if (netif_msg_rx_err(sky2) && net_ratelimit())
2192 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2193 dev->name, status, length);
2194 goto resubmit;
2195
2196 error:
2197 ++dev->stats.rx_errors;
2198 if (status & GMR_FS_RX_FF_OV) {
2199 dev->stats.rx_over_errors++;
2200 goto resubmit;
2201 }
2202
2203 if (netif_msg_rx_err(sky2) && net_ratelimit())
2204 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
2205 dev->name, status, length);
2206
2207 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
2208 dev->stats.rx_length_errors++;
2209 if (status & GMR_FS_FRAGMENT)
2210 dev->stats.rx_frame_errors++;
2211 if (status & GMR_FS_CRC_ERR)
2212 dev->stats.rx_crc_errors++;
2213
2214 goto resubmit;
2215 }
2216
2217 /* Transmit complete */
2218 static inline void sky2_tx_done(struct net_device *dev, u16 last)
2219 {
2220 struct sky2_port *sky2 = netdev_priv(dev);
2221
2222 if (netif_running(dev)) {
2223 netif_tx_lock(dev);
2224 sky2_tx_complete(sky2, last);
2225 netif_tx_unlock(dev);
2226 }
2227 }
2228
2229 /* Process status response ring */
2230 static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
2231 {
2232 int work_done = 0;
2233 unsigned rx[2] = { 0, 0 };
2234
2235 rmb();
2236 do {
2237 struct sky2_port *sky2;
2238 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2239 unsigned port;
2240 struct net_device *dev;
2241 struct sk_buff *skb;
2242 u32 status;
2243 u16 length;
2244 u8 opcode = le->opcode;
2245
2246 if (!(opcode & HW_OWNER))
2247 break;
2248
2249 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
2250
2251 port = le->css & CSS_LINK_BIT;
2252 dev = hw->dev[port];
2253 sky2 = netdev_priv(dev);
2254 length = le16_to_cpu(le->length);
2255 status = le32_to_cpu(le->status);
2256
2257 le->opcode = 0;
2258 switch (opcode & ~HW_OWNER) {
2259 case OP_RXSTAT:
2260 ++rx[port];
2261 skb = sky2_receive(dev, length, status);
2262 if (unlikely(!skb)) {
2263 dev->stats.rx_dropped++;
2264 break;
2265 }
2266
2267 /* This chip reports checksum status differently */
2268 if (hw->flags & SKY2_HW_NEW_LE) {
2269 if (sky2->rx_csum &&
2270 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2271 (le->css & CSS_TCPUDPCSOK))
2272 skb->ip_summed = CHECKSUM_UNNECESSARY;
2273 else
2274 skb->ip_summed = CHECKSUM_NONE;
2275 }
2276
2277 skb->protocol = eth_type_trans(skb, dev);
2278 dev->stats.rx_packets++;
2279 dev->stats.rx_bytes += skb->len;
2280 dev->last_rx = jiffies;
2281
2282 #ifdef SKY2_VLAN_TAG_USED
2283 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2284 vlan_hwaccel_receive_skb(skb,
2285 sky2->vlgrp,
2286 be16_to_cpu(sky2->rx_tag));
2287 } else
2288 #endif
2289 netif_receive_skb(skb);
2290
2291 /* Stop after net poll weight */
2292 if (++work_done >= to_do)
2293 goto exit_loop;
2294 break;
2295
2296 #ifdef SKY2_VLAN_TAG_USED
2297 case OP_RXVLAN:
2298 sky2->rx_tag = length;
2299 break;
2300
2301 case OP_RXCHKSVLAN:
2302 sky2->rx_tag = length;
2303 /* fall through */
2304 #endif
2305 case OP_RXCHKS:
2306 if (!sky2->rx_csum)
2307 break;
2308
2309 /* If this happens then driver assuming wrong format */
2310 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2311 if (net_ratelimit())
2312 printk(KERN_NOTICE "%s: unexpected"
2313 " checksum status\n",
2314 dev->name);
2315 break;
2316 }
2317
2318 /* Both checksum counters are programmed to start at
2319 * the same offset, so unless there is a problem they
2320 * should match. This failure is an early indication that
2321 * hardware receive checksumming won't work.
2322 */
2323 if (likely(status >> 16 == (status & 0xffff))) {
2324 skb = sky2->rx_ring[sky2->rx_next].skb;
2325 skb->ip_summed = CHECKSUM_COMPLETE;
2326 skb->csum = status & 0xffff;
2327 } else {
2328 printk(KERN_NOTICE PFX "%s: hardware receive "
2329 "checksum problem (status = %#x)\n",
2330 dev->name, status);
2331 sky2->rx_csum = 0;
2332 sky2_write32(sky2->hw,
2333 Q_ADDR(rxqaddr[port], Q_CSR),
2334 BMU_DIS_RX_CHKSUM);
2335 }
2336 break;
2337
2338 case OP_TXINDEXLE:
2339 /* TX index reports status for both ports */
2340 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2341 sky2_tx_done(hw->dev[0], status & 0xfff);
2342 if (hw->dev[1])
2343 sky2_tx_done(hw->dev[1],
2344 ((status >> 24) & 0xff)
2345 | (u16)(length & 0xf) << 8);
2346 break;
2347
2348 default:
2349 if (net_ratelimit())
2350 printk(KERN_WARNING PFX
2351 "unknown status opcode 0x%x\n", opcode);
2352 }
2353 } while (hw->st_idx != idx);
2354
2355 /* Fully processed status ring so clear irq */
2356 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2357
2358 exit_loop:
2359 if (rx[0])
2360 sky2_rx_update(netdev_priv(hw->dev[0]), Q_R1);
2361
2362 if (rx[1])
2363 sky2_rx_update(netdev_priv(hw->dev[1]), Q_R2);
2364
2365 return work_done;
2366 }
2367
2368 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2369 {
2370 struct net_device *dev = hw->dev[port];
2371
2372 if (net_ratelimit())
2373 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2374 dev->name, status);
2375
2376 if (status & Y2_IS_PAR_RD1) {
2377 if (net_ratelimit())
2378 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2379 dev->name);
2380 /* Clear IRQ */
2381 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2382 }
2383
2384 if (status & Y2_IS_PAR_WR1) {
2385 if (net_ratelimit())
2386 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2387 dev->name);
2388
2389 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2390 }
2391
2392 if (status & Y2_IS_PAR_MAC1) {
2393 if (net_ratelimit())
2394 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
2395 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2396 }
2397
2398 if (status & Y2_IS_PAR_RX1) {
2399 if (net_ratelimit())
2400 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
2401 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2402 }
2403
2404 if (status & Y2_IS_TCP_TXA1) {
2405 if (net_ratelimit())
2406 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2407 dev->name);
2408 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2409 }
2410 }
2411
2412 static void sky2_hw_intr(struct sky2_hw *hw)
2413 {
2414 struct pci_dev *pdev = hw->pdev;
2415 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2416 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2417
2418 status &= hwmsk;
2419
2420 if (status & Y2_IS_TIST_OV)
2421 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2422
2423 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2424 u16 pci_err;
2425
2426 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2427 if (net_ratelimit())
2428 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
2429 pci_err);
2430
2431 sky2_pci_write16(hw, PCI_STATUS,
2432 pci_err | PCI_STATUS_ERROR_BITS);
2433 }
2434
2435 if (status & Y2_IS_PCI_EXP) {
2436 /* PCI-Express uncorrectable Error occurred */
2437 u32 err;
2438
2439 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2440 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2441 0xfffffffful);
2442 if (net_ratelimit())
2443 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
2444
2445 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2446 }
2447
2448 if (status & Y2_HWE_L1_MASK)
2449 sky2_hw_error(hw, 0, status);
2450 status >>= 8;
2451 if (status & Y2_HWE_L1_MASK)
2452 sky2_hw_error(hw, 1, status);
2453 }
2454
2455 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2456 {
2457 struct net_device *dev = hw->dev[port];
2458 struct sky2_port *sky2 = netdev_priv(dev);
2459 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2460
2461 if (netif_msg_intr(sky2))
2462 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2463 dev->name, status);
2464
2465 if (status & GM_IS_RX_CO_OV)
2466 gma_read16(hw, port, GM_RX_IRQ_SRC);
2467
2468 if (status & GM_IS_TX_CO_OV)
2469 gma_read16(hw, port, GM_TX_IRQ_SRC);
2470
2471 if (status & GM_IS_RX_FF_OR) {
2472 ++dev->stats.rx_fifo_errors;
2473 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2474 }
2475
2476 if (status & GM_IS_TX_FF_UR) {
2477 ++dev->stats.tx_fifo_errors;
2478 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2479 }
2480 }
2481
2482 /* This should never happen it is a bug. */
2483 static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2484 u16 q, unsigned ring_size)
2485 {
2486 struct net_device *dev = hw->dev[port];
2487 struct sky2_port *sky2 = netdev_priv(dev);
2488 unsigned idx;
2489 const u64 *le = (q == Q_R1 || q == Q_R2)
2490 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
2491
2492 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2493 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2494 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2495 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
2496
2497 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
2498 }
2499
2500 static int sky2_rx_hung(struct net_device *dev)
2501 {
2502 struct sky2_port *sky2 = netdev_priv(dev);
2503 struct sky2_hw *hw = sky2->hw;
2504 unsigned port = sky2->port;
2505 unsigned rxq = rxqaddr[port];
2506 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2507 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2508 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2509 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2510
2511 /* If idle and MAC or PCI is stuck */
2512 if (sky2->check.last == dev->last_rx &&
2513 ((mac_rp == sky2->check.mac_rp &&
2514 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2515 /* Check if the PCI RX hang */
2516 (fifo_rp == sky2->check.fifo_rp &&
2517 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2518 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2519 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2520 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2521 return 1;
2522 } else {
2523 sky2->check.last = dev->last_rx;
2524 sky2->check.mac_rp = mac_rp;
2525 sky2->check.mac_lev = mac_lev;
2526 sky2->check.fifo_rp = fifo_rp;
2527 sky2->check.fifo_lev = fifo_lev;
2528 return 0;
2529 }
2530 }
2531
2532 static void sky2_watchdog(unsigned long arg)
2533 {
2534 struct sky2_hw *hw = (struct sky2_hw *) arg;
2535
2536 /* Check for lost IRQ once a second */
2537 if (sky2_read32(hw, B0_ISRC)) {
2538 napi_schedule(&hw->napi);
2539 } else {
2540 int i, active = 0;
2541
2542 for (i = 0; i < hw->ports; i++) {
2543 struct net_device *dev = hw->dev[i];
2544 if (!netif_running(dev))
2545 continue;
2546 ++active;
2547
2548 /* For chips with Rx FIFO, check if stuck */
2549 if ((hw->flags & SKY2_HW_FIFO_HANG_CHECK) &&
2550 sky2_rx_hung(dev)) {
2551 pr_info(PFX "%s: receiver hang detected\n",
2552 dev->name);
2553 schedule_work(&hw->restart_work);
2554 return;
2555 }
2556 }
2557
2558 if (active == 0)
2559 return;
2560 }
2561
2562 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
2563 }
2564
2565 /* Hardware/software error handling */
2566 static void sky2_err_intr(struct sky2_hw *hw, u32 status)
2567 {
2568 if (net_ratelimit())
2569 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
2570
2571 if (status & Y2_IS_HW_ERR)
2572 sky2_hw_intr(hw);
2573
2574 if (status & Y2_IS_IRQ_MAC1)
2575 sky2_mac_intr(hw, 0);
2576
2577 if (status & Y2_IS_IRQ_MAC2)
2578 sky2_mac_intr(hw, 1);
2579
2580 if (status & Y2_IS_CHK_RX1)
2581 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
2582
2583 if (status & Y2_IS_CHK_RX2)
2584 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
2585
2586 if (status & Y2_IS_CHK_TXA1)
2587 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
2588
2589 if (status & Y2_IS_CHK_TXA2)
2590 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2591 }
2592
2593 static int sky2_poll(struct napi_struct *napi, int work_limit)
2594 {
2595 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
2596 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2597 int work_done = 0;
2598 u16 idx;
2599
2600 if (unlikely(status & Y2_IS_ERROR))
2601 sky2_err_intr(hw, status);
2602
2603 if (status & Y2_IS_IRQ_PHY1)
2604 sky2_phy_intr(hw, 0);
2605
2606 if (status & Y2_IS_IRQ_PHY2)
2607 sky2_phy_intr(hw, 1);
2608
2609 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2610 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
2611
2612 if (work_done >= work_limit)
2613 goto done;
2614 }
2615
2616 /* Bug/Errata workaround?
2617 * Need to kick the TX irq moderation timer.
2618 */
2619 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) {
2620 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2621 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2622 }
2623 napi_complete(napi);
2624 sky2_read32(hw, B0_Y2_SP_LISR);
2625 done:
2626
2627 return work_done;
2628 }
2629
2630 static irqreturn_t sky2_intr(int irq, void *dev_id)
2631 {
2632 struct sky2_hw *hw = dev_id;
2633 u32 status;
2634
2635 /* Reading this mask interrupts as side effect */
2636 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2637 if (status == 0 || status == ~0)
2638 return IRQ_NONE;
2639
2640 prefetch(&hw->st_le[hw->st_idx]);
2641
2642 napi_schedule(&hw->napi);
2643
2644 return IRQ_HANDLED;
2645 }
2646
2647 #ifdef CONFIG_NET_POLL_CONTROLLER
2648 static void sky2_netpoll(struct net_device *dev)
2649 {
2650 struct sky2_port *sky2 = netdev_priv(dev);
2651
2652 napi_schedule(&sky2->hw->napi);
2653 }
2654 #endif
2655
2656 /* Chip internal frequency for clock calculations */
2657 static u32 sky2_mhz(const struct sky2_hw *hw)
2658 {
2659 switch (hw->chip_id) {
2660 case CHIP_ID_YUKON_EC:
2661 case CHIP_ID_YUKON_EC_U:
2662 case CHIP_ID_YUKON_EX:
2663 return 125;
2664
2665 case CHIP_ID_YUKON_FE:
2666 return 100;
2667
2668 case CHIP_ID_YUKON_FE_P:
2669 return 50;
2670
2671 case CHIP_ID_YUKON_XL:
2672 return 156;
2673
2674 default:
2675 BUG();
2676 }
2677 }
2678
2679 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2680 {
2681 return sky2_mhz(hw) * us;
2682 }
2683
2684 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2685 {
2686 return clk / sky2_mhz(hw);
2687 }
2688
2689
2690 static int __devinit sky2_init(struct sky2_hw *hw)
2691 {
2692 u8 t8;
2693
2694 /* Enable all clocks and check for bad PCI access */
2695 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2696
2697 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2698
2699 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2700 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2701
2702 switch(hw->chip_id) {
2703 case CHIP_ID_YUKON_XL:
2704 hw->flags = SKY2_HW_GIGABIT
2705 | SKY2_HW_NEWER_PHY;
2706 if (hw->chip_rev < 3)
2707 hw->flags |= SKY2_HW_FIFO_HANG_CHECK;
2708
2709 break;
2710
2711 case CHIP_ID_YUKON_EC_U:
2712 hw->flags = SKY2_HW_GIGABIT
2713 | SKY2_HW_NEWER_PHY
2714 | SKY2_HW_ADV_POWER_CTL;
2715 break;
2716
2717 case CHIP_ID_YUKON_EX:
2718 hw->flags = SKY2_HW_GIGABIT
2719 | SKY2_HW_NEWER_PHY
2720 | SKY2_HW_NEW_LE
2721 | SKY2_HW_ADV_POWER_CTL;
2722
2723 /* New transmit checksum */
2724 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2725 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2726 break;
2727
2728 case CHIP_ID_YUKON_EC:
2729 /* This rev is really old, and requires untested workarounds */
2730 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2731 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2732 return -EOPNOTSUPP;
2733 }
2734 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_FIFO_HANG_CHECK;
2735 break;
2736
2737 case CHIP_ID_YUKON_FE:
2738 break;
2739
2740 case CHIP_ID_YUKON_FE_P:
2741 hw->flags = SKY2_HW_NEWER_PHY
2742 | SKY2_HW_NEW_LE
2743 | SKY2_HW_AUTO_TX_SUM
2744 | SKY2_HW_ADV_POWER_CTL;
2745 break;
2746 default:
2747 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2748 hw->chip_id);
2749 return -EOPNOTSUPP;
2750 }
2751
2752 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2753 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2754 hw->flags |= SKY2_HW_FIBRE_PHY;
2755
2756
2757 hw->ports = 1;
2758 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2759 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2760 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2761 ++hw->ports;
2762 }
2763
2764 return 0;
2765 }
2766
2767 static void sky2_reset(struct sky2_hw *hw)
2768 {
2769 struct pci_dev *pdev = hw->pdev;
2770 u16 status;
2771 int i, cap;
2772 u32 hwe_mask = Y2_HWE_ALL_MASK;
2773
2774 /* disable ASF */
2775 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2776 status = sky2_read16(hw, HCU_CCSR);
2777 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2778 HCU_CCSR_UC_STATE_MSK);
2779 sky2_write16(hw, HCU_CCSR, status);
2780 } else
2781 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2782 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2783
2784 /* do a SW reset */
2785 sky2_write8(hw, B0_CTST, CS_RST_SET);
2786 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2787
2788 /* allow writes to PCI config */
2789 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2790
2791 /* clear PCI errors, if any */
2792 status = sky2_pci_read16(hw, PCI_STATUS);
2793 status |= PCI_STATUS_ERROR_BITS;
2794 sky2_pci_write16(hw, PCI_STATUS, status);
2795
2796 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2797
2798 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2799 if (cap) {
2800 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2801 0xfffffffful);
2802
2803 /* If error bit is stuck on ignore it */
2804 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
2805 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
2806 else
2807 hwe_mask |= Y2_IS_PCI_EXP;
2808 }
2809
2810 sky2_power_on(hw);
2811
2812 for (i = 0; i < hw->ports; i++) {
2813 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2814 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2815
2816 if (hw->chip_id == CHIP_ID_YUKON_EX)
2817 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
2818 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
2819 | GMC_BYP_RETR_ON);
2820 }
2821
2822 /* Clear I2C IRQ noise */
2823 sky2_write32(hw, B2_I2C_IRQ, 1);
2824
2825 /* turn off hardware timer (unused) */
2826 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2827 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2828
2829 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2830
2831 /* Turn off descriptor polling */
2832 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
2833
2834 /* Turn off receive timestamp */
2835 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2836 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2837
2838 /* enable the Tx Arbiters */
2839 for (i = 0; i < hw->ports; i++)
2840 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2841
2842 /* Initialize ram interface */
2843 for (i = 0; i < hw->ports; i++) {
2844 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2845
2846 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2847 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2848 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2849 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2850 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2851 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2852 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2853 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2854 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2855 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2856 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2857 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2858 }
2859
2860 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
2861
2862 for (i = 0; i < hw->ports; i++)
2863 sky2_gmac_reset(hw, i);
2864
2865 memset(hw->st_le, 0, STATUS_LE_BYTES);
2866 hw->st_idx = 0;
2867
2868 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2869 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2870
2871 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
2872 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
2873
2874 /* Set the list last index */
2875 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
2876
2877 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2878 sky2_write8(hw, STAT_FIFO_WM, 16);
2879
2880 /* set Status-FIFO ISR watermark */
2881 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2882 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2883 else
2884 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
2885
2886 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
2887 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2888 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
2889
2890 /* enable status unit */
2891 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2892
2893 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2894 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2895 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2896 }
2897
2898 static void sky2_restart(struct work_struct *work)
2899 {
2900 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
2901 struct net_device *dev;
2902 int i, err;
2903
2904 rtnl_lock();
2905 for (i = 0; i < hw->ports; i++) {
2906 dev = hw->dev[i];
2907 if (netif_running(dev))
2908 sky2_down(dev);
2909 }
2910
2911 napi_disable(&hw->napi);
2912 sky2_write32(hw, B0_IMSK, 0);
2913 sky2_reset(hw);
2914 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
2915 napi_enable(&hw->napi);
2916
2917 for (i = 0; i < hw->ports; i++) {
2918 dev = hw->dev[i];
2919 if (netif_running(dev)) {
2920 err = sky2_up(dev);
2921 if (err) {
2922 printk(KERN_INFO PFX "%s: could not restart %d\n",
2923 dev->name, err);
2924 dev_close(dev);
2925 }
2926 }
2927 }
2928
2929 rtnl_unlock();
2930 }
2931
2932 static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
2933 {
2934 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
2935 }
2936
2937 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2938 {
2939 const struct sky2_port *sky2 = netdev_priv(dev);
2940
2941 wol->supported = sky2_wol_supported(sky2->hw);
2942 wol->wolopts = sky2->wol;
2943 }
2944
2945 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2946 {
2947 struct sky2_port *sky2 = netdev_priv(dev);
2948 struct sky2_hw *hw = sky2->hw;
2949
2950 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
2951 return -EOPNOTSUPP;
2952
2953 sky2->wol = wol->wolopts;
2954
2955 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
2956 hw->chip_id == CHIP_ID_YUKON_EX ||
2957 hw->chip_id == CHIP_ID_YUKON_FE_P)
2958 sky2_write32(hw, B0_CTST, sky2->wol
2959 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
2960
2961 if (!netif_running(dev))
2962 sky2_wol_init(sky2);
2963 return 0;
2964 }
2965
2966 static u32 sky2_supported_modes(const struct sky2_hw *hw)
2967 {
2968 if (sky2_is_copper(hw)) {
2969 u32 modes = SUPPORTED_10baseT_Half
2970 | SUPPORTED_10baseT_Full
2971 | SUPPORTED_100baseT_Half
2972 | SUPPORTED_100baseT_Full
2973 | SUPPORTED_Autoneg | SUPPORTED_TP;
2974
2975 if (hw->flags & SKY2_HW_GIGABIT)
2976 modes |= SUPPORTED_1000baseT_Half
2977 | SUPPORTED_1000baseT_Full;
2978 return modes;
2979 } else
2980 return SUPPORTED_1000baseT_Half
2981 | SUPPORTED_1000baseT_Full
2982 | SUPPORTED_Autoneg
2983 | SUPPORTED_FIBRE;
2984 }
2985
2986 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2987 {
2988 struct sky2_port *sky2 = netdev_priv(dev);
2989 struct sky2_hw *hw = sky2->hw;
2990
2991 ecmd->transceiver = XCVR_INTERNAL;
2992 ecmd->supported = sky2_supported_modes(hw);
2993 ecmd->phy_address = PHY_ADDR_MARV;
2994 if (sky2_is_copper(hw)) {
2995 ecmd->port = PORT_TP;
2996 ecmd->speed = sky2->speed;
2997 } else {
2998 ecmd->speed = SPEED_1000;
2999 ecmd->port = PORT_FIBRE;
3000 }
3001
3002 ecmd->advertising = sky2->advertising;
3003 ecmd->autoneg = sky2->autoneg;
3004 ecmd->duplex = sky2->duplex;
3005 return 0;
3006 }
3007
3008 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3009 {
3010 struct sky2_port *sky2 = netdev_priv(dev);
3011 const struct sky2_hw *hw = sky2->hw;
3012 u32 supported = sky2_supported_modes(hw);
3013
3014 if (ecmd->autoneg == AUTONEG_ENABLE) {
3015 ecmd->advertising = supported;
3016 sky2->duplex = -1;
3017 sky2->speed = -1;
3018 } else {
3019 u32 setting;
3020
3021 switch (ecmd->speed) {
3022 case SPEED_1000:
3023 if (ecmd->duplex == DUPLEX_FULL)
3024 setting = SUPPORTED_1000baseT_Full;
3025 else if (ecmd->duplex == DUPLEX_HALF)
3026 setting = SUPPORTED_1000baseT_Half;
3027 else
3028 return -EINVAL;
3029 break;
3030 case SPEED_100:
3031 if (ecmd->duplex == DUPLEX_FULL)
3032 setting = SUPPORTED_100baseT_Full;
3033 else if (ecmd->duplex == DUPLEX_HALF)
3034 setting = SUPPORTED_100baseT_Half;
3035 else
3036 return -EINVAL;
3037 break;
3038
3039 case SPEED_10:
3040 if (ecmd->duplex == DUPLEX_FULL)
3041 setting = SUPPORTED_10baseT_Full;
3042 else if (ecmd->duplex == DUPLEX_HALF)
3043 setting = SUPPORTED_10baseT_Half;
3044 else
3045 return -EINVAL;
3046 break;
3047 default:
3048 return -EINVAL;
3049 }
3050
3051 if ((setting & supported) == 0)
3052 return -EINVAL;
3053
3054 sky2->speed = ecmd->speed;
3055 sky2->duplex = ecmd->duplex;
3056 }
3057
3058 sky2->autoneg = ecmd->autoneg;
3059 sky2->advertising = ecmd->advertising;
3060
3061 if (netif_running(dev)) {
3062 sky2_phy_reinit(sky2);
3063 sky2_set_multicast(dev);
3064 }
3065
3066 return 0;
3067 }
3068
3069 static void sky2_get_drvinfo(struct net_device *dev,
3070 struct ethtool_drvinfo *info)
3071 {
3072 struct sky2_port *sky2 = netdev_priv(dev);
3073
3074 strcpy(info->driver, DRV_NAME);
3075 strcpy(info->version, DRV_VERSION);
3076 strcpy(info->fw_version, "N/A");
3077 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3078 }
3079
3080 static const struct sky2_stat {
3081 char name[ETH_GSTRING_LEN];
3082 u16 offset;
3083 } sky2_stats[] = {
3084 { "tx_bytes", GM_TXO_OK_HI },
3085 { "rx_bytes", GM_RXO_OK_HI },
3086 { "tx_broadcast", GM_TXF_BC_OK },
3087 { "rx_broadcast", GM_RXF_BC_OK },
3088 { "tx_multicast", GM_TXF_MC_OK },
3089 { "rx_multicast", GM_RXF_MC_OK },
3090 { "tx_unicast", GM_TXF_UC_OK },
3091 { "rx_unicast", GM_RXF_UC_OK },
3092 { "tx_mac_pause", GM_TXF_MPAUSE },
3093 { "rx_mac_pause", GM_RXF_MPAUSE },
3094 { "collisions", GM_TXF_COL },
3095 { "late_collision",GM_TXF_LAT_COL },
3096 { "aborted", GM_TXF_ABO_COL },
3097 { "single_collisions", GM_TXF_SNG_COL },
3098 { "multi_collisions", GM_TXF_MUL_COL },
3099
3100 { "rx_short", GM_RXF_SHT },
3101 { "rx_runt", GM_RXE_FRAG },
3102 { "rx_64_byte_packets", GM_RXF_64B },
3103 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3104 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3105 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3106 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3107 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3108 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
3109 { "rx_too_long", GM_RXF_LNG_ERR },
3110 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3111 { "rx_jabber", GM_RXF_JAB_PKT },
3112 { "rx_fcs_error", GM_RXF_FCS_ERR },
3113
3114 { "tx_64_byte_packets", GM_TXF_64B },
3115 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3116 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3117 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3118 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3119 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3120 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3121 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
3122 };
3123
3124 static u32 sky2_get_rx_csum(struct net_device *dev)
3125 {
3126 struct sky2_port *sky2 = netdev_priv(dev);
3127
3128 return sky2->rx_csum;
3129 }
3130
3131 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3132 {
3133 struct sky2_port *sky2 = netdev_priv(dev);
3134
3135 sky2->rx_csum = data;
3136
3137 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3138 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3139
3140 return 0;
3141 }
3142
3143 static u32 sky2_get_msglevel(struct net_device *netdev)
3144 {
3145 struct sky2_port *sky2 = netdev_priv(netdev);
3146 return sky2->msg_enable;
3147 }
3148
3149 static int sky2_nway_reset(struct net_device *dev)
3150 {
3151 struct sky2_port *sky2 = netdev_priv(dev);
3152
3153 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
3154 return -EINVAL;
3155
3156 sky2_phy_reinit(sky2);
3157 sky2_set_multicast(dev);
3158
3159 return 0;
3160 }
3161
3162 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
3163 {
3164 struct sky2_hw *hw = sky2->hw;
3165 unsigned port = sky2->port;
3166 int i;
3167
3168 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
3169 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
3170 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
3171 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
3172
3173 for (i = 2; i < count; i++)
3174 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3175 }
3176
3177 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3178 {
3179 struct sky2_port *sky2 = netdev_priv(netdev);
3180 sky2->msg_enable = value;
3181 }
3182
3183 static int sky2_get_sset_count(struct net_device *dev, int sset)
3184 {
3185 switch (sset) {
3186 case ETH_SS_STATS:
3187 return ARRAY_SIZE(sky2_stats);
3188 default:
3189 return -EOPNOTSUPP;
3190 }
3191 }
3192
3193 static void sky2_get_ethtool_stats(struct net_device *dev,
3194 struct ethtool_stats *stats, u64 * data)
3195 {
3196 struct sky2_port *sky2 = netdev_priv(dev);
3197
3198 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
3199 }
3200
3201 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
3202 {
3203 int i;
3204
3205 switch (stringset) {
3206 case ETH_SS_STATS:
3207 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3208 memcpy(data + i * ETH_GSTRING_LEN,
3209 sky2_stats[i].name, ETH_GSTRING_LEN);
3210 break;
3211 }
3212 }
3213
3214 static int sky2_set_mac_address(struct net_device *dev, void *p)
3215 {
3216 struct sky2_port *sky2 = netdev_priv(dev);
3217 struct sky2_hw *hw = sky2->hw;
3218 unsigned port = sky2->port;
3219 const struct sockaddr *addr = p;
3220
3221 if (!is_valid_ether_addr(addr->sa_data))
3222 return -EADDRNOTAVAIL;
3223
3224 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3225 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
3226 dev->dev_addr, ETH_ALEN);
3227 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
3228 dev->dev_addr, ETH_ALEN);
3229
3230 /* virtual address for data */
3231 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3232
3233 /* physical address: used for pause frames */
3234 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3235
3236 return 0;
3237 }
3238
3239 static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3240 {
3241 u32 bit;
3242
3243 bit = ether_crc(ETH_ALEN, addr) & 63;
3244 filter[bit >> 3] |= 1 << (bit & 7);
3245 }
3246
3247 static void sky2_set_multicast(struct net_device *dev)
3248 {
3249 struct sky2_port *sky2 = netdev_priv(dev);
3250 struct sky2_hw *hw = sky2->hw;
3251 unsigned port = sky2->port;
3252 struct dev_mc_list *list = dev->mc_list;
3253 u16 reg;
3254 u8 filter[8];
3255 int rx_pause;
3256 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3257
3258 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
3259 memset(filter, 0, sizeof(filter));
3260
3261 reg = gma_read16(hw, port, GM_RX_CTRL);
3262 reg |= GM_RXCR_UCF_ENA;
3263
3264 if (dev->flags & IFF_PROMISC) /* promiscuous */
3265 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3266 else if (dev->flags & IFF_ALLMULTI)
3267 memset(filter, 0xff, sizeof(filter));
3268 else if (dev->mc_count == 0 && !rx_pause)
3269 reg &= ~GM_RXCR_MCF_ENA;
3270 else {
3271 int i;
3272 reg |= GM_RXCR_MCF_ENA;
3273
3274 if (rx_pause)
3275 sky2_add_filter(filter, pause_mc_addr);
3276
3277 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3278 sky2_add_filter(filter, list->dmi_addr);
3279 }
3280
3281 gma_write16(hw, port, GM_MC_ADDR_H1,
3282 (u16) filter[0] | ((u16) filter[1] << 8));
3283 gma_write16(hw, port, GM_MC_ADDR_H2,
3284 (u16) filter[2] | ((u16) filter[3] << 8));
3285 gma_write16(hw, port, GM_MC_ADDR_H3,
3286 (u16) filter[4] | ((u16) filter[5] << 8));
3287 gma_write16(hw, port, GM_MC_ADDR_H4,
3288 (u16) filter[6] | ((u16) filter[7] << 8));
3289
3290 gma_write16(hw, port, GM_RX_CTRL, reg);
3291 }
3292
3293 /* Can have one global because blinking is controlled by
3294 * ethtool and that is always under RTNL mutex
3295 */
3296 static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
3297 {
3298 u16 pg;
3299
3300 switch (hw->chip_id) {
3301 case CHIP_ID_YUKON_XL:
3302 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3303 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3304 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3305 on ? (PHY_M_LEDC_LOS_CTRL(1) |
3306 PHY_M_LEDC_INIT_CTRL(7) |
3307 PHY_M_LEDC_STA1_CTRL(7) |
3308 PHY_M_LEDC_STA0_CTRL(7))
3309 : 0);
3310
3311 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3312 break;
3313
3314 default:
3315 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
3316 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3317 on ? PHY_M_LED_ALL : 0);
3318 }
3319 }
3320
3321 /* blink LED's for finding board */
3322 static int sky2_phys_id(struct net_device *dev, u32 data)
3323 {
3324 struct sky2_port *sky2 = netdev_priv(dev);
3325 struct sky2_hw *hw = sky2->hw;
3326 unsigned port = sky2->port;
3327 u16 ledctrl, ledover = 0;
3328 long ms;
3329 int interrupted;
3330 int onoff = 1;
3331
3332 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
3333 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
3334 else
3335 ms = data * 1000;
3336
3337 /* save initial values */
3338 spin_lock_bh(&sky2->phy_lock);
3339 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3340 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3341 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3342 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
3343 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3344 } else {
3345 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
3346 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
3347 }
3348
3349 interrupted = 0;
3350 while (!interrupted && ms > 0) {
3351 sky2_led(hw, port, onoff);
3352 onoff = !onoff;
3353
3354 spin_unlock_bh(&sky2->phy_lock);
3355 interrupted = msleep_interruptible(250);
3356 spin_lock_bh(&sky2->phy_lock);
3357
3358 ms -= 250;
3359 }
3360
3361 /* resume regularly scheduled programming */
3362 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3363 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3364 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3365 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
3366 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3367 } else {
3368 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
3369 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
3370 }
3371 spin_unlock_bh(&sky2->phy_lock);
3372
3373 return 0;
3374 }
3375
3376 static void sky2_get_pauseparam(struct net_device *dev,
3377 struct ethtool_pauseparam *ecmd)
3378 {
3379 struct sky2_port *sky2 = netdev_priv(dev);
3380
3381 switch (sky2->flow_mode) {
3382 case FC_NONE:
3383 ecmd->tx_pause = ecmd->rx_pause = 0;
3384 break;
3385 case FC_TX:
3386 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3387 break;
3388 case FC_RX:
3389 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3390 break;
3391 case FC_BOTH:
3392 ecmd->tx_pause = ecmd->rx_pause = 1;
3393 }
3394
3395 ecmd->autoneg = sky2->autoneg;
3396 }
3397
3398 static int sky2_set_pauseparam(struct net_device *dev,
3399 struct ethtool_pauseparam *ecmd)
3400 {
3401 struct sky2_port *sky2 = netdev_priv(dev);
3402
3403 sky2->autoneg = ecmd->autoneg;
3404 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
3405
3406 if (netif_running(dev))
3407 sky2_phy_reinit(sky2);
3408
3409 return 0;
3410 }
3411
3412 static int sky2_get_coalesce(struct net_device *dev,
3413 struct ethtool_coalesce *ecmd)
3414 {
3415 struct sky2_port *sky2 = netdev_priv(dev);
3416 struct sky2_hw *hw = sky2->hw;
3417
3418 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3419 ecmd->tx_coalesce_usecs = 0;
3420 else {
3421 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3422 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3423 }
3424 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3425
3426 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3427 ecmd->rx_coalesce_usecs = 0;
3428 else {
3429 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3430 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3431 }
3432 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3433
3434 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3435 ecmd->rx_coalesce_usecs_irq = 0;
3436 else {
3437 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3438 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3439 }
3440
3441 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3442
3443 return 0;
3444 }
3445
3446 /* Note: this affect both ports */
3447 static int sky2_set_coalesce(struct net_device *dev,
3448 struct ethtool_coalesce *ecmd)
3449 {
3450 struct sky2_port *sky2 = netdev_priv(dev);
3451 struct sky2_hw *hw = sky2->hw;
3452 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
3453
3454 if (ecmd->tx_coalesce_usecs > tmax ||
3455 ecmd->rx_coalesce_usecs > tmax ||
3456 ecmd->rx_coalesce_usecs_irq > tmax)
3457 return -EINVAL;
3458
3459 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
3460 return -EINVAL;
3461 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
3462 return -EINVAL;
3463 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
3464 return -EINVAL;
3465
3466 if (ecmd->tx_coalesce_usecs == 0)
3467 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3468 else {
3469 sky2_write32(hw, STAT_TX_TIMER_INI,
3470 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3471 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3472 }
3473 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3474
3475 if (ecmd->rx_coalesce_usecs == 0)
3476 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3477 else {
3478 sky2_write32(hw, STAT_LEV_TIMER_INI,
3479 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3480 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3481 }
3482 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3483
3484 if (ecmd->rx_coalesce_usecs_irq == 0)
3485 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3486 else {
3487 sky2_write32(hw, STAT_ISR_TIMER_INI,
3488 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3489 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3490 }
3491 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3492 return 0;
3493 }
3494
3495 static void sky2_get_ringparam(struct net_device *dev,
3496 struct ethtool_ringparam *ering)
3497 {
3498 struct sky2_port *sky2 = netdev_priv(dev);
3499
3500 ering->rx_max_pending = RX_MAX_PENDING;
3501 ering->rx_mini_max_pending = 0;
3502 ering->rx_jumbo_max_pending = 0;
3503 ering->tx_max_pending = TX_RING_SIZE - 1;
3504
3505 ering->rx_pending = sky2->rx_pending;
3506 ering->rx_mini_pending = 0;
3507 ering->rx_jumbo_pending = 0;
3508 ering->tx_pending = sky2->tx_pending;
3509 }
3510
3511 static int sky2_set_ringparam(struct net_device *dev,
3512 struct ethtool_ringparam *ering)
3513 {
3514 struct sky2_port *sky2 = netdev_priv(dev);
3515 int err = 0;
3516
3517 if (ering->rx_pending > RX_MAX_PENDING ||
3518 ering->rx_pending < 8 ||
3519 ering->tx_pending < MAX_SKB_TX_LE ||
3520 ering->tx_pending > TX_RING_SIZE - 1)
3521 return -EINVAL;
3522
3523 if (netif_running(dev))
3524 sky2_down(dev);
3525
3526 sky2->rx_pending = ering->rx_pending;
3527 sky2->tx_pending = ering->tx_pending;
3528
3529 if (netif_running(dev)) {
3530 err = sky2_up(dev);
3531 if (err)
3532 dev_close(dev);
3533 else
3534 sky2_set_multicast(dev);
3535 }
3536
3537 return err;
3538 }
3539
3540 static int sky2_get_regs_len(struct net_device *dev)
3541 {
3542 return 0x4000;
3543 }
3544
3545 /*
3546 * Returns copy of control register region
3547 * Note: ethtool_get_regs always provides full size (16k) buffer
3548 */
3549 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3550 void *p)
3551 {
3552 const struct sky2_port *sky2 = netdev_priv(dev);
3553 const void __iomem *io = sky2->hw->regs;
3554 unsigned int b;
3555
3556 regs->version = 1;
3557
3558 for (b = 0; b < 128; b++) {
3559 /* This complicated switch statement is to make sure and
3560 * only access regions that are unreserved.
3561 * Some blocks are only valid on dual port cards.
3562 * and block 3 has some special diagnostic registers that
3563 * are poison.
3564 */
3565 switch (b) {
3566 case 3:
3567 /* skip diagnostic ram region */
3568 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
3569 break;
3570
3571 /* dual port cards only */
3572 case 5: /* Tx Arbiter 2 */
3573 case 9: /* RX2 */
3574 case 14 ... 15: /* TX2 */
3575 case 17: case 19: /* Ram Buffer 2 */
3576 case 22 ... 23: /* Tx Ram Buffer 2 */
3577 case 25: /* Rx MAC Fifo 1 */
3578 case 27: /* Tx MAC Fifo 2 */
3579 case 31: /* GPHY 2 */
3580 case 40 ... 47: /* Pattern Ram 2 */
3581 case 52: case 54: /* TCP Segmentation 2 */
3582 case 112 ... 116: /* GMAC 2 */
3583 if (sky2->hw->ports == 1)
3584 goto reserved;
3585 /* fall through */
3586 case 0: /* Control */
3587 case 2: /* Mac address */
3588 case 4: /* Tx Arbiter 1 */
3589 case 7: /* PCI express reg */
3590 case 8: /* RX1 */
3591 case 12 ... 13: /* TX1 */
3592 case 16: case 18:/* Rx Ram Buffer 1 */
3593 case 20 ... 21: /* Tx Ram Buffer 1 */
3594 case 24: /* Rx MAC Fifo 1 */
3595 case 26: /* Tx MAC Fifo 1 */
3596 case 28 ... 29: /* Descriptor and status unit */
3597 case 30: /* GPHY 1*/
3598 case 32 ... 39: /* Pattern Ram 1 */
3599 case 48: case 50: /* TCP Segmentation 1 */
3600 case 56 ... 60: /* PCI space */
3601 case 80 ... 84: /* GMAC 1 */
3602 memcpy_fromio(p, io, 128);
3603 break;
3604 default:
3605 reserved:
3606 memset(p, 0, 128);
3607 }
3608
3609 p += 128;
3610 io += 128;
3611 }
3612 }
3613
3614 /* In order to do Jumbo packets on these chips, need to turn off the
3615 * transmit store/forward. Therefore checksum offload won't work.
3616 */
3617 static int no_tx_offload(struct net_device *dev)
3618 {
3619 const struct sky2_port *sky2 = netdev_priv(dev);
3620 const struct sky2_hw *hw = sky2->hw;
3621
3622 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
3623 }
3624
3625 static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3626 {
3627 if (data && no_tx_offload(dev))
3628 return -EINVAL;
3629
3630 return ethtool_op_set_tx_csum(dev, data);
3631 }
3632
3633
3634 static int sky2_set_tso(struct net_device *dev, u32 data)
3635 {
3636 if (data && no_tx_offload(dev))
3637 return -EINVAL;
3638
3639 return ethtool_op_set_tso(dev, data);
3640 }
3641
3642 static int sky2_get_eeprom_len(struct net_device *dev)
3643 {
3644 struct sky2_port *sky2 = netdev_priv(dev);
3645 struct sky2_hw *hw = sky2->hw;
3646 u16 reg2;
3647
3648 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
3649 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3650 }
3651
3652 static u32 sky2_vpd_read(struct sky2_hw *hw, int cap, u16 offset)
3653 {
3654 u32 val;
3655
3656 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
3657
3658 do {
3659 offset = sky2_pci_read16(hw, cap + PCI_VPD_ADDR);
3660 } while (!(offset & PCI_VPD_ADDR_F));
3661
3662 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
3663 return val;
3664 }
3665
3666 static void sky2_vpd_write(struct sky2_hw *hw, int cap, u16 offset, u32 val)
3667 {
3668 sky2_pci_write16(hw, cap + PCI_VPD_DATA, val);
3669 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
3670 do {
3671 offset = sky2_pci_read16(hw, cap + PCI_VPD_ADDR);
3672 } while (offset & PCI_VPD_ADDR_F);
3673 }
3674
3675 static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3676 u8 *data)
3677 {
3678 struct sky2_port *sky2 = netdev_priv(dev);
3679 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3680 int length = eeprom->len;
3681 u16 offset = eeprom->offset;
3682
3683 if (!cap)
3684 return -EINVAL;
3685
3686 eeprom->magic = SKY2_EEPROM_MAGIC;
3687
3688 while (length > 0) {
3689 u32 val = sky2_vpd_read(sky2->hw, cap, offset);
3690 int n = min_t(int, length, sizeof(val));
3691
3692 memcpy(data, &val, n);
3693 length -= n;
3694 data += n;
3695 offset += n;
3696 }
3697 return 0;
3698 }
3699
3700 static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3701 u8 *data)
3702 {
3703 struct sky2_port *sky2 = netdev_priv(dev);
3704 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3705 int length = eeprom->len;
3706 u16 offset = eeprom->offset;
3707
3708 if (!cap)
3709 return -EINVAL;
3710
3711 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3712 return -EINVAL;
3713
3714 while (length > 0) {
3715 u32 val;
3716 int n = min_t(int, length, sizeof(val));
3717
3718 if (n < sizeof(val))
3719 val = sky2_vpd_read(sky2->hw, cap, offset);
3720 memcpy(&val, data, n);
3721
3722 sky2_vpd_write(sky2->hw, cap, offset, val);
3723
3724 length -= n;
3725 data += n;
3726 offset += n;
3727 }
3728 return 0;
3729 }
3730
3731
3732 static const struct ethtool_ops sky2_ethtool_ops = {
3733 .get_settings = sky2_get_settings,
3734 .set_settings = sky2_set_settings,
3735 .get_drvinfo = sky2_get_drvinfo,
3736 .get_wol = sky2_get_wol,
3737 .set_wol = sky2_set_wol,
3738 .get_msglevel = sky2_get_msglevel,
3739 .set_msglevel = sky2_set_msglevel,
3740 .nway_reset = sky2_nway_reset,
3741 .get_regs_len = sky2_get_regs_len,
3742 .get_regs = sky2_get_regs,
3743 .get_link = ethtool_op_get_link,
3744 .get_eeprom_len = sky2_get_eeprom_len,
3745 .get_eeprom = sky2_get_eeprom,
3746 .set_eeprom = sky2_set_eeprom,
3747 .set_sg = ethtool_op_set_sg,
3748 .set_tx_csum = sky2_set_tx_csum,
3749 .set_tso = sky2_set_tso,
3750 .get_rx_csum = sky2_get_rx_csum,
3751 .set_rx_csum = sky2_set_rx_csum,
3752 .get_strings = sky2_get_strings,
3753 .get_coalesce = sky2_get_coalesce,
3754 .set_coalesce = sky2_set_coalesce,
3755 .get_ringparam = sky2_get_ringparam,
3756 .set_ringparam = sky2_set_ringparam,
3757 .get_pauseparam = sky2_get_pauseparam,
3758 .set_pauseparam = sky2_set_pauseparam,
3759 .phys_id = sky2_phys_id,
3760 .get_sset_count = sky2_get_sset_count,
3761 .get_ethtool_stats = sky2_get_ethtool_stats,
3762 };
3763
3764 #ifdef CONFIG_SKY2_DEBUG
3765
3766 static struct dentry *sky2_debug;
3767
3768 static int sky2_debug_show(struct seq_file *seq, void *v)
3769 {
3770 struct net_device *dev = seq->private;
3771 const struct sky2_port *sky2 = netdev_priv(dev);
3772 struct sky2_hw *hw = sky2->hw;
3773 unsigned port = sky2->port;
3774 unsigned idx, last;
3775 int sop;
3776
3777 if (!netif_running(dev))
3778 return -ENETDOWN;
3779
3780 seq_printf(seq, "IRQ src=%x mask=%x control=%x\n",
3781 sky2_read32(hw, B0_ISRC),
3782 sky2_read32(hw, B0_IMSK),
3783 sky2_read32(hw, B0_Y2_SP_ICR));
3784
3785 napi_disable(&hw->napi);
3786 last = sky2_read16(hw, STAT_PUT_IDX);
3787
3788 if (hw->st_idx == last)
3789 seq_puts(seq, "Status ring (empty)\n");
3790 else {
3791 seq_puts(seq, "Status ring\n");
3792 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
3793 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
3794 const struct sky2_status_le *le = hw->st_le + idx;
3795 seq_printf(seq, "[%d] %#x %d %#x\n",
3796 idx, le->opcode, le->length, le->status);
3797 }
3798 seq_puts(seq, "\n");
3799 }
3800
3801 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
3802 sky2->tx_cons, sky2->tx_prod,
3803 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
3804 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
3805
3806 /* Dump contents of tx ring */
3807 sop = 1;
3808 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < TX_RING_SIZE;
3809 idx = RING_NEXT(idx, TX_RING_SIZE)) {
3810 const struct sky2_tx_le *le = sky2->tx_le + idx;
3811 u32 a = le32_to_cpu(le->addr);
3812
3813 if (sop)
3814 seq_printf(seq, "%u:", idx);
3815 sop = 0;
3816
3817 switch(le->opcode & ~HW_OWNER) {
3818 case OP_ADDR64:
3819 seq_printf(seq, " %#x:", a);
3820 break;
3821 case OP_LRGLEN:
3822 seq_printf(seq, " mtu=%d", a);
3823 break;
3824 case OP_VLAN:
3825 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
3826 break;
3827 case OP_TCPLISW:
3828 seq_printf(seq, " csum=%#x", a);
3829 break;
3830 case OP_LARGESEND:
3831 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
3832 break;
3833 case OP_PACKET:
3834 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
3835 break;
3836 case OP_BUFFER:
3837 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
3838 break;
3839 default:
3840 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
3841 a, le16_to_cpu(le->length));
3842 }
3843
3844 if (le->ctrl & EOP) {
3845 seq_putc(seq, '\n');
3846 sop = 1;
3847 }
3848 }
3849
3850 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
3851 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
3852 last = sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3853 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
3854
3855 sky2_read32(hw, B0_Y2_SP_LISR);
3856 napi_enable(&hw->napi);
3857 return 0;
3858 }
3859
3860 static int sky2_debug_open(struct inode *inode, struct file *file)
3861 {
3862 return single_open(file, sky2_debug_show, inode->i_private);
3863 }
3864
3865 static const struct file_operations sky2_debug_fops = {
3866 .owner = THIS_MODULE,
3867 .open = sky2_debug_open,
3868 .read = seq_read,
3869 .llseek = seq_lseek,
3870 .release = single_release,
3871 };
3872
3873 /*
3874 * Use network device events to create/remove/rename
3875 * debugfs file entries
3876 */
3877 static int sky2_device_event(struct notifier_block *unused,
3878 unsigned long event, void *ptr)
3879 {
3880 struct net_device *dev = ptr;
3881 struct sky2_port *sky2 = netdev_priv(dev);
3882
3883 if (dev->open != sky2_up || !sky2_debug)
3884 return NOTIFY_DONE;
3885
3886 switch(event) {
3887 case NETDEV_CHANGENAME:
3888 if (sky2->debugfs) {
3889 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
3890 sky2_debug, dev->name);
3891 }
3892 break;
3893
3894 case NETDEV_GOING_DOWN:
3895 if (sky2->debugfs) {
3896 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
3897 dev->name);
3898 debugfs_remove(sky2->debugfs);
3899 sky2->debugfs = NULL;
3900 }
3901 break;
3902
3903 case NETDEV_UP:
3904 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
3905 sky2_debug, dev,
3906 &sky2_debug_fops);
3907 if (IS_ERR(sky2->debugfs))
3908 sky2->debugfs = NULL;
3909 }
3910
3911 return NOTIFY_DONE;
3912 }
3913
3914 static struct notifier_block sky2_notifier = {
3915 .notifier_call = sky2_device_event,
3916 };
3917
3918
3919 static __init void sky2_debug_init(void)
3920 {
3921 struct dentry *ent;
3922
3923 ent = debugfs_create_dir("sky2", NULL);
3924 if (!ent || IS_ERR(ent))
3925 return;
3926
3927 sky2_debug = ent;
3928 register_netdevice_notifier(&sky2_notifier);
3929 }
3930
3931 static __exit void sky2_debug_cleanup(void)
3932 {
3933 if (sky2_debug) {
3934 unregister_netdevice_notifier(&sky2_notifier);
3935 debugfs_remove(sky2_debug);
3936 sky2_debug = NULL;
3937 }
3938 }
3939
3940 #else
3941 #define sky2_debug_init()
3942 #define sky2_debug_cleanup()
3943 #endif
3944
3945
3946 /* Initialize network device */
3947 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3948 unsigned port,
3949 int highmem, int wol)
3950 {
3951 struct sky2_port *sky2;
3952 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3953
3954 if (!dev) {
3955 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
3956 return NULL;
3957 }
3958
3959 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3960 dev->irq = hw->pdev->irq;
3961 dev->open = sky2_up;
3962 dev->stop = sky2_down;
3963 dev->do_ioctl = sky2_ioctl;
3964 dev->hard_start_xmit = sky2_xmit_frame;
3965 dev->set_multicast_list = sky2_set_multicast;
3966 dev->set_mac_address = sky2_set_mac_address;
3967 dev->change_mtu = sky2_change_mtu;
3968 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3969 dev->tx_timeout = sky2_tx_timeout;
3970 dev->watchdog_timeo = TX_WATCHDOG;
3971 #ifdef CONFIG_NET_POLL_CONTROLLER
3972 if (port == 0)
3973 dev->poll_controller = sky2_netpoll;
3974 #endif
3975
3976 sky2 = netdev_priv(dev);
3977 sky2->netdev = dev;
3978 sky2->hw = hw;
3979 sky2->msg_enable = netif_msg_init(debug, default_msg);
3980
3981 /* Auto speed and flow control */
3982 sky2->autoneg = AUTONEG_ENABLE;
3983 sky2->flow_mode = FC_BOTH;
3984
3985 sky2->duplex = -1;
3986 sky2->speed = -1;
3987 sky2->advertising = sky2_supported_modes(hw);
3988 sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
3989 sky2->wol = wol;
3990
3991 spin_lock_init(&sky2->phy_lock);
3992 sky2->tx_pending = TX_DEF_PENDING;
3993 sky2->rx_pending = RX_DEF_PENDING;
3994
3995 hw->dev[port] = dev;
3996
3997 sky2->port = port;
3998
3999 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
4000 if (highmem)
4001 dev->features |= NETIF_F_HIGHDMA;
4002
4003 #ifdef SKY2_VLAN_TAG_USED
4004 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4005 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4006 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4007 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4008 dev->vlan_rx_register = sky2_vlan_rx_register;
4009 }
4010 #endif
4011
4012 /* read the mac address */
4013 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
4014 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
4015
4016 return dev;
4017 }
4018
4019 static void __devinit sky2_show_addr(struct net_device *dev)
4020 {
4021 const struct sky2_port *sky2 = netdev_priv(dev);
4022 DECLARE_MAC_BUF(mac);
4023
4024 if (netif_msg_probe(sky2))
4025 printk(KERN_INFO PFX "%s: addr %s\n",
4026 dev->name, print_mac(mac, dev->dev_addr));
4027 }
4028
4029 /* Handle software interrupt used during MSI test */
4030 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
4031 {
4032 struct sky2_hw *hw = dev_id;
4033 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4034
4035 if (status == 0)
4036 return IRQ_NONE;
4037
4038 if (status & Y2_IS_IRQ_SW) {
4039 hw->flags |= SKY2_HW_USE_MSI;
4040 wake_up(&hw->msi_wait);
4041 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4042 }
4043 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4044
4045 return IRQ_HANDLED;
4046 }
4047
4048 /* Test interrupt path by forcing a a software IRQ */
4049 static int __devinit sky2_test_msi(struct sky2_hw *hw)
4050 {
4051 struct pci_dev *pdev = hw->pdev;
4052 int err;
4053
4054 init_waitqueue_head (&hw->msi_wait);
4055
4056 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4057
4058 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
4059 if (err) {
4060 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4061 return err;
4062 }
4063
4064 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
4065 sky2_read8(hw, B0_CTST);
4066
4067 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
4068
4069 if (!(hw->flags & SKY2_HW_USE_MSI)) {
4070 /* MSI test failed, go back to INTx mode */
4071 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4072 "switching to INTx mode.\n");
4073
4074 err = -EOPNOTSUPP;
4075 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4076 }
4077
4078 sky2_write32(hw, B0_IMSK, 0);
4079 sky2_read32(hw, B0_IMSK);
4080
4081 free_irq(pdev->irq, hw);
4082
4083 return err;
4084 }
4085
4086 static int __devinit pci_wake_enabled(struct pci_dev *dev)
4087 {
4088 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
4089 u16 value;
4090
4091 if (!pm)
4092 return 0;
4093 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
4094 return 0;
4095 return value & PCI_PM_CTRL_PME_ENABLE;
4096 }
4097
4098 static int __devinit sky2_probe(struct pci_dev *pdev,
4099 const struct pci_device_id *ent)
4100 {
4101 struct net_device *dev;
4102 struct sky2_hw *hw;
4103 int err, using_dac = 0, wol_default;
4104
4105 err = pci_enable_device(pdev);
4106 if (err) {
4107 dev_err(&pdev->dev, "cannot enable PCI device\n");
4108 goto err_out;
4109 }
4110
4111 err = pci_request_regions(pdev, DRV_NAME);
4112 if (err) {
4113 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
4114 goto err_out_disable;
4115 }
4116
4117 pci_set_master(pdev);
4118
4119 if (sizeof(dma_addr_t) > sizeof(u32) &&
4120 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
4121 using_dac = 1;
4122 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
4123 if (err < 0) {
4124 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4125 "for consistent allocations\n");
4126 goto err_out_free_regions;
4127 }
4128 } else {
4129 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
4130 if (err) {
4131 dev_err(&pdev->dev, "no usable DMA configuration\n");
4132 goto err_out_free_regions;
4133 }
4134 }
4135
4136 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
4137
4138 err = -ENOMEM;
4139 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
4140 if (!hw) {
4141 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
4142 goto err_out_free_regions;
4143 }
4144
4145 hw->pdev = pdev;
4146
4147 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4148 if (!hw->regs) {
4149 dev_err(&pdev->dev, "cannot map device registers\n");
4150 goto err_out_free_hw;
4151 }
4152
4153 #ifdef __BIG_ENDIAN
4154 /* The sk98lin vendor driver uses hardware byte swapping but
4155 * this driver uses software swapping.
4156 */
4157 {
4158 u32 reg;
4159 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
4160 reg &= ~PCI_REV_DESC;
4161 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
4162 }
4163 #endif
4164
4165 /* ring for status responses */
4166 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
4167 if (!hw->st_le)
4168 goto err_out_iounmap;
4169
4170 err = sky2_init(hw);
4171 if (err)
4172 goto err_out_iounmap;
4173
4174 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
4175 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
4176 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
4177 hw->chip_id, hw->chip_rev);
4178
4179 sky2_reset(hw);
4180
4181 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
4182 if (!dev) {
4183 err = -ENOMEM;
4184 goto err_out_free_pci;
4185 }
4186
4187 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4188 err = sky2_test_msi(hw);
4189 if (err == -EOPNOTSUPP)
4190 pci_disable_msi(pdev);
4191 else if (err)
4192 goto err_out_free_netdev;
4193 }
4194
4195 err = register_netdev(dev);
4196 if (err) {
4197 dev_err(&pdev->dev, "cannot register net device\n");
4198 goto err_out_free_netdev;
4199 }
4200
4201 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4202
4203 err = request_irq(pdev->irq, sky2_intr,
4204 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
4205 dev->name, hw);
4206 if (err) {
4207 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4208 goto err_out_unregister;
4209 }
4210 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4211 napi_enable(&hw->napi);
4212
4213 sky2_show_addr(dev);
4214
4215 if (hw->ports > 1) {
4216 struct net_device *dev1;
4217
4218 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
4219 if (!dev1)
4220 dev_warn(&pdev->dev, "allocation for second device failed\n");
4221 else if ((err = register_netdev(dev1))) {
4222 dev_warn(&pdev->dev,
4223 "register of second port failed (%d)\n", err);
4224 hw->dev[1] = NULL;
4225 free_netdev(dev1);
4226 } else
4227 sky2_show_addr(dev1);
4228 }
4229
4230 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
4231 INIT_WORK(&hw->restart_work, sky2_restart);
4232
4233 pci_set_drvdata(pdev, hw);
4234
4235 return 0;
4236
4237 err_out_unregister:
4238 if (hw->flags & SKY2_HW_USE_MSI)
4239 pci_disable_msi(pdev);
4240 unregister_netdev(dev);
4241 err_out_free_netdev:
4242 free_netdev(dev);
4243 err_out_free_pci:
4244 sky2_write8(hw, B0_CTST, CS_RST_SET);
4245 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4246 err_out_iounmap:
4247 iounmap(hw->regs);
4248 err_out_free_hw:
4249 kfree(hw);
4250 err_out_free_regions:
4251 pci_release_regions(pdev);
4252 err_out_disable:
4253 pci_disable_device(pdev);
4254 err_out:
4255 pci_set_drvdata(pdev, NULL);
4256 return err;
4257 }
4258
4259 static void __devexit sky2_remove(struct pci_dev *pdev)
4260 {
4261 struct sky2_hw *hw = pci_get_drvdata(pdev);
4262 int i;
4263
4264 if (!hw)
4265 return;
4266
4267 del_timer_sync(&hw->watchdog_timer);
4268 cancel_work_sync(&hw->restart_work);
4269
4270 for (i = hw->ports-1; i >= 0; --i)
4271 unregister_netdev(hw->dev[i]);
4272
4273 sky2_write32(hw, B0_IMSK, 0);
4274
4275 sky2_power_aux(hw);
4276
4277 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
4278 sky2_write8(hw, B0_CTST, CS_RST_SET);
4279 sky2_read8(hw, B0_CTST);
4280
4281 free_irq(pdev->irq, hw);
4282 if (hw->flags & SKY2_HW_USE_MSI)
4283 pci_disable_msi(pdev);
4284 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4285 pci_release_regions(pdev);
4286 pci_disable_device(pdev);
4287
4288 for (i = hw->ports-1; i >= 0; --i)
4289 free_netdev(hw->dev[i]);
4290
4291 iounmap(hw->regs);
4292 kfree(hw);
4293
4294 pci_set_drvdata(pdev, NULL);
4295 }
4296
4297 #ifdef CONFIG_PM
4298 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4299 {
4300 struct sky2_hw *hw = pci_get_drvdata(pdev);
4301 int i, wol = 0;
4302
4303 if (!hw)
4304 return 0;
4305
4306 for (i = 0; i < hw->ports; i++) {
4307 struct net_device *dev = hw->dev[i];
4308 struct sky2_port *sky2 = netdev_priv(dev);
4309
4310 if (netif_running(dev))
4311 sky2_down(dev);
4312
4313 if (sky2->wol)
4314 sky2_wol_init(sky2);
4315
4316 wol |= sky2->wol;
4317 }
4318
4319 sky2_write32(hw, B0_IMSK, 0);
4320 napi_disable(&hw->napi);
4321 sky2_power_aux(hw);
4322
4323 pci_save_state(pdev);
4324 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
4325 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4326
4327 return 0;
4328 }
4329
4330 static int sky2_resume(struct pci_dev *pdev)
4331 {
4332 struct sky2_hw *hw = pci_get_drvdata(pdev);
4333 int i, err;
4334
4335 if (!hw)
4336 return 0;
4337
4338 err = pci_set_power_state(pdev, PCI_D0);
4339 if (err)
4340 goto out;
4341
4342 err = pci_restore_state(pdev);
4343 if (err)
4344 goto out;
4345
4346 pci_enable_wake(pdev, PCI_D0, 0);
4347
4348 /* Re-enable all clocks */
4349 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4350 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4351 hw->chip_id == CHIP_ID_YUKON_FE_P)
4352 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
4353
4354 sky2_reset(hw);
4355 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4356 napi_enable(&hw->napi);
4357
4358 for (i = 0; i < hw->ports; i++) {
4359 struct net_device *dev = hw->dev[i];
4360 if (netif_running(dev)) {
4361 err = sky2_up(dev);
4362 if (err) {
4363 printk(KERN_ERR PFX "%s: could not up: %d\n",
4364 dev->name, err);
4365 dev_close(dev);
4366 goto out;
4367 }
4368
4369 sky2_set_multicast(dev);
4370 }
4371 }
4372
4373 return 0;
4374 out:
4375 dev_err(&pdev->dev, "resume failed (%d)\n", err);
4376 pci_disable_device(pdev);
4377 return err;
4378 }
4379 #endif
4380
4381 static void sky2_shutdown(struct pci_dev *pdev)
4382 {
4383 struct sky2_hw *hw = pci_get_drvdata(pdev);
4384 int i, wol = 0;
4385
4386 if (!hw)
4387 return;
4388
4389 del_timer_sync(&hw->watchdog_timer);
4390
4391 for (i = 0; i < hw->ports; i++) {
4392 struct net_device *dev = hw->dev[i];
4393 struct sky2_port *sky2 = netdev_priv(dev);
4394
4395 if (sky2->wol) {
4396 wol = 1;
4397 sky2_wol_init(sky2);
4398 }
4399 }
4400
4401 if (wol)
4402 sky2_power_aux(hw);
4403
4404 pci_enable_wake(pdev, PCI_D3hot, wol);
4405 pci_enable_wake(pdev, PCI_D3cold, wol);
4406
4407 pci_disable_device(pdev);
4408 pci_set_power_state(pdev, PCI_D3hot);
4409
4410 }
4411
4412 static struct pci_driver sky2_driver = {
4413 .name = DRV_NAME,
4414 .id_table = sky2_id_table,
4415 .probe = sky2_probe,
4416 .remove = __devexit_p(sky2_remove),
4417 #ifdef CONFIG_PM
4418 .suspend = sky2_suspend,
4419 .resume = sky2_resume,
4420 #endif
4421 .shutdown = sky2_shutdown,
4422 };
4423
4424 static int __init sky2_init_module(void)
4425 {
4426 sky2_debug_init();
4427 return pci_register_driver(&sky2_driver);
4428 }
4429
4430 static void __exit sky2_cleanup_module(void)
4431 {
4432 pci_unregister_driver(&sky2_driver);
4433 sky2_debug_cleanup();
4434 }
4435
4436 module_init(sky2_init_module);
4437 module_exit(sky2_cleanup_module);
4438
4439 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
4440 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
4441 MODULE_LICENSE("GPL");
4442 MODULE_VERSION(DRV_VERSION);
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