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omap1: Fix gpio mpuio bank to work for multi-omap for 7xx/15xx/16xx
[linux-2.6.git] / arch / arm / plat-omap / gpio.c
blob8d493b992e703b65ed904c80017c46c61f7f59d8
1 /*
2 * linux/arch/arm/plat-omap/gpio.c
3 *
4 * Support functions for OMAP GPIO
5 *
6 * Copyright (C) 2003-2005 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
8 *
9 * Copyright (C) 2009 Texas Instruments
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/interrupt.h>
20 #include <linux/sysdev.h>
21 #include <linux/err.h>
22 #include <linux/clk.h>
23 #include <linux/io.h>
24 #include <linux/slab.h>
25 #include <linux/pm_runtime.h>
26
27 #include <mach/hardware.h>
28 #include <asm/irq.h>
29 #include <mach/irqs.h>
30 #include <mach/gpio.h>
31 #include <asm/mach/irq.h>
32 #include <plat/powerdomain.h>
33
34 /*
35 * OMAP1510 GPIO registers
36 */
37 #define OMAP1510_GPIO_DATA_INPUT 0x00
38 #define OMAP1510_GPIO_DATA_OUTPUT 0x04
39 #define OMAP1510_GPIO_DIR_CONTROL 0x08
40 #define OMAP1510_GPIO_INT_CONTROL 0x0c
41 #define OMAP1510_GPIO_INT_MASK 0x10
42 #define OMAP1510_GPIO_INT_STATUS 0x14
43 #define OMAP1510_GPIO_PIN_CONTROL 0x18
44
45 #define OMAP1510_IH_GPIO_BASE 64
46
47 /*
48 * OMAP1610 specific GPIO registers
49 */
50 #define OMAP1610_GPIO_REVISION 0x0000
51 #define OMAP1610_GPIO_SYSCONFIG 0x0010
52 #define OMAP1610_GPIO_SYSSTATUS 0x0014
53 #define OMAP1610_GPIO_IRQSTATUS1 0x0018
54 #define OMAP1610_GPIO_IRQENABLE1 0x001c
55 #define OMAP1610_GPIO_WAKEUPENABLE 0x0028
56 #define OMAP1610_GPIO_DATAIN 0x002c
57 #define OMAP1610_GPIO_DATAOUT 0x0030
58 #define OMAP1610_GPIO_DIRECTION 0x0034
59 #define OMAP1610_GPIO_EDGE_CTRL1 0x0038
60 #define OMAP1610_GPIO_EDGE_CTRL2 0x003c
61 #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
62 #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
63 #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
64 #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
65 #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
66 #define OMAP1610_GPIO_SET_DATAOUT 0x00f0
67
68 /*
69 * OMAP7XX specific GPIO registers
70 */
71 #define OMAP7XX_GPIO_DATA_INPUT 0x00
72 #define OMAP7XX_GPIO_DATA_OUTPUT 0x04
73 #define OMAP7XX_GPIO_DIR_CONTROL 0x08
74 #define OMAP7XX_GPIO_INT_CONTROL 0x0c
75 #define OMAP7XX_GPIO_INT_MASK 0x10
76 #define OMAP7XX_GPIO_INT_STATUS 0x14
77
78 /*
79 * omap2+ specific GPIO registers
80 */
81 #define OMAP24XX_GPIO_REVISION 0x0000
82 #define OMAP24XX_GPIO_IRQSTATUS1 0x0018
83 #define OMAP24XX_GPIO_IRQSTATUS2 0x0028
84 #define OMAP24XX_GPIO_IRQENABLE2 0x002c
85 #define OMAP24XX_GPIO_IRQENABLE1 0x001c
86 #define OMAP24XX_GPIO_WAKE_EN 0x0020
87 #define OMAP24XX_GPIO_CTRL 0x0030
88 #define OMAP24XX_GPIO_OE 0x0034
89 #define OMAP24XX_GPIO_DATAIN 0x0038
90 #define OMAP24XX_GPIO_DATAOUT 0x003c
91 #define OMAP24XX_GPIO_LEVELDETECT0 0x0040
92 #define OMAP24XX_GPIO_LEVELDETECT1 0x0044
93 #define OMAP24XX_GPIO_RISINGDETECT 0x0048
94 #define OMAP24XX_GPIO_FALLINGDETECT 0x004c
95 #define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
96 #define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
97 #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
98 #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
99 #define OMAP24XX_GPIO_CLEARWKUENA 0x0080
100 #define OMAP24XX_GPIO_SETWKUENA 0x0084
101 #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
102 #define OMAP24XX_GPIO_SETDATAOUT 0x0094
103
104 #define OMAP4_GPIO_REVISION 0x0000
105 #define OMAP4_GPIO_EOI 0x0020
106 #define OMAP4_GPIO_IRQSTATUSRAW0 0x0024
107 #define OMAP4_GPIO_IRQSTATUSRAW1 0x0028
108 #define OMAP4_GPIO_IRQSTATUS0 0x002c
109 #define OMAP4_GPIO_IRQSTATUS1 0x0030
110 #define OMAP4_GPIO_IRQSTATUSSET0 0x0034
111 #define OMAP4_GPIO_IRQSTATUSSET1 0x0038
112 #define OMAP4_GPIO_IRQSTATUSCLR0 0x003c
113 #define OMAP4_GPIO_IRQSTATUSCLR1 0x0040
114 #define OMAP4_GPIO_IRQWAKEN0 0x0044
115 #define OMAP4_GPIO_IRQWAKEN1 0x0048
116 #define OMAP4_GPIO_IRQENABLE1 0x011c
117 #define OMAP4_GPIO_WAKE_EN 0x0120
118 #define OMAP4_GPIO_IRQSTATUS2 0x0128
119 #define OMAP4_GPIO_IRQENABLE2 0x012c
120 #define OMAP4_GPIO_CTRL 0x0130
121 #define OMAP4_GPIO_OE 0x0134
122 #define OMAP4_GPIO_DATAIN 0x0138
123 #define OMAP4_GPIO_DATAOUT 0x013c
124 #define OMAP4_GPIO_LEVELDETECT0 0x0140
125 #define OMAP4_GPIO_LEVELDETECT1 0x0144
126 #define OMAP4_GPIO_RISINGDETECT 0x0148
127 #define OMAP4_GPIO_FALLINGDETECT 0x014c
128 #define OMAP4_GPIO_DEBOUNCENABLE 0x0150
129 #define OMAP4_GPIO_DEBOUNCINGTIME 0x0154
130 #define OMAP4_GPIO_CLEARIRQENABLE1 0x0160
131 #define OMAP4_GPIO_SETIRQENABLE1 0x0164
132 #define OMAP4_GPIO_CLEARWKUENA 0x0180
133 #define OMAP4_GPIO_SETWKUENA 0x0184
134 #define OMAP4_GPIO_CLEARDATAOUT 0x0190
135 #define OMAP4_GPIO_SETDATAOUT 0x0194
136
137 struct gpio_bank {
138 unsigned long pbase;
139 void __iomem *base;
140 u16 irq;
141 u16 virtual_irq_start;
142 int method;
143 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
144 u32 suspend_wakeup;
145 u32 saved_wakeup;
146 #endif
147 u32 non_wakeup_gpios;
148 u32 enabled_non_wakeup_gpios;
149
150 u32 saved_datain;
151 u32 saved_fallingdetect;
152 u32 saved_risingdetect;
153 u32 level_mask;
154 u32 toggle_mask;
155 spinlock_t lock;
156 struct gpio_chip chip;
157 struct clk *dbck;
158 u32 mod_usage;
159 u32 dbck_enable_mask;
160 struct device *dev;
161 bool dbck_flag;
162 int stride;
163 };
164
165 #ifdef CONFIG_ARCH_OMAP3
166 struct omap3_gpio_regs {
167 u32 irqenable1;
168 u32 irqenable2;
169 u32 wake_en;
170 u32 ctrl;
171 u32 oe;
172 u32 leveldetect0;
173 u32 leveldetect1;
174 u32 risingdetect;
175 u32 fallingdetect;
176 u32 dataout;
177 };
178
179 static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
180 #endif
181
182 /*
183 * TODO: Cleanup gpio_bank usage as it is having information
184 * related to all instances of the device
185 */
186 static struct gpio_bank *gpio_bank;
187
188 static int bank_width;
189
190 /* TODO: Analyze removing gpio_bank_count usage from driver code */
191 int gpio_bank_count;
192
193 static inline struct gpio_bank *get_gpio_bank(int gpio)
194 {
195 if (cpu_is_omap15xx()) {
196 if (OMAP_GPIO_IS_MPUIO(gpio))
197 return &gpio_bank[0];
198 return &gpio_bank[1];
199 }
200 if (cpu_is_omap16xx()) {
201 if (OMAP_GPIO_IS_MPUIO(gpio))
202 return &gpio_bank[0];
203 return &gpio_bank[1 + (gpio >> 4)];
204 }
205 if (cpu_is_omap7xx()) {
206 if (OMAP_GPIO_IS_MPUIO(gpio))
207 return &gpio_bank[0];
208 return &gpio_bank[1 + (gpio >> 5)];
209 }
210 if (cpu_is_omap24xx())
211 return &gpio_bank[gpio >> 5];
212 if (cpu_is_omap34xx() || cpu_is_omap44xx())
213 return &gpio_bank[gpio >> 5];
214 BUG();
215 return NULL;
216 }
217
218 static inline int get_gpio_index(int gpio)
219 {
220 if (cpu_is_omap7xx())
221 return gpio & 0x1f;
222 if (cpu_is_omap24xx())
223 return gpio & 0x1f;
224 if (cpu_is_omap34xx() || cpu_is_omap44xx())
225 return gpio & 0x1f;
226 return gpio & 0x0f;
227 }
228
229 static inline int gpio_valid(int gpio)
230 {
231 if (gpio < 0)
232 return -1;
233 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
234 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
235 return -1;
236 return 0;
237 }
238 if (cpu_is_omap15xx() && gpio < 16)
239 return 0;
240 if ((cpu_is_omap16xx()) && gpio < 64)
241 return 0;
242 if (cpu_is_omap7xx() && gpio < 192)
243 return 0;
244 if (cpu_is_omap2420() && gpio < 128)
245 return 0;
246 if (cpu_is_omap2430() && gpio < 160)
247 return 0;
248 if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192)
249 return 0;
250 return -1;
251 }
252
253 static int check_gpio(int gpio)
254 {
255 if (unlikely(gpio_valid(gpio) < 0)) {
256 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
257 dump_stack();
258 return -1;
259 }
260 return 0;
261 }
262
263 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
264 {
265 void __iomem *reg = bank->base;
266 u32 l;
267
268 switch (bank->method) {
269 #ifdef CONFIG_ARCH_OMAP1
270 case METHOD_MPUIO:
271 reg += OMAP_MPUIO_IO_CNTL / bank->stride;
272 break;
273 #endif
274 #ifdef CONFIG_ARCH_OMAP15XX
275 case METHOD_GPIO_1510:
276 reg += OMAP1510_GPIO_DIR_CONTROL;
277 break;
278 #endif
279 #ifdef CONFIG_ARCH_OMAP16XX
280 case METHOD_GPIO_1610:
281 reg += OMAP1610_GPIO_DIRECTION;
282 break;
283 #endif
284 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
285 case METHOD_GPIO_7XX:
286 reg += OMAP7XX_GPIO_DIR_CONTROL;
287 break;
288 #endif
289 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
290 case METHOD_GPIO_24XX:
291 reg += OMAP24XX_GPIO_OE;
292 break;
293 #endif
294 #if defined(CONFIG_ARCH_OMAP4)
295 case METHOD_GPIO_44XX:
296 reg += OMAP4_GPIO_OE;
297 break;
298 #endif
299 default:
300 WARN_ON(1);
301 return;
302 }
303 l = __raw_readl(reg);
304 if (is_input)
305 l |= 1 << gpio;
306 else
307 l &= ~(1 << gpio);
308 __raw_writel(l, reg);
309 }
310
311 static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
312 {
313 void __iomem *reg = bank->base;
314 u32 l = 0;
315
316 switch (bank->method) {
317 #ifdef CONFIG_ARCH_OMAP1
318 case METHOD_MPUIO:
319 reg += OMAP_MPUIO_OUTPUT / bank->stride;
320 l = __raw_readl(reg);
321 if (enable)
322 l |= 1 << gpio;
323 else
324 l &= ~(1 << gpio);
325 break;
326 #endif
327 #ifdef CONFIG_ARCH_OMAP15XX
328 case METHOD_GPIO_1510:
329 reg += OMAP1510_GPIO_DATA_OUTPUT;
330 l = __raw_readl(reg);
331 if (enable)
332 l |= 1 << gpio;
333 else
334 l &= ~(1 << gpio);
335 break;
336 #endif
337 #ifdef CONFIG_ARCH_OMAP16XX
338 case METHOD_GPIO_1610:
339 if (enable)
340 reg += OMAP1610_GPIO_SET_DATAOUT;
341 else
342 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
343 l = 1 << gpio;
344 break;
345 #endif
346 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
347 case METHOD_GPIO_7XX:
348 reg += OMAP7XX_GPIO_DATA_OUTPUT;
349 l = __raw_readl(reg);
350 if (enable)
351 l |= 1 << gpio;
352 else
353 l &= ~(1 << gpio);
354 break;
355 #endif
356 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
357 case METHOD_GPIO_24XX:
358 if (enable)
359 reg += OMAP24XX_GPIO_SETDATAOUT;
360 else
361 reg += OMAP24XX_GPIO_CLEARDATAOUT;
362 l = 1 << gpio;
363 break;
364 #endif
365 #ifdef CONFIG_ARCH_OMAP4
366 case METHOD_GPIO_44XX:
367 if (enable)
368 reg += OMAP4_GPIO_SETDATAOUT;
369 else
370 reg += OMAP4_GPIO_CLEARDATAOUT;
371 l = 1 << gpio;
372 break;
373 #endif
374 default:
375 WARN_ON(1);
376 return;
377 }
378 __raw_writel(l, reg);
379 }
380
381 static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
382 {
383 void __iomem *reg;
384
385 if (check_gpio(gpio) < 0)
386 return -EINVAL;
387 reg = bank->base;
388 switch (bank->method) {
389 #ifdef CONFIG_ARCH_OMAP1
390 case METHOD_MPUIO:
391 reg += OMAP_MPUIO_INPUT_LATCH / bank->stride;
392 break;
393 #endif
394 #ifdef CONFIG_ARCH_OMAP15XX
395 case METHOD_GPIO_1510:
396 reg += OMAP1510_GPIO_DATA_INPUT;
397 break;
398 #endif
399 #ifdef CONFIG_ARCH_OMAP16XX
400 case METHOD_GPIO_1610:
401 reg += OMAP1610_GPIO_DATAIN;
402 break;
403 #endif
404 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
405 case METHOD_GPIO_7XX:
406 reg += OMAP7XX_GPIO_DATA_INPUT;
407 break;
408 #endif
409 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
410 case METHOD_GPIO_24XX:
411 reg += OMAP24XX_GPIO_DATAIN;
412 break;
413 #endif
414 #ifdef CONFIG_ARCH_OMAP4
415 case METHOD_GPIO_44XX:
416 reg += OMAP4_GPIO_DATAIN;
417 break;
418 #endif
419 default:
420 return -EINVAL;
421 }
422 return (__raw_readl(reg)
423 & (1 << get_gpio_index(gpio))) != 0;
424 }
425
426 static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
427 {
428 void __iomem *reg;
429
430 if (check_gpio(gpio) < 0)
431 return -EINVAL;
432 reg = bank->base;
433
434 switch (bank->method) {
435 #ifdef CONFIG_ARCH_OMAP1
436 case METHOD_MPUIO:
437 reg += OMAP_MPUIO_OUTPUT / bank->stride;
438 break;
439 #endif
440 #ifdef CONFIG_ARCH_OMAP15XX
441 case METHOD_GPIO_1510:
442 reg += OMAP1510_GPIO_DATA_OUTPUT;
443 break;
444 #endif
445 #ifdef CONFIG_ARCH_OMAP16XX
446 case METHOD_GPIO_1610:
447 reg += OMAP1610_GPIO_DATAOUT;
448 break;
449 #endif
450 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
451 case METHOD_GPIO_7XX:
452 reg += OMAP7XX_GPIO_DATA_OUTPUT;
453 break;
454 #endif
455 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
456 case METHOD_GPIO_24XX:
457 reg += OMAP24XX_GPIO_DATAOUT;
458 break;
459 #endif
460 #ifdef CONFIG_ARCH_OMAP4
461 case METHOD_GPIO_44XX:
462 reg += OMAP4_GPIO_DATAOUT;
463 break;
464 #endif
465 default:
466 return -EINVAL;
467 }
468
469 return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0;
470 }
471
472 #define MOD_REG_BIT(reg, bit_mask, set) \
473 do { \
474 int l = __raw_readl(base + reg); \
475 if (set) l |= bit_mask; \
476 else l &= ~bit_mask; \
477 __raw_writel(l, base + reg); \
478 } while(0)
479
480 /**
481 * _set_gpio_debounce - low level gpio debounce time
482 * @bank: the gpio bank we're acting upon
483 * @gpio: the gpio number on this @gpio
484 * @debounce: debounce time to use
485 *
486 * OMAP's debounce time is in 31us steps so we need
487 * to convert and round up to the closest unit.
488 */
489 static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
490 unsigned debounce)
491 {
492 void __iomem *reg = bank->base;
493 u32 val;
494 u32 l;
495
496 if (!bank->dbck_flag)
497 return;
498
499 if (debounce < 32)
500 debounce = 0x01;
501 else if (debounce > 7936)
502 debounce = 0xff;
503 else
504 debounce = (debounce / 0x1f) - 1;
505
506 l = 1 << get_gpio_index(gpio);
507
508 if (bank->method == METHOD_GPIO_44XX)
509 reg += OMAP4_GPIO_DEBOUNCINGTIME;
510 else
511 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
512
513 __raw_writel(debounce, reg);
514
515 reg = bank->base;
516 if (bank->method == METHOD_GPIO_44XX)
517 reg += OMAP4_GPIO_DEBOUNCENABLE;
518 else
519 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
520
521 val = __raw_readl(reg);
522
523 if (debounce) {
524 val |= l;
525 clk_enable(bank->dbck);
526 } else {
527 val &= ~l;
528 clk_disable(bank->dbck);
529 }
530 bank->dbck_enable_mask = val;
531
532 __raw_writel(val, reg);
533 }
534
535 #ifdef CONFIG_ARCH_OMAP2PLUS
536 static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
537 int trigger)
538 {
539 void __iomem *base = bank->base;
540 u32 gpio_bit = 1 << gpio;
541 u32 val;
542
543 if (cpu_is_omap44xx()) {
544 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit,
545 trigger & IRQ_TYPE_LEVEL_LOW);
546 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit,
547 trigger & IRQ_TYPE_LEVEL_HIGH);
548 MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit,
549 trigger & IRQ_TYPE_EDGE_RISING);
550 MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit,
551 trigger & IRQ_TYPE_EDGE_FALLING);
552 } else {
553 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
554 trigger & IRQ_TYPE_LEVEL_LOW);
555 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
556 trigger & IRQ_TYPE_LEVEL_HIGH);
557 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
558 trigger & IRQ_TYPE_EDGE_RISING);
559 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
560 trigger & IRQ_TYPE_EDGE_FALLING);
561 }
562 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
563 if (cpu_is_omap44xx()) {
564 if (trigger != 0)
565 __raw_writel(1 << gpio, bank->base+
566 OMAP4_GPIO_IRQWAKEN0);
567 else {
568 val = __raw_readl(bank->base +
569 OMAP4_GPIO_IRQWAKEN0);
570 __raw_writel(val & (~(1 << gpio)), bank->base +
571 OMAP4_GPIO_IRQWAKEN0);
572 }
573 } else {
574 /*
575 * GPIO wakeup request can only be generated on edge
576 * transitions
577 */
578 if (trigger & IRQ_TYPE_EDGE_BOTH)
579 __raw_writel(1 << gpio, bank->base
580 + OMAP24XX_GPIO_SETWKUENA);
581 else
582 __raw_writel(1 << gpio, bank->base
583 + OMAP24XX_GPIO_CLEARWKUENA);
584 }
585 }
586 /* This part needs to be executed always for OMAP34xx */
587 if (cpu_is_omap34xx() || (bank->non_wakeup_gpios & gpio_bit)) {
588 /*
589 * Log the edge gpio and manually trigger the IRQ
590 * after resume if the input level changes
591 * to avoid irq lost during PER RET/OFF mode
592 * Applies for omap2 non-wakeup gpio and all omap3 gpios
593 */
594 if (trigger & IRQ_TYPE_EDGE_BOTH)
595 bank->enabled_non_wakeup_gpios |= gpio_bit;
596 else
597 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
598 }
599
600 if (cpu_is_omap44xx()) {
601 bank->level_mask =
602 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
603 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
604 } else {
605 bank->level_mask =
606 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
607 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
608 }
609 }
610 #endif
611
612 #ifdef CONFIG_ARCH_OMAP1
613 /*
614 * This only applies to chips that can't do both rising and falling edge
615 * detection at once. For all other chips, this function is a noop.
616 */
617 static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
618 {
619 void __iomem *reg = bank->base;
620 u32 l = 0;
621
622 switch (bank->method) {
623 case METHOD_MPUIO:
624 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
625 break;
626 #ifdef CONFIG_ARCH_OMAP15XX
627 case METHOD_GPIO_1510:
628 reg += OMAP1510_GPIO_INT_CONTROL;
629 break;
630 #endif
631 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
632 case METHOD_GPIO_7XX:
633 reg += OMAP7XX_GPIO_INT_CONTROL;
634 break;
635 #endif
636 default:
637 return;
638 }
639
640 l = __raw_readl(reg);
641 if ((l >> gpio) & 1)
642 l &= ~(1 << gpio);
643 else
644 l |= 1 << gpio;
645
646 __raw_writel(l, reg);
647 }
648 #endif
649
650 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
651 {
652 void __iomem *reg = bank->base;
653 u32 l = 0;
654
655 switch (bank->method) {
656 #ifdef CONFIG_ARCH_OMAP1
657 case METHOD_MPUIO:
658 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
659 l = __raw_readl(reg);
660 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
661 bank->toggle_mask |= 1 << gpio;
662 if (trigger & IRQ_TYPE_EDGE_RISING)
663 l |= 1 << gpio;
664 else if (trigger & IRQ_TYPE_EDGE_FALLING)
665 l &= ~(1 << gpio);
666 else
667 goto bad;
668 break;
669 #endif
670 #ifdef CONFIG_ARCH_OMAP15XX
671 case METHOD_GPIO_1510:
672 reg += OMAP1510_GPIO_INT_CONTROL;
673 l = __raw_readl(reg);
674 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
675 bank->toggle_mask |= 1 << gpio;
676 if (trigger & IRQ_TYPE_EDGE_RISING)
677 l |= 1 << gpio;
678 else if (trigger & IRQ_TYPE_EDGE_FALLING)
679 l &= ~(1 << gpio);
680 else
681 goto bad;
682 break;
683 #endif
684 #ifdef CONFIG_ARCH_OMAP16XX
685 case METHOD_GPIO_1610:
686 if (gpio & 0x08)
687 reg += OMAP1610_GPIO_EDGE_CTRL2;
688 else
689 reg += OMAP1610_GPIO_EDGE_CTRL1;
690 gpio &= 0x07;
691 l = __raw_readl(reg);
692 l &= ~(3 << (gpio << 1));
693 if (trigger & IRQ_TYPE_EDGE_RISING)
694 l |= 2 << (gpio << 1);
695 if (trigger & IRQ_TYPE_EDGE_FALLING)
696 l |= 1 << (gpio << 1);
697 if (trigger)
698 /* Enable wake-up during idle for dynamic tick */
699 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
700 else
701 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
702 break;
703 #endif
704 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
705 case METHOD_GPIO_7XX:
706 reg += OMAP7XX_GPIO_INT_CONTROL;
707 l = __raw_readl(reg);
708 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
709 bank->toggle_mask |= 1 << gpio;
710 if (trigger & IRQ_TYPE_EDGE_RISING)
711 l |= 1 << gpio;
712 else if (trigger & IRQ_TYPE_EDGE_FALLING)
713 l &= ~(1 << gpio);
714 else
715 goto bad;
716 break;
717 #endif
718 #ifdef CONFIG_ARCH_OMAP2PLUS
719 case METHOD_GPIO_24XX:
720 case METHOD_GPIO_44XX:
721 set_24xx_gpio_triggering(bank, gpio, trigger);
722 break;
723 #endif
724 default:
725 goto bad;
726 }
727 __raw_writel(l, reg);
728 return 0;
729 bad:
730 return -EINVAL;
731 }
732
733 static int gpio_irq_type(unsigned irq, unsigned type)
734 {
735 struct gpio_bank *bank;
736 unsigned gpio;
737 int retval;
738 unsigned long flags;
739
740 if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE)
741 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
742 else
743 gpio = irq - IH_GPIO_BASE;
744
745 if (check_gpio(gpio) < 0)
746 return -EINVAL;
747
748 if (type & ~IRQ_TYPE_SENSE_MASK)
749 return -EINVAL;
750
751 /* OMAP1 allows only only edge triggering */
752 if (!cpu_class_is_omap2()
753 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
754 return -EINVAL;
755
756 bank = get_irq_chip_data(irq);
757 spin_lock_irqsave(&bank->lock, flags);
758 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
759 if (retval == 0) {
760 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
761 irq_desc[irq].status |= type;
762 }
763 spin_unlock_irqrestore(&bank->lock, flags);
764
765 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
766 __set_irq_handler_unlocked(irq, handle_level_irq);
767 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
768 __set_irq_handler_unlocked(irq, handle_edge_irq);
769
770 return retval;
771 }
772
773 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
774 {
775 void __iomem *reg = bank->base;
776
777 switch (bank->method) {
778 #ifdef CONFIG_ARCH_OMAP1
779 case METHOD_MPUIO:
780 /* MPUIO irqstatus is reset by reading the status register,
781 * so do nothing here */
782 return;
783 #endif
784 #ifdef CONFIG_ARCH_OMAP15XX
785 case METHOD_GPIO_1510:
786 reg += OMAP1510_GPIO_INT_STATUS;
787 break;
788 #endif
789 #ifdef CONFIG_ARCH_OMAP16XX
790 case METHOD_GPIO_1610:
791 reg += OMAP1610_GPIO_IRQSTATUS1;
792 break;
793 #endif
794 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
795 case METHOD_GPIO_7XX:
796 reg += OMAP7XX_GPIO_INT_STATUS;
797 break;
798 #endif
799 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
800 case METHOD_GPIO_24XX:
801 reg += OMAP24XX_GPIO_IRQSTATUS1;
802 break;
803 #endif
804 #if defined(CONFIG_ARCH_OMAP4)
805 case METHOD_GPIO_44XX:
806 reg += OMAP4_GPIO_IRQSTATUS0;
807 break;
808 #endif
809 default:
810 WARN_ON(1);
811 return;
812 }
813 __raw_writel(gpio_mask, reg);
814
815 /* Workaround for clearing DSP GPIO interrupts to allow retention */
816 if (cpu_is_omap24xx() || cpu_is_omap34xx())
817 reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2;
818 else if (cpu_is_omap44xx())
819 reg = bank->base + OMAP4_GPIO_IRQSTATUS1;
820
821 if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
822 __raw_writel(gpio_mask, reg);
823
824 /* Flush posted write for the irq status to avoid spurious interrupts */
825 __raw_readl(reg);
826 }
827 }
828
829 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
830 {
831 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
832 }
833
834 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
835 {
836 void __iomem *reg = bank->base;
837 int inv = 0;
838 u32 l;
839 u32 mask;
840
841 switch (bank->method) {
842 #ifdef CONFIG_ARCH_OMAP1
843 case METHOD_MPUIO:
844 reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride;
845 mask = 0xffff;
846 inv = 1;
847 break;
848 #endif
849 #ifdef CONFIG_ARCH_OMAP15XX
850 case METHOD_GPIO_1510:
851 reg += OMAP1510_GPIO_INT_MASK;
852 mask = 0xffff;
853 inv = 1;
854 break;
855 #endif
856 #ifdef CONFIG_ARCH_OMAP16XX
857 case METHOD_GPIO_1610:
858 reg += OMAP1610_GPIO_IRQENABLE1;
859 mask = 0xffff;
860 break;
861 #endif
862 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
863 case METHOD_GPIO_7XX:
864 reg += OMAP7XX_GPIO_INT_MASK;
865 mask = 0xffffffff;
866 inv = 1;
867 break;
868 #endif
869 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
870 case METHOD_GPIO_24XX:
871 reg += OMAP24XX_GPIO_IRQENABLE1;
872 mask = 0xffffffff;
873 break;
874 #endif
875 #if defined(CONFIG_ARCH_OMAP4)
876 case METHOD_GPIO_44XX:
877 reg += OMAP4_GPIO_IRQSTATUSSET0;
878 mask = 0xffffffff;
879 break;
880 #endif
881 default:
882 WARN_ON(1);
883 return 0;
884 }
885
886 l = __raw_readl(reg);
887 if (inv)
888 l = ~l;
889 l &= mask;
890 return l;
891 }
892
893 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
894 {
895 void __iomem *reg = bank->base;
896 u32 l;
897
898 switch (bank->method) {
899 #ifdef CONFIG_ARCH_OMAP1
900 case METHOD_MPUIO:
901 reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride;
902 l = __raw_readl(reg);
903 if (enable)
904 l &= ~(gpio_mask);
905 else
906 l |= gpio_mask;
907 break;
908 #endif
909 #ifdef CONFIG_ARCH_OMAP15XX
910 case METHOD_GPIO_1510:
911 reg += OMAP1510_GPIO_INT_MASK;
912 l = __raw_readl(reg);
913 if (enable)
914 l &= ~(gpio_mask);
915 else
916 l |= gpio_mask;
917 break;
918 #endif
919 #ifdef CONFIG_ARCH_OMAP16XX
920 case METHOD_GPIO_1610:
921 if (enable)
922 reg += OMAP1610_GPIO_SET_IRQENABLE1;
923 else
924 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
925 l = gpio_mask;
926 break;
927 #endif
928 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
929 case METHOD_GPIO_7XX:
930 reg += OMAP7XX_GPIO_INT_MASK;
931 l = __raw_readl(reg);
932 if (enable)
933 l &= ~(gpio_mask);
934 else
935 l |= gpio_mask;
936 break;
937 #endif
938 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
939 case METHOD_GPIO_24XX:
940 if (enable)
941 reg += OMAP24XX_GPIO_SETIRQENABLE1;
942 else
943 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
944 l = gpio_mask;
945 break;
946 #endif
947 #ifdef CONFIG_ARCH_OMAP4
948 case METHOD_GPIO_44XX:
949 if (enable)
950 reg += OMAP4_GPIO_IRQSTATUSSET0;
951 else
952 reg += OMAP4_GPIO_IRQSTATUSCLR0;
953 l = gpio_mask;
954 break;
955 #endif
956 default:
957 WARN_ON(1);
958 return;
959 }
960 __raw_writel(l, reg);
961 }
962
963 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
964 {
965 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
966 }
967
968 /*
969 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
970 * 1510 does not seem to have a wake-up register. If JTAG is connected
971 * to the target, system will wake up always on GPIO events. While
972 * system is running all registered GPIO interrupts need to have wake-up
973 * enabled. When system is suspended, only selected GPIO interrupts need
974 * to have wake-up enabled.
975 */
976 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
977 {
978 unsigned long uninitialized_var(flags);
979
980 switch (bank->method) {
981 #ifdef CONFIG_ARCH_OMAP16XX
982 case METHOD_MPUIO:
983 case METHOD_GPIO_1610:
984 spin_lock_irqsave(&bank->lock, flags);
985 if (enable)
986 bank->suspend_wakeup |= (1 << gpio);
987 else
988 bank->suspend_wakeup &= ~(1 << gpio);
989 spin_unlock_irqrestore(&bank->lock, flags);
990 return 0;
991 #endif
992 #ifdef CONFIG_ARCH_OMAP2PLUS
993 case METHOD_GPIO_24XX:
994 case METHOD_GPIO_44XX:
995 if (bank->non_wakeup_gpios & (1 << gpio)) {
996 printk(KERN_ERR "Unable to modify wakeup on "
997 "non-wakeup GPIO%d\n",
998 (bank - gpio_bank) * 32 + gpio);
999 return -EINVAL;
1000 }
1001 spin_lock_irqsave(&bank->lock, flags);
1002 if (enable)
1003 bank->suspend_wakeup |= (1 << gpio);
1004 else
1005 bank->suspend_wakeup &= ~(1 << gpio);
1006 spin_unlock_irqrestore(&bank->lock, flags);
1007 return 0;
1008 #endif
1009 default:
1010 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
1011 bank->method);
1012 return -EINVAL;
1013 }
1014 }
1015
1016 static void _reset_gpio(struct gpio_bank *bank, int gpio)
1017 {
1018 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
1019 _set_gpio_irqenable(bank, gpio, 0);
1020 _clear_gpio_irqstatus(bank, gpio);
1021 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
1022 }
1023
1024 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
1025 static int gpio_wake_enable(unsigned int irq, unsigned int enable)
1026 {
1027 unsigned int gpio = irq - IH_GPIO_BASE;
1028 struct gpio_bank *bank;
1029 int retval;
1030
1031 if (check_gpio(gpio) < 0)
1032 return -ENODEV;
1033 bank = get_irq_chip_data(irq);
1034 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
1035
1036 return retval;
1037 }
1038
1039 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
1040 {
1041 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
1042 unsigned long flags;
1043
1044 spin_lock_irqsave(&bank->lock, flags);
1045
1046 /* Set trigger to none. You need to enable the desired trigger with
1047 * request_irq() or set_irq_type().
1048 */
1049 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
1050
1051 #ifdef CONFIG_ARCH_OMAP15XX
1052 if (bank->method == METHOD_GPIO_1510) {
1053 void __iomem *reg;
1054
1055 /* Claim the pin for MPU */
1056 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
1057 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
1058 }
1059 #endif
1060 if (!cpu_class_is_omap1()) {
1061 if (!bank->mod_usage) {
1062 void __iomem *reg = bank->base;
1063 u32 ctrl;
1064
1065 if (cpu_is_omap24xx() || cpu_is_omap34xx())
1066 reg += OMAP24XX_GPIO_CTRL;
1067 else if (cpu_is_omap44xx())
1068 reg += OMAP4_GPIO_CTRL;
1069 ctrl = __raw_readl(reg);
1070 /* Module is enabled, clocks are not gated */
1071 ctrl &= 0xFFFFFFFE;
1072 __raw_writel(ctrl, reg);
1073 }
1074 bank->mod_usage |= 1 << offset;
1075 }
1076 spin_unlock_irqrestore(&bank->lock, flags);
1077
1078 return 0;
1079 }
1080
1081 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
1082 {
1083 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
1084 unsigned long flags;
1085
1086 spin_lock_irqsave(&bank->lock, flags);
1087 #ifdef CONFIG_ARCH_OMAP16XX
1088 if (bank->method == METHOD_GPIO_1610) {
1089 /* Disable wake-up during idle for dynamic tick */
1090 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1091 __raw_writel(1 << offset, reg);
1092 }
1093 #endif
1094 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1095 if (bank->method == METHOD_GPIO_24XX) {
1096 /* Disable wake-up during idle for dynamic tick */
1097 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1098 __raw_writel(1 << offset, reg);
1099 }
1100 #endif
1101 #ifdef CONFIG_ARCH_OMAP4
1102 if (bank->method == METHOD_GPIO_44XX) {
1103 /* Disable wake-up during idle for dynamic tick */
1104 void __iomem *reg = bank->base + OMAP4_GPIO_IRQWAKEN0;
1105 __raw_writel(1 << offset, reg);
1106 }
1107 #endif
1108 if (!cpu_class_is_omap1()) {
1109 bank->mod_usage &= ~(1 << offset);
1110 if (!bank->mod_usage) {
1111 void __iomem *reg = bank->base;
1112 u32 ctrl;
1113
1114 if (cpu_is_omap24xx() || cpu_is_omap34xx())
1115 reg += OMAP24XX_GPIO_CTRL;
1116 else if (cpu_is_omap44xx())
1117 reg += OMAP4_GPIO_CTRL;
1118 ctrl = __raw_readl(reg);
1119 /* Module is disabled, clocks are gated */
1120 ctrl |= 1;
1121 __raw_writel(ctrl, reg);
1122 }
1123 }
1124 _reset_gpio(bank, bank->chip.base + offset);
1125 spin_unlock_irqrestore(&bank->lock, flags);
1126 }
1127
1128 /*
1129 * We need to unmask the GPIO bank interrupt as soon as possible to
1130 * avoid missing GPIO interrupts for other lines in the bank.
1131 * Then we need to mask-read-clear-unmask the triggered GPIO lines
1132 * in the bank to avoid missing nested interrupts for a GPIO line.
1133 * If we wait to unmask individual GPIO lines in the bank after the
1134 * line's interrupt handler has been run, we may miss some nested
1135 * interrupts.
1136 */
1137 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1138 {
1139 void __iomem *isr_reg = NULL;
1140 u32 isr;
1141 unsigned int gpio_irq, gpio_index;
1142 struct gpio_bank *bank;
1143 u32 retrigger = 0;
1144 int unmasked = 0;
1145
1146 desc->chip->ack(irq);
1147
1148 bank = get_irq_data(irq);
1149 #ifdef CONFIG_ARCH_OMAP1
1150 if (bank->method == METHOD_MPUIO)
1151 isr_reg = bank->base +
1152 OMAP_MPUIO_GPIO_INT / bank->stride;
1153 #endif
1154 #ifdef CONFIG_ARCH_OMAP15XX
1155 if (bank->method == METHOD_GPIO_1510)
1156 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
1157 #endif
1158 #if defined(CONFIG_ARCH_OMAP16XX)
1159 if (bank->method == METHOD_GPIO_1610)
1160 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
1161 #endif
1162 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1163 if (bank->method == METHOD_GPIO_7XX)
1164 isr_reg = bank->base + OMAP7XX_GPIO_INT_STATUS;
1165 #endif
1166 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1167 if (bank->method == METHOD_GPIO_24XX)
1168 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
1169 #endif
1170 #if defined(CONFIG_ARCH_OMAP4)
1171 if (bank->method == METHOD_GPIO_44XX)
1172 isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0;
1173 #endif
1174
1175 if (WARN_ON(!isr_reg))
1176 goto exit;
1177
1178 while(1) {
1179 u32 isr_saved, level_mask = 0;
1180 u32 enabled;
1181
1182 enabled = _get_gpio_irqbank_mask(bank);
1183 isr_saved = isr = __raw_readl(isr_reg) & enabled;
1184
1185 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
1186 isr &= 0x0000ffff;
1187
1188 if (cpu_class_is_omap2()) {
1189 level_mask = bank->level_mask & enabled;
1190 }
1191
1192 /* clear edge sensitive interrupts before handler(s) are
1193 called so that we don't miss any interrupt occurred while
1194 executing them */
1195 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1196 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1197 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1198
1199 /* if there is only edge sensitive GPIO pin interrupts
1200 configured, we could unmask GPIO bank interrupt immediately */
1201 if (!level_mask && !unmasked) {
1202 unmasked = 1;
1203 desc->chip->unmask(irq);
1204 }
1205
1206 isr |= retrigger;
1207 retrigger = 0;
1208 if (!isr)
1209 break;
1210
1211 gpio_irq = bank->virtual_irq_start;
1212 for (; isr != 0; isr >>= 1, gpio_irq++) {
1213 gpio_index = get_gpio_index(irq_to_gpio(gpio_irq));
1214
1215 if (!(isr & 1))
1216 continue;
1217
1218 #ifdef CONFIG_ARCH_OMAP1
1219 /*
1220 * Some chips can't respond to both rising and falling
1221 * at the same time. If this irq was requested with
1222 * both flags, we need to flip the ICR data for the IRQ
1223 * to respond to the IRQ for the opposite direction.
1224 * This will be indicated in the bank toggle_mask.
1225 */
1226 if (bank->toggle_mask & (1 << gpio_index))
1227 _toggle_gpio_edge_triggering(bank, gpio_index);
1228 #endif
1229
1230 generic_handle_irq(gpio_irq);
1231 }
1232 }
1233 /* if bank has any level sensitive GPIO pin interrupt
1234 configured, we must unmask the bank interrupt only after
1235 handler(s) are executed in order to avoid spurious bank
1236 interrupt */
1237 exit:
1238 if (!unmasked)
1239 desc->chip->unmask(irq);
1240
1241 }
1242
1243 static void gpio_irq_shutdown(unsigned int irq)
1244 {
1245 unsigned int gpio = irq - IH_GPIO_BASE;
1246 struct gpio_bank *bank = get_irq_chip_data(irq);
1247
1248 _reset_gpio(bank, gpio);
1249 }
1250
1251 static void gpio_ack_irq(unsigned int irq)
1252 {
1253 unsigned int gpio = irq - IH_GPIO_BASE;
1254 struct gpio_bank *bank = get_irq_chip_data(irq);
1255
1256 _clear_gpio_irqstatus(bank, gpio);
1257 }
1258
1259 static void gpio_mask_irq(unsigned int irq)
1260 {
1261 unsigned int gpio = irq - IH_GPIO_BASE;
1262 struct gpio_bank *bank = get_irq_chip_data(irq);
1263
1264 _set_gpio_irqenable(bank, gpio, 0);
1265 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
1266 }
1267
1268 static void gpio_unmask_irq(unsigned int irq)
1269 {
1270 unsigned int gpio = irq - IH_GPIO_BASE;
1271 struct gpio_bank *bank = get_irq_chip_data(irq);
1272 unsigned int irq_mask = 1 << get_gpio_index(gpio);
1273 struct irq_desc *desc = irq_to_desc(irq);
1274 u32 trigger = desc->status & IRQ_TYPE_SENSE_MASK;
1275
1276 if (trigger)
1277 _set_gpio_triggering(bank, get_gpio_index(gpio), trigger);
1278
1279 /* For level-triggered GPIOs, the clearing must be done after
1280 * the HW source is cleared, thus after the handler has run */
1281 if (bank->level_mask & irq_mask) {
1282 _set_gpio_irqenable(bank, gpio, 0);
1283 _clear_gpio_irqstatus(bank, gpio);
1284 }
1285
1286 _set_gpio_irqenable(bank, gpio, 1);
1287 }
1288
1289 static struct irq_chip gpio_irq_chip = {
1290 .name = "GPIO",
1291 .shutdown = gpio_irq_shutdown,
1292 .ack = gpio_ack_irq,
1293 .mask = gpio_mask_irq,
1294 .unmask = gpio_unmask_irq,
1295 .set_type = gpio_irq_type,
1296 .set_wake = gpio_wake_enable,
1297 };
1298
1299 /*---------------------------------------------------------------------*/
1300
1301 #ifdef CONFIG_ARCH_OMAP1
1302
1303 /* MPUIO uses the always-on 32k clock */
1304
1305 static void mpuio_ack_irq(unsigned int irq)
1306 {
1307 /* The ISR is reset automatically, so do nothing here. */
1308 }
1309
1310 static void mpuio_mask_irq(unsigned int irq)
1311 {
1312 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1313 struct gpio_bank *bank = get_irq_chip_data(irq);
1314
1315 _set_gpio_irqenable(bank, gpio, 0);
1316 }
1317
1318 static void mpuio_unmask_irq(unsigned int irq)
1319 {
1320 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1321 struct gpio_bank *bank = get_irq_chip_data(irq);
1322
1323 _set_gpio_irqenable(bank, gpio, 1);
1324 }
1325
1326 static struct irq_chip mpuio_irq_chip = {
1327 .name = "MPUIO",
1328 .ack = mpuio_ack_irq,
1329 .mask = mpuio_mask_irq,
1330 .unmask = mpuio_unmask_irq,
1331 .set_type = gpio_irq_type,
1332 #ifdef CONFIG_ARCH_OMAP16XX
1333 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1334 .set_wake = gpio_wake_enable,
1335 #endif
1336 };
1337
1338
1339 #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1340
1341
1342 #ifdef CONFIG_ARCH_OMAP16XX
1343
1344 #include <linux/platform_device.h>
1345
1346 static int omap_mpuio_suspend_noirq(struct device *dev)
1347 {
1348 struct platform_device *pdev = to_platform_device(dev);
1349 struct gpio_bank *bank = platform_get_drvdata(pdev);
1350 void __iomem *mask_reg = bank->base +
1351 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
1352 unsigned long flags;
1353
1354 spin_lock_irqsave(&bank->lock, flags);
1355 bank->saved_wakeup = __raw_readl(mask_reg);
1356 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
1357 spin_unlock_irqrestore(&bank->lock, flags);
1358
1359 return 0;
1360 }
1361
1362 static int omap_mpuio_resume_noirq(struct device *dev)
1363 {
1364 struct platform_device *pdev = to_platform_device(dev);
1365 struct gpio_bank *bank = platform_get_drvdata(pdev);
1366 void __iomem *mask_reg = bank->base +
1367 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
1368 unsigned long flags;
1369
1370 spin_lock_irqsave(&bank->lock, flags);
1371 __raw_writel(bank->saved_wakeup, mask_reg);
1372 spin_unlock_irqrestore(&bank->lock, flags);
1373
1374 return 0;
1375 }
1376
1377 static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
1378 .suspend_noirq = omap_mpuio_suspend_noirq,
1379 .resume_noirq = omap_mpuio_resume_noirq,
1380 };
1381
1382 /* use platform_driver for this, now that there's no longer any
1383 * point to sys_device (other than not disturbing old code).
1384 */
1385 static struct platform_driver omap_mpuio_driver = {
1386 .driver = {
1387 .name = "mpuio",
1388 .pm = &omap_mpuio_dev_pm_ops,
1389 },
1390 };
1391
1392 static struct platform_device omap_mpuio_device = {
1393 .name = "mpuio",
1394 .id = -1,
1395 .dev = {
1396 .driver = &omap_mpuio_driver.driver,
1397 }
1398 /* could list the /proc/iomem resources */
1399 };
1400
1401 static inline void mpuio_init(void)
1402 {
1403 struct gpio_bank *bank = get_gpio_bank(OMAP_MPUIO(0));
1404 platform_set_drvdata(&omap_mpuio_device, bank);
1405
1406 if (platform_driver_register(&omap_mpuio_driver) == 0)
1407 (void) platform_device_register(&omap_mpuio_device);
1408 }
1409
1410 #else
1411 static inline void mpuio_init(void) {}
1412 #endif /* 16xx */
1413
1414 #else
1415
1416 extern struct irq_chip mpuio_irq_chip;
1417
1418 #define bank_is_mpuio(bank) 0
1419 static inline void mpuio_init(void) {}
1420
1421 #endif
1422
1423 /*---------------------------------------------------------------------*/
1424
1425 /* REVISIT these are stupid implementations! replace by ones that
1426 * don't switch on METHOD_* and which mostly avoid spinlocks
1427 */
1428
1429 static int gpio_input(struct gpio_chip *chip, unsigned offset)
1430 {
1431 struct gpio_bank *bank;
1432 unsigned long flags;
1433
1434 bank = container_of(chip, struct gpio_bank, chip);
1435 spin_lock_irqsave(&bank->lock, flags);
1436 _set_gpio_direction(bank, offset, 1);
1437 spin_unlock_irqrestore(&bank->lock, flags);
1438 return 0;
1439 }
1440
1441 static int gpio_is_input(struct gpio_bank *bank, int mask)
1442 {
1443 void __iomem *reg = bank->base;
1444
1445 switch (bank->method) {
1446 case METHOD_MPUIO:
1447 reg += OMAP_MPUIO_IO_CNTL / bank->stride;
1448 break;
1449 case METHOD_GPIO_1510:
1450 reg += OMAP1510_GPIO_DIR_CONTROL;
1451 break;
1452 case METHOD_GPIO_1610:
1453 reg += OMAP1610_GPIO_DIRECTION;
1454 break;
1455 case METHOD_GPIO_7XX:
1456 reg += OMAP7XX_GPIO_DIR_CONTROL;
1457 break;
1458 case METHOD_GPIO_24XX:
1459 reg += OMAP24XX_GPIO_OE;
1460 break;
1461 case METHOD_GPIO_44XX:
1462 reg += OMAP4_GPIO_OE;
1463 break;
1464 default:
1465 WARN_ONCE(1, "gpio_is_input: incorrect OMAP GPIO method");
1466 return -EINVAL;
1467 }
1468 return __raw_readl(reg) & mask;
1469 }
1470
1471 static int gpio_get(struct gpio_chip *chip, unsigned offset)
1472 {
1473 struct gpio_bank *bank;
1474 void __iomem *reg;
1475 int gpio;
1476 u32 mask;
1477
1478 gpio = chip->base + offset;
1479 bank = get_gpio_bank(gpio);
1480 reg = bank->base;
1481 mask = 1 << get_gpio_index(gpio);
1482
1483 if (gpio_is_input(bank, mask))
1484 return _get_gpio_datain(bank, gpio);
1485 else
1486 return _get_gpio_dataout(bank, gpio);
1487 }
1488
1489 static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1490 {
1491 struct gpio_bank *bank;
1492 unsigned long flags;
1493
1494 bank = container_of(chip, struct gpio_bank, chip);
1495 spin_lock_irqsave(&bank->lock, flags);
1496 _set_gpio_dataout(bank, offset, value);
1497 _set_gpio_direction(bank, offset, 0);
1498 spin_unlock_irqrestore(&bank->lock, flags);
1499 return 0;
1500 }
1501
1502 static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
1503 unsigned debounce)
1504 {
1505 struct gpio_bank *bank;
1506 unsigned long flags;
1507
1508 bank = container_of(chip, struct gpio_bank, chip);
1509
1510 if (!bank->dbck) {
1511 bank->dbck = clk_get(bank->dev, "dbclk");
1512 if (IS_ERR(bank->dbck))
1513 dev_err(bank->dev, "Could not get gpio dbck\n");
1514 }
1515
1516 spin_lock_irqsave(&bank->lock, flags);
1517 _set_gpio_debounce(bank, offset, debounce);
1518 spin_unlock_irqrestore(&bank->lock, flags);
1519
1520 return 0;
1521 }
1522
1523 static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1524 {
1525 struct gpio_bank *bank;
1526 unsigned long flags;
1527
1528 bank = container_of(chip, struct gpio_bank, chip);
1529 spin_lock_irqsave(&bank->lock, flags);
1530 _set_gpio_dataout(bank, offset, value);
1531 spin_unlock_irqrestore(&bank->lock, flags);
1532 }
1533
1534 static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
1535 {
1536 struct gpio_bank *bank;
1537
1538 bank = container_of(chip, struct gpio_bank, chip);
1539 return bank->virtual_irq_start + offset;
1540 }
1541
1542 /*---------------------------------------------------------------------*/
1543
1544 static void __init omap_gpio_show_rev(struct gpio_bank *bank)
1545 {
1546 u32 rev;
1547
1548 if (cpu_is_omap16xx() && !(bank->method != METHOD_MPUIO))
1549 rev = __raw_readw(bank->base + OMAP1610_GPIO_REVISION);
1550 else if (cpu_is_omap24xx() || cpu_is_omap34xx())
1551 rev = __raw_readl(bank->base + OMAP24XX_GPIO_REVISION);
1552 else if (cpu_is_omap44xx())
1553 rev = __raw_readl(bank->base + OMAP4_GPIO_REVISION);
1554 else
1555 return;
1556
1557 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1558 (rev >> 4) & 0x0f, rev & 0x0f);
1559 }
1560
1561 /* This lock class tells lockdep that GPIO irqs are in a different
1562 * category than their parents, so it won't report false recursion.
1563 */
1564 static struct lock_class_key gpio_lock_class;
1565
1566 static inline int init_gpio_info(struct platform_device *pdev)
1567 {
1568 /* TODO: Analyze removing gpio_bank_count usage from driver code */
1569 gpio_bank = kzalloc(gpio_bank_count * sizeof(struct gpio_bank),
1570 GFP_KERNEL);
1571 if (!gpio_bank) {
1572 dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n");
1573 return -ENOMEM;
1574 }
1575 return 0;
1576 }
1577
1578 /* TODO: Cleanup cpu_is_* checks */
1579 static void omap_gpio_mod_init(struct gpio_bank *bank, int id)
1580 {
1581 if (cpu_class_is_omap2()) {
1582 if (cpu_is_omap44xx()) {
1583 __raw_writel(0xffffffff, bank->base +
1584 OMAP4_GPIO_IRQSTATUSCLR0);
1585 __raw_writel(0x00000000, bank->base +
1586 OMAP4_GPIO_DEBOUNCENABLE);
1587 /* Initialize interface clk ungated, module enabled */
1588 __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
1589 } else if (cpu_is_omap34xx()) {
1590 __raw_writel(0x00000000, bank->base +
1591 OMAP24XX_GPIO_IRQENABLE1);
1592 __raw_writel(0xffffffff, bank->base +
1593 OMAP24XX_GPIO_IRQSTATUS1);
1594 __raw_writel(0x00000000, bank->base +
1595 OMAP24XX_GPIO_DEBOUNCE_EN);
1596
1597 /* Initialize interface clk ungated, module enabled */
1598 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1599 } else if (cpu_is_omap24xx()) {
1600 static const u32 non_wakeup_gpios[] = {
1601 0xe203ffc0, 0x08700040
1602 };
1603 if (id < ARRAY_SIZE(non_wakeup_gpios))
1604 bank->non_wakeup_gpios = non_wakeup_gpios[id];
1605 }
1606 } else if (cpu_class_is_omap1()) {
1607 if (bank_is_mpuio(bank))
1608 __raw_writew(0xffff, bank->base +
1609 OMAP_MPUIO_GPIO_MASKIT / bank->stride);
1610 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1611 __raw_writew(0xffff, bank->base
1612 + OMAP1510_GPIO_INT_MASK);
1613 __raw_writew(0x0000, bank->base
1614 + OMAP1510_GPIO_INT_STATUS);
1615 }
1616 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1617 __raw_writew(0x0000, bank->base
1618 + OMAP1610_GPIO_IRQENABLE1);
1619 __raw_writew(0xffff, bank->base
1620 + OMAP1610_GPIO_IRQSTATUS1);
1621 __raw_writew(0x0014, bank->base
1622 + OMAP1610_GPIO_SYSCONFIG);
1623
1624 /*
1625 * Enable system clock for GPIO module.
1626 * The CAM_CLK_CTRL *is* really the right place.
1627 */
1628 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
1629 ULPD_CAM_CLK_CTRL);
1630 }
1631 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
1632 __raw_writel(0xffffffff, bank->base
1633 + OMAP7XX_GPIO_INT_MASK);
1634 __raw_writel(0x00000000, bank->base
1635 + OMAP7XX_GPIO_INT_STATUS);
1636 }
1637 }
1638 }
1639
1640 static void __init omap_gpio_chip_init(struct gpio_bank *bank)
1641 {
1642 int j;
1643 static int gpio;
1644
1645 bank->mod_usage = 0;
1646 /*
1647 * REVISIT eventually switch from OMAP-specific gpio structs
1648 * over to the generic ones
1649 */
1650 bank->chip.request = omap_gpio_request;
1651 bank->chip.free = omap_gpio_free;
1652 bank->chip.direction_input = gpio_input;
1653 bank->chip.get = gpio_get;
1654 bank->chip.direction_output = gpio_output;
1655 bank->chip.set_debounce = gpio_debounce;
1656 bank->chip.set = gpio_set;
1657 bank->chip.to_irq = gpio_2irq;
1658 if (bank_is_mpuio(bank)) {
1659 bank->chip.label = "mpuio";
1660 #ifdef CONFIG_ARCH_OMAP16XX
1661 bank->chip.dev = &omap_mpuio_device.dev;
1662 #endif
1663 bank->chip.base = OMAP_MPUIO(0);
1664 } else {
1665 bank->chip.label = "gpio";
1666 bank->chip.base = gpio;
1667 gpio += bank_width;
1668 }
1669 bank->chip.ngpio = bank_width;
1670
1671 gpiochip_add(&bank->chip);
1672
1673 for (j = bank->virtual_irq_start;
1674 j < bank->virtual_irq_start + bank_width; j++) {
1675 lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class);
1676 set_irq_chip_data(j, bank);
1677 if (bank_is_mpuio(bank))
1678 set_irq_chip(j, &mpuio_irq_chip);
1679 else
1680 set_irq_chip(j, &gpio_irq_chip);
1681 set_irq_handler(j, handle_simple_irq);
1682 set_irq_flags(j, IRQF_VALID);
1683 }
1684 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1685 set_irq_data(bank->irq, bank);
1686 }
1687
1688 static int __devinit omap_gpio_probe(struct platform_device *pdev)
1689 {
1690 static int gpio_init_done;
1691 struct omap_gpio_platform_data *pdata;
1692 struct resource *res;
1693 int id;
1694 struct gpio_bank *bank;
1695
1696 if (!pdev->dev.platform_data)
1697 return -EINVAL;
1698
1699 pdata = pdev->dev.platform_data;
1700
1701 if (!gpio_init_done) {
1702 int ret;
1703
1704 ret = init_gpio_info(pdev);
1705 if (ret)
1706 return ret;
1707 }
1708
1709 id = pdev->id;
1710 bank = &gpio_bank[id];
1711
1712 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1713 if (unlikely(!res)) {
1714 dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n", id);
1715 return -ENODEV;
1716 }
1717
1718 bank->irq = res->start;
1719 bank->virtual_irq_start = pdata->virtual_irq_start;
1720 bank->method = pdata->bank_type;
1721 bank->dev = &pdev->dev;
1722 bank->dbck_flag = pdata->dbck_flag;
1723 bank->stride = pdata->bank_stride;
1724 bank_width = pdata->bank_width;
1725
1726 spin_lock_init(&bank->lock);
1727
1728 /* Static mapping, never released */
1729 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1730 if (unlikely(!res)) {
1731 dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n", id);
1732 return -ENODEV;
1733 }
1734
1735 bank->base = ioremap(res->start, resource_size(res));
1736 if (!bank->base) {
1737 dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n", id);
1738 return -ENOMEM;
1739 }
1740
1741 pm_runtime_enable(bank->dev);
1742 pm_runtime_get_sync(bank->dev);
1743
1744 omap_gpio_mod_init(bank, id);
1745 omap_gpio_chip_init(bank);
1746 omap_gpio_show_rev(bank);
1747
1748 if (!gpio_init_done)
1749 gpio_init_done = 1;
1750
1751 return 0;
1752 }
1753
1754 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
1755 static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1756 {
1757 int i;
1758
1759 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1760 return 0;
1761
1762 for (i = 0; i < gpio_bank_count; i++) {
1763 struct gpio_bank *bank = &gpio_bank[i];
1764 void __iomem *wake_status;
1765 void __iomem *wake_clear;
1766 void __iomem *wake_set;
1767 unsigned long flags;
1768
1769 switch (bank->method) {
1770 #ifdef CONFIG_ARCH_OMAP16XX
1771 case METHOD_GPIO_1610:
1772 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1773 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1774 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1775 break;
1776 #endif
1777 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1778 case METHOD_GPIO_24XX:
1779 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
1780 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1781 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1782 break;
1783 #endif
1784 #ifdef CONFIG_ARCH_OMAP4
1785 case METHOD_GPIO_44XX:
1786 wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
1787 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1788 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1789 break;
1790 #endif
1791 default:
1792 continue;
1793 }
1794
1795 spin_lock_irqsave(&bank->lock, flags);
1796 bank->saved_wakeup = __raw_readl(wake_status);
1797 __raw_writel(0xffffffff, wake_clear);
1798 __raw_writel(bank->suspend_wakeup, wake_set);
1799 spin_unlock_irqrestore(&bank->lock, flags);
1800 }
1801
1802 return 0;
1803 }
1804
1805 static int omap_gpio_resume(struct sys_device *dev)
1806 {
1807 int i;
1808
1809 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1810 return 0;
1811
1812 for (i = 0; i < gpio_bank_count; i++) {
1813 struct gpio_bank *bank = &gpio_bank[i];
1814 void __iomem *wake_clear;
1815 void __iomem *wake_set;
1816 unsigned long flags;
1817
1818 switch (bank->method) {
1819 #ifdef CONFIG_ARCH_OMAP16XX
1820 case METHOD_GPIO_1610:
1821 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1822 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1823 break;
1824 #endif
1825 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1826 case METHOD_GPIO_24XX:
1827 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1828 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1829 break;
1830 #endif
1831 #ifdef CONFIG_ARCH_OMAP4
1832 case METHOD_GPIO_44XX:
1833 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1834 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1835 break;
1836 #endif
1837 default:
1838 continue;
1839 }
1840
1841 spin_lock_irqsave(&bank->lock, flags);
1842 __raw_writel(0xffffffff, wake_clear);
1843 __raw_writel(bank->saved_wakeup, wake_set);
1844 spin_unlock_irqrestore(&bank->lock, flags);
1845 }
1846
1847 return 0;
1848 }
1849
1850 static struct sysdev_class omap_gpio_sysclass = {
1851 .name = "gpio",
1852 .suspend = omap_gpio_suspend,
1853 .resume = omap_gpio_resume,
1854 };
1855
1856 static struct sys_device omap_gpio_device = {
1857 .id = 0,
1858 .cls = &omap_gpio_sysclass,
1859 };
1860
1861 #endif
1862
1863 #ifdef CONFIG_ARCH_OMAP2PLUS
1864
1865 static int workaround_enabled;
1866
1867 void omap2_gpio_prepare_for_idle(int power_state)
1868 {
1869 int i, c = 0;
1870 int min = 0;
1871
1872 if (cpu_is_omap34xx())
1873 min = 1;
1874
1875 for (i = min; i < gpio_bank_count; i++) {
1876 struct gpio_bank *bank = &gpio_bank[i];
1877 u32 l1 = 0, l2 = 0;
1878 int j;
1879
1880 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
1881 clk_disable(bank->dbck);
1882
1883 if (power_state > PWRDM_POWER_OFF)
1884 continue;
1885
1886 /* If going to OFF, remove triggering for all
1887 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1888 * generated. See OMAP2420 Errata item 1.101. */
1889 if (!(bank->enabled_non_wakeup_gpios))
1890 continue;
1891
1892 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1893 bank->saved_datain = __raw_readl(bank->base +
1894 OMAP24XX_GPIO_DATAIN);
1895 l1 = __raw_readl(bank->base +
1896 OMAP24XX_GPIO_FALLINGDETECT);
1897 l2 = __raw_readl(bank->base +
1898 OMAP24XX_GPIO_RISINGDETECT);
1899 }
1900
1901 if (cpu_is_omap44xx()) {
1902 bank->saved_datain = __raw_readl(bank->base +
1903 OMAP4_GPIO_DATAIN);
1904 l1 = __raw_readl(bank->base +
1905 OMAP4_GPIO_FALLINGDETECT);
1906 l2 = __raw_readl(bank->base +
1907 OMAP4_GPIO_RISINGDETECT);
1908 }
1909
1910 bank->saved_fallingdetect = l1;
1911 bank->saved_risingdetect = l2;
1912 l1 &= ~bank->enabled_non_wakeup_gpios;
1913 l2 &= ~bank->enabled_non_wakeup_gpios;
1914
1915 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1916 __raw_writel(l1, bank->base +
1917 OMAP24XX_GPIO_FALLINGDETECT);
1918 __raw_writel(l2, bank->base +
1919 OMAP24XX_GPIO_RISINGDETECT);
1920 }
1921
1922 if (cpu_is_omap44xx()) {
1923 __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
1924 __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
1925 }
1926
1927 c++;
1928 }
1929 if (!c) {
1930 workaround_enabled = 0;
1931 return;
1932 }
1933 workaround_enabled = 1;
1934 }
1935
1936 void omap2_gpio_resume_after_idle(void)
1937 {
1938 int i;
1939 int min = 0;
1940
1941 if (cpu_is_omap34xx())
1942 min = 1;
1943 for (i = min; i < gpio_bank_count; i++) {
1944 struct gpio_bank *bank = &gpio_bank[i];
1945 u32 l = 0, gen, gen0, gen1;
1946 int j;
1947
1948 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
1949 clk_enable(bank->dbck);
1950
1951 if (!workaround_enabled)
1952 continue;
1953
1954 if (!(bank->enabled_non_wakeup_gpios))
1955 continue;
1956
1957 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1958 __raw_writel(bank->saved_fallingdetect,
1959 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1960 __raw_writel(bank->saved_risingdetect,
1961 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1962 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1963 }
1964
1965 if (cpu_is_omap44xx()) {
1966 __raw_writel(bank->saved_fallingdetect,
1967 bank->base + OMAP4_GPIO_FALLINGDETECT);
1968 __raw_writel(bank->saved_risingdetect,
1969 bank->base + OMAP4_GPIO_RISINGDETECT);
1970 l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
1971 }
1972
1973 /* Check if any of the non-wakeup interrupt GPIOs have changed
1974 * state. If so, generate an IRQ by software. This is
1975 * horribly racy, but it's the best we can do to work around
1976 * this silicon bug. */
1977 l ^= bank->saved_datain;
1978 l &= bank->enabled_non_wakeup_gpios;
1979
1980 /*
1981 * No need to generate IRQs for the rising edge for gpio IRQs
1982 * configured with falling edge only; and vice versa.
1983 */
1984 gen0 = l & bank->saved_fallingdetect;
1985 gen0 &= bank->saved_datain;
1986
1987 gen1 = l & bank->saved_risingdetect;
1988 gen1 &= ~(bank->saved_datain);
1989
1990 /* FIXME: Consider GPIO IRQs with level detections properly! */
1991 gen = l & (~(bank->saved_fallingdetect) &
1992 ~(bank->saved_risingdetect));
1993 /* Consider all GPIO IRQs needed to be updated */
1994 gen |= gen0 | gen1;
1995
1996 if (gen) {
1997 u32 old0, old1;
1998
1999 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
2000 old0 = __raw_readl(bank->base +
2001 OMAP24XX_GPIO_LEVELDETECT0);
2002 old1 = __raw_readl(bank->base +
2003 OMAP24XX_GPIO_LEVELDETECT1);
2004 __raw_writel(old0 | gen, bank->base +
2005 OMAP24XX_GPIO_LEVELDETECT0);
2006 __raw_writel(old1 | gen, bank->base +
2007 OMAP24XX_GPIO_LEVELDETECT1);
2008 __raw_writel(old0, bank->base +
2009 OMAP24XX_GPIO_LEVELDETECT0);
2010 __raw_writel(old1, bank->base +
2011 OMAP24XX_GPIO_LEVELDETECT1);
2012 }
2013
2014 if (cpu_is_omap44xx()) {
2015 old0 = __raw_readl(bank->base +
2016 OMAP4_GPIO_LEVELDETECT0);
2017 old1 = __raw_readl(bank->base +
2018 OMAP4_GPIO_LEVELDETECT1);
2019 __raw_writel(old0 | l, bank->base +
2020 OMAP4_GPIO_LEVELDETECT0);
2021 __raw_writel(old1 | l, bank->base +
2022 OMAP4_GPIO_LEVELDETECT1);
2023 __raw_writel(old0, bank->base +
2024 OMAP4_GPIO_LEVELDETECT0);
2025 __raw_writel(old1, bank->base +
2026 OMAP4_GPIO_LEVELDETECT1);
2027 }
2028 }
2029 }
2030
2031 }
2032
2033 #endif
2034
2035 #ifdef CONFIG_ARCH_OMAP3
2036 /* save the registers of bank 2-6 */
2037 void omap_gpio_save_context(void)
2038 {
2039 int i;
2040
2041 /* saving banks from 2-6 only since GPIO1 is in WKUP */
2042 for (i = 1; i < gpio_bank_count; i++) {
2043 struct gpio_bank *bank = &gpio_bank[i];
2044 gpio_context[i].irqenable1 =
2045 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
2046 gpio_context[i].irqenable2 =
2047 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
2048 gpio_context[i].wake_en =
2049 __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
2050 gpio_context[i].ctrl =
2051 __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
2052 gpio_context[i].oe =
2053 __raw_readl(bank->base + OMAP24XX_GPIO_OE);
2054 gpio_context[i].leveldetect0 =
2055 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2056 gpio_context[i].leveldetect1 =
2057 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
2058 gpio_context[i].risingdetect =
2059 __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
2060 gpio_context[i].fallingdetect =
2061 __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2062 gpio_context[i].dataout =
2063 __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
2064 }
2065 }
2066
2067 /* restore the required registers of bank 2-6 */
2068 void omap_gpio_restore_context(void)
2069 {
2070 int i;
2071
2072 for (i = 1; i < gpio_bank_count; i++) {
2073 struct gpio_bank *bank = &gpio_bank[i];
2074 __raw_writel(gpio_context[i].irqenable1,
2075 bank->base + OMAP24XX_GPIO_IRQENABLE1);
2076 __raw_writel(gpio_context[i].irqenable2,
2077 bank->base + OMAP24XX_GPIO_IRQENABLE2);
2078 __raw_writel(gpio_context[i].wake_en,
2079 bank->base + OMAP24XX_GPIO_WAKE_EN);
2080 __raw_writel(gpio_context[i].ctrl,
2081 bank->base + OMAP24XX_GPIO_CTRL);
2082 __raw_writel(gpio_context[i].oe,
2083 bank->base + OMAP24XX_GPIO_OE);
2084 __raw_writel(gpio_context[i].leveldetect0,
2085 bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2086 __raw_writel(gpio_context[i].leveldetect1,
2087 bank->base + OMAP24XX_GPIO_LEVELDETECT1);
2088 __raw_writel(gpio_context[i].risingdetect,
2089 bank->base + OMAP24XX_GPIO_RISINGDETECT);
2090 __raw_writel(gpio_context[i].fallingdetect,
2091 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2092 __raw_writel(gpio_context[i].dataout,
2093 bank->base + OMAP24XX_GPIO_DATAOUT);
2094 }
2095 }
2096 #endif
2097
2098 static struct platform_driver omap_gpio_driver = {
2099 .probe = omap_gpio_probe,
2100 .driver = {
2101 .name = "omap_gpio",
2102 },
2103 };
2104
2105 /*
2106 * gpio driver register needs to be done before
2107 * machine_init functions access gpio APIs.
2108 * Hence omap_gpio_drv_reg() is a postcore_initcall.
2109 */
2110 static int __init omap_gpio_drv_reg(void)
2111 {
2112 return platform_driver_register(&omap_gpio_driver);
2113 }
2114 postcore_initcall(omap_gpio_drv_reg);
2115
2116 static int __init omap_gpio_sysinit(void)
2117 {
2118 int ret = 0;
2119
2120 mpuio_init();
2121
2122 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
2123 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
2124 if (ret == 0) {
2125 ret = sysdev_class_register(&omap_gpio_sysclass);
2126 if (ret == 0)
2127 ret = sysdev_register(&omap_gpio_device);
2128 }
2129 }
2130 #endif
2131
2132 return ret;
2133 }
2134
2135 arch_initcall(omap_gpio_sysinit);
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