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[PATCH] pciehp_hpc build fix
[linux-2.6.git] / drivers / pci / hotplug / pciehp_hpc.c
blob2387e75da0feee0ab93e4491fc3b1ee0ad0d0f62
1 /*
2 * PCI Express PCI Hot Plug Driver
3 *
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
8 *
9 * All rights reserved.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
20 * details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
27 *
28 */
29
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/types.h>
33 #include <linux/pci.h>
34 #include <linux/interrupt.h>
35
36 #include "../pci.h"
37 #include "pciehp.h"
38
39 #ifdef DEBUG
40 #define DBG_K_TRACE_ENTRY ((unsigned int)0x00000001) /* On function entry */
41 #define DBG_K_TRACE_EXIT ((unsigned int)0x00000002) /* On function exit */
42 #define DBG_K_INFO ((unsigned int)0x00000004) /* Info messages */
43 #define DBG_K_ERROR ((unsigned int)0x00000008) /* Error messages */
44 #define DBG_K_TRACE (DBG_K_TRACE_ENTRY|DBG_K_TRACE_EXIT)
45 #define DBG_K_STANDARD (DBG_K_INFO|DBG_K_ERROR|DBG_K_TRACE)
46 /* Redefine this flagword to set debug level */
47 #define DEBUG_LEVEL DBG_K_STANDARD
48
49 #define DEFINE_DBG_BUFFER char __dbg_str_buf[256];
50
51 #define DBG_PRINT( dbg_flags, args... ) \
52 do { \
53 if ( DEBUG_LEVEL & ( dbg_flags ) ) \
54 { \
55 int len; \
56 len = sprintf( __dbg_str_buf, "%s:%d: %s: ", \
57 __FILE__, __LINE__, __FUNCTION__ ); \
58 sprintf( __dbg_str_buf + len, args ); \
59 printk( KERN_NOTICE "%s\n", __dbg_str_buf ); \
60 } \
61 } while (0)
62
63 #define DBG_ENTER_ROUTINE DBG_PRINT (DBG_K_TRACE_ENTRY, "%s", "[Entry]");
64 #define DBG_LEAVE_ROUTINE DBG_PRINT (DBG_K_TRACE_EXIT, "%s", "[Exit]");
65 #else
66 #define DEFINE_DBG_BUFFER
67 #define DBG_ENTER_ROUTINE
68 #define DBG_LEAVE_ROUTINE
69 #endif /* DEBUG */
70
71 struct ctrl_reg {
72 u8 cap_id;
73 u8 nxt_ptr;
74 u16 cap_reg;
75 u32 dev_cap;
76 u16 dev_ctrl;
77 u16 dev_status;
78 u32 lnk_cap;
79 u16 lnk_ctrl;
80 u16 lnk_status;
81 u32 slot_cap;
82 u16 slot_ctrl;
83 u16 slot_status;
84 u16 root_ctrl;
85 u16 rsvp;
86 u32 root_status;
87 } __attribute__ ((packed));
88
89 /* offsets to the controller registers based on the above structure layout */
90 enum ctrl_offsets {
91 PCIECAPID = offsetof(struct ctrl_reg, cap_id),
92 NXTCAPPTR = offsetof(struct ctrl_reg, nxt_ptr),
93 CAPREG = offsetof(struct ctrl_reg, cap_reg),
94 DEVCAP = offsetof(struct ctrl_reg, dev_cap),
95 DEVCTRL = offsetof(struct ctrl_reg, dev_ctrl),
96 DEVSTATUS = offsetof(struct ctrl_reg, dev_status),
97 LNKCAP = offsetof(struct ctrl_reg, lnk_cap),
98 LNKCTRL = offsetof(struct ctrl_reg, lnk_ctrl),
99 LNKSTATUS = offsetof(struct ctrl_reg, lnk_status),
100 SLOTCAP = offsetof(struct ctrl_reg, slot_cap),
101 SLOTCTRL = offsetof(struct ctrl_reg, slot_ctrl),
102 SLOTSTATUS = offsetof(struct ctrl_reg, slot_status),
103 ROOTCTRL = offsetof(struct ctrl_reg, root_ctrl),
104 ROOTSTATUS = offsetof(struct ctrl_reg, root_status),
105 };
106 static int pcie_cap_base = 0; /* Base of the PCI Express capability item structure */
107
108 #define PCIE_CAP_ID(cb) ( cb + PCIECAPID )
109 #define NXT_CAP_PTR(cb) ( cb + NXTCAPPTR )
110 #define CAP_REG(cb) ( cb + CAPREG )
111 #define DEV_CAP(cb) ( cb + DEVCAP )
112 #define DEV_CTRL(cb) ( cb + DEVCTRL )
113 #define DEV_STATUS(cb) ( cb + DEVSTATUS )
114 #define LNK_CAP(cb) ( cb + LNKCAP )
115 #define LNK_CTRL(cb) ( cb + LNKCTRL )
116 #define LNK_STATUS(cb) ( cb + LNKSTATUS )
117 #define SLOT_CAP(cb) ( cb + SLOTCAP )
118 #define SLOT_CTRL(cb) ( cb + SLOTCTRL )
119 #define SLOT_STATUS(cb) ( cb + SLOTSTATUS )
120 #define ROOT_CTRL(cb) ( cb + ROOTCTRL )
121 #define ROOT_STATUS(cb) ( cb + ROOTSTATUS )
122
123 #define hp_register_read_word(pdev, reg , value) \
124 pci_read_config_word(pdev, reg, &value)
125
126 #define hp_register_read_dword(pdev, reg , value) \
127 pci_read_config_dword(pdev, reg, &value)
128
129 #define hp_register_write_word(pdev, reg , value) \
130 pci_write_config_word(pdev, reg, value)
131
132 #define hp_register_dwrite_word(pdev, reg , value) \
133 pci_write_config_dword(pdev, reg, value)
134
135 /* Field definitions in PCI Express Capabilities Register */
136 #define CAP_VER 0x000F
137 #define DEV_PORT_TYPE 0x00F0
138 #define SLOT_IMPL 0x0100
139 #define MSG_NUM 0x3E00
140
141 /* Device or Port Type */
142 #define NAT_ENDPT 0x00
143 #define LEG_ENDPT 0x01
144 #define ROOT_PORT 0x04
145 #define UP_STREAM 0x05
146 #define DN_STREAM 0x06
147 #define PCIE_PCI_BRDG 0x07
148 #define PCI_PCIE_BRDG 0x10
149
150 /* Field definitions in Device Capabilities Register */
151 #define DATTN_BUTTN_PRSN 0x1000
152 #define DATTN_LED_PRSN 0x2000
153 #define DPWR_LED_PRSN 0x4000
154
155 /* Field definitions in Link Capabilities Register */
156 #define MAX_LNK_SPEED 0x000F
157 #define MAX_LNK_WIDTH 0x03F0
158
159 /* Link Width Encoding */
160 #define LNK_X1 0x01
161 #define LNK_X2 0x02
162 #define LNK_X4 0x04
163 #define LNK_X8 0x08
164 #define LNK_X12 0x0C
165 #define LNK_X16 0x10
166 #define LNK_X32 0x20
167
168 /*Field definitions of Link Status Register */
169 #define LNK_SPEED 0x000F
170 #define NEG_LINK_WD 0x03F0
171 #define LNK_TRN_ERR 0x0400
172 #define LNK_TRN 0x0800
173 #define SLOT_CLK_CONF 0x1000
174
175 /* Field definitions in Slot Capabilities Register */
176 #define ATTN_BUTTN_PRSN 0x00000001
177 #define PWR_CTRL_PRSN 0x00000002
178 #define MRL_SENS_PRSN 0x00000004
179 #define ATTN_LED_PRSN 0x00000008
180 #define PWR_LED_PRSN 0x00000010
181 #define HP_SUPR_RM_SUP 0x00000020
182 #define HP_CAP 0x00000040
183 #define SLOT_PWR_VALUE 0x000003F8
184 #define SLOT_PWR_LIMIT 0x00000C00
185 #define PSN 0xFFF80000 /* PSN: Physical Slot Number */
186
187 /* Field definitions in Slot Control Register */
188 #define ATTN_BUTTN_ENABLE 0x0001
189 #define PWR_FAULT_DETECT_ENABLE 0x0002
190 #define MRL_DETECT_ENABLE 0x0004
191 #define PRSN_DETECT_ENABLE 0x0008
192 #define CMD_CMPL_INTR_ENABLE 0x0010
193 #define HP_INTR_ENABLE 0x0020
194 #define ATTN_LED_CTRL 0x00C0
195 #define PWR_LED_CTRL 0x0300
196 #define PWR_CTRL 0x0400
197
198 /* Attention indicator and Power indicator states */
199 #define LED_ON 0x01
200 #define LED_BLINK 0x10
201 #define LED_OFF 0x11
202
203 /* Power Control Command */
204 #define POWER_ON 0
205 #define POWER_OFF 0x0400
206
207 /* Field definitions in Slot Status Register */
208 #define ATTN_BUTTN_PRESSED 0x0001
209 #define PWR_FAULT_DETECTED 0x0002
210 #define MRL_SENS_CHANGED 0x0004
211 #define PRSN_DETECT_CHANGED 0x0008
212 #define CMD_COMPLETED 0x0010
213 #define MRL_STATE 0x0020
214 #define PRSN_STATE 0x0040
215
216 static spinlock_t hpc_event_lock;
217
218 DEFINE_DBG_BUFFER /* Debug string buffer for entire HPC defined here */
219 static struct php_ctlr_state_s *php_ctlr_list_head; /* HPC state linked list */
220 static int ctlr_seq_num = 0; /* Controller sequence # */
221 static spinlock_t list_lock;
222
223 static irqreturn_t pcie_isr(int IRQ, void *dev_id, struct pt_regs *regs);
224
225 static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int seconds);
226
227 /* This is the interrupt polling timeout function. */
228 static void int_poll_timeout(unsigned long lphp_ctlr)
229 {
230 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *)lphp_ctlr;
231
232 DBG_ENTER_ROUTINE
233
234 if ( !php_ctlr ) {
235 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
236 return;
237 }
238
239 /* Poll for interrupt events. regs == NULL => polling */
240 pcie_isr( 0, (void *)php_ctlr, NULL );
241
242 init_timer(&php_ctlr->int_poll_timer);
243
244 if (!pciehp_poll_time)
245 pciehp_poll_time = 2; /* reset timer to poll in 2 secs if user doesn't specify at module installation*/
246
247 start_int_poll_timer(php_ctlr, pciehp_poll_time);
248
249 return;
250 }
251
252 /* This function starts the interrupt polling timer. */
253 static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int seconds)
254 {
255 if (!php_ctlr) {
256 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
257 return;
258 }
259
260 if ( ( seconds <= 0 ) || ( seconds > 60 ) )
261 seconds = 2; /* Clamp to sane value */
262
263 php_ctlr->int_poll_timer.function = &int_poll_timeout;
264 php_ctlr->int_poll_timer.data = (unsigned long)php_ctlr; /* Instance data */
265 php_ctlr->int_poll_timer.expires = jiffies + seconds * HZ;
266 add_timer(&php_ctlr->int_poll_timer);
267
268 return;
269 }
270
271 static int pcie_write_cmd(struct slot *slot, u16 cmd)
272 {
273 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
274 int retval = 0;
275 u16 slot_status;
276
277 DBG_ENTER_ROUTINE
278
279 if (!php_ctlr) {
280 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
281 return -1;
282 }
283
284 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(slot->ctrl->cap_base), slot_status);
285 if (retval) {
286 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
287 return retval;
288 }
289
290 if ((slot_status & CMD_COMPLETED) == CMD_COMPLETED ) {
291 /* After 1 sec and CMD_COMPLETED still not set, just proceed forward to issue
292 the next command according to spec. Just print out the error message */
293 dbg("%s : CMD_COMPLETED not clear after 1 sec.\n", __FUNCTION__);
294 }
295
296 retval = hp_register_write_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), cmd | CMD_CMPL_INTR_ENABLE);
297 if (retval) {
298 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__);
299 return retval;
300 }
301
302 DBG_LEAVE_ROUTINE
303 return retval;
304 }
305
306 static int hpc_check_lnk_status(struct controller *ctrl)
307 {
308 struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle;
309 u16 lnk_status;
310 int retval = 0;
311
312 DBG_ENTER_ROUTINE
313
314 if (!php_ctlr) {
315 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
316 return -1;
317 }
318
319 retval = hp_register_read_word(php_ctlr->pci_dev, LNK_STATUS(ctrl->cap_base), lnk_status);
320
321 if (retval) {
322 err("%s : hp_register_read_word LNK_STATUS failed\n", __FUNCTION__);
323 return retval;
324 }
325
326 dbg("%s: lnk_status = %x\n", __FUNCTION__, lnk_status);
327 if ( (lnk_status & LNK_TRN) || (lnk_status & LNK_TRN_ERR) ||
328 !(lnk_status & NEG_LINK_WD)) {
329 err("%s : Link Training Error occurs \n", __FUNCTION__);
330 retval = -1;
331 return retval;
332 }
333
334 DBG_LEAVE_ROUTINE
335 return retval;
336 }
337
338
339 static int hpc_get_attention_status(struct slot *slot, u8 *status)
340 {
341 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
342 u16 slot_ctrl;
343 u8 atten_led_state;
344 int retval = 0;
345
346 DBG_ENTER_ROUTINE
347
348 if (!php_ctlr) {
349 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
350 return -1;
351 }
352
353 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
354
355 if (retval) {
356 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
357 return retval;
358 }
359
360 dbg("%s: SLOT_CTRL %x, value read %x\n", __FUNCTION__,SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
361
362 atten_led_state = (slot_ctrl & ATTN_LED_CTRL) >> 6;
363
364 switch (atten_led_state) {
365 case 0:
366 *status = 0xFF; /* Reserved */
367 break;
368 case 1:
369 *status = 1; /* On */
370 break;
371 case 2:
372 *status = 2; /* Blink */
373 break;
374 case 3:
375 *status = 0; /* Off */
376 break;
377 default:
378 *status = 0xFF;
379 break;
380 }
381
382 DBG_LEAVE_ROUTINE
383 return 0;
384 }
385
386 static int hpc_get_power_status(struct slot * slot, u8 *status)
387 {
388 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
389 u16 slot_ctrl;
390 u8 pwr_state;
391 int retval = 0;
392
393 DBG_ENTER_ROUTINE
394
395 if (!php_ctlr) {
396 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
397 return -1;
398 }
399
400 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
401
402 if (retval) {
403 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
404 return retval;
405 }
406 dbg("%s: SLOT_CTRL %x value read %x\n", __FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
407
408 pwr_state = (slot_ctrl & PWR_CTRL) >> 10;
409
410 switch (pwr_state) {
411 case 0:
412 *status = 1;
413 break;
414 case 1:
415 *status = 0;
416 break;
417 default:
418 *status = 0xFF;
419 break;
420 }
421
422 DBG_LEAVE_ROUTINE
423 return retval;
424 }
425
426
427 static int hpc_get_latch_status(struct slot *slot, u8 *status)
428 {
429 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
430 u16 slot_status;
431 int retval = 0;
432
433 DBG_ENTER_ROUTINE
434
435 if (!php_ctlr) {
436 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
437 return -1;
438 }
439
440 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(slot->ctrl->cap_base), slot_status);
441
442 if (retval) {
443 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
444 return retval;
445 }
446
447 *status = (((slot_status & MRL_STATE) >> 5) == 0) ? 0 : 1;
448
449 DBG_LEAVE_ROUTINE
450 return 0;
451 }
452
453 static int hpc_get_adapter_status(struct slot *slot, u8 *status)
454 {
455 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
456 u16 slot_status;
457 u8 card_state;
458 int retval = 0;
459
460 DBG_ENTER_ROUTINE
461
462 if (!php_ctlr) {
463 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
464 return -1;
465 }
466
467 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(slot->ctrl->cap_base), slot_status);
468
469 if (retval) {
470 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
471 return retval;
472 }
473 card_state = (u8)((slot_status & PRSN_STATE) >> 6);
474 *status = (card_state == 1) ? 1 : 0;
475
476 DBG_LEAVE_ROUTINE
477 return 0;
478 }
479
480 static int hpc_query_power_fault(struct slot * slot)
481 {
482 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
483 u16 slot_status;
484 u8 pwr_fault;
485 int retval = 0;
486
487 DBG_ENTER_ROUTINE
488
489 if (!php_ctlr) {
490 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
491 return -1;
492 }
493
494 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(slot->ctrl->cap_base), slot_status);
495
496 if (retval) {
497 err("%s : Cannot check for power fault\n", __FUNCTION__);
498 return retval;
499 }
500 pwr_fault = (u8)((slot_status & PWR_FAULT_DETECTED) >> 1);
501
502 DBG_LEAVE_ROUTINE
503 return pwr_fault;
504 }
505
506 static int hpc_set_attention_status(struct slot *slot, u8 value)
507 {
508 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
509 u16 slot_cmd = 0;
510 u16 slot_ctrl;
511 int rc = 0;
512
513 DBG_ENTER_ROUTINE
514
515 if (!php_ctlr) {
516 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
517 return -1;
518 }
519
520 if (slot->hp_slot >= php_ctlr->num_slots) {
521 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
522 return -1;
523 }
524 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
525
526 if (rc) {
527 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
528 return rc;
529 }
530
531 switch (value) {
532 case 0 : /* turn off */
533 slot_cmd = (slot_ctrl & ~ATTN_LED_CTRL) | 0x00C0;
534 break;
535 case 1: /* turn on */
536 slot_cmd = (slot_ctrl & ~ATTN_LED_CTRL) | 0x0040;
537 break;
538 case 2: /* turn blink */
539 slot_cmd = (slot_ctrl & ~ATTN_LED_CTRL) | 0x0080;
540 break;
541 default:
542 return -1;
543 }
544 if (!pciehp_poll_mode)
545 slot_cmd = slot_cmd | HP_INTR_ENABLE;
546
547 pcie_write_cmd(slot, slot_cmd);
548 dbg("%s: SLOT_CTRL %x write cmd %x\n", __FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd);
549
550 DBG_LEAVE_ROUTINE
551 return rc;
552 }
553
554
555 static void hpc_set_green_led_on(struct slot *slot)
556 {
557 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
558 u16 slot_cmd;
559 u16 slot_ctrl;
560 int rc = 0;
561
562 DBG_ENTER_ROUTINE
563
564 if (!php_ctlr) {
565 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
566 return ;
567 }
568
569 if (slot->hp_slot >= php_ctlr->num_slots) {
570 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
571 return ;
572 }
573
574 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
575
576 if (rc) {
577 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
578 return;
579 }
580 slot_cmd = (slot_ctrl & ~PWR_LED_CTRL) | 0x0100;
581 if (!pciehp_poll_mode)
582 slot_cmd = slot_cmd | HP_INTR_ENABLE;
583
584 pcie_write_cmd(slot, slot_cmd);
585
586 dbg("%s: SLOT_CTRL %x write cmd %x\n",__FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd);
587 DBG_LEAVE_ROUTINE
588 return;
589 }
590
591 static void hpc_set_green_led_off(struct slot *slot)
592 {
593 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
594 u16 slot_cmd;
595 u16 slot_ctrl;
596 int rc = 0;
597
598 DBG_ENTER_ROUTINE
599
600 if (!php_ctlr) {
601 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
602 return ;
603 }
604
605 if (slot->hp_slot >= php_ctlr->num_slots) {
606 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
607 return ;
608 }
609
610 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
611
612 if (rc) {
613 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
614 return;
615 }
616
617 slot_cmd = (slot_ctrl & ~PWR_LED_CTRL) | 0x0300;
618
619 if (!pciehp_poll_mode)
620 slot_cmd = slot_cmd | HP_INTR_ENABLE;
621 pcie_write_cmd(slot, slot_cmd);
622 dbg("%s: SLOT_CTRL %x write cmd %x\n", __FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd);
623
624 DBG_LEAVE_ROUTINE
625 return;
626 }
627
628 static void hpc_set_green_led_blink(struct slot *slot)
629 {
630 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
631 u16 slot_cmd;
632 u16 slot_ctrl;
633 int rc = 0;
634
635 DBG_ENTER_ROUTINE
636
637 if (!php_ctlr) {
638 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
639 return ;
640 }
641
642 if (slot->hp_slot >= php_ctlr->num_slots) {
643 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
644 return ;
645 }
646
647 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
648
649 if (rc) {
650 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
651 return;
652 }
653
654 slot_cmd = (slot_ctrl & ~PWR_LED_CTRL) | 0x0200;
655
656 if (!pciehp_poll_mode)
657 slot_cmd = slot_cmd | HP_INTR_ENABLE;
658 pcie_write_cmd(slot, slot_cmd);
659
660 dbg("%s: SLOT_CTRL %x write cmd %x\n",__FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd);
661 DBG_LEAVE_ROUTINE
662 return;
663 }
664
665 int pcie_get_ctlr_slot_config(struct controller *ctrl,
666 int *num_ctlr_slots, /* number of slots in this HPC; only 1 in PCIE */
667 int *first_device_num, /* PCI dev num of the first slot in this PCIE */
668 int *physical_slot_num, /* phy slot num of the first slot in this PCIE */
669 u8 *ctrlcap)
670 {
671 struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle;
672 u32 slot_cap;
673 int rc = 0;
674
675 DBG_ENTER_ROUTINE
676
677 if (!php_ctlr) {
678 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
679 return -1;
680 }
681
682 *first_device_num = 0;
683 *num_ctlr_slots = 1;
684
685 rc = hp_register_read_dword(php_ctlr->pci_dev, SLOT_CAP(ctrl->cap_base), slot_cap);
686
687 if (rc) {
688 err("%s : hp_register_read_dword SLOT_CAP failed\n", __FUNCTION__);
689 return -1;
690 }
691
692 *physical_slot_num = slot_cap >> 19;
693 dbg("%s: PSN %d \n", __FUNCTION__, *physical_slot_num);
694
695 *ctrlcap = slot_cap & 0x0000007f;
696
697 DBG_LEAVE_ROUTINE
698 return 0;
699 }
700
701 static void hpc_release_ctlr(struct controller *ctrl)
702 {
703 struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle;
704 struct php_ctlr_state_s *p, *p_prev;
705
706 DBG_ENTER_ROUTINE
707
708 if (!php_ctlr) {
709 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
710 return ;
711 }
712
713 if (pciehp_poll_mode) {
714 del_timer(&php_ctlr->int_poll_timer);
715 } else {
716 if (php_ctlr->irq) {
717 free_irq(php_ctlr->irq, ctrl);
718 php_ctlr->irq = 0;
719 if (!pcie_mch_quirk)
720 pci_disable_msi(php_ctlr->pci_dev);
721 }
722 }
723 if (php_ctlr->pci_dev)
724 php_ctlr->pci_dev = NULL;
725
726 spin_lock(&list_lock);
727 p = php_ctlr_list_head;
728 p_prev = NULL;
729 while (p) {
730 if (p == php_ctlr) {
731 if (p_prev)
732 p_prev->pnext = p->pnext;
733 else
734 php_ctlr_list_head = p->pnext;
735 break;
736 } else {
737 p_prev = p;
738 p = p->pnext;
739 }
740 }
741 spin_unlock(&list_lock);
742
743 kfree(php_ctlr);
744
745 DBG_LEAVE_ROUTINE
746
747 }
748
749 static int hpc_power_on_slot(struct slot * slot)
750 {
751 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
752 u16 slot_cmd;
753 u16 slot_ctrl;
754
755 int retval = 0;
756
757 DBG_ENTER_ROUTINE
758
759 if (!php_ctlr) {
760 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
761 return -1;
762 }
763
764 dbg("%s: slot->hp_slot %x\n", __FUNCTION__, slot->hp_slot);
765 if (slot->hp_slot >= php_ctlr->num_slots) {
766 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
767 return -1;
768 }
769
770 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
771
772 if (retval) {
773 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
774 return retval;
775 }
776
777 slot_cmd = (slot_ctrl & ~PWR_CTRL) | POWER_ON;
778
779 if (!pciehp_poll_mode)
780 slot_cmd = slot_cmd | HP_INTR_ENABLE;
781
782 retval = pcie_write_cmd(slot, slot_cmd);
783
784 if (retval) {
785 err("%s: Write %x command failed!\n", __FUNCTION__, slot_cmd);
786 return -1;
787 }
788 dbg("%s: SLOT_CTRL %x write cmd %x\n",__FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd);
789
790 DBG_LEAVE_ROUTINE
791
792 return retval;
793 }
794
795 static int hpc_power_off_slot(struct slot * slot)
796 {
797 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
798 u16 slot_cmd;
799 u16 slot_ctrl;
800
801 int retval = 0;
802
803 DBG_ENTER_ROUTINE
804
805 if (!php_ctlr) {
806 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
807 return -1;
808 }
809
810 dbg("%s: slot->hp_slot %x\n", __FUNCTION__, slot->hp_slot);
811 slot->hp_slot = 0;
812 if (slot->hp_slot >= php_ctlr->num_slots) {
813 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
814 return -1;
815 }
816 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
817
818 if (retval) {
819 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
820 return retval;
821 }
822
823 slot_cmd = (slot_ctrl & ~PWR_CTRL) | POWER_OFF;
824
825 if (!pciehp_poll_mode)
826 slot_cmd = slot_cmd | HP_INTR_ENABLE;
827
828 retval = pcie_write_cmd(slot, slot_cmd);
829
830 if (retval) {
831 err("%s: Write command failed!\n", __FUNCTION__);
832 return -1;
833 }
834 dbg("%s: SLOT_CTRL %x write cmd %x\n",__FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd);
835
836 DBG_LEAVE_ROUTINE
837
838 return retval;
839 }
840
841 static irqreturn_t pcie_isr(int IRQ, void *dev_id, struct pt_regs *regs)
842 {
843 struct controller *ctrl = NULL;
844 struct php_ctlr_state_s *php_ctlr;
845 u8 schedule_flag = 0;
846 u16 slot_status, intr_detect, intr_loc;
847 u16 temp_word;
848 int hp_slot = 0; /* only 1 slot per PCI Express port */
849 int rc = 0;
850
851 if (!dev_id)
852 return IRQ_NONE;
853
854 if (!pciehp_poll_mode) {
855 ctrl = dev_id;
856 php_ctlr = ctrl->hpc_ctlr_handle;
857 } else {
858 php_ctlr = dev_id;
859 ctrl = (struct controller *)php_ctlr->callback_instance_id;
860 }
861
862 if (!ctrl) {
863 dbg("%s: dev_id %p ctlr == NULL\n", __FUNCTION__, (void*) dev_id);
864 return IRQ_NONE;
865 }
866
867 if (!php_ctlr) {
868 dbg("%s: php_ctlr == NULL\n", __FUNCTION__);
869 return IRQ_NONE;
870 }
871
872 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status);
873 if (rc) {
874 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
875 return IRQ_NONE;
876 }
877
878 intr_detect = ( ATTN_BUTTN_PRESSED | PWR_FAULT_DETECTED | MRL_SENS_CHANGED |
879 PRSN_DETECT_CHANGED | CMD_COMPLETED );
880
881 intr_loc = slot_status & intr_detect;
882
883 /* Check to see if it was our interrupt */
884 if ( !intr_loc )
885 return IRQ_NONE;
886
887 dbg("%s: intr_loc %x\n", __FUNCTION__, intr_loc);
888 /* Mask Hot-plug Interrupt Enable */
889 if (!pciehp_poll_mode) {
890 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(ctrl->cap_base), temp_word);
891 if (rc) {
892 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
893 return IRQ_NONE;
894 }
895
896 dbg("%s: hp_register_read_word SLOT_CTRL with value %x\n", __FUNCTION__, temp_word);
897 temp_word = (temp_word & ~HP_INTR_ENABLE & ~CMD_CMPL_INTR_ENABLE) | 0x00;
898
899 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_CTRL(ctrl->cap_base), temp_word);
900 if (rc) {
901 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__);
902 return IRQ_NONE;
903 }
904
905 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status);
906 if (rc) {
907 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
908 return IRQ_NONE;
909 }
910 dbg("%s: hp_register_read_word SLOT_STATUS with value %x\n", __FUNCTION__, slot_status);
911
912 /* Clear command complete interrupt caused by this write */
913 temp_word = 0x1f;
914 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), temp_word);
915 if (rc) {
916 err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__);
917 return IRQ_NONE;
918 }
919 }
920
921 if (intr_loc & CMD_COMPLETED) {
922 /*
923 * Command Complete Interrupt Pending
924 */
925 wake_up_interruptible(&ctrl->queue);
926 }
927
928 if ((php_ctlr->switch_change_callback) && (intr_loc & MRL_SENS_CHANGED))
929 schedule_flag += php_ctlr->switch_change_callback(
930 hp_slot, php_ctlr->callback_instance_id);
931 if ((php_ctlr->attention_button_callback) && (intr_loc & ATTN_BUTTN_PRESSED))
932 schedule_flag += php_ctlr->attention_button_callback(
933 hp_slot, php_ctlr->callback_instance_id);
934 if ((php_ctlr->presence_change_callback) && (intr_loc & PRSN_DETECT_CHANGED))
935 schedule_flag += php_ctlr->presence_change_callback(
936 hp_slot , php_ctlr->callback_instance_id);
937 if ((php_ctlr->power_fault_callback) && (intr_loc & PWR_FAULT_DETECTED))
938 schedule_flag += php_ctlr->power_fault_callback(
939 hp_slot, php_ctlr->callback_instance_id);
940
941 /* Clear all events after serving them */
942 temp_word = 0x1F;
943 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), temp_word);
944 if (rc) {
945 err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__);
946 return IRQ_NONE;
947 }
948 /* Unmask Hot-plug Interrupt Enable */
949 if (!pciehp_poll_mode) {
950 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(ctrl->cap_base), temp_word);
951 if (rc) {
952 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
953 return IRQ_NONE;
954 }
955
956 dbg("%s: Unmask Hot-plug Interrupt Enable\n", __FUNCTION__);
957 temp_word = (temp_word & ~HP_INTR_ENABLE) | HP_INTR_ENABLE;
958
959 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_CTRL(ctrl->cap_base), temp_word);
960 if (rc) {
961 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__);
962 return IRQ_NONE;
963 }
964
965 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status);
966 if (rc) {
967 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
968 return IRQ_NONE;
969 }
970
971 /* Clear command complete interrupt caused by this write */
972 temp_word = 0x1F;
973 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), temp_word);
974 if (rc) {
975 err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__);
976 return IRQ_NONE;
977 }
978 dbg("%s: hp_register_write_word SLOT_STATUS with value %x\n", __FUNCTION__, temp_word);
979 }
980
981 return IRQ_HANDLED;
982 }
983
984 static int hpc_get_max_lnk_speed (struct slot *slot, enum pci_bus_speed *value)
985 {
986 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
987 enum pcie_link_speed lnk_speed;
988 u32 lnk_cap;
989 int retval = 0;
990
991 DBG_ENTER_ROUTINE
992
993 if (!php_ctlr) {
994 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
995 return -1;
996 }
997
998 if (slot->hp_slot >= php_ctlr->num_slots) {
999 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
1000 return -1;
1001 }
1002
1003 retval = hp_register_read_dword(php_ctlr->pci_dev, LNK_CAP(slot->ctrl->cap_base), lnk_cap);
1004
1005 if (retval) {
1006 err("%s : hp_register_read_dword LNK_CAP failed\n", __FUNCTION__);
1007 return retval;
1008 }
1009
1010 switch (lnk_cap & 0x000F) {
1011 case 1:
1012 lnk_speed = PCIE_2PT5GB;
1013 break;
1014 default:
1015 lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
1016 break;
1017 }
1018
1019 *value = lnk_speed;
1020 dbg("Max link speed = %d\n", lnk_speed);
1021 DBG_LEAVE_ROUTINE
1022 return retval;
1023 }
1024
1025 static int hpc_get_max_lnk_width (struct slot *slot, enum pcie_link_width *value)
1026 {
1027 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
1028 enum pcie_link_width lnk_wdth;
1029 u32 lnk_cap;
1030 int retval = 0;
1031
1032 DBG_ENTER_ROUTINE
1033
1034 if (!php_ctlr) {
1035 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
1036 return -1;
1037 }
1038
1039 if (slot->hp_slot >= php_ctlr->num_slots) {
1040 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
1041 return -1;
1042 }
1043
1044 retval = hp_register_read_dword(php_ctlr->pci_dev, LNK_CAP(slot->ctrl->cap_base), lnk_cap);
1045
1046 if (retval) {
1047 err("%s : hp_register_read_dword LNK_CAP failed\n", __FUNCTION__);
1048 return retval;
1049 }
1050
1051 switch ((lnk_cap & 0x03F0) >> 4){
1052 case 0:
1053 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
1054 break;
1055 case 1:
1056 lnk_wdth = PCIE_LNK_X1;
1057 break;
1058 case 2:
1059 lnk_wdth = PCIE_LNK_X2;
1060 break;
1061 case 4:
1062 lnk_wdth = PCIE_LNK_X4;
1063 break;
1064 case 8:
1065 lnk_wdth = PCIE_LNK_X8;
1066 break;
1067 case 12:
1068 lnk_wdth = PCIE_LNK_X12;
1069 break;
1070 case 16:
1071 lnk_wdth = PCIE_LNK_X16;
1072 break;
1073 case 32:
1074 lnk_wdth = PCIE_LNK_X32;
1075 break;
1076 default:
1077 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
1078 break;
1079 }
1080
1081 *value = lnk_wdth;
1082 dbg("Max link width = %d\n", lnk_wdth);
1083 DBG_LEAVE_ROUTINE
1084 return retval;
1085 }
1086
1087 static int hpc_get_cur_lnk_speed (struct slot *slot, enum pci_bus_speed *value)
1088 {
1089 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
1090 enum pcie_link_speed lnk_speed = PCI_SPEED_UNKNOWN;
1091 int retval = 0;
1092 u16 lnk_status;
1093
1094 DBG_ENTER_ROUTINE
1095
1096 if (!php_ctlr) {
1097 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
1098 return -1;
1099 }
1100
1101 if (slot->hp_slot >= php_ctlr->num_slots) {
1102 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
1103 return -1;
1104 }
1105
1106 retval = hp_register_read_word(php_ctlr->pci_dev, LNK_STATUS(slot->ctrl->cap_base), lnk_status);
1107
1108 if (retval) {
1109 err("%s : hp_register_read_word LNK_STATUS failed\n", __FUNCTION__);
1110 return retval;
1111 }
1112
1113 switch (lnk_status & 0x0F) {
1114 case 1:
1115 lnk_speed = PCIE_2PT5GB;
1116 break;
1117 default:
1118 lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
1119 break;
1120 }
1121
1122 *value = lnk_speed;
1123 dbg("Current link speed = %d\n", lnk_speed);
1124 DBG_LEAVE_ROUTINE
1125 return retval;
1126 }
1127
1128 static int hpc_get_cur_lnk_width (struct slot *slot, enum pcie_link_width *value)
1129 {
1130 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
1131 enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
1132 int retval = 0;
1133 u16 lnk_status;
1134
1135 DBG_ENTER_ROUTINE
1136
1137 if (!php_ctlr) {
1138 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
1139 return -1;
1140 }
1141
1142 if (slot->hp_slot >= php_ctlr->num_slots) {
1143 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
1144 return -1;
1145 }
1146
1147 retval = hp_register_read_word(php_ctlr->pci_dev, LNK_STATUS(slot->ctrl->cap_base), lnk_status);
1148
1149 if (retval) {
1150 err("%s : hp_register_read_word LNK_STATUS failed\n", __FUNCTION__);
1151 return retval;
1152 }
1153
1154 switch ((lnk_status & 0x03F0) >> 4){
1155 case 0:
1156 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
1157 break;
1158 case 1:
1159 lnk_wdth = PCIE_LNK_X1;
1160 break;
1161 case 2:
1162 lnk_wdth = PCIE_LNK_X2;
1163 break;
1164 case 4:
1165 lnk_wdth = PCIE_LNK_X4;
1166 break;
1167 case 8:
1168 lnk_wdth = PCIE_LNK_X8;
1169 break;
1170 case 12:
1171 lnk_wdth = PCIE_LNK_X12;
1172 break;
1173 case 16:
1174 lnk_wdth = PCIE_LNK_X16;
1175 break;
1176 case 32:
1177 lnk_wdth = PCIE_LNK_X32;
1178 break;
1179 default:
1180 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
1181 break;
1182 }
1183
1184 *value = lnk_wdth;
1185 dbg("Current link width = %d\n", lnk_wdth);
1186 DBG_LEAVE_ROUTINE
1187 return retval;
1188 }
1189
1190 static struct hpc_ops pciehp_hpc_ops = {
1191 .power_on_slot = hpc_power_on_slot,
1192 .power_off_slot = hpc_power_off_slot,
1193 .set_attention_status = hpc_set_attention_status,
1194 .get_power_status = hpc_get_power_status,
1195 .get_attention_status = hpc_get_attention_status,
1196 .get_latch_status = hpc_get_latch_status,
1197 .get_adapter_status = hpc_get_adapter_status,
1198
1199 .get_max_bus_speed = hpc_get_max_lnk_speed,
1200 .get_cur_bus_speed = hpc_get_cur_lnk_speed,
1201 .get_max_lnk_width = hpc_get_max_lnk_width,
1202 .get_cur_lnk_width = hpc_get_cur_lnk_width,
1203
1204 .query_power_fault = hpc_query_power_fault,
1205 .green_led_on = hpc_set_green_led_on,
1206 .green_led_off = hpc_set_green_led_off,
1207 .green_led_blink = hpc_set_green_led_blink,
1208
1209 .release_ctlr = hpc_release_ctlr,
1210 .check_lnk_status = hpc_check_lnk_status,
1211 };
1212
1213 int pcie_init(struct controller * ctrl, struct pcie_device *dev)
1214 {
1215 struct php_ctlr_state_s *php_ctlr, *p;
1216 void *instance_id = ctrl;
1217 int rc;
1218 static int first = 1;
1219 u16 temp_word;
1220 u16 cap_reg;
1221 u16 intr_enable = 0;
1222 u32 slot_cap;
1223 int cap_base, saved_cap_base;
1224 u16 slot_status, slot_ctrl;
1225 struct pci_dev *pdev;
1226
1227 DBG_ENTER_ROUTINE
1228
1229 spin_lock_init(&list_lock);
1230 php_ctlr = (struct php_ctlr_state_s *) kmalloc(sizeof(struct php_ctlr_state_s), GFP_KERNEL);
1231
1232 if (!php_ctlr) { /* allocate controller state data */
1233 err("%s: HPC controller memory allocation error!\n", __FUNCTION__);
1234 goto abort;
1235 }
1236
1237 memset(php_ctlr, 0, sizeof(struct php_ctlr_state_s));
1238
1239 pdev = dev->port;
1240 php_ctlr->pci_dev = pdev; /* save pci_dev in context */
1241
1242 dbg("%s: hotplug controller vendor id 0x%x device id 0x%x\n",
1243 __FUNCTION__, pdev->vendor, pdev->device);
1244
1245 saved_cap_base = pcie_cap_base;
1246
1247 if ((cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP)) == 0) {
1248 dbg("%s: Can't find PCI_CAP_ID_EXP (0x10)\n", __FUNCTION__);
1249 goto abort_free_ctlr;
1250 }
1251
1252 ctrl->cap_base = cap_base;
1253
1254 dbg("%s: pcie_cap_base %x\n", __FUNCTION__, pcie_cap_base);
1255
1256 rc = hp_register_read_word(pdev, CAP_REG(ctrl->cap_base), cap_reg);
1257 if (rc) {
1258 err("%s : hp_register_read_word CAP_REG failed\n", __FUNCTION__);
1259 goto abort_free_ctlr;
1260 }
1261 dbg("%s: CAP_REG offset %x cap_reg %x\n", __FUNCTION__, CAP_REG(ctrl->cap_base), cap_reg);
1262
1263 if (((cap_reg & SLOT_IMPL) == 0) || (((cap_reg & DEV_PORT_TYPE) != 0x0040)
1264 && ((cap_reg & DEV_PORT_TYPE) != 0x0060))) {
1265 dbg("%s : This is not a root port or the port is not connected to a slot\n", __FUNCTION__);
1266 goto abort_free_ctlr;
1267 }
1268
1269 rc = hp_register_read_dword(php_ctlr->pci_dev, SLOT_CAP(ctrl->cap_base), slot_cap);
1270 if (rc) {
1271 err("%s : hp_register_read_word CAP_REG failed\n", __FUNCTION__);
1272 goto abort_free_ctlr;
1273 }
1274 dbg("%s: SLOT_CAP offset %x slot_cap %x\n", __FUNCTION__, SLOT_CAP(ctrl->cap_base), slot_cap);
1275
1276 if (!(slot_cap & HP_CAP)) {
1277 dbg("%s : This slot is not hot-plug capable\n", __FUNCTION__);
1278 goto abort_free_ctlr;
1279 }
1280 /* For debugging purpose */
1281 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status);
1282 if (rc) {
1283 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
1284 goto abort_free_ctlr;
1285 }
1286 dbg("%s: SLOT_STATUS offset %x slot_status %x\n", __FUNCTION__, SLOT_STATUS(ctrl->cap_base), slot_status);
1287
1288 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(ctrl->cap_base), slot_ctrl);
1289 if (rc) {
1290 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
1291 goto abort_free_ctlr;
1292 }
1293 dbg("%s: SLOT_CTRL offset %x slot_ctrl %x\n", __FUNCTION__, SLOT_CTRL(ctrl->cap_base), slot_ctrl);
1294
1295 if (first) {
1296 spin_lock_init(&hpc_event_lock);
1297 first = 0;
1298 }
1299
1300 for ( rc = 0; rc < DEVICE_COUNT_RESOURCE; rc++)
1301 if (pci_resource_len(pdev, rc) > 0)
1302 dbg("pci resource[%d] start=0x%lx(len=0x%lx)\n", rc,
1303 pci_resource_start(pdev, rc), pci_resource_len(pdev, rc));
1304
1305 info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", pdev->vendor, pdev->device,
1306 pdev->subsystem_vendor, pdev->subsystem_device);
1307
1308 if (pci_enable_device(pdev))
1309 goto abort_free_ctlr;
1310
1311 init_MUTEX(&ctrl->crit_sect);
1312 /* setup wait queue */
1313 init_waitqueue_head(&ctrl->queue);
1314
1315 /* find the IRQ */
1316 php_ctlr->irq = dev->irq;
1317
1318 /* Save interrupt callback info */
1319 php_ctlr->attention_button_callback = pciehp_handle_attention_button;
1320 php_ctlr->switch_change_callback = pciehp_handle_switch_change;
1321 php_ctlr->presence_change_callback = pciehp_handle_presence_change;
1322 php_ctlr->power_fault_callback = pciehp_handle_power_fault;
1323 php_ctlr->callback_instance_id = instance_id;
1324
1325 /* return PCI Controller Info */
1326 php_ctlr->slot_device_offset = 0;
1327 php_ctlr->num_slots = 1;
1328
1329 /* Mask Hot-plug Interrupt Enable */
1330 rc = hp_register_read_word(pdev, SLOT_CTRL(ctrl->cap_base), temp_word);
1331 if (rc) {
1332 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
1333 goto abort_free_ctlr;
1334 }
1335
1336 dbg("%s: SLOT_CTRL %x value read %x\n", __FUNCTION__, SLOT_CTRL(ctrl->cap_base), temp_word);
1337 temp_word = (temp_word & ~HP_INTR_ENABLE & ~CMD_CMPL_INTR_ENABLE) | 0x00;
1338
1339 rc = hp_register_write_word(pdev, SLOT_CTRL(ctrl->cap_base), temp_word);
1340 if (rc) {
1341 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__);
1342 goto abort_free_ctlr;
1343 }
1344
1345 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status);
1346 if (rc) {
1347 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
1348 goto abort_free_ctlr;
1349 }
1350
1351 temp_word = 0x1F; /* Clear all events */
1352 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), temp_word);
1353 if (rc) {
1354 err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__);
1355 goto abort_free_ctlr;
1356 }
1357
1358 if (pciehp_poll_mode) {/* Install interrupt polling code */
1359 /* Install and start the interrupt polling timer */
1360 init_timer(&php_ctlr->int_poll_timer);
1361 start_int_poll_timer( php_ctlr, 10 ); /* start with 10 second delay */
1362 } else {
1363 /* Installs the interrupt handler */
1364 rc = request_irq(php_ctlr->irq, pcie_isr, SA_SHIRQ, MY_NAME, (void *) ctrl);
1365 dbg("%s: request_irq %d for hpc%d (returns %d)\n", __FUNCTION__, php_ctlr->irq, ctlr_seq_num, rc);
1366 if (rc) {
1367 err("Can't get irq %d for the hotplug controller\n", php_ctlr->irq);
1368 goto abort_free_ctlr;
1369 }
1370 }
1371
1372 dbg("pciehp ctrl b:d:f:irq=0x%x:%x:%x:%x\n", pdev->bus->number,
1373 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), dev->irq);
1374
1375 rc = hp_register_read_word(pdev, SLOT_CTRL(ctrl->cap_base), temp_word);
1376 if (rc) {
1377 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
1378 goto abort_free_ctlr;
1379 }
1380
1381 intr_enable = intr_enable | PRSN_DETECT_ENABLE;
1382
1383 if (ATTN_BUTTN(slot_cap))
1384 intr_enable = intr_enable | ATTN_BUTTN_ENABLE;
1385
1386 if (POWER_CTRL(slot_cap))
1387 intr_enable = intr_enable | PWR_FAULT_DETECT_ENABLE;
1388
1389 if (MRL_SENS(slot_cap))
1390 intr_enable = intr_enable | MRL_DETECT_ENABLE;
1391
1392 temp_word = (temp_word & ~intr_enable) | intr_enable;
1393
1394 if (pciehp_poll_mode) {
1395 temp_word = (temp_word & ~HP_INTR_ENABLE) | 0x0;
1396 } else {
1397 temp_word = (temp_word & ~HP_INTR_ENABLE) | HP_INTR_ENABLE;
1398 }
1399
1400 /* Unmask Hot-plug Interrupt Enable for the interrupt notification mechanism case */
1401 rc = hp_register_write_word(pdev, SLOT_CTRL(ctrl->cap_base), temp_word);
1402 if (rc) {
1403 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__);
1404 goto abort_free_ctlr;
1405 }
1406 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status);
1407 if (rc) {
1408 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
1409 goto abort_free_ctlr;
1410 }
1411
1412 temp_word = 0x1F; /* Clear all events */
1413 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), temp_word);
1414 if (rc) {
1415 err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__);
1416 goto abort_free_ctlr;
1417 }
1418
1419 if (pciehp_force) {
1420 dbg("Bypassing BIOS check for pciehp use on %s\n",
1421 pci_name(ctrl->pci_dev));
1422 } else {
1423 rc = pciehp_get_hp_hw_control_from_firmware(ctrl->pci_dev);
1424 if (rc)
1425 goto abort_free_ctlr;
1426 }
1427
1428 /* Add this HPC instance into the HPC list */
1429 spin_lock(&list_lock);
1430 if (php_ctlr_list_head == 0) {
1431 php_ctlr_list_head = php_ctlr;
1432 p = php_ctlr_list_head;
1433 p->pnext = NULL;
1434 } else {
1435 p = php_ctlr_list_head;
1436
1437 while (p->pnext)
1438 p = p->pnext;
1439
1440 p->pnext = php_ctlr;
1441 }
1442 spin_unlock(&list_lock);
1443
1444 ctlr_seq_num++;
1445 ctrl->hpc_ctlr_handle = php_ctlr;
1446 ctrl->hpc_ops = &pciehp_hpc_ops;
1447
1448 DBG_LEAVE_ROUTINE
1449 return 0;
1450
1451 /* We end up here for the many possible ways to fail this API. */
1452 abort_free_ctlr:
1453 pcie_cap_base = saved_cap_base;
1454 kfree(php_ctlr);
1455 abort:
1456 DBG_LEAVE_ROUTINE
1457 return -1;
1458 }
Linus' kernel tree