2 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/acpi.h>
22 #include <linux/gfp.h>
23 #include <linux/list.h>
24 #include <asm/pci-direct.h>
25 #include <asm/amd_iommu_types.h>
29 * definitions for the ACPI scanning code
31 #define UPDATE_LAST_BDF(x) do {\
32 if ((x) > amd_iommu_last_bdf) \
33 amd_iommu_last_bdf = (x); \
36 #define DEVID(bus, devfn) (((bus) << 8) | (devfn))
37 #define PCI_BUS(x) (((x) >> 8) & 0xff)
38 #define IVRS_HEADER_LENGTH 48
39 #define TBL_SIZE(x) (1 << (PAGE_SHIFT + get_order(amd_iommu_last_bdf * (x))))
41 #define ACPI_IVHD_TYPE 0x10
42 #define ACPI_IVMD_TYPE_ALL 0x20
43 #define ACPI_IVMD_TYPE 0x21
44 #define ACPI_IVMD_TYPE_RANGE 0x22
46 #define IVHD_DEV_ALL 0x01
47 #define IVHD_DEV_SELECT 0x02
48 #define IVHD_DEV_SELECT_RANGE_START 0x03
49 #define IVHD_DEV_RANGE_END 0x04
50 #define IVHD_DEV_ALIAS 0x42
51 #define IVHD_DEV_ALIAS_RANGE 0x43
52 #define IVHD_DEV_EXT_SELECT 0x46
53 #define IVHD_DEV_EXT_SELECT_RANGE 0x47
55 #define IVHD_FLAG_HT_TUN_EN 0x00
56 #define IVHD_FLAG_PASSPW_EN 0x01
57 #define IVHD_FLAG_RESPASSPW_EN 0x02
58 #define IVHD_FLAG_ISOC_EN 0x03
60 #define IVMD_FLAG_EXCL_RANGE 0x08
61 #define IVMD_FLAG_UNITY_MAP 0x01
63 #define ACPI_DEVFLAG_INITPASS 0x01
64 #define ACPI_DEVFLAG_EXTINT 0x02
65 #define ACPI_DEVFLAG_NMI 0x04
66 #define ACPI_DEVFLAG_SYSMGT1 0x10
67 #define ACPI_DEVFLAG_SYSMGT2 0x20
68 #define ACPI_DEVFLAG_LINT0 0x40
69 #define ACPI_DEVFLAG_LINT1 0x80
70 #define ACPI_DEVFLAG_ATSDIS 0x10000000
82 } __attribute__((packed
));
89 } __attribute__((packed
));
100 } __attribute__((packed
));
102 static int __initdata amd_iommu_disable
;
104 u16 amd_iommu_last_bdf
;
105 struct list_head amd_iommu_unity_map
;
106 unsigned amd_iommu_aperture_order
= 26;
107 int amd_iommu_isolate
;
109 struct list_head amd_iommu_list
;
110 struct dev_table_entry
*amd_iommu_dev_table
;
111 u16
*amd_iommu_alias_table
;
112 struct amd_iommu
**amd_iommu_rlookup_table
;
113 struct protection_domain
**amd_iommu_pd_table
;
114 unsigned long *amd_iommu_pd_alloc_bitmap
;
116 static u32 dev_table_size
;
117 static u32 alias_table_size
;
118 static u32 rlookup_table_size
;
120 static void __init
iommu_set_exclusion_range(struct amd_iommu
*iommu
)
122 u64 start
= iommu
->exclusion_start
& PAGE_MASK
;
123 u64 limit
= (start
+ iommu
->exclusion_length
) & PAGE_MASK
;
126 if (!iommu
->exclusion_start
)
129 entry
= start
| MMIO_EXCL_ENABLE_MASK
;
130 memcpy_toio(iommu
->mmio_base
+ MMIO_EXCL_BASE_OFFSET
,
131 &entry
, sizeof(entry
));
134 memcpy_toio(iommu
->mmio_base
+ MMIO_EXCL_LIMIT_OFFSET
,
135 &entry
, sizeof(entry
));
138 static void __init
iommu_set_device_table(struct amd_iommu
*iommu
)
142 BUG_ON(iommu
->mmio_base
== NULL
);
144 entry
= virt_to_phys(amd_iommu_dev_table
);
145 entry
|= (dev_table_size
>> 12) - 1;
146 memcpy_toio(iommu
->mmio_base
+ MMIO_DEV_TABLE_OFFSET
,
147 &entry
, sizeof(entry
));
150 static void __init
iommu_feature_enable(struct amd_iommu
*iommu
, u8 bit
)
154 ctrl
= readl(iommu
->mmio_base
+ MMIO_CONTROL_OFFSET
);
156 writel(ctrl
, iommu
->mmio_base
+ MMIO_CONTROL_OFFSET
);
159 static void __init
iommu_feature_disable(struct amd_iommu
*iommu
, u8 bit
)
163 ctrl
= (u64
)readl(iommu
->mmio_base
+ MMIO_CONTROL_OFFSET
);
165 writel(ctrl
, iommu
->mmio_base
+ MMIO_CONTROL_OFFSET
);
168 void __init
iommu_enable(struct amd_iommu
*iommu
)
172 printk(KERN_INFO
"AMD IOMMU: Enabling IOMMU at ");
173 print_devid(iommu
->devid
, 0);
174 printk(" cap 0x%hx\n", iommu
->cap_ptr
);
176 iommu_feature_enable(iommu
, CONTROL_IOMMU_EN
);
177 ctrl
= readl(iommu
->mmio_base
+ MMIO_CONTROL_OFFSET
);
180 static u8
* __init
iommu_map_mmio_space(u64 address
)
184 if (!request_mem_region(address
, MMIO_REGION_LENGTH
, "amd_iommu"))
187 ret
= ioremap_nocache(address
, MMIO_REGION_LENGTH
);
191 release_mem_region(address
, MMIO_REGION_LENGTH
);
196 static void __init
iommu_unmap_mmio_space(struct amd_iommu
*iommu
)
198 if (iommu
->mmio_base
)
199 iounmap(iommu
->mmio_base
);
200 release_mem_region(iommu
->mmio_phys
, MMIO_REGION_LENGTH
);
203 static int __init
find_last_devid_on_pci(int bus
, int dev
, int fn
, int cap_ptr
)
207 cap
= read_pci_config(bus
, dev
, fn
, cap_ptr
+MMIO_RANGE_OFFSET
);
208 UPDATE_LAST_BDF(DEVID(MMIO_GET_BUS(cap
), MMIO_GET_LD(cap
)));
213 static int __init
find_last_devid_from_ivhd(struct ivhd_header
*h
)
215 u8
*p
= (void *)h
, *end
= (void *)h
;
216 struct ivhd_entry
*dev
;
221 find_last_devid_on_pci(PCI_BUS(h
->devid
),
227 dev
= (struct ivhd_entry
*)p
;
229 case IVHD_DEV_SELECT
:
230 case IVHD_DEV_RANGE_END
:
232 case IVHD_DEV_EXT_SELECT
:
233 UPDATE_LAST_BDF(dev
->devid
);
238 p
+= 0x04 << (*p
>> 6);
246 static int __init
find_last_devid_acpi(struct acpi_table_header
*table
)
249 u8 checksum
= 0, *p
= (u8
*)table
, *end
= (u8
*)table
;
250 struct ivhd_header
*h
;
253 * Validate checksum here so we don't need to do it when
254 * we actually parse the table
256 for (i
= 0; i
< table
->length
; ++i
)
259 /* ACPI table corrupt */
262 p
+= IVRS_HEADER_LENGTH
;
264 end
+= table
->length
;
266 h
= (struct ivhd_header
*)p
;
269 find_last_devid_from_ivhd(h
);
281 static u8
* __init
alloc_command_buffer(struct amd_iommu
*iommu
)
283 u8
*cmd_buf
= (u8
*)__get_free_pages(GFP_KERNEL
,
284 get_order(CMD_BUFFER_SIZE
));
290 iommu
->cmd_buf_size
= CMD_BUFFER_SIZE
;
292 memset(cmd_buf
, 0, CMD_BUFFER_SIZE
);
294 entry
= (u64
)virt_to_phys(cmd_buf
);
295 entry
|= MMIO_CMD_SIZE_512
;
296 memcpy_toio(iommu
->mmio_base
+ MMIO_CMD_BUF_OFFSET
,
297 &entry
, sizeof(entry
));
299 iommu_feature_enable(iommu
, CONTROL_CMDBUF_EN
);
304 static void __init
free_command_buffer(struct amd_iommu
*iommu
)
307 free_pages((unsigned long)iommu
->cmd_buf
,
308 get_order(CMD_BUFFER_SIZE
));
311 static void set_dev_entry_bit(u16 devid
, u8 bit
)
313 int i
= (bit
>> 5) & 0x07;
314 int _bit
= bit
& 0x1f;
316 amd_iommu_dev_table
[devid
].data
[i
] |= (1 << _bit
);
319 static void __init
set_dev_entry_from_acpi(u16 devid
, u32 flags
, u32 ext_flags
)
321 if (flags
& ACPI_DEVFLAG_INITPASS
)
322 set_dev_entry_bit(devid
, DEV_ENTRY_INIT_PASS
);
323 if (flags
& ACPI_DEVFLAG_EXTINT
)
324 set_dev_entry_bit(devid
, DEV_ENTRY_EINT_PASS
);
325 if (flags
& ACPI_DEVFLAG_NMI
)
326 set_dev_entry_bit(devid
, DEV_ENTRY_NMI_PASS
);
327 if (flags
& ACPI_DEVFLAG_SYSMGT1
)
328 set_dev_entry_bit(devid
, DEV_ENTRY_SYSMGT1
);
329 if (flags
& ACPI_DEVFLAG_SYSMGT2
)
330 set_dev_entry_bit(devid
, DEV_ENTRY_SYSMGT2
);
331 if (flags
& ACPI_DEVFLAG_LINT0
)
332 set_dev_entry_bit(devid
, DEV_ENTRY_LINT0_PASS
);
333 if (flags
& ACPI_DEVFLAG_LINT1
)
334 set_dev_entry_bit(devid
, DEV_ENTRY_LINT1_PASS
);
337 static void __init
set_iommu_for_device(struct amd_iommu
*iommu
, u16 devid
)
339 amd_iommu_rlookup_table
[devid
] = iommu
;
342 static void __init
set_device_exclusion_range(u16 devid
, struct ivmd_header
*m
)
344 struct amd_iommu
*iommu
= amd_iommu_rlookup_table
[devid
];
346 if (!(m
->flags
& IVMD_FLAG_EXCL_RANGE
))
350 set_dev_entry_bit(m
->devid
, DEV_ENTRY_EX
);
351 iommu
->exclusion_start
= m
->range_start
;
352 iommu
->exclusion_length
= m
->range_length
;
356 static void __init
init_iommu_from_pci(struct amd_iommu
*iommu
)
358 int bus
= PCI_BUS(iommu
->devid
);
359 int dev
= PCI_SLOT(iommu
->devid
);
360 int fn
= PCI_FUNC(iommu
->devid
);
361 int cap_ptr
= iommu
->cap_ptr
;
364 iommu
->cap
= read_pci_config(bus
, dev
, fn
, cap_ptr
+MMIO_CAP_HDR_OFFSET
);
366 range
= read_pci_config(bus
, dev
, fn
, cap_ptr
+MMIO_RANGE_OFFSET
);
367 iommu
->first_device
= DEVID(MMIO_GET_BUS(range
), MMIO_GET_FD(range
));
368 iommu
->last_device
= DEVID(MMIO_GET_BUS(range
), MMIO_GET_LD(range
));
371 static void __init
init_iommu_from_acpi(struct amd_iommu
*iommu
,
372 struct ivhd_header
*h
)
375 u8
*end
= p
, flags
= 0;
376 u16 dev_i
, devid
= 0, devid_start
= 0, devid_to
= 0;
379 struct ivhd_entry
*e
;
382 * First set the recommended feature enable bits from ACPI
383 * into the IOMMU control registers
385 h
->flags
& IVHD_FLAG_HT_TUN_EN
?
386 iommu_feature_enable(iommu
, CONTROL_HT_TUN_EN
) :
387 iommu_feature_disable(iommu
, CONTROL_HT_TUN_EN
);
389 h
->flags
& IVHD_FLAG_PASSPW_EN
?
390 iommu_feature_enable(iommu
, CONTROL_PASSPW_EN
) :
391 iommu_feature_disable(iommu
, CONTROL_PASSPW_EN
);
393 h
->flags
& IVHD_FLAG_RESPASSPW_EN
?
394 iommu_feature_enable(iommu
, CONTROL_RESPASSPW_EN
) :
395 iommu_feature_disable(iommu
, CONTROL_RESPASSPW_EN
);
397 h
->flags
& IVHD_FLAG_ISOC_EN
?
398 iommu_feature_enable(iommu
, CONTROL_ISOC_EN
) :
399 iommu_feature_disable(iommu
, CONTROL_ISOC_EN
);
402 * make IOMMU memory accesses cache coherent
404 iommu_feature_enable(iommu
, CONTROL_COHERENT_EN
);
407 * Done. Now parse the device entries
409 p
+= sizeof(struct ivhd_header
);
413 e
= (struct ivhd_entry
*)p
;
416 for (dev_i
= iommu
->first_device
;
417 dev_i
<= iommu
->last_device
; ++dev_i
)
418 set_dev_entry_from_acpi(dev_i
, e
->flags
, 0);
420 case IVHD_DEV_SELECT
:
422 set_dev_entry_from_acpi(devid
, e
->flags
, 0);
424 case IVHD_DEV_SELECT_RANGE_START
:
425 devid_start
= e
->devid
;
432 devid_to
= e
->ext
>> 8;
433 set_dev_entry_from_acpi(devid
, e
->flags
, 0);
434 amd_iommu_alias_table
[devid
] = devid_to
;
436 case IVHD_DEV_ALIAS_RANGE
:
437 devid_start
= e
->devid
;
439 devid_to
= e
->ext
>> 8;
443 case IVHD_DEV_EXT_SELECT
:
445 set_dev_entry_from_acpi(devid
, e
->flags
, e
->ext
);
447 case IVHD_DEV_EXT_SELECT_RANGE
:
448 devid_start
= e
->devid
;
453 case IVHD_DEV_RANGE_END
:
455 for (dev_i
= devid_start
; dev_i
<= devid
; ++dev_i
) {
457 amd_iommu_alias_table
[dev_i
] = devid_to
;
458 set_dev_entry_from_acpi(
459 amd_iommu_alias_table
[dev_i
],
467 p
+= 0x04 << (e
->type
>> 6);
471 static int __init
init_iommu_devices(struct amd_iommu
*iommu
)
475 for (i
= iommu
->first_device
; i
<= iommu
->last_device
; ++i
)
476 set_iommu_for_device(iommu
, i
);