1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2008 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
29 #include <linux/delay.h>
33 static s32
e1000_get_phy_cfg_done(struct e1000_hw
*hw
);
34 static s32
e1000_phy_force_speed_duplex(struct e1000_hw
*hw
);
35 static s32
e1000_set_d0_lplu_state(struct e1000_hw
*hw
, bool active
);
36 static s32
e1000_wait_autoneg(struct e1000_hw
*hw
);
37 static u32
e1000_get_phy_addr_for_bm_page(u32 page
, u32 reg
);
38 static s32
e1000_access_phy_wakeup_reg_bm(struct e1000_hw
*hw
, u32 offset
,
39 u16
*data
, bool read
);
40 static u32
e1000_get_phy_addr_for_hv_page(u32 page
);
41 static s32
e1000_access_phy_debug_regs_hv(struct e1000_hw
*hw
, u32 offset
,
42 u16
*data
, bool read
);
44 /* Cable length tables */
45 static const u16 e1000_m88_cable_length_table
[] =
46 { 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED
};
48 static const u16 e1000_igp_2_cable_length_table
[] =
49 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
50 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
51 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
52 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
53 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
54 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
55 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
57 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
58 ARRAY_SIZE(e1000_igp_2_cable_length_table)
60 #define BM_PHY_REG_PAGE(offset) \
61 ((u16)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF))
62 #define BM_PHY_REG_NUM(offset) \
63 ((u16)(((offset) & MAX_PHY_REG_ADDRESS) |\
64 (((offset) >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) &\
65 ~MAX_PHY_REG_ADDRESS)))
67 #define HV_INTC_FC_PAGE_START 768
68 #define I82578_ADDR_REG 29
69 #define I82577_ADDR_REG 16
70 #define I82577_CFG_REG 22
71 #define I82577_CFG_ASSERT_CRS_ON_TX (1 << 15)
72 #define I82577_CFG_ENABLE_DOWNSHIFT (3 << 10) /* auto downshift 100/10 */
73 #define I82577_CTRL_REG 23
74 #define I82577_CTRL_DOWNSHIFT_MASK (7 << 10)
76 /* 82577 specific PHY registers */
77 #define I82577_PHY_CTRL_2 18
78 #define I82577_PHY_STATUS_2 26
79 #define I82577_PHY_DIAG_STATUS 31
81 /* I82577 PHY Status 2 */
82 #define I82577_PHY_STATUS2_REV_POLARITY 0x0400
83 #define I82577_PHY_STATUS2_MDIX 0x0800
84 #define I82577_PHY_STATUS2_SPEED_MASK 0x0300
85 #define I82577_PHY_STATUS2_SPEED_1000MBPS 0x0200
87 /* I82577 PHY Control 2 */
88 #define I82577_PHY_CTRL2_AUTO_MDIX 0x0400
89 #define I82577_PHY_CTRL2_FORCE_MDI_MDIX 0x0200
91 /* I82577 PHY Diagnostics Status */
92 #define I82577_DSTATUS_CABLE_LENGTH 0x03FC
93 #define I82577_DSTATUS_CABLE_LENGTH_SHIFT 2
95 /* BM PHY Copper Specific Control 1 */
96 #define BM_CS_CTRL1 16
98 /* BM PHY Copper Specific Status */
99 #define BM_CS_STATUS 17
100 #define BM_CS_STATUS_LINK_UP 0x0400
101 #define BM_CS_STATUS_RESOLVED 0x0800
102 #define BM_CS_STATUS_SPEED_MASK 0xC000
103 #define BM_CS_STATUS_SPEED_1000 0x8000
105 #define HV_MUX_DATA_CTRL PHY_REG(776, 16)
106 #define HV_MUX_DATA_CTRL_GEN_TO_MAC 0x0400
107 #define HV_MUX_DATA_CTRL_FORCE_SPEED 0x0004
110 * e1000e_check_reset_block_generic - Check if PHY reset is blocked
111 * @hw: pointer to the HW structure
113 * Read the PHY management control register and check whether a PHY reset
114 * is blocked. If a reset is not blocked return 0, otherwise
115 * return E1000_BLK_PHY_RESET (12).
117 s32
e1000e_check_reset_block_generic(struct e1000_hw
*hw
)
123 return (manc
& E1000_MANC_BLK_PHY_RST_ON_IDE
) ?
124 E1000_BLK_PHY_RESET
: 0;
128 * e1000e_get_phy_id - Retrieve the PHY ID and revision
129 * @hw: pointer to the HW structure
131 * Reads the PHY registers and stores the PHY ID and possibly the PHY
132 * revision in the hardware structure.
134 s32
e1000e_get_phy_id(struct e1000_hw
*hw
)
136 struct e1000_phy_info
*phy
= &hw
->phy
;
141 if (!(phy
->ops
.read_phy_reg
))
144 while (retry_count
< 2) {
145 ret_val
= e1e_rphy(hw
, PHY_ID1
, &phy_id
);
149 phy
->id
= (u32
)(phy_id
<< 16);
151 ret_val
= e1e_rphy(hw
, PHY_ID2
, &phy_id
);
155 phy
->id
|= (u32
)(phy_id
& PHY_REVISION_MASK
);
156 phy
->revision
= (u32
)(phy_id
& ~PHY_REVISION_MASK
);
158 if (phy
->id
!= 0 && phy
->id
!= PHY_REVISION_MASK
)
162 * If the PHY ID is still unknown, we may have an 82577i
163 * without link. We will try again after setting Slow
164 * MDIC mode. No harm in trying again in this case since
165 * the PHY ID is unknown at this point anyway
167 ret_val
= phy
->ops
.acquire_phy(hw
);
170 ret_val
= e1000_set_mdio_slow_mode_hv(hw
, true);
173 phy
->ops
.release_phy(hw
);
178 /* Revert to MDIO fast mode, if applicable */
180 ret_val
= phy
->ops
.acquire_phy(hw
);
183 ret_val
= e1000_set_mdio_slow_mode_hv(hw
, false);
184 phy
->ops
.release_phy(hw
);
191 * e1000e_phy_reset_dsp - Reset PHY DSP
192 * @hw: pointer to the HW structure
194 * Reset the digital signal processor.
196 s32
e1000e_phy_reset_dsp(struct e1000_hw
*hw
)
200 ret_val
= e1e_wphy(hw
, M88E1000_PHY_GEN_CONTROL
, 0xC1);
204 return e1e_wphy(hw
, M88E1000_PHY_GEN_CONTROL
, 0);
208 * e1000e_read_phy_reg_mdic - Read MDI control register
209 * @hw: pointer to the HW structure
210 * @offset: register offset to be read
211 * @data: pointer to the read data
213 * Reads the MDI control register in the PHY at offset and stores the
214 * information read to data.
216 s32
e1000e_read_phy_reg_mdic(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
218 struct e1000_phy_info
*phy
= &hw
->phy
;
221 if (offset
> MAX_PHY_REG_ADDRESS
) {
222 hw_dbg(hw
, "PHY Address %d is out of range\n", offset
);
223 return -E1000_ERR_PARAM
;
227 * Set up Op-code, Phy Address, and register offset in the MDI
228 * Control register. The MAC will take care of interfacing with the
229 * PHY to retrieve the desired data.
231 mdic
= ((offset
<< E1000_MDIC_REG_SHIFT
) |
232 (phy
->addr
<< E1000_MDIC_PHY_SHIFT
) |
233 (E1000_MDIC_OP_READ
));
238 * Poll the ready bit to see if the MDI read completed
239 * Increasing the time out as testing showed failures with
242 for (i
= 0; i
< (E1000_GEN_POLL_TIMEOUT
* 3); i
++) {
245 if (mdic
& E1000_MDIC_READY
)
248 if (!(mdic
& E1000_MDIC_READY
)) {
249 hw_dbg(hw
, "MDI Read did not complete\n");
250 return -E1000_ERR_PHY
;
252 if (mdic
& E1000_MDIC_ERROR
) {
253 hw_dbg(hw
, "MDI Error\n");
254 return -E1000_ERR_PHY
;
262 * e1000e_write_phy_reg_mdic - Write MDI control register
263 * @hw: pointer to the HW structure
264 * @offset: register offset to write to
265 * @data: data to write to register at offset
267 * Writes data to MDI control register in the PHY at offset.
269 s32
e1000e_write_phy_reg_mdic(struct e1000_hw
*hw
, u32 offset
, u16 data
)
271 struct e1000_phy_info
*phy
= &hw
->phy
;
274 if (offset
> MAX_PHY_REG_ADDRESS
) {
275 hw_dbg(hw
, "PHY Address %d is out of range\n", offset
);
276 return -E1000_ERR_PARAM
;
280 * Set up Op-code, Phy Address, and register offset in the MDI
281 * Control register. The MAC will take care of interfacing with the
282 * PHY to retrieve the desired data.
284 mdic
= (((u32
)data
) |
285 (offset
<< E1000_MDIC_REG_SHIFT
) |
286 (phy
->addr
<< E1000_MDIC_PHY_SHIFT
) |
287 (E1000_MDIC_OP_WRITE
));
292 * Poll the ready bit to see if the MDI read completed
293 * Increasing the time out as testing showed failures with
296 for (i
= 0; i
< (E1000_GEN_POLL_TIMEOUT
* 3); i
++) {
299 if (mdic
& E1000_MDIC_READY
)
302 if (!(mdic
& E1000_MDIC_READY
)) {
303 hw_dbg(hw
, "MDI Write did not complete\n");
304 return -E1000_ERR_PHY
;
306 if (mdic
& E1000_MDIC_ERROR
) {
307 hw_dbg(hw
, "MDI Error\n");
308 return -E1000_ERR_PHY
;
315 * e1000e_read_phy_reg_m88 - Read m88 PHY register
316 * @hw: pointer to the HW structure
317 * @offset: register offset to be read
318 * @data: pointer to the read data
320 * Acquires semaphore, if necessary, then reads the PHY register at offset
321 * and storing the retrieved information in data. Release any acquired
322 * semaphores before exiting.
324 s32
e1000e_read_phy_reg_m88(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
328 ret_val
= hw
->phy
.ops
.acquire_phy(hw
);
332 ret_val
= e1000e_read_phy_reg_mdic(hw
, MAX_PHY_REG_ADDRESS
& offset
,
335 hw
->phy
.ops
.release_phy(hw
);
341 * e1000e_write_phy_reg_m88 - Write m88 PHY register
342 * @hw: pointer to the HW structure
343 * @offset: register offset to write to
344 * @data: data to write at register offset
346 * Acquires semaphore, if necessary, then writes the data to PHY register
347 * at the offset. Release any acquired semaphores before exiting.
349 s32
e1000e_write_phy_reg_m88(struct e1000_hw
*hw
, u32 offset
, u16 data
)
353 ret_val
= hw
->phy
.ops
.acquire_phy(hw
);
357 ret_val
= e1000e_write_phy_reg_mdic(hw
, MAX_PHY_REG_ADDRESS
& offset
,
360 hw
->phy
.ops
.release_phy(hw
);
366 * __e1000e_read_phy_reg_igp - Read igp PHY register
367 * @hw: pointer to the HW structure
368 * @offset: register offset to be read
369 * @data: pointer to the read data
370 * @locked: semaphore has already been acquired or not
372 * Acquires semaphore, if necessary, then reads the PHY register at offset
373 * and stores the retrieved information in data. Release any acquired
374 * semaphores before exiting.
376 static s32
__e1000e_read_phy_reg_igp(struct e1000_hw
*hw
, u32 offset
, u16
*data
,
382 if (!(hw
->phy
.ops
.acquire_phy
))
385 ret_val
= hw
->phy
.ops
.acquire_phy(hw
);
390 if (offset
> MAX_PHY_MULTI_PAGE_REG
) {
391 ret_val
= e1000e_write_phy_reg_mdic(hw
,
392 IGP01E1000_PHY_PAGE_SELECT
,
398 ret_val
= e1000e_read_phy_reg_mdic(hw
, MAX_PHY_REG_ADDRESS
& offset
,
403 hw
->phy
.ops
.release_phy(hw
);
409 * e1000e_read_phy_reg_igp - Read igp PHY register
410 * @hw: pointer to the HW structure
411 * @offset: register offset to be read
412 * @data: pointer to the read data
414 * Acquires semaphore then reads the PHY register at offset and stores the
415 * retrieved information in data.
416 * Release the acquired semaphore before exiting.
418 s32
e1000e_read_phy_reg_igp(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
420 return __e1000e_read_phy_reg_igp(hw
, offset
, data
, false);
424 * e1000e_read_phy_reg_igp_locked - Read igp PHY register
425 * @hw: pointer to the HW structure
426 * @offset: register offset to be read
427 * @data: pointer to the read data
429 * Reads the PHY register at offset and stores the retrieved information
430 * in data. Assumes semaphore already acquired.
432 s32
e1000e_read_phy_reg_igp_locked(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
434 return __e1000e_read_phy_reg_igp(hw
, offset
, data
, true);
438 * e1000e_write_phy_reg_igp - Write igp PHY register
439 * @hw: pointer to the HW structure
440 * @offset: register offset to write to
441 * @data: data to write at register offset
442 * @locked: semaphore has already been acquired or not
444 * Acquires semaphore, if necessary, then writes the data to PHY register
445 * at the offset. Release any acquired semaphores before exiting.
447 static s32
__e1000e_write_phy_reg_igp(struct e1000_hw
*hw
, u32 offset
, u16 data
,
453 if (!(hw
->phy
.ops
.acquire_phy
))
456 ret_val
= hw
->phy
.ops
.acquire_phy(hw
);
461 if (offset
> MAX_PHY_MULTI_PAGE_REG
) {
462 ret_val
= e1000e_write_phy_reg_mdic(hw
,
463 IGP01E1000_PHY_PAGE_SELECT
,
469 ret_val
= e1000e_write_phy_reg_mdic(hw
, MAX_PHY_REG_ADDRESS
& offset
,
474 hw
->phy
.ops
.release_phy(hw
);
481 * e1000e_write_phy_reg_igp - Write igp PHY register
482 * @hw: pointer to the HW structure
483 * @offset: register offset to write to
484 * @data: data to write at register offset
486 * Acquires semaphore then writes the data to PHY register
487 * at the offset. Release any acquired semaphores before exiting.
489 s32
e1000e_write_phy_reg_igp(struct e1000_hw
*hw
, u32 offset
, u16 data
)
491 return __e1000e_write_phy_reg_igp(hw
, offset
, data
, false);
495 * e1000e_write_phy_reg_igp_locked - Write igp PHY register
496 * @hw: pointer to the HW structure
497 * @offset: register offset to write to
498 * @data: data to write at register offset
500 * Writes the data to PHY register at the offset.
501 * Assumes semaphore already acquired.
503 s32
e1000e_write_phy_reg_igp_locked(struct e1000_hw
*hw
, u32 offset
, u16 data
)
505 return __e1000e_write_phy_reg_igp(hw
, offset
, data
, true);
509 * __e1000_read_kmrn_reg - Read kumeran register
510 * @hw: pointer to the HW structure
511 * @offset: register offset to be read
512 * @data: pointer to the read data
513 * @locked: semaphore has already been acquired or not
515 * Acquires semaphore, if necessary. Then reads the PHY register at offset
516 * using the kumeran interface. The information retrieved is stored in data.
517 * Release any acquired semaphores before exiting.
519 static s32
__e1000_read_kmrn_reg(struct e1000_hw
*hw
, u32 offset
, u16
*data
,
526 if (!(hw
->phy
.ops
.acquire_phy
))
529 ret_val
= hw
->phy
.ops
.acquire_phy(hw
);
534 kmrnctrlsta
= ((offset
<< E1000_KMRNCTRLSTA_OFFSET_SHIFT
) &
535 E1000_KMRNCTRLSTA_OFFSET
) | E1000_KMRNCTRLSTA_REN
;
536 ew32(KMRNCTRLSTA
, kmrnctrlsta
);
540 kmrnctrlsta
= er32(KMRNCTRLSTA
);
541 *data
= (u16
)kmrnctrlsta
;
544 hw
->phy
.ops
.release_phy(hw
);
551 * e1000e_read_kmrn_reg - Read kumeran register
552 * @hw: pointer to the HW structure
553 * @offset: register offset to be read
554 * @data: pointer to the read data
556 * Acquires semaphore then reads the PHY register at offset using the
557 * kumeran interface. The information retrieved is stored in data.
558 * Release the acquired semaphore before exiting.
560 s32
e1000e_read_kmrn_reg(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
562 return __e1000_read_kmrn_reg(hw
, offset
, data
, false);
566 * e1000_read_kmrn_reg_locked - Read kumeran register
567 * @hw: pointer to the HW structure
568 * @offset: register offset to be read
569 * @data: pointer to the read data
571 * Reads the PHY register at offset using the kumeran interface. The
572 * information retrieved is stored in data.
573 * Assumes semaphore already acquired.
575 s32
e1000_read_kmrn_reg_locked(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
577 return __e1000_read_kmrn_reg(hw
, offset
, data
, true);
581 * __e1000_write_kmrn_reg - Write kumeran register
582 * @hw: pointer to the HW structure
583 * @offset: register offset to write to
584 * @data: data to write at register offset
585 * @locked: semaphore has already been acquired or not
587 * Acquires semaphore, if necessary. Then write the data to PHY register
588 * at the offset using the kumeran interface. Release any acquired semaphores
591 static s32
__e1000_write_kmrn_reg(struct e1000_hw
*hw
, u32 offset
, u16 data
,
598 if (!(hw
->phy
.ops
.acquire_phy
))
601 ret_val
= hw
->phy
.ops
.acquire_phy(hw
);
606 kmrnctrlsta
= ((offset
<< E1000_KMRNCTRLSTA_OFFSET_SHIFT
) &
607 E1000_KMRNCTRLSTA_OFFSET
) | data
;
608 ew32(KMRNCTRLSTA
, kmrnctrlsta
);
613 hw
->phy
.ops
.release_phy(hw
);
620 * e1000e_write_kmrn_reg - Write kumeran register
621 * @hw: pointer to the HW structure
622 * @offset: register offset to write to
623 * @data: data to write at register offset
625 * Acquires semaphore then writes the data to the PHY register at the offset
626 * using the kumeran interface. Release the acquired semaphore before exiting.
628 s32
e1000e_write_kmrn_reg(struct e1000_hw
*hw
, u32 offset
, u16 data
)
630 return __e1000_write_kmrn_reg(hw
, offset
, data
, false);
634 * e1000_write_kmrn_reg_locked - Write kumeran register
635 * @hw: pointer to the HW structure
636 * @offset: register offset to write to
637 * @data: data to write at register offset
639 * Write the data to PHY register at the offset using the kumeran interface.
640 * Assumes semaphore already acquired.
642 s32
e1000_write_kmrn_reg_locked(struct e1000_hw
*hw
, u32 offset
, u16 data
)
644 return __e1000_write_kmrn_reg(hw
, offset
, data
, true);
648 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
649 * @hw: pointer to the HW structure
651 * Sets up Carrier-sense on Transmit and downshift values.
653 s32
e1000_copper_link_setup_82577(struct e1000_hw
*hw
)
655 struct e1000_phy_info
*phy
= &hw
->phy
;
659 /* Enable CRS on TX. This must be set for half-duplex operation. */
660 ret_val
= phy
->ops
.read_phy_reg(hw
, I82577_CFG_REG
, &phy_data
);
664 phy_data
|= I82577_CFG_ASSERT_CRS_ON_TX
;
666 /* Enable downshift */
667 phy_data
|= I82577_CFG_ENABLE_DOWNSHIFT
;
669 ret_val
= phy
->ops
.write_phy_reg(hw
, I82577_CFG_REG
, phy_data
);
673 /* Set number of link attempts before downshift */
674 ret_val
= phy
->ops
.read_phy_reg(hw
, I82577_CTRL_REG
, &phy_data
);
677 phy_data
&= ~I82577_CTRL_DOWNSHIFT_MASK
;
678 ret_val
= phy
->ops
.write_phy_reg(hw
, I82577_CTRL_REG
, phy_data
);
685 * e1000e_copper_link_setup_m88 - Setup m88 PHY's for copper link
686 * @hw: pointer to the HW structure
688 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
689 * and downshift values are set also.
691 s32
e1000e_copper_link_setup_m88(struct e1000_hw
*hw
)
693 struct e1000_phy_info
*phy
= &hw
->phy
;
697 /* Enable CRS on Tx. This must be set for half-duplex operation. */
698 ret_val
= e1e_rphy(hw
, M88E1000_PHY_SPEC_CTRL
, &phy_data
);
702 /* For BM PHY this bit is downshift enable */
703 if (phy
->type
!= e1000_phy_bm
)
704 phy_data
|= M88E1000_PSCR_ASSERT_CRS_ON_TX
;
708 * MDI/MDI-X = 0 (default)
709 * 0 - Auto for all speeds
712 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
714 phy_data
&= ~M88E1000_PSCR_AUTO_X_MODE
;
718 phy_data
|= M88E1000_PSCR_MDI_MANUAL_MODE
;
721 phy_data
|= M88E1000_PSCR_MDIX_MANUAL_MODE
;
724 phy_data
|= M88E1000_PSCR_AUTO_X_1000T
;
728 phy_data
|= M88E1000_PSCR_AUTO_X_MODE
;
734 * disable_polarity_correction = 0 (default)
735 * Automatic Correction for Reversed Cable Polarity
739 phy_data
&= ~M88E1000_PSCR_POLARITY_REVERSAL
;
740 if (phy
->disable_polarity_correction
== 1)
741 phy_data
|= M88E1000_PSCR_POLARITY_REVERSAL
;
743 /* Enable downshift on BM (disabled by default) */
744 if (phy
->type
== e1000_phy_bm
)
745 phy_data
|= BME1000_PSCR_ENABLE_DOWNSHIFT
;
747 ret_val
= e1e_wphy(hw
, M88E1000_PHY_SPEC_CTRL
, phy_data
);
751 if ((phy
->type
== e1000_phy_m88
) &&
752 (phy
->revision
< E1000_REVISION_4
) &&
753 (phy
->id
!= BME1000_E_PHY_ID_R2
)) {
755 * Force TX_CLK in the Extended PHY Specific Control Register
758 ret_val
= e1e_rphy(hw
, M88E1000_EXT_PHY_SPEC_CTRL
, &phy_data
);
762 phy_data
|= M88E1000_EPSCR_TX_CLK_25
;
764 if ((phy
->revision
== 2) &&
765 (phy
->id
== M88E1111_I_PHY_ID
)) {
766 /* 82573L PHY - set the downshift counter to 5x. */
767 phy_data
&= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK
;
768 phy_data
|= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X
;
770 /* Configure Master and Slave downshift values */
771 phy_data
&= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK
|
772 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK
);
773 phy_data
|= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X
|
774 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X
);
776 ret_val
= e1e_wphy(hw
, M88E1000_EXT_PHY_SPEC_CTRL
, phy_data
);
781 if ((phy
->type
== e1000_phy_bm
) && (phy
->id
== BME1000_E_PHY_ID_R2
)) {
782 /* Set PHY page 0, register 29 to 0x0003 */
783 ret_val
= e1e_wphy(hw
, 29, 0x0003);
787 /* Set PHY page 0, register 30 to 0x0000 */
788 ret_val
= e1e_wphy(hw
, 30, 0x0000);
793 /* Commit the changes. */
794 ret_val
= e1000e_commit_phy(hw
);
796 hw_dbg(hw
, "Error committing the PHY changes\n");
800 if (phy
->type
== e1000_phy_82578
) {
801 ret_val
= phy
->ops
.read_phy_reg(hw
, M88E1000_EXT_PHY_SPEC_CTRL
,
806 /* 82578 PHY - set the downshift count to 1x. */
807 phy_data
|= I82578_EPSCR_DOWNSHIFT_ENABLE
;
808 phy_data
&= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK
;
809 ret_val
= phy
->ops
.write_phy_reg(hw
, M88E1000_EXT_PHY_SPEC_CTRL
,
819 * e1000e_copper_link_setup_igp - Setup igp PHY's for copper link
820 * @hw: pointer to the HW structure
822 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
825 s32
e1000e_copper_link_setup_igp(struct e1000_hw
*hw
)
827 struct e1000_phy_info
*phy
= &hw
->phy
;
831 ret_val
= e1000_phy_hw_reset(hw
);
833 hw_dbg(hw
, "Error resetting the PHY.\n");
838 * Wait 100ms for MAC to configure PHY from NVM settings, to avoid
839 * timeout issues when LFS is enabled.
843 /* disable lplu d0 during driver init */
844 ret_val
= e1000_set_d0_lplu_state(hw
, 0);
846 hw_dbg(hw
, "Error Disabling LPLU D0\n");
849 /* Configure mdi-mdix settings */
850 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CTRL
, &data
);
854 data
&= ~IGP01E1000_PSCR_AUTO_MDIX
;
858 data
&= ~IGP01E1000_PSCR_FORCE_MDI_MDIX
;
861 data
|= IGP01E1000_PSCR_FORCE_MDI_MDIX
;
865 data
|= IGP01E1000_PSCR_AUTO_MDIX
;
868 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CTRL
, data
);
872 /* set auto-master slave resolution settings */
873 if (hw
->mac
.autoneg
) {
875 * when autonegotiation advertisement is only 1000Mbps then we
876 * should disable SmartSpeed and enable Auto MasterSlave
877 * resolution as hardware default.
879 if (phy
->autoneg_advertised
== ADVERTISE_1000_FULL
) {
880 /* Disable SmartSpeed */
881 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
886 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
887 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
892 /* Set auto Master/Slave resolution process */
893 ret_val
= e1e_rphy(hw
, PHY_1000T_CTRL
, &data
);
897 data
&= ~CR_1000T_MS_ENABLE
;
898 ret_val
= e1e_wphy(hw
, PHY_1000T_CTRL
, data
);
903 ret_val
= e1e_rphy(hw
, PHY_1000T_CTRL
, &data
);
907 /* load defaults for future use */
908 phy
->original_ms_type
= (data
& CR_1000T_MS_ENABLE
) ?
909 ((data
& CR_1000T_MS_VALUE
) ?
910 e1000_ms_force_master
:
911 e1000_ms_force_slave
) :
914 switch (phy
->ms_type
) {
915 case e1000_ms_force_master
:
916 data
|= (CR_1000T_MS_ENABLE
| CR_1000T_MS_VALUE
);
918 case e1000_ms_force_slave
:
919 data
|= CR_1000T_MS_ENABLE
;
920 data
&= ~(CR_1000T_MS_VALUE
);
923 data
&= ~CR_1000T_MS_ENABLE
;
927 ret_val
= e1e_wphy(hw
, PHY_1000T_CTRL
, data
);
934 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
935 * @hw: pointer to the HW structure
937 * Reads the MII auto-neg advertisement register and/or the 1000T control
938 * register and if the PHY is already setup for auto-negotiation, then
939 * return successful. Otherwise, setup advertisement and flow control to
940 * the appropriate values for the wanted auto-negotiation.
942 static s32
e1000_phy_setup_autoneg(struct e1000_hw
*hw
)
944 struct e1000_phy_info
*phy
= &hw
->phy
;
946 u16 mii_autoneg_adv_reg
;
947 u16 mii_1000t_ctrl_reg
= 0;
949 phy
->autoneg_advertised
&= phy
->autoneg_mask
;
951 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
952 ret_val
= e1e_rphy(hw
, PHY_AUTONEG_ADV
, &mii_autoneg_adv_reg
);
956 if (phy
->autoneg_mask
& ADVERTISE_1000_FULL
) {
957 /* Read the MII 1000Base-T Control Register (Address 9). */
958 ret_val
= e1e_rphy(hw
, PHY_1000T_CTRL
, &mii_1000t_ctrl_reg
);
964 * Need to parse both autoneg_advertised and fc and set up
965 * the appropriate PHY registers. First we will parse for
966 * autoneg_advertised software override. Since we can advertise
967 * a plethora of combinations, we need to check each bit
972 * First we clear all the 10/100 mb speed bits in the Auto-Neg
973 * Advertisement Register (Address 4) and the 1000 mb speed bits in
974 * the 1000Base-T Control Register (Address 9).
976 mii_autoneg_adv_reg
&= ~(NWAY_AR_100TX_FD_CAPS
|
977 NWAY_AR_100TX_HD_CAPS
|
978 NWAY_AR_10T_FD_CAPS
|
979 NWAY_AR_10T_HD_CAPS
);
980 mii_1000t_ctrl_reg
&= ~(CR_1000T_HD_CAPS
| CR_1000T_FD_CAPS
);
982 hw_dbg(hw
, "autoneg_advertised %x\n", phy
->autoneg_advertised
);
984 /* Do we want to advertise 10 Mb Half Duplex? */
985 if (phy
->autoneg_advertised
& ADVERTISE_10_HALF
) {
986 hw_dbg(hw
, "Advertise 10mb Half duplex\n");
987 mii_autoneg_adv_reg
|= NWAY_AR_10T_HD_CAPS
;
990 /* Do we want to advertise 10 Mb Full Duplex? */
991 if (phy
->autoneg_advertised
& ADVERTISE_10_FULL
) {
992 hw_dbg(hw
, "Advertise 10mb Full duplex\n");
993 mii_autoneg_adv_reg
|= NWAY_AR_10T_FD_CAPS
;
996 /* Do we want to advertise 100 Mb Half Duplex? */
997 if (phy
->autoneg_advertised
& ADVERTISE_100_HALF
) {
998 hw_dbg(hw
, "Advertise 100mb Half duplex\n");
999 mii_autoneg_adv_reg
|= NWAY_AR_100TX_HD_CAPS
;
1002 /* Do we want to advertise 100 Mb Full Duplex? */
1003 if (phy
->autoneg_advertised
& ADVERTISE_100_FULL
) {
1004 hw_dbg(hw
, "Advertise 100mb Full duplex\n");
1005 mii_autoneg_adv_reg
|= NWAY_AR_100TX_FD_CAPS
;
1008 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1009 if (phy
->autoneg_advertised
& ADVERTISE_1000_HALF
)
1010 hw_dbg(hw
, "Advertise 1000mb Half duplex request denied!\n");
1012 /* Do we want to advertise 1000 Mb Full Duplex? */
1013 if (phy
->autoneg_advertised
& ADVERTISE_1000_FULL
) {
1014 hw_dbg(hw
, "Advertise 1000mb Full duplex\n");
1015 mii_1000t_ctrl_reg
|= CR_1000T_FD_CAPS
;
1019 * Check for a software override of the flow control settings, and
1020 * setup the PHY advertisement registers accordingly. If
1021 * auto-negotiation is enabled, then software will have to set the
1022 * "PAUSE" bits to the correct value in the Auto-Negotiation
1023 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
1026 * The possible values of the "fc" parameter are:
1027 * 0: Flow control is completely disabled
1028 * 1: Rx flow control is enabled (we can receive pause frames
1029 * but not send pause frames).
1030 * 2: Tx flow control is enabled (we can send pause frames
1031 * but we do not support receiving pause frames).
1032 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1033 * other: No software override. The flow control configuration
1034 * in the EEPROM is used.
1036 switch (hw
->fc
.current_mode
) {
1039 * Flow control (Rx & Tx) is completely disabled by a
1040 * software over-ride.
1042 mii_autoneg_adv_reg
&= ~(NWAY_AR_ASM_DIR
| NWAY_AR_PAUSE
);
1044 case e1000_fc_rx_pause
:
1046 * Rx Flow control is enabled, and Tx Flow control is
1047 * disabled, by a software over-ride.
1049 * Since there really isn't a way to advertise that we are
1050 * capable of Rx Pause ONLY, we will advertise that we
1051 * support both symmetric and asymmetric Rx PAUSE. Later
1052 * (in e1000e_config_fc_after_link_up) we will disable the
1053 * hw's ability to send PAUSE frames.
1055 mii_autoneg_adv_reg
|= (NWAY_AR_ASM_DIR
| NWAY_AR_PAUSE
);
1057 case e1000_fc_tx_pause
:
1059 * Tx Flow control is enabled, and Rx Flow control is
1060 * disabled, by a software over-ride.
1062 mii_autoneg_adv_reg
|= NWAY_AR_ASM_DIR
;
1063 mii_autoneg_adv_reg
&= ~NWAY_AR_PAUSE
;
1067 * Flow control (both Rx and Tx) is enabled by a software
1070 mii_autoneg_adv_reg
|= (NWAY_AR_ASM_DIR
| NWAY_AR_PAUSE
);
1073 hw_dbg(hw
, "Flow control param set incorrectly\n");
1074 ret_val
= -E1000_ERR_CONFIG
;
1078 ret_val
= e1e_wphy(hw
, PHY_AUTONEG_ADV
, mii_autoneg_adv_reg
);
1082 hw_dbg(hw
, "Auto-Neg Advertising %x\n", mii_autoneg_adv_reg
);
1084 if (phy
->autoneg_mask
& ADVERTISE_1000_FULL
) {
1085 ret_val
= e1e_wphy(hw
, PHY_1000T_CTRL
, mii_1000t_ctrl_reg
);
1092 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
1093 * @hw: pointer to the HW structure
1095 * Performs initial bounds checking on autoneg advertisement parameter, then
1096 * configure to advertise the full capability. Setup the PHY to autoneg
1097 * and restart the negotiation process between the link partner. If
1098 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
1100 static s32
e1000_copper_link_autoneg(struct e1000_hw
*hw
)
1102 struct e1000_phy_info
*phy
= &hw
->phy
;
1107 * Perform some bounds checking on the autoneg advertisement
1110 phy
->autoneg_advertised
&= phy
->autoneg_mask
;
1113 * If autoneg_advertised is zero, we assume it was not defaulted
1114 * by the calling code so we set to advertise full capability.
1116 if (phy
->autoneg_advertised
== 0)
1117 phy
->autoneg_advertised
= phy
->autoneg_mask
;
1119 hw_dbg(hw
, "Reconfiguring auto-neg advertisement params\n");
1120 ret_val
= e1000_phy_setup_autoneg(hw
);
1122 hw_dbg(hw
, "Error Setting up Auto-Negotiation\n");
1125 hw_dbg(hw
, "Restarting Auto-Neg\n");
1128 * Restart auto-negotiation by setting the Auto Neg Enable bit and
1129 * the Auto Neg Restart bit in the PHY control register.
1131 ret_val
= e1e_rphy(hw
, PHY_CONTROL
, &phy_ctrl
);
1135 phy_ctrl
|= (MII_CR_AUTO_NEG_EN
| MII_CR_RESTART_AUTO_NEG
);
1136 ret_val
= e1e_wphy(hw
, PHY_CONTROL
, phy_ctrl
);
1141 * Does the user want to wait for Auto-Neg to complete here, or
1142 * check at a later time (for example, callback routine).
1144 if (phy
->autoneg_wait_to_complete
) {
1145 ret_val
= e1000_wait_autoneg(hw
);
1147 hw_dbg(hw
, "Error while waiting for "
1148 "autoneg to complete\n");
1153 hw
->mac
.get_link_status
= 1;
1159 * e1000e_setup_copper_link - Configure copper link settings
1160 * @hw: pointer to the HW structure
1162 * Calls the appropriate function to configure the link for auto-neg or forced
1163 * speed and duplex. Then we check for link, once link is established calls
1164 * to configure collision distance and flow control are called. If link is
1165 * not established, we return -E1000_ERR_PHY (-2).
1167 s32
e1000e_setup_copper_link(struct e1000_hw
*hw
)
1172 if (hw
->mac
.autoneg
) {
1174 * Setup autoneg and flow control advertisement and perform
1177 ret_val
= e1000_copper_link_autoneg(hw
);
1182 * PHY will be set to 10H, 10F, 100H or 100F
1183 * depending on user settings.
1185 hw_dbg(hw
, "Forcing Speed and Duplex\n");
1186 ret_val
= e1000_phy_force_speed_duplex(hw
);
1188 hw_dbg(hw
, "Error Forcing Speed and Duplex\n");
1194 * Check link status. Wait up to 100 microseconds for link to become
1197 ret_val
= e1000e_phy_has_link_generic(hw
,
1198 COPPER_LINK_UP_LIMIT
,
1205 hw_dbg(hw
, "Valid link established!!!\n");
1206 e1000e_config_collision_dist(hw
);
1207 ret_val
= e1000e_config_fc_after_link_up(hw
);
1209 hw_dbg(hw
, "Unable to establish link!!!\n");
1216 * e1000e_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1217 * @hw: pointer to the HW structure
1219 * Calls the PHY setup function to force speed and duplex. Clears the
1220 * auto-crossover to force MDI manually. Waits for link and returns
1221 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1223 s32
e1000e_phy_force_speed_duplex_igp(struct e1000_hw
*hw
)
1225 struct e1000_phy_info
*phy
= &hw
->phy
;
1230 ret_val
= e1e_rphy(hw
, PHY_CONTROL
, &phy_data
);
1234 e1000e_phy_force_speed_duplex_setup(hw
, &phy_data
);
1236 ret_val
= e1e_wphy(hw
, PHY_CONTROL
, phy_data
);
1241 * Clear Auto-Crossover to force MDI manually. IGP requires MDI
1242 * forced whenever speed and duplex are forced.
1244 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CTRL
, &phy_data
);
1248 phy_data
&= ~IGP01E1000_PSCR_AUTO_MDIX
;
1249 phy_data
&= ~IGP01E1000_PSCR_FORCE_MDI_MDIX
;
1251 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CTRL
, phy_data
);
1255 hw_dbg(hw
, "IGP PSCR: %X\n", phy_data
);
1259 if (phy
->autoneg_wait_to_complete
) {
1260 hw_dbg(hw
, "Waiting for forced speed/duplex link on IGP phy.\n");
1262 ret_val
= e1000e_phy_has_link_generic(hw
,
1270 hw_dbg(hw
, "Link taking longer than expected.\n");
1273 ret_val
= e1000e_phy_has_link_generic(hw
,
1285 * e1000e_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1286 * @hw: pointer to the HW structure
1288 * Calls the PHY setup function to force speed and duplex. Clears the
1289 * auto-crossover to force MDI manually. Resets the PHY to commit the
1290 * changes. If time expires while waiting for link up, we reset the DSP.
1291 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
1292 * successful completion, else return corresponding error code.
1294 s32
e1000e_phy_force_speed_duplex_m88(struct e1000_hw
*hw
)
1296 struct e1000_phy_info
*phy
= &hw
->phy
;
1302 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1303 * forced whenever speed and duplex are forced.
1305 ret_val
= e1e_rphy(hw
, M88E1000_PHY_SPEC_CTRL
, &phy_data
);
1309 phy_data
&= ~M88E1000_PSCR_AUTO_X_MODE
;
1310 ret_val
= e1e_wphy(hw
, M88E1000_PHY_SPEC_CTRL
, phy_data
);
1314 hw_dbg(hw
, "M88E1000 PSCR: %X\n", phy_data
);
1316 ret_val
= e1e_rphy(hw
, PHY_CONTROL
, &phy_data
);
1320 e1000e_phy_force_speed_duplex_setup(hw
, &phy_data
);
1322 ret_val
= e1e_wphy(hw
, PHY_CONTROL
, phy_data
);
1326 /* Reset the phy to commit changes. */
1327 ret_val
= e1000e_commit_phy(hw
);
1331 if (phy
->autoneg_wait_to_complete
) {
1332 hw_dbg(hw
, "Waiting for forced speed/duplex link on M88 phy.\n");
1334 ret_val
= e1000e_phy_has_link_generic(hw
, PHY_FORCE_LIMIT
,
1341 * We didn't get link.
1342 * Reset the DSP and cross our fingers.
1344 ret_val
= e1e_wphy(hw
, M88E1000_PHY_PAGE_SELECT
,
1348 ret_val
= e1000e_phy_reset_dsp(hw
);
1354 ret_val
= e1000e_phy_has_link_generic(hw
, PHY_FORCE_LIMIT
,
1360 ret_val
= e1e_rphy(hw
, M88E1000_EXT_PHY_SPEC_CTRL
, &phy_data
);
1365 * Resetting the phy means we need to re-force TX_CLK in the
1366 * Extended PHY Specific Control Register to 25MHz clock from
1367 * the reset value of 2.5MHz.
1369 phy_data
|= M88E1000_EPSCR_TX_CLK_25
;
1370 ret_val
= e1e_wphy(hw
, M88E1000_EXT_PHY_SPEC_CTRL
, phy_data
);
1375 * In addition, we must re-enable CRS on Tx for both half and full
1378 ret_val
= e1e_rphy(hw
, M88E1000_PHY_SPEC_CTRL
, &phy_data
);
1382 phy_data
|= M88E1000_PSCR_ASSERT_CRS_ON_TX
;
1383 ret_val
= e1e_wphy(hw
, M88E1000_PHY_SPEC_CTRL
, phy_data
);
1389 * e1000e_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1390 * @hw: pointer to the HW structure
1391 * @phy_ctrl: pointer to current value of PHY_CONTROL
1393 * Forces speed and duplex on the PHY by doing the following: disable flow
1394 * control, force speed/duplex on the MAC, disable auto speed detection,
1395 * disable auto-negotiation, configure duplex, configure speed, configure
1396 * the collision distance, write configuration to CTRL register. The
1397 * caller must write to the PHY_CONTROL register for these settings to
1400 void e1000e_phy_force_speed_duplex_setup(struct e1000_hw
*hw
, u16
*phy_ctrl
)
1402 struct e1000_mac_info
*mac
= &hw
->mac
;
1405 /* Turn off flow control when forcing speed/duplex */
1406 hw
->fc
.current_mode
= e1000_fc_none
;
1408 /* Force speed/duplex on the mac */
1410 ctrl
|= (E1000_CTRL_FRCSPD
| E1000_CTRL_FRCDPX
);
1411 ctrl
&= ~E1000_CTRL_SPD_SEL
;
1413 /* Disable Auto Speed Detection */
1414 ctrl
&= ~E1000_CTRL_ASDE
;
1416 /* Disable autoneg on the phy */
1417 *phy_ctrl
&= ~MII_CR_AUTO_NEG_EN
;
1419 /* Forcing Full or Half Duplex? */
1420 if (mac
->forced_speed_duplex
& E1000_ALL_HALF_DUPLEX
) {
1421 ctrl
&= ~E1000_CTRL_FD
;
1422 *phy_ctrl
&= ~MII_CR_FULL_DUPLEX
;
1423 hw_dbg(hw
, "Half Duplex\n");
1425 ctrl
|= E1000_CTRL_FD
;
1426 *phy_ctrl
|= MII_CR_FULL_DUPLEX
;
1427 hw_dbg(hw
, "Full Duplex\n");
1430 /* Forcing 10mb or 100mb? */
1431 if (mac
->forced_speed_duplex
& E1000_ALL_100_SPEED
) {
1432 ctrl
|= E1000_CTRL_SPD_100
;
1433 *phy_ctrl
|= MII_CR_SPEED_100
;
1434 *phy_ctrl
&= ~(MII_CR_SPEED_1000
| MII_CR_SPEED_10
);
1435 hw_dbg(hw
, "Forcing 100mb\n");
1437 ctrl
&= ~(E1000_CTRL_SPD_1000
| E1000_CTRL_SPD_100
);
1438 *phy_ctrl
|= MII_CR_SPEED_10
;
1439 *phy_ctrl
&= ~(MII_CR_SPEED_1000
| MII_CR_SPEED_100
);
1440 hw_dbg(hw
, "Forcing 10mb\n");
1443 e1000e_config_collision_dist(hw
);
1449 * e1000e_set_d3_lplu_state - Sets low power link up state for D3
1450 * @hw: pointer to the HW structure
1451 * @active: boolean used to enable/disable lplu
1453 * Success returns 0, Failure returns 1
1455 * The low power link up (lplu) state is set to the power management level D3
1456 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1457 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1458 * is used during Dx states where the power conservation is most important.
1459 * During driver activity, SmartSpeed should be enabled so performance is
1462 s32
e1000e_set_d3_lplu_state(struct e1000_hw
*hw
, bool active
)
1464 struct e1000_phy_info
*phy
= &hw
->phy
;
1468 ret_val
= e1e_rphy(hw
, IGP02E1000_PHY_POWER_MGMT
, &data
);
1473 data
&= ~IGP02E1000_PM_D3_LPLU
;
1474 ret_val
= e1e_wphy(hw
, IGP02E1000_PHY_POWER_MGMT
, data
);
1478 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1479 * during Dx states where the power conservation is most
1480 * important. During driver activity we should enable
1481 * SmartSpeed, so performance is maintained.
1483 if (phy
->smart_speed
== e1000_smart_speed_on
) {
1484 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
1489 data
|= IGP01E1000_PSCFR_SMART_SPEED
;
1490 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
1494 } else if (phy
->smart_speed
== e1000_smart_speed_off
) {
1495 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
1500 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
1501 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
1506 } else if ((phy
->autoneg_advertised
== E1000_ALL_SPEED_DUPLEX
) ||
1507 (phy
->autoneg_advertised
== E1000_ALL_NOT_GIG
) ||
1508 (phy
->autoneg_advertised
== E1000_ALL_10_SPEED
)) {
1509 data
|= IGP02E1000_PM_D3_LPLU
;
1510 ret_val
= e1e_wphy(hw
, IGP02E1000_PHY_POWER_MGMT
, data
);
1514 /* When LPLU is enabled, we should disable SmartSpeed */
1515 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, &data
);
1519 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
1520 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, data
);
1527 * e1000e_check_downshift - Checks whether a downshift in speed occurred
1528 * @hw: pointer to the HW structure
1530 * Success returns 0, Failure returns 1
1532 * A downshift is detected by querying the PHY link health.
1534 s32
e1000e_check_downshift(struct e1000_hw
*hw
)
1536 struct e1000_phy_info
*phy
= &hw
->phy
;
1538 u16 phy_data
, offset
, mask
;
1540 switch (phy
->type
) {
1542 case e1000_phy_gg82563
:
1543 case e1000_phy_82578
:
1544 case e1000_phy_82577
:
1545 offset
= M88E1000_PHY_SPEC_STATUS
;
1546 mask
= M88E1000_PSSR_DOWNSHIFT
;
1548 case e1000_phy_igp_2
:
1549 case e1000_phy_igp_3
:
1550 offset
= IGP01E1000_PHY_LINK_HEALTH
;
1551 mask
= IGP01E1000_PLHR_SS_DOWNGRADE
;
1554 /* speed downshift not supported */
1555 phy
->speed_downgraded
= 0;
1559 ret_val
= e1e_rphy(hw
, offset
, &phy_data
);
1562 phy
->speed_downgraded
= (phy_data
& mask
);
1568 * e1000_check_polarity_m88 - Checks the polarity.
1569 * @hw: pointer to the HW structure
1571 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1573 * Polarity is determined based on the PHY specific status register.
1575 static s32
e1000_check_polarity_m88(struct e1000_hw
*hw
)
1577 struct e1000_phy_info
*phy
= &hw
->phy
;
1581 ret_val
= e1e_rphy(hw
, M88E1000_PHY_SPEC_STATUS
, &data
);
1584 phy
->cable_polarity
= (data
& M88E1000_PSSR_REV_POLARITY
)
1585 ? e1000_rev_polarity_reversed
1586 : e1000_rev_polarity_normal
;
1592 * e1000_check_polarity_igp - Checks the polarity.
1593 * @hw: pointer to the HW structure
1595 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1597 * Polarity is determined based on the PHY port status register, and the
1598 * current speed (since there is no polarity at 100Mbps).
1600 static s32
e1000_check_polarity_igp(struct e1000_hw
*hw
)
1602 struct e1000_phy_info
*phy
= &hw
->phy
;
1604 u16 data
, offset
, mask
;
1607 * Polarity is determined based on the speed of
1610 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_STATUS
, &data
);
1614 if ((data
& IGP01E1000_PSSR_SPEED_MASK
) ==
1615 IGP01E1000_PSSR_SPEED_1000MBPS
) {
1616 offset
= IGP01E1000_PHY_PCS_INIT_REG
;
1617 mask
= IGP01E1000_PHY_POLARITY_MASK
;
1620 * This really only applies to 10Mbps since
1621 * there is no polarity for 100Mbps (always 0).
1623 offset
= IGP01E1000_PHY_PORT_STATUS
;
1624 mask
= IGP01E1000_PSSR_POLARITY_REVERSED
;
1627 ret_val
= e1e_rphy(hw
, offset
, &data
);
1630 phy
->cable_polarity
= (data
& mask
)
1631 ? e1000_rev_polarity_reversed
1632 : e1000_rev_polarity_normal
;
1638 * e1000_wait_autoneg - Wait for auto-neg completion
1639 * @hw: pointer to the HW structure
1641 * Waits for auto-negotiation to complete or for the auto-negotiation time
1642 * limit to expire, which ever happens first.
1644 static s32
e1000_wait_autoneg(struct e1000_hw
*hw
)
1649 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
1650 for (i
= PHY_AUTO_NEG_LIMIT
; i
> 0; i
--) {
1651 ret_val
= e1e_rphy(hw
, PHY_STATUS
, &phy_status
);
1654 ret_val
= e1e_rphy(hw
, PHY_STATUS
, &phy_status
);
1657 if (phy_status
& MII_SR_AUTONEG_COMPLETE
)
1663 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
1670 * e1000e_phy_has_link_generic - Polls PHY for link
1671 * @hw: pointer to the HW structure
1672 * @iterations: number of times to poll for link
1673 * @usec_interval: delay between polling attempts
1674 * @success: pointer to whether polling was successful or not
1676 * Polls the PHY status register for link, 'iterations' number of times.
1678 s32
e1000e_phy_has_link_generic(struct e1000_hw
*hw
, u32 iterations
,
1679 u32 usec_interval
, bool *success
)
1684 for (i
= 0; i
< iterations
; i
++) {
1686 * Some PHYs require the PHY_STATUS register to be read
1687 * twice due to the link bit being sticky. No harm doing
1688 * it across the board.
1690 ret_val
= e1e_rphy(hw
, PHY_STATUS
, &phy_status
);
1693 * If the first read fails, another entity may have
1694 * ownership of the resources, wait and try again to
1695 * see if they have relinquished the resources yet.
1697 udelay(usec_interval
);
1698 ret_val
= e1e_rphy(hw
, PHY_STATUS
, &phy_status
);
1701 if (phy_status
& MII_SR_LINK_STATUS
)
1703 if (usec_interval
>= 1000)
1704 mdelay(usec_interval
/1000);
1706 udelay(usec_interval
);
1709 *success
= (i
< iterations
);
1715 * e1000e_get_cable_length_m88 - Determine cable length for m88 PHY
1716 * @hw: pointer to the HW structure
1718 * Reads the PHY specific status register to retrieve the cable length
1719 * information. The cable length is determined by averaging the minimum and
1720 * maximum values to get the "average" cable length. The m88 PHY has four
1721 * possible cable length values, which are:
1722 * Register Value Cable Length
1726 * 3 110 - 140 meters
1729 s32
e1000e_get_cable_length_m88(struct e1000_hw
*hw
)
1731 struct e1000_phy_info
*phy
= &hw
->phy
;
1733 u16 phy_data
, index
;
1735 ret_val
= e1e_rphy(hw
, M88E1000_PHY_SPEC_STATUS
, &phy_data
);
1739 index
= (phy_data
& M88E1000_PSSR_CABLE_LENGTH
) >>
1740 M88E1000_PSSR_CABLE_LENGTH_SHIFT
;
1741 phy
->min_cable_length
= e1000_m88_cable_length_table
[index
];
1742 phy
->max_cable_length
= e1000_m88_cable_length_table
[index
+1];
1744 phy
->cable_length
= (phy
->min_cable_length
+ phy
->max_cable_length
) / 2;
1750 * e1000e_get_cable_length_igp_2 - Determine cable length for igp2 PHY
1751 * @hw: pointer to the HW structure
1753 * The automatic gain control (agc) normalizes the amplitude of the
1754 * received signal, adjusting for the attenuation produced by the
1755 * cable. By reading the AGC registers, which represent the
1756 * combination of course and fine gain value, the value can be put
1757 * into a lookup table to obtain the approximate cable length
1760 s32
e1000e_get_cable_length_igp_2(struct e1000_hw
*hw
)
1762 struct e1000_phy_info
*phy
= &hw
->phy
;
1764 u16 phy_data
, i
, agc_value
= 0;
1765 u16 cur_agc_index
, max_agc_index
= 0;
1766 u16 min_agc_index
= IGP02E1000_CABLE_LENGTH_TABLE_SIZE
- 1;
1767 u16 agc_reg_array
[IGP02E1000_PHY_CHANNEL_NUM
] =
1768 {IGP02E1000_PHY_AGC_A
,
1769 IGP02E1000_PHY_AGC_B
,
1770 IGP02E1000_PHY_AGC_C
,
1771 IGP02E1000_PHY_AGC_D
};
1773 /* Read the AGC registers for all channels */
1774 for (i
= 0; i
< IGP02E1000_PHY_CHANNEL_NUM
; i
++) {
1775 ret_val
= e1e_rphy(hw
, agc_reg_array
[i
], &phy_data
);
1780 * Getting bits 15:9, which represent the combination of
1781 * course and fine gain values. The result is a number
1782 * that can be put into the lookup table to obtain the
1783 * approximate cable length.
1785 cur_agc_index
= (phy_data
>> IGP02E1000_AGC_LENGTH_SHIFT
) &
1786 IGP02E1000_AGC_LENGTH_MASK
;
1788 /* Array index bound check. */
1789 if ((cur_agc_index
>= IGP02E1000_CABLE_LENGTH_TABLE_SIZE
) ||
1790 (cur_agc_index
== 0))
1791 return -E1000_ERR_PHY
;
1793 /* Remove min & max AGC values from calculation. */
1794 if (e1000_igp_2_cable_length_table
[min_agc_index
] >
1795 e1000_igp_2_cable_length_table
[cur_agc_index
])
1796 min_agc_index
= cur_agc_index
;
1797 if (e1000_igp_2_cable_length_table
[max_agc_index
] <
1798 e1000_igp_2_cable_length_table
[cur_agc_index
])
1799 max_agc_index
= cur_agc_index
;
1801 agc_value
+= e1000_igp_2_cable_length_table
[cur_agc_index
];
1804 agc_value
-= (e1000_igp_2_cable_length_table
[min_agc_index
] +
1805 e1000_igp_2_cable_length_table
[max_agc_index
]);
1806 agc_value
/= (IGP02E1000_PHY_CHANNEL_NUM
- 2);
1808 /* Calculate cable length with the error range of +/- 10 meters. */
1809 phy
->min_cable_length
= ((agc_value
- IGP02E1000_AGC_RANGE
) > 0) ?
1810 (agc_value
- IGP02E1000_AGC_RANGE
) : 0;
1811 phy
->max_cable_length
= agc_value
+ IGP02E1000_AGC_RANGE
;
1813 phy
->cable_length
= (phy
->min_cable_length
+ phy
->max_cable_length
) / 2;
1819 * e1000e_get_phy_info_m88 - Retrieve PHY information
1820 * @hw: pointer to the HW structure
1822 * Valid for only copper links. Read the PHY status register (sticky read)
1823 * to verify that link is up. Read the PHY special control register to
1824 * determine the polarity and 10base-T extended distance. Read the PHY
1825 * special status register to determine MDI/MDIx and current speed. If
1826 * speed is 1000, then determine cable length, local and remote receiver.
1828 s32
e1000e_get_phy_info_m88(struct e1000_hw
*hw
)
1830 struct e1000_phy_info
*phy
= &hw
->phy
;
1835 if (hw
->phy
.media_type
!= e1000_media_type_copper
) {
1836 hw_dbg(hw
, "Phy info is only valid for copper media\n");
1837 return -E1000_ERR_CONFIG
;
1840 ret_val
= e1000e_phy_has_link_generic(hw
, 1, 0, &link
);
1845 hw_dbg(hw
, "Phy info is only valid if link is up\n");
1846 return -E1000_ERR_CONFIG
;
1849 ret_val
= e1e_rphy(hw
, M88E1000_PHY_SPEC_CTRL
, &phy_data
);
1853 phy
->polarity_correction
= (phy_data
&
1854 M88E1000_PSCR_POLARITY_REVERSAL
);
1856 ret_val
= e1000_check_polarity_m88(hw
);
1860 ret_val
= e1e_rphy(hw
, M88E1000_PHY_SPEC_STATUS
, &phy_data
);
1864 phy
->is_mdix
= (phy_data
& M88E1000_PSSR_MDIX
);
1866 if ((phy_data
& M88E1000_PSSR_SPEED
) == M88E1000_PSSR_1000MBS
) {
1867 ret_val
= e1000_get_cable_length(hw
);
1871 ret_val
= e1e_rphy(hw
, PHY_1000T_STATUS
, &phy_data
);
1875 phy
->local_rx
= (phy_data
& SR_1000T_LOCAL_RX_STATUS
)
1876 ? e1000_1000t_rx_status_ok
1877 : e1000_1000t_rx_status_not_ok
;
1879 phy
->remote_rx
= (phy_data
& SR_1000T_REMOTE_RX_STATUS
)
1880 ? e1000_1000t_rx_status_ok
1881 : e1000_1000t_rx_status_not_ok
;
1883 /* Set values to "undefined" */
1884 phy
->cable_length
= E1000_CABLE_LENGTH_UNDEFINED
;
1885 phy
->local_rx
= e1000_1000t_rx_status_undefined
;
1886 phy
->remote_rx
= e1000_1000t_rx_status_undefined
;
1893 * e1000e_get_phy_info_igp - Retrieve igp PHY information
1894 * @hw: pointer to the HW structure
1896 * Read PHY status to determine if link is up. If link is up, then
1897 * set/determine 10base-T extended distance and polarity correction. Read
1898 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
1899 * determine on the cable length, local and remote receiver.
1901 s32
e1000e_get_phy_info_igp(struct e1000_hw
*hw
)
1903 struct e1000_phy_info
*phy
= &hw
->phy
;
1908 ret_val
= e1000e_phy_has_link_generic(hw
, 1, 0, &link
);
1913 hw_dbg(hw
, "Phy info is only valid if link is up\n");
1914 return -E1000_ERR_CONFIG
;
1917 phy
->polarity_correction
= 1;
1919 ret_val
= e1000_check_polarity_igp(hw
);
1923 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_STATUS
, &data
);
1927 phy
->is_mdix
= (data
& IGP01E1000_PSSR_MDIX
);
1929 if ((data
& IGP01E1000_PSSR_SPEED_MASK
) ==
1930 IGP01E1000_PSSR_SPEED_1000MBPS
) {
1931 ret_val
= e1000_get_cable_length(hw
);
1935 ret_val
= e1e_rphy(hw
, PHY_1000T_STATUS
, &data
);
1939 phy
->local_rx
= (data
& SR_1000T_LOCAL_RX_STATUS
)
1940 ? e1000_1000t_rx_status_ok
1941 : e1000_1000t_rx_status_not_ok
;
1943 phy
->remote_rx
= (data
& SR_1000T_REMOTE_RX_STATUS
)
1944 ? e1000_1000t_rx_status_ok
1945 : e1000_1000t_rx_status_not_ok
;
1947 phy
->cable_length
= E1000_CABLE_LENGTH_UNDEFINED
;
1948 phy
->local_rx
= e1000_1000t_rx_status_undefined
;
1949 phy
->remote_rx
= e1000_1000t_rx_status_undefined
;
1956 * e1000e_phy_sw_reset - PHY software reset
1957 * @hw: pointer to the HW structure
1959 * Does a software reset of the PHY by reading the PHY control register and
1960 * setting/write the control register reset bit to the PHY.
1962 s32
e1000e_phy_sw_reset(struct e1000_hw
*hw
)
1967 ret_val
= e1e_rphy(hw
, PHY_CONTROL
, &phy_ctrl
);
1971 phy_ctrl
|= MII_CR_RESET
;
1972 ret_val
= e1e_wphy(hw
, PHY_CONTROL
, phy_ctrl
);
1982 * e1000e_phy_hw_reset_generic - PHY hardware reset
1983 * @hw: pointer to the HW structure
1985 * Verify the reset block is not blocking us from resetting. Acquire
1986 * semaphore (if necessary) and read/set/write the device control reset
1987 * bit in the PHY. Wait the appropriate delay time for the device to
1988 * reset and release the semaphore (if necessary).
1990 s32
e1000e_phy_hw_reset_generic(struct e1000_hw
*hw
)
1992 struct e1000_phy_info
*phy
= &hw
->phy
;
1996 ret_val
= e1000_check_reset_block(hw
);
2000 ret_val
= phy
->ops
.acquire_phy(hw
);
2005 ew32(CTRL
, ctrl
| E1000_CTRL_PHY_RST
);
2008 udelay(phy
->reset_delay_us
);
2015 phy
->ops
.release_phy(hw
);
2017 return e1000_get_phy_cfg_done(hw
);
2021 * e1000e_get_cfg_done - Generic configuration done
2022 * @hw: pointer to the HW structure
2024 * Generic function to wait 10 milli-seconds for configuration to complete
2025 * and return success.
2027 s32
e1000e_get_cfg_done(struct e1000_hw
*hw
)
2034 * e1000e_phy_init_script_igp3 - Inits the IGP3 PHY
2035 * @hw: pointer to the HW structure
2037 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2039 s32
e1000e_phy_init_script_igp3(struct e1000_hw
*hw
)
2041 hw_dbg(hw
, "Running IGP 3 PHY init script\n");
2043 /* PHY init IGP 3 */
2044 /* Enable rise/fall, 10-mode work in class-A */
2045 e1e_wphy(hw
, 0x2F5B, 0x9018);
2046 /* Remove all caps from Replica path filter */
2047 e1e_wphy(hw
, 0x2F52, 0x0000);
2048 /* Bias trimming for ADC, AFE and Driver (Default) */
2049 e1e_wphy(hw
, 0x2FB1, 0x8B24);
2050 /* Increase Hybrid poly bias */
2051 e1e_wphy(hw
, 0x2FB2, 0xF8F0);
2052 /* Add 4% to Tx amplitude in Gig mode */
2053 e1e_wphy(hw
, 0x2010, 0x10B0);
2054 /* Disable trimming (TTT) */
2055 e1e_wphy(hw
, 0x2011, 0x0000);
2056 /* Poly DC correction to 94.6% + 2% for all channels */
2057 e1e_wphy(hw
, 0x20DD, 0x249A);
2058 /* ABS DC correction to 95.9% */
2059 e1e_wphy(hw
, 0x20DE, 0x00D3);
2060 /* BG temp curve trim */
2061 e1e_wphy(hw
, 0x28B4, 0x04CE);
2062 /* Increasing ADC OPAMP stage 1 currents to max */
2063 e1e_wphy(hw
, 0x2F70, 0x29E4);
2064 /* Force 1000 ( required for enabling PHY regs configuration) */
2065 e1e_wphy(hw
, 0x0000, 0x0140);
2066 /* Set upd_freq to 6 */
2067 e1e_wphy(hw
, 0x1F30, 0x1606);
2069 e1e_wphy(hw
, 0x1F31, 0xB814);
2070 /* Disable adaptive fixed FFE (Default) */
2071 e1e_wphy(hw
, 0x1F35, 0x002A);
2072 /* Enable FFE hysteresis */
2073 e1e_wphy(hw
, 0x1F3E, 0x0067);
2074 /* Fixed FFE for short cable lengths */
2075 e1e_wphy(hw
, 0x1F54, 0x0065);
2076 /* Fixed FFE for medium cable lengths */
2077 e1e_wphy(hw
, 0x1F55, 0x002A);
2078 /* Fixed FFE for long cable lengths */
2079 e1e_wphy(hw
, 0x1F56, 0x002A);
2080 /* Enable Adaptive Clip Threshold */
2081 e1e_wphy(hw
, 0x1F72, 0x3FB0);
2082 /* AHT reset limit to 1 */
2083 e1e_wphy(hw
, 0x1F76, 0xC0FF);
2084 /* Set AHT master delay to 127 msec */
2085 e1e_wphy(hw
, 0x1F77, 0x1DEC);
2086 /* Set scan bits for AHT */
2087 e1e_wphy(hw
, 0x1F78, 0xF9EF);
2088 /* Set AHT Preset bits */
2089 e1e_wphy(hw
, 0x1F79, 0x0210);
2090 /* Change integ_factor of channel A to 3 */
2091 e1e_wphy(hw
, 0x1895, 0x0003);
2092 /* Change prop_factor of channels BCD to 8 */
2093 e1e_wphy(hw
, 0x1796, 0x0008);
2094 /* Change cg_icount + enable integbp for channels BCD */
2095 e1e_wphy(hw
, 0x1798, 0xD008);
2097 * Change cg_icount + enable integbp + change prop_factor_master
2098 * to 8 for channel A
2100 e1e_wphy(hw
, 0x1898, 0xD918);
2101 /* Disable AHT in Slave mode on channel A */
2102 e1e_wphy(hw
, 0x187A, 0x0800);
2104 * Enable LPLU and disable AN to 1000 in non-D0a states,
2107 e1e_wphy(hw
, 0x0019, 0x008D);
2108 /* Enable restart AN on an1000_dis change */
2109 e1e_wphy(hw
, 0x001B, 0x2080);
2110 /* Enable wh_fifo read clock in 10/100 modes */
2111 e1e_wphy(hw
, 0x0014, 0x0045);
2112 /* Restart AN, Speed selection is 1000 */
2113 e1e_wphy(hw
, 0x0000, 0x1340);
2118 /* Internal function pointers */
2121 * e1000_get_phy_cfg_done - Generic PHY configuration done
2122 * @hw: pointer to the HW structure
2124 * Return success if silicon family did not implement a family specific
2125 * get_cfg_done function.
2127 static s32
e1000_get_phy_cfg_done(struct e1000_hw
*hw
)
2129 if (hw
->phy
.ops
.get_cfg_done
)
2130 return hw
->phy
.ops
.get_cfg_done(hw
);
2136 * e1000_phy_force_speed_duplex - Generic force PHY speed/duplex
2137 * @hw: pointer to the HW structure
2139 * When the silicon family has not implemented a forced speed/duplex
2140 * function for the PHY, simply return 0.
2142 static s32
e1000_phy_force_speed_duplex(struct e1000_hw
*hw
)
2144 if (hw
->phy
.ops
.force_speed_duplex
)
2145 return hw
->phy
.ops
.force_speed_duplex(hw
);
2151 * e1000e_get_phy_type_from_id - Get PHY type from id
2152 * @phy_id: phy_id read from the phy
2154 * Returns the phy type from the id.
2156 enum e1000_phy_type
e1000e_get_phy_type_from_id(u32 phy_id
)
2158 enum e1000_phy_type phy_type
= e1000_phy_unknown
;
2161 case M88E1000_I_PHY_ID
:
2162 case M88E1000_E_PHY_ID
:
2163 case M88E1111_I_PHY_ID
:
2164 case M88E1011_I_PHY_ID
:
2165 phy_type
= e1000_phy_m88
;
2167 case IGP01E1000_I_PHY_ID
: /* IGP 1 & 2 share this */
2168 phy_type
= e1000_phy_igp_2
;
2170 case GG82563_E_PHY_ID
:
2171 phy_type
= e1000_phy_gg82563
;
2173 case IGP03E1000_E_PHY_ID
:
2174 phy_type
= e1000_phy_igp_3
;
2177 case IFE_PLUS_E_PHY_ID
:
2178 case IFE_C_E_PHY_ID
:
2179 phy_type
= e1000_phy_ife
;
2181 case BME1000_E_PHY_ID
:
2182 case BME1000_E_PHY_ID_R2
:
2183 phy_type
= e1000_phy_bm
;
2185 case I82578_E_PHY_ID
:
2186 phy_type
= e1000_phy_82578
;
2188 case I82577_E_PHY_ID
:
2189 phy_type
= e1000_phy_82577
;
2192 phy_type
= e1000_phy_unknown
;
2199 * e1000e_determine_phy_address - Determines PHY address.
2200 * @hw: pointer to the HW structure
2202 * This uses a trial and error method to loop through possible PHY
2203 * addresses. It tests each by reading the PHY ID registers and
2204 * checking for a match.
2206 s32
e1000e_determine_phy_address(struct e1000_hw
*hw
)
2208 s32 ret_val
= -E1000_ERR_PHY_TYPE
;
2211 enum e1000_phy_type phy_type
= e1000_phy_unknown
;
2214 for (phy_addr
= 0; phy_addr
< 4; phy_addr
++) {
2215 hw
->phy
.addr
= phy_addr
;
2216 e1000e_get_phy_id(hw
);
2217 phy_type
= e1000e_get_phy_type_from_id(hw
->phy
.id
);
2220 * If phy_type is valid, break - we found our
2223 if (phy_type
!= e1000_phy_unknown
) {
2229 } while ((ret_val
!= 0) && (i
< 100));
2235 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address
2236 * @page: page to access
2238 * Returns the phy address for the page requested.
2240 static u32
e1000_get_phy_addr_for_bm_page(u32 page
, u32 reg
)
2244 if ((page
>= 768) || (page
== 0 && reg
== 25) || (reg
== 31))
2251 * e1000e_write_phy_reg_bm - Write BM PHY register
2252 * @hw: pointer to the HW structure
2253 * @offset: register offset to write to
2254 * @data: data to write at register offset
2256 * Acquires semaphore, if necessary, then writes the data to PHY register
2257 * at the offset. Release any acquired semaphores before exiting.
2259 s32
e1000e_write_phy_reg_bm(struct e1000_hw
*hw
, u32 offset
, u16 data
)
2262 u32 page_select
= 0;
2263 u32 page
= offset
>> IGP_PAGE_SHIFT
;
2266 ret_val
= hw
->phy
.ops
.acquire_phy(hw
);
2270 /* Page 800 works differently than the rest so it has its own func */
2271 if (page
== BM_WUC_PAGE
) {
2272 ret_val
= e1000_access_phy_wakeup_reg_bm(hw
, offset
, &data
,
2277 hw
->phy
.addr
= e1000_get_phy_addr_for_bm_page(page
, offset
);
2279 if (offset
> MAX_PHY_MULTI_PAGE_REG
) {
2281 * Page select is register 31 for phy address 1 and 22 for
2282 * phy address 2 and 3. Page select is shifted only for
2285 if (hw
->phy
.addr
== 1) {
2286 page_shift
= IGP_PAGE_SHIFT
;
2287 page_select
= IGP01E1000_PHY_PAGE_SELECT
;
2290 page_select
= BM_PHY_PAGE_SELECT
;
2293 /* Page is shifted left, PHY expects (page x 32) */
2294 ret_val
= e1000e_write_phy_reg_mdic(hw
, page_select
,
2295 (page
<< page_shift
));
2300 ret_val
= e1000e_write_phy_reg_mdic(hw
, MAX_PHY_REG_ADDRESS
& offset
,
2304 hw
->phy
.ops
.release_phy(hw
);
2309 * e1000e_read_phy_reg_bm - Read BM PHY register
2310 * @hw: pointer to the HW structure
2311 * @offset: register offset to be read
2312 * @data: pointer to the read data
2314 * Acquires semaphore, if necessary, then reads the PHY register at offset
2315 * and storing the retrieved information in data. Release any acquired
2316 * semaphores before exiting.
2318 s32
e1000e_read_phy_reg_bm(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
2321 u32 page_select
= 0;
2322 u32 page
= offset
>> IGP_PAGE_SHIFT
;
2325 ret_val
= hw
->phy
.ops
.acquire_phy(hw
);
2329 /* Page 800 works differently than the rest so it has its own func */
2330 if (page
== BM_WUC_PAGE
) {
2331 ret_val
= e1000_access_phy_wakeup_reg_bm(hw
, offset
, data
,
2336 hw
->phy
.addr
= e1000_get_phy_addr_for_bm_page(page
, offset
);
2338 if (offset
> MAX_PHY_MULTI_PAGE_REG
) {
2340 * Page select is register 31 for phy address 1 and 22 for
2341 * phy address 2 and 3. Page select is shifted only for
2344 if (hw
->phy
.addr
== 1) {
2345 page_shift
= IGP_PAGE_SHIFT
;
2346 page_select
= IGP01E1000_PHY_PAGE_SELECT
;
2349 page_select
= BM_PHY_PAGE_SELECT
;
2352 /* Page is shifted left, PHY expects (page x 32) */
2353 ret_val
= e1000e_write_phy_reg_mdic(hw
, page_select
,
2354 (page
<< page_shift
));
2359 ret_val
= e1000e_read_phy_reg_mdic(hw
, MAX_PHY_REG_ADDRESS
& offset
,
2362 hw
->phy
.ops
.release_phy(hw
);
2367 * e1000e_read_phy_reg_bm2 - Read BM PHY register
2368 * @hw: pointer to the HW structure
2369 * @offset: register offset to be read
2370 * @data: pointer to the read data
2372 * Acquires semaphore, if necessary, then reads the PHY register at offset
2373 * and storing the retrieved information in data. Release any acquired
2374 * semaphores before exiting.
2376 s32
e1000e_read_phy_reg_bm2(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
2379 u16 page
= (u16
)(offset
>> IGP_PAGE_SHIFT
);
2381 ret_val
= hw
->phy
.ops
.acquire_phy(hw
);
2385 /* Page 800 works differently than the rest so it has its own func */
2386 if (page
== BM_WUC_PAGE
) {
2387 ret_val
= e1000_access_phy_wakeup_reg_bm(hw
, offset
, data
,
2394 if (offset
> MAX_PHY_MULTI_PAGE_REG
) {
2396 /* Page is shifted left, PHY expects (page x 32) */
2397 ret_val
= e1000e_write_phy_reg_mdic(hw
, BM_PHY_PAGE_SELECT
,
2404 ret_val
= e1000e_read_phy_reg_mdic(hw
, MAX_PHY_REG_ADDRESS
& offset
,
2407 hw
->phy
.ops
.release_phy(hw
);
2412 * e1000e_write_phy_reg_bm2 - Write BM PHY register
2413 * @hw: pointer to the HW structure
2414 * @offset: register offset to write to
2415 * @data: data to write at register offset
2417 * Acquires semaphore, if necessary, then writes the data to PHY register
2418 * at the offset. Release any acquired semaphores before exiting.
2420 s32
e1000e_write_phy_reg_bm2(struct e1000_hw
*hw
, u32 offset
, u16 data
)
2423 u16 page
= (u16
)(offset
>> IGP_PAGE_SHIFT
);
2425 ret_val
= hw
->phy
.ops
.acquire_phy(hw
);
2429 /* Page 800 works differently than the rest so it has its own func */
2430 if (page
== BM_WUC_PAGE
) {
2431 ret_val
= e1000_access_phy_wakeup_reg_bm(hw
, offset
, &data
,
2438 if (offset
> MAX_PHY_MULTI_PAGE_REG
) {
2439 /* Page is shifted left, PHY expects (page x 32) */
2440 ret_val
= e1000e_write_phy_reg_mdic(hw
, BM_PHY_PAGE_SELECT
,
2447 ret_val
= e1000e_write_phy_reg_mdic(hw
, MAX_PHY_REG_ADDRESS
& offset
,
2451 hw
->phy
.ops
.release_phy(hw
);
2456 * e1000_access_phy_wakeup_reg_bm - Read BM PHY wakeup register
2457 * @hw: pointer to the HW structure
2458 * @offset: register offset to be read or written
2459 * @data: pointer to the data to read or write
2460 * @read: determines if operation is read or write
2462 * Acquires semaphore, if necessary, then reads the PHY register at offset
2463 * and storing the retrieved information in data. Release any acquired
2464 * semaphores before exiting. Note that procedure to read the wakeup
2465 * registers are different. It works as such:
2466 * 1) Set page 769, register 17, bit 2 = 1
2467 * 2) Set page to 800 for host (801 if we were manageability)
2468 * 3) Write the address using the address opcode (0x11)
2469 * 4) Read or write the data using the data opcode (0x12)
2470 * 5) Restore 769_17.2 to its original value
2472 * Assumes semaphore already acquired.
2474 static s32
e1000_access_phy_wakeup_reg_bm(struct e1000_hw
*hw
, u32 offset
,
2475 u16
*data
, bool read
)
2478 u16 reg
= BM_PHY_REG_NUM(offset
);
2481 /* Gig must be disabled for MDIO accesses to page 800 */
2482 if ((hw
->mac
.type
== e1000_pchlan
) &&
2483 (!(er32(PHY_CTRL
) & E1000_PHY_CTRL_GBE_DISABLE
)))
2484 hw_dbg(hw
, "Attempting to access page 800 while gig enabled\n");
2486 /* All operations in this function are phy address 1 */
2490 e1000e_write_phy_reg_mdic(hw
, IGP01E1000_PHY_PAGE_SELECT
,
2491 (BM_WUC_ENABLE_PAGE
<< IGP_PAGE_SHIFT
));
2493 ret_val
= e1000e_read_phy_reg_mdic(hw
, BM_WUC_ENABLE_REG
, &phy_reg
);
2497 /* First clear bit 4 to avoid a power state change */
2498 phy_reg
&= ~(BM_WUC_HOST_WU_BIT
);
2499 ret_val
= e1000e_write_phy_reg_mdic(hw
, BM_WUC_ENABLE_REG
, phy_reg
);
2503 /* Write bit 2 = 1, and clear bit 4 to 769_17 */
2504 ret_val
= e1000e_write_phy_reg_mdic(hw
, BM_WUC_ENABLE_REG
,
2505 phy_reg
| BM_WUC_ENABLE_BIT
);
2509 /* Select page 800 */
2510 ret_val
= e1000e_write_phy_reg_mdic(hw
, IGP01E1000_PHY_PAGE_SELECT
,
2511 (BM_WUC_PAGE
<< IGP_PAGE_SHIFT
));
2513 /* Write the page 800 offset value using opcode 0x11 */
2514 ret_val
= e1000e_write_phy_reg_mdic(hw
, BM_WUC_ADDRESS_OPCODE
, reg
);
2519 /* Read the page 800 value using opcode 0x12 */
2520 ret_val
= e1000e_read_phy_reg_mdic(hw
, BM_WUC_DATA_OPCODE
,
2523 /* Read the page 800 value using opcode 0x12 */
2524 ret_val
= e1000e_write_phy_reg_mdic(hw
, BM_WUC_DATA_OPCODE
,
2532 * Restore 769_17.2 to its original value
2535 e1000e_write_phy_reg_mdic(hw
, IGP01E1000_PHY_PAGE_SELECT
,
2536 (BM_WUC_ENABLE_PAGE
<< IGP_PAGE_SHIFT
));
2538 /* Clear 769_17.2 */
2539 ret_val
= e1000e_write_phy_reg_mdic(hw
, BM_WUC_ENABLE_REG
, phy_reg
);
2546 * e1000e_commit_phy - Soft PHY reset
2547 * @hw: pointer to the HW structure
2549 * Performs a soft PHY reset on those that apply. This is a function pointer
2550 * entry point called by drivers.
2552 s32
e1000e_commit_phy(struct e1000_hw
*hw
)
2554 if (hw
->phy
.ops
.commit_phy
)
2555 return hw
->phy
.ops
.commit_phy(hw
);
2561 * e1000_set_d0_lplu_state - Sets low power link up state for D0
2562 * @hw: pointer to the HW structure
2563 * @active: boolean used to enable/disable lplu
2565 * Success returns 0, Failure returns 1
2567 * The low power link up (lplu) state is set to the power management level D0
2568 * and SmartSpeed is disabled when active is true, else clear lplu for D0
2569 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
2570 * is used during Dx states where the power conservation is most important.
2571 * During driver activity, SmartSpeed should be enabled so performance is
2572 * maintained. This is a function pointer entry point called by drivers.
2574 static s32
e1000_set_d0_lplu_state(struct e1000_hw
*hw
, bool active
)
2576 if (hw
->phy
.ops
.set_d0_lplu_state
)
2577 return hw
->phy
.ops
.set_d0_lplu_state(hw
, active
);
2583 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2584 * @hw: pointer to the HW structure
2585 * @slow: true for slow mode, false for normal mode
2587 * Assumes semaphore already acquired.
2589 s32
e1000_set_mdio_slow_mode_hv(struct e1000_hw
*hw
, bool slow
)
2594 /* Set MDIO mode - page 769, register 16: 0x2580==slow, 0x2180==fast */
2596 ret_val
= e1000e_write_phy_reg_mdic(hw
, IGP01E1000_PHY_PAGE_SELECT
,
2597 (BM_PORT_CTRL_PAGE
<< IGP_PAGE_SHIFT
));
2601 ret_val
= e1000e_write_phy_reg_mdic(hw
, BM_CS_CTRL1
,
2602 (0x2180 | (slow
<< 10)));
2606 /* dummy read when reverting to fast mode - throw away result */
2608 ret_val
= e1000e_read_phy_reg_mdic(hw
, BM_CS_CTRL1
, &data
);
2615 * __e1000_read_phy_reg_hv - Read HV PHY register
2616 * @hw: pointer to the HW structure
2617 * @offset: register offset to be read
2618 * @data: pointer to the read data
2619 * @locked: semaphore has already been acquired or not
2621 * Acquires semaphore, if necessary, then reads the PHY register at offset
2622 * and stores the retrieved information in data. Release any acquired
2623 * semaphore before exiting.
2625 static s32
__e1000_read_phy_reg_hv(struct e1000_hw
*hw
, u32 offset
, u16
*data
,
2629 u16 page
= BM_PHY_REG_PAGE(offset
);
2630 u16 reg
= BM_PHY_REG_NUM(offset
);
2631 bool in_slow_mode
= false;
2634 ret_val
= hw
->phy
.ops
.acquire_phy(hw
);
2639 /* Workaround failure in MDIO access while cable is disconnected */
2640 if ((hw
->phy
.type
== e1000_phy_82577
) &&
2641 !(er32(STATUS
) & E1000_STATUS_LU
)) {
2642 ret_val
= e1000_set_mdio_slow_mode_hv(hw
, true);
2646 in_slow_mode
= true;
2649 /* Page 800 works differently than the rest so it has its own func */
2650 if (page
== BM_WUC_PAGE
) {
2651 ret_val
= e1000_access_phy_wakeup_reg_bm(hw
, offset
,
2656 if (page
> 0 && page
< HV_INTC_FC_PAGE_START
) {
2657 ret_val
= e1000_access_phy_debug_regs_hv(hw
, offset
,
2662 hw
->phy
.addr
= e1000_get_phy_addr_for_hv_page(page
);
2664 if (page
== HV_INTC_FC_PAGE_START
)
2667 if (reg
> MAX_PHY_MULTI_PAGE_REG
) {
2668 if ((hw
->phy
.type
!= e1000_phy_82578
) ||
2669 ((reg
!= I82578_ADDR_REG
) &&
2670 (reg
!= I82578_ADDR_REG
+ 1))) {
2671 u32 phy_addr
= hw
->phy
.addr
;
2675 /* Page is shifted left, PHY expects (page x 32) */
2676 ret_val
= e1000e_write_phy_reg_mdic(hw
,
2677 IGP01E1000_PHY_PAGE_SELECT
,
2678 (page
<< IGP_PAGE_SHIFT
));
2679 hw
->phy
.addr
= phy_addr
;
2683 ret_val
= e1000e_read_phy_reg_mdic(hw
, MAX_PHY_REG_ADDRESS
& reg
,
2686 /* Revert to MDIO fast mode, if applicable */
2687 if ((hw
->phy
.type
== e1000_phy_82577
) && in_slow_mode
)
2688 ret_val
= e1000_set_mdio_slow_mode_hv(hw
, false);
2691 hw
->phy
.ops
.release_phy(hw
);
2697 * e1000_read_phy_reg_hv - Read HV PHY register
2698 * @hw: pointer to the HW structure
2699 * @offset: register offset to be read
2700 * @data: pointer to the read data
2702 * Acquires semaphore then reads the PHY register at offset and stores
2703 * the retrieved information in data. Release the acquired semaphore
2706 s32
e1000_read_phy_reg_hv(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
2708 return __e1000_read_phy_reg_hv(hw
, offset
, data
, false);
2712 * e1000_read_phy_reg_hv_locked - Read HV PHY register
2713 * @hw: pointer to the HW structure
2714 * @offset: register offset to be read
2715 * @data: pointer to the read data
2717 * Reads the PHY register at offset and stores the retrieved information
2718 * in data. Assumes semaphore already acquired.
2720 s32
e1000_read_phy_reg_hv_locked(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
2722 return __e1000_read_phy_reg_hv(hw
, offset
, data
, true);
2726 * __e1000_write_phy_reg_hv - Write HV PHY register
2727 * @hw: pointer to the HW structure
2728 * @offset: register offset to write to
2729 * @data: data to write at register offset
2730 * @locked: semaphore has already been acquired or not
2732 * Acquires semaphore, if necessary, then writes the data to PHY register
2733 * at the offset. Release any acquired semaphores before exiting.
2735 static s32
__e1000_write_phy_reg_hv(struct e1000_hw
*hw
, u32 offset
, u16 data
,
2739 u16 page
= BM_PHY_REG_PAGE(offset
);
2740 u16 reg
= BM_PHY_REG_NUM(offset
);
2741 bool in_slow_mode
= false;
2744 ret_val
= hw
->phy
.ops
.acquire_phy(hw
);
2749 /* Workaround failure in MDIO access while cable is disconnected */
2750 if ((hw
->phy
.type
== e1000_phy_82577
) &&
2751 !(er32(STATUS
) & E1000_STATUS_LU
)) {
2752 ret_val
= e1000_set_mdio_slow_mode_hv(hw
, true);
2756 in_slow_mode
= true;
2759 /* Page 800 works differently than the rest so it has its own func */
2760 if (page
== BM_WUC_PAGE
) {
2761 ret_val
= e1000_access_phy_wakeup_reg_bm(hw
, offset
,
2766 if (page
> 0 && page
< HV_INTC_FC_PAGE_START
) {
2767 ret_val
= e1000_access_phy_debug_regs_hv(hw
, offset
,
2772 hw
->phy
.addr
= e1000_get_phy_addr_for_hv_page(page
);
2774 if (page
== HV_INTC_FC_PAGE_START
)
2778 * Workaround MDIO accesses being disabled after entering IEEE Power
2779 * Down (whenever bit 11 of the PHY Control register is set)
2781 if ((hw
->phy
.type
== e1000_phy_82578
) &&
2782 (hw
->phy
.revision
>= 1) &&
2783 (hw
->phy
.addr
== 2) &&
2784 ((MAX_PHY_REG_ADDRESS
& reg
) == 0) &&
2785 (data
& (1 << 11))) {
2787 ret_val
= e1000_access_phy_debug_regs_hv(hw
, (1 << 6) | 0x3,
2793 if (reg
> MAX_PHY_MULTI_PAGE_REG
) {
2794 if ((hw
->phy
.type
!= e1000_phy_82578
) ||
2795 ((reg
!= I82578_ADDR_REG
) &&
2796 (reg
!= I82578_ADDR_REG
+ 1))) {
2797 u32 phy_addr
= hw
->phy
.addr
;
2801 /* Page is shifted left, PHY expects (page x 32) */
2802 ret_val
= e1000e_write_phy_reg_mdic(hw
,
2803 IGP01E1000_PHY_PAGE_SELECT
,
2804 (page
<< IGP_PAGE_SHIFT
));
2805 hw
->phy
.addr
= phy_addr
;
2809 ret_val
= e1000e_write_phy_reg_mdic(hw
, MAX_PHY_REG_ADDRESS
& reg
,
2813 /* Revert to MDIO fast mode, if applicable */
2814 if ((hw
->phy
.type
== e1000_phy_82577
) && in_slow_mode
)
2815 ret_val
= e1000_set_mdio_slow_mode_hv(hw
, false);
2818 hw
->phy
.ops
.release_phy(hw
);
2824 * e1000_write_phy_reg_hv - Write HV PHY register
2825 * @hw: pointer to the HW structure
2826 * @offset: register offset to write to
2827 * @data: data to write at register offset
2829 * Acquires semaphore then writes the data to PHY register at the offset.
2830 * Release the acquired semaphores before exiting.
2832 s32
e1000_write_phy_reg_hv(struct e1000_hw
*hw
, u32 offset
, u16 data
)
2834 return __e1000_write_phy_reg_hv(hw
, offset
, data
, false);
2838 * e1000_write_phy_reg_hv_locked - Write HV PHY register
2839 * @hw: pointer to the HW structure
2840 * @offset: register offset to write to
2841 * @data: data to write at register offset
2843 * Writes the data to PHY register at the offset. Assumes semaphore
2846 s32
e1000_write_phy_reg_hv_locked(struct e1000_hw
*hw
, u32 offset
, u16 data
)
2848 return __e1000_write_phy_reg_hv(hw
, offset
, data
, true);
2852 * e1000_get_phy_addr_for_hv_page - Get PHY adrress based on page
2853 * @page: page to be accessed
2855 static u32
e1000_get_phy_addr_for_hv_page(u32 page
)
2859 if (page
>= HV_INTC_FC_PAGE_START
)
2866 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers
2867 * @hw: pointer to the HW structure
2868 * @offset: register offset to be read or written
2869 * @data: pointer to the data to be read or written
2870 * @read: determines if operation is read or written
2872 * Reads the PHY register at offset and stores the retreived information
2873 * in data. Assumes semaphore already acquired. Note that the procedure
2874 * to read these regs uses the address port and data port to read/write.
2876 static s32
e1000_access_phy_debug_regs_hv(struct e1000_hw
*hw
, u32 offset
,
2877 u16
*data
, bool read
)
2883 /* This takes care of the difference with desktop vs mobile phy */
2884 addr_reg
= (hw
->phy
.type
== e1000_phy_82578
) ?
2885 I82578_ADDR_REG
: I82577_ADDR_REG
;
2886 data_reg
= addr_reg
+ 1;
2888 /* All operations in this function are phy address 2 */
2891 /* masking with 0x3F to remove the page from offset */
2892 ret_val
= e1000e_write_phy_reg_mdic(hw
, addr_reg
, (u16
)offset
& 0x3F);
2894 hw_dbg(hw
, "Could not write PHY the HV address register\n");
2898 /* Read or write the data value next */
2900 ret_val
= e1000e_read_phy_reg_mdic(hw
, data_reg
, data
);
2902 ret_val
= e1000e_write_phy_reg_mdic(hw
, data_reg
, *data
);
2905 hw_dbg(hw
, "Could not read data value from HV data register\n");
2914 * e1000_link_stall_workaround_hv - Si workaround
2915 * @hw: pointer to the HW structure
2917 * This function works around a Si bug where the link partner can get
2918 * a link up indication before the PHY does. If small packets are sent
2919 * by the link partner they can be placed in the packet buffer without
2920 * being properly accounted for by the PHY and will stall preventing
2921 * further packets from being received. The workaround is to clear the
2922 * packet buffer after the PHY detects link up.
2924 s32
e1000_link_stall_workaround_hv(struct e1000_hw
*hw
)
2929 if (hw
->phy
.type
!= e1000_phy_82578
)
2932 /* Do not apply workaround if in PHY loopback bit 14 set */
2933 hw
->phy
.ops
.read_phy_reg(hw
, PHY_CONTROL
, &data
);
2934 if (data
& PHY_CONTROL_LB
)
2937 /* check if link is up and at 1Gbps */
2938 ret_val
= hw
->phy
.ops
.read_phy_reg(hw
, BM_CS_STATUS
, &data
);
2942 data
&= BM_CS_STATUS_LINK_UP
|
2943 BM_CS_STATUS_RESOLVED
|
2944 BM_CS_STATUS_SPEED_MASK
;
2946 if (data
!= (BM_CS_STATUS_LINK_UP
|
2947 BM_CS_STATUS_RESOLVED
|
2948 BM_CS_STATUS_SPEED_1000
))
2953 /* flush the packets in the fifo buffer */
2954 ret_val
= hw
->phy
.ops
.write_phy_reg(hw
, HV_MUX_DATA_CTRL
,
2955 HV_MUX_DATA_CTRL_GEN_TO_MAC
|
2956 HV_MUX_DATA_CTRL_FORCE_SPEED
);
2960 ret_val
= hw
->phy
.ops
.write_phy_reg(hw
, HV_MUX_DATA_CTRL
,
2961 HV_MUX_DATA_CTRL_GEN_TO_MAC
);
2968 * e1000_check_polarity_82577 - Checks the polarity.
2969 * @hw: pointer to the HW structure
2971 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2973 * Polarity is determined based on the PHY specific status register.
2975 s32
e1000_check_polarity_82577(struct e1000_hw
*hw
)
2977 struct e1000_phy_info
*phy
= &hw
->phy
;
2981 ret_val
= phy
->ops
.read_phy_reg(hw
, I82577_PHY_STATUS_2
, &data
);
2984 phy
->cable_polarity
= (data
& I82577_PHY_STATUS2_REV_POLARITY
)
2985 ? e1000_rev_polarity_reversed
2986 : e1000_rev_polarity_normal
;
2992 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY
2993 * @hw: pointer to the HW structure
2995 * Calls the PHY setup function to force speed and duplex. Clears the
2996 * auto-crossover to force MDI manually. Waits for link and returns
2997 * successful if link up is successful, else -E1000_ERR_PHY (-2).
2999 s32
e1000_phy_force_speed_duplex_82577(struct e1000_hw
*hw
)
3001 struct e1000_phy_info
*phy
= &hw
->phy
;
3006 ret_val
= phy
->ops
.read_phy_reg(hw
, PHY_CONTROL
, &phy_data
);
3010 e1000e_phy_force_speed_duplex_setup(hw
, &phy_data
);
3012 ret_val
= phy
->ops
.write_phy_reg(hw
, PHY_CONTROL
, phy_data
);
3017 * Clear Auto-Crossover to force MDI manually. 82577 requires MDI
3018 * forced whenever speed and duplex are forced.
3020 ret_val
= phy
->ops
.read_phy_reg(hw
, I82577_PHY_CTRL_2
, &phy_data
);
3024 phy_data
&= ~I82577_PHY_CTRL2_AUTO_MDIX
;
3025 phy_data
&= ~I82577_PHY_CTRL2_FORCE_MDI_MDIX
;
3027 ret_val
= phy
->ops
.write_phy_reg(hw
, I82577_PHY_CTRL_2
, phy_data
);
3031 hw_dbg(hw
, "I82577_PHY_CTRL_2: %X\n", phy_data
);
3035 if (phy
->autoneg_wait_to_complete
) {
3036 hw_dbg(hw
, "Waiting for forced speed/duplex link on 82577 phy\n");
3038 ret_val
= e1000e_phy_has_link_generic(hw
,
3046 hw_dbg(hw
, "Link taking longer than expected.\n");
3049 ret_val
= e1000e_phy_has_link_generic(hw
,
3062 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information
3063 * @hw: pointer to the HW structure
3065 * Read PHY status to determine if link is up. If link is up, then
3066 * set/determine 10base-T extended distance and polarity correction. Read
3067 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
3068 * determine on the cable length, local and remote receiver.
3070 s32
e1000_get_phy_info_82577(struct e1000_hw
*hw
)
3072 struct e1000_phy_info
*phy
= &hw
->phy
;
3077 ret_val
= e1000e_phy_has_link_generic(hw
, 1, 0, &link
);
3082 hw_dbg(hw
, "Phy info is only valid if link is up\n");
3083 ret_val
= -E1000_ERR_CONFIG
;
3087 phy
->polarity_correction
= true;
3089 ret_val
= e1000_check_polarity_82577(hw
);
3093 ret_val
= phy
->ops
.read_phy_reg(hw
, I82577_PHY_STATUS_2
, &data
);
3097 phy
->is_mdix
= (data
& I82577_PHY_STATUS2_MDIX
) ? true : false;
3099 if ((data
& I82577_PHY_STATUS2_SPEED_MASK
) ==
3100 I82577_PHY_STATUS2_SPEED_1000MBPS
) {
3101 ret_val
= hw
->phy
.ops
.get_cable_length(hw
);
3105 ret_val
= phy
->ops
.read_phy_reg(hw
, PHY_1000T_STATUS
, &data
);
3109 phy
->local_rx
= (data
& SR_1000T_LOCAL_RX_STATUS
)
3110 ? e1000_1000t_rx_status_ok
3111 : e1000_1000t_rx_status_not_ok
;
3113 phy
->remote_rx
= (data
& SR_1000T_REMOTE_RX_STATUS
)
3114 ? e1000_1000t_rx_status_ok
3115 : e1000_1000t_rx_status_not_ok
;
3117 phy
->cable_length
= E1000_CABLE_LENGTH_UNDEFINED
;
3118 phy
->local_rx
= e1000_1000t_rx_status_undefined
;
3119 phy
->remote_rx
= e1000_1000t_rx_status_undefined
;
3127 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
3128 * @hw: pointer to the HW structure
3130 * Reads the diagnostic status register and verifies result is valid before
3131 * placing it in the phy_cable_length field.
3133 s32
e1000_get_cable_length_82577(struct e1000_hw
*hw
)
3135 struct e1000_phy_info
*phy
= &hw
->phy
;
3137 u16 phy_data
, length
;
3139 ret_val
= phy
->ops
.read_phy_reg(hw
, I82577_PHY_DIAG_STATUS
, &phy_data
);
3143 length
= (phy_data
& I82577_DSTATUS_CABLE_LENGTH
) >>
3144 I82577_DSTATUS_CABLE_LENGTH_SHIFT
;
3146 if (length
== E1000_CABLE_LENGTH_UNDEFINED
)
3147 ret_val
= E1000_ERR_PHY
;
3149 phy
->cable_length
= length
;