2 * OHCI HCD (Host Controller Driver) for USB.
4 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
5 * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net>
7 * [ Initialisation is based on Linus' ]
8 * [ uhci code and gregs ohci fragments ]
9 * [ (C) Copyright 1999 Linus Torvalds ]
10 * [ (C) Copyright 1999 Gregory P. Smith]
13 * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller
14 * interfaces (though some non-x86 Intel chips use it). It supports
15 * smarter hardware than UHCI. A download link for the spec available
16 * through the http://www.usb.org website.
18 * This file is licenced under the GPL.
21 #include <linux/module.h>
22 #include <linux/moduleparam.h>
23 #include <linux/pci.h>
24 #include <linux/kernel.h>
25 #include <linux/delay.h>
26 #include <linux/ioport.h>
27 #include <linux/sched.h>
28 #include <linux/slab.h>
29 #include <linux/errno.h>
30 #include <linux/init.h>
31 #include <linux/timer.h>
32 #include <linux/list.h>
33 #include <linux/usb.h>
34 #include <linux/usb/otg.h>
35 #include <linux/dma-mapping.h>
36 #include <linux/dmapool.h>
37 #include <linux/reboot.h>
41 #include <asm/system.h>
42 #include <asm/unaligned.h>
43 #include <asm/byteorder.h>
45 #include <asm/firmware.h>
48 #include "../core/hcd.h"
50 #define DRIVER_VERSION "2006 August 04"
51 #define DRIVER_AUTHOR "Roman Weissgaerber, David Brownell"
52 #define DRIVER_DESC "USB 1.1 'Open' Host Controller (OHCI) Driver"
54 /*-------------------------------------------------------------------------*/
56 #undef OHCI_VERBOSE_DEBUG /* not always helpful */
58 /* For initializing controller (mask in an HCFS mode too) */
59 #define OHCI_CONTROL_INIT OHCI_CTRL_CBSR
60 #define OHCI_INTR_INIT \
61 (OHCI_INTR_MIE | OHCI_INTR_RHSC | OHCI_INTR_UE \
62 | OHCI_INTR_RD | OHCI_INTR_WDH)
65 /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */
69 #ifdef CONFIG_ARCH_OMAP
70 /* OMAP doesn't support IR (no SMM; not needed) */
74 /*-------------------------------------------------------------------------*/
76 static const char hcd_name
[] = "ohci_hcd";
78 #define STATECHANGE_DELAY msecs_to_jiffies(300)
82 static void ohci_dump (struct ohci_hcd
*ohci
, int verbose
);
83 static int ohci_init (struct ohci_hcd
*ohci
);
84 static void ohci_stop (struct usb_hcd
*hcd
);
93 * On architectures with edge-triggered interrupts we must never return
96 #if defined(CONFIG_SA1111) /* ... or other edge-triggered systems */
97 #define IRQ_NOTMINE IRQ_HANDLED
99 #define IRQ_NOTMINE IRQ_NONE
103 /* Some boards misreport power switching/overcurrent */
104 static int distrust_firmware
= 1;
105 module_param (distrust_firmware
, bool, 0);
106 MODULE_PARM_DESC (distrust_firmware
,
107 "true to distrust firmware power/overcurrent setup");
109 /* Some boards leave IR set wrongly, since they fail BIOS/SMM handshakes */
110 static int no_handshake
= 0;
111 module_param (no_handshake
, bool, 0);
112 MODULE_PARM_DESC (no_handshake
, "true (not default) disables BIOS handshake");
114 /*-------------------------------------------------------------------------*/
117 * queue up an urb for anything except the root hub
119 static int ohci_urb_enqueue (
121 struct usb_host_endpoint
*ep
,
125 struct ohci_hcd
*ohci
= hcd_to_ohci (hcd
);
127 urb_priv_t
*urb_priv
;
128 unsigned int pipe
= urb
->pipe
;
133 #ifdef OHCI_VERBOSE_DEBUG
134 urb_print (urb
, "SUB", usb_pipein (pipe
));
137 /* every endpoint has a ed, locate and maybe (re)initialize it */
138 if (! (ed
= ed_get (ohci
, ep
, urb
->dev
, pipe
, urb
->interval
)))
141 /* for the private part of the URB we need the number of TDs (size) */
144 /* td_submit_urb() doesn't yet handle these */
145 if (urb
->transfer_buffer_length
> 4096)
148 /* 1 TD for setup, 1 for ACK, plus ... */
151 // case PIPE_INTERRUPT:
154 /* one TD for every 4096 Bytes (can be upto 8K) */
155 size
+= urb
->transfer_buffer_length
/ 4096;
156 /* ... and for any remaining bytes ... */
157 if ((urb
->transfer_buffer_length
% 4096) != 0)
159 /* ... and maybe a zero length packet to wrap it up */
162 else if ((urb
->transfer_flags
& URB_ZERO_PACKET
) != 0
163 && (urb
->transfer_buffer_length
164 % usb_maxpacket (urb
->dev
, pipe
,
165 usb_pipeout (pipe
))) == 0)
168 case PIPE_ISOCHRONOUS
: /* number of packets from URB */
169 size
= urb
->number_of_packets
;
173 /* allocate the private part of the URB */
174 urb_priv
= kmalloc (sizeof (urb_priv_t
) + size
* sizeof (struct td
*),
178 memset (urb_priv
, 0, sizeof (urb_priv_t
) + size
* sizeof (struct td
*));
179 INIT_LIST_HEAD (&urb_priv
->pending
);
180 urb_priv
->length
= size
;
183 /* allocate the TDs (deferring hash chain updates) */
184 for (i
= 0; i
< size
; i
++) {
185 urb_priv
->td
[i
] = td_alloc (ohci
, mem_flags
);
186 if (!urb_priv
->td
[i
]) {
187 urb_priv
->length
= i
;
188 urb_free_priv (ohci
, urb_priv
);
193 spin_lock_irqsave (&ohci
->lock
, flags
);
195 /* don't submit to a dead HC */
196 if (!test_bit(HCD_FLAG_HW_ACCESSIBLE
, &hcd
->flags
)) {
200 if (!HC_IS_RUNNING(hcd
->state
)) {
205 /* in case of unlink-during-submit */
206 spin_lock (&urb
->lock
);
207 if (urb
->status
!= -EINPROGRESS
) {
208 spin_unlock (&urb
->lock
);
209 urb
->hcpriv
= urb_priv
;
210 finish_urb (ohci
, urb
);
215 /* schedule the ed if needed */
216 if (ed
->state
== ED_IDLE
) {
217 retval
= ed_schedule (ohci
, ed
);
220 if (ed
->type
== PIPE_ISOCHRONOUS
) {
221 u16 frame
= ohci_frame_no(ohci
);
223 /* delay a few frames before the first TD */
224 frame
+= max_t (u16
, 8, ed
->interval
);
225 frame
&= ~(ed
->interval
- 1);
227 urb
->start_frame
= frame
;
229 /* yes, only URB_ISO_ASAP is supported, and
230 * urb->start_frame is never used as input.
233 } else if (ed
->type
== PIPE_ISOCHRONOUS
)
234 urb
->start_frame
= ed
->last_iso
+ ed
->interval
;
236 /* fill the TDs and link them to the ed; and
237 * enable that part of the schedule, if needed
238 * and update count of queued periodic urbs
240 urb
->hcpriv
= urb_priv
;
241 td_submit_urb (ohci
, urb
);
244 spin_unlock (&urb
->lock
);
247 urb_free_priv (ohci
, urb_priv
);
248 spin_unlock_irqrestore (&ohci
->lock
, flags
);
253 * decouple the URB from the HC queues (TDs, urb_priv); it's
254 * already marked using urb->status. reporting is always done
255 * asynchronously, and we might be dealing with an urb that's
256 * partially transferred, or an ED with other urbs being unlinked.
258 static int ohci_urb_dequeue (struct usb_hcd
*hcd
, struct urb
*urb
)
260 struct ohci_hcd
*ohci
= hcd_to_ohci (hcd
);
263 #ifdef OHCI_VERBOSE_DEBUG
264 urb_print (urb
, "UNLINK", 1);
267 spin_lock_irqsave (&ohci
->lock
, flags
);
268 if (HC_IS_RUNNING(hcd
->state
)) {
269 urb_priv_t
*urb_priv
;
271 /* Unless an IRQ completed the unlink while it was being
272 * handed to us, flag it for unlink and giveback, and force
273 * some upcoming INTR_SF to call finish_unlinks()
275 urb_priv
= urb
->hcpriv
;
277 if (urb_priv
->ed
->state
== ED_OPER
)
278 start_ed_unlink (ohci
, urb_priv
->ed
);
282 * with HC dead, we won't respect hc queue pointers
283 * any more ... just clean up every urb's memory.
286 finish_urb (ohci
, urb
);
288 spin_unlock_irqrestore (&ohci
->lock
, flags
);
292 /*-------------------------------------------------------------------------*/
294 /* frees config/altsetting state for endpoints,
295 * including ED memory, dummy TD, and bulk/intr data toggle
299 ohci_endpoint_disable (struct usb_hcd
*hcd
, struct usb_host_endpoint
*ep
)
301 struct ohci_hcd
*ohci
= hcd_to_ohci (hcd
);
303 struct ed
*ed
= ep
->hcpriv
;
304 unsigned limit
= 1000;
306 /* ASSERT: any requests/urbs are being unlinked */
307 /* ASSERT: nobody can be submitting urbs for this any more */
313 spin_lock_irqsave (&ohci
->lock
, flags
);
315 if (!HC_IS_RUNNING (hcd
->state
)) {
318 finish_unlinks (ohci
, 0);
322 case ED_UNLINK
: /* wait for hw to finish? */
323 /* major IRQ delivery trouble loses INTR_SF too... */
325 ohci_warn (ohci
, "IRQ INTR_SF lossage\n");
328 spin_unlock_irqrestore (&ohci
->lock
, flags
);
329 schedule_timeout_uninterruptible(1);
331 case ED_IDLE
: /* fully unlinked */
332 if (list_empty (&ed
->td_list
)) {
333 td_free (ohci
, ed
->dummy
);
337 /* else FALL THROUGH */
339 /* caller was supposed to have unlinked any requests;
340 * that's not our job. can't recover; must leak ed.
342 ohci_err (ohci
, "leak ed %p (#%02x) state %d%s\n",
343 ed
, ep
->desc
.bEndpointAddress
, ed
->state
,
344 list_empty (&ed
->td_list
) ? "" : " (has tds)");
345 td_free (ohci
, ed
->dummy
);
349 spin_unlock_irqrestore (&ohci
->lock
, flags
);
353 static int ohci_get_frame (struct usb_hcd
*hcd
)
355 struct ohci_hcd
*ohci
= hcd_to_ohci (hcd
);
357 return ohci_frame_no(ohci
);
360 static void ohci_usb_reset (struct ohci_hcd
*ohci
)
362 ohci
->hc_control
= ohci_readl (ohci
, &ohci
->regs
->control
);
363 ohci
->hc_control
&= OHCI_CTRL_RWC
;
364 ohci_writel (ohci
, ohci
->hc_control
, &ohci
->regs
->control
);
367 /* ohci_shutdown forcibly disables IRQs and DMA, helping kexec and
368 * other cases where the next software may expect clean state from the
369 * "firmware". this is bus-neutral, unlike shutdown() methods.
372 ohci_shutdown (struct usb_hcd
*hcd
)
374 struct ohci_hcd
*ohci
;
376 ohci
= hcd_to_ohci (hcd
);
377 ohci_writel (ohci
, OHCI_INTR_MIE
, &ohci
->regs
->intrdisable
);
378 ohci_usb_reset (ohci
);
379 /* flush the writes */
380 (void) ohci_readl (ohci
, &ohci
->regs
->control
);
383 /*-------------------------------------------------------------------------*
385 *-------------------------------------------------------------------------*/
387 /* init memory, and kick BIOS/SMM off */
389 static int ohci_init (struct ohci_hcd
*ohci
)
392 struct usb_hcd
*hcd
= ohci_to_hcd(ohci
);
395 ohci
->regs
= hcd
->regs
;
397 /* REVISIT this BIOS handshake is now moved into PCI "quirks", and
398 * was never needed for most non-PCI systems ... remove the code?
402 /* SMM owns the HC? not for long! */
403 if (!no_handshake
&& ohci_readl (ohci
,
404 &ohci
->regs
->control
) & OHCI_CTRL_IR
) {
407 ohci_dbg (ohci
, "USB HC TakeOver from BIOS/SMM\n");
409 /* this timeout is arbitrary. we make it long, so systems
410 * depending on usb keyboards may be usable even if the
411 * BIOS/SMM code seems pretty broken.
413 temp
= 500; /* arbitrary: five seconds */
415 ohci_writel (ohci
, OHCI_INTR_OC
, &ohci
->regs
->intrenable
);
416 ohci_writel (ohci
, OHCI_OCR
, &ohci
->regs
->cmdstatus
);
417 while (ohci_readl (ohci
, &ohci
->regs
->control
) & OHCI_CTRL_IR
) {
420 ohci_err (ohci
, "USB HC takeover failed!"
421 " (BIOS/SMM bug)\n");
425 ohci_usb_reset (ohci
);
429 /* Disable HC interrupts */
430 ohci_writel (ohci
, OHCI_INTR_MIE
, &ohci
->regs
->intrdisable
);
432 /* flush the writes, and save key bits like RWC */
433 if (ohci_readl (ohci
, &ohci
->regs
->control
) & OHCI_CTRL_RWC
)
434 ohci
->hc_control
|= OHCI_CTRL_RWC
;
436 /* Read the number of ports unless overridden */
437 if (ohci
->num_ports
== 0)
438 ohci
->num_ports
= roothub_a(ohci
) & RH_A_NDP
;
443 ohci
->hcca
= dma_alloc_coherent (hcd
->self
.controller
,
444 sizeof *ohci
->hcca
, &ohci
->hcca_dma
, 0);
448 if ((ret
= ohci_mem_init (ohci
)) < 0)
451 create_debug_files (ohci
);
457 /*-------------------------------------------------------------------------*/
459 /* Start an OHCI controller, set the BUS operational
460 * resets USB and controller
463 static int ohci_run (struct ohci_hcd
*ohci
)
466 int first
= ohci
->fminterval
== 0;
467 struct usb_hcd
*hcd
= ohci_to_hcd(ohci
);
471 /* boot firmware should have set this up (5.1.1.3.1) */
474 temp
= ohci_readl (ohci
, &ohci
->regs
->fminterval
);
475 ohci
->fminterval
= temp
& 0x3fff;
476 if (ohci
->fminterval
!= FI
)
477 ohci_dbg (ohci
, "fminterval delta %d\n",
478 ohci
->fminterval
- FI
);
479 ohci
->fminterval
|= FSMP (ohci
->fminterval
) << 16;
480 /* also: power/overcurrent flags in roothub.a */
483 /* Reset USB nearly "by the book". RemoteWakeupConnected was
484 * saved if boot firmware (BIOS/SMM/...) told us it's connected,
485 * or if bus glue did the same (e.g. for PCI add-in cards with
488 if ((ohci
->hc_control
& OHCI_CTRL_RWC
) != 0
489 && !device_may_wakeup(hcd
->self
.controller
))
490 device_init_wakeup(hcd
->self
.controller
, 1);
492 switch (ohci
->hc_control
& OHCI_CTRL_HCFS
) {
496 case OHCI_USB_SUSPEND
:
497 case OHCI_USB_RESUME
:
498 ohci
->hc_control
&= OHCI_CTRL_RWC
;
499 ohci
->hc_control
|= OHCI_USB_RESUME
;
500 temp
= 10 /* msec wait */;
502 // case OHCI_USB_RESET:
504 ohci
->hc_control
&= OHCI_CTRL_RWC
;
505 ohci
->hc_control
|= OHCI_USB_RESET
;
506 temp
= 50 /* msec wait */;
509 ohci_writel (ohci
, ohci
->hc_control
, &ohci
->regs
->control
);
511 (void) ohci_readl (ohci
, &ohci
->regs
->control
);
513 temp
= roothub_a (ohci
);
514 if (!(temp
& RH_A_NPS
)) {
515 /* power down each port */
516 for (temp
= 0; temp
< ohci
->num_ports
; temp
++)
517 ohci_writel (ohci
, RH_PS_LSDA
,
518 &ohci
->regs
->roothub
.portstatus
[temp
]);
520 // flush those writes
521 (void) ohci_readl (ohci
, &ohci
->regs
->control
);
522 memset (ohci
->hcca
, 0, sizeof (struct ohci_hcca
));
524 /* 2msec timelimit here means no irqs/preempt */
525 spin_lock_irq (&ohci
->lock
);
528 /* HC Reset requires max 10 us delay */
529 ohci_writel (ohci
, OHCI_HCR
, &ohci
->regs
->cmdstatus
);
530 temp
= 30; /* ... allow extra time */
531 while ((ohci_readl (ohci
, &ohci
->regs
->cmdstatus
) & OHCI_HCR
) != 0) {
533 spin_unlock_irq (&ohci
->lock
);
534 ohci_err (ohci
, "USB HC reset timed out!\n");
540 /* now we're in the SUSPEND state ... must go OPERATIONAL
541 * within 2msec else HC enters RESUME
543 * ... but some hardware won't init fmInterval "by the book"
544 * (SiS, OPTi ...), so reset again instead. SiS doesn't need
545 * this if we write fmInterval after we're OPERATIONAL.
546 * Unclear about ALi, ServerWorks, and others ... this could
547 * easily be a longstanding bug in chip init on Linux.
549 if (ohci
->flags
& OHCI_QUIRK_INITRESET
) {
550 ohci_writel (ohci
, ohci
->hc_control
, &ohci
->regs
->control
);
551 // flush those writes
552 (void) ohci_readl (ohci
, &ohci
->regs
->control
);
555 /* Tell the controller where the control and bulk lists are
556 * The lists are empty now. */
557 ohci_writel (ohci
, 0, &ohci
->regs
->ed_controlhead
);
558 ohci_writel (ohci
, 0, &ohci
->regs
->ed_bulkhead
);
560 /* a reset clears this */
561 ohci_writel (ohci
, (u32
) ohci
->hcca_dma
, &ohci
->regs
->hcca
);
563 periodic_reinit (ohci
);
565 /* some OHCI implementations are finicky about how they init.
566 * bogus values here mean not even enumeration could work.
568 if ((ohci_readl (ohci
, &ohci
->regs
->fminterval
) & 0x3fff0000) == 0
569 || !ohci_readl (ohci
, &ohci
->regs
->periodicstart
)) {
570 if (!(ohci
->flags
& OHCI_QUIRK_INITRESET
)) {
571 ohci
->flags
|= OHCI_QUIRK_INITRESET
;
572 ohci_dbg (ohci
, "enabling initreset quirk\n");
575 spin_unlock_irq (&ohci
->lock
);
576 ohci_err (ohci
, "init err (%08x %04x)\n",
577 ohci_readl (ohci
, &ohci
->regs
->fminterval
),
578 ohci_readl (ohci
, &ohci
->regs
->periodicstart
));
582 /* use rhsc irqs after khubd is fully initialized */
584 hcd
->uses_new_polling
= 1;
586 /* start controller operations */
587 ohci
->hc_control
&= OHCI_CTRL_RWC
;
588 ohci
->hc_control
|= OHCI_CONTROL_INIT
| OHCI_USB_OPER
;
589 ohci_writel (ohci
, ohci
->hc_control
, &ohci
->regs
->control
);
590 hcd
->state
= HC_STATE_RUNNING
;
592 /* wake on ConnectStatusChange, matching external hubs */
593 ohci_writel (ohci
, RH_HS_DRWE
, &ohci
->regs
->roothub
.status
);
595 /* Choose the interrupts we care about now, others later on demand */
596 mask
= OHCI_INTR_INIT
;
597 ohci_writel (ohci
, ~0, &ohci
->regs
->intrstatus
);
598 ohci_writel (ohci
, mask
, &ohci
->regs
->intrenable
);
600 /* handle root hub init quirks ... */
601 temp
= roothub_a (ohci
);
602 temp
&= ~(RH_A_PSM
| RH_A_OCPM
);
603 if (ohci
->flags
& OHCI_QUIRK_SUPERIO
) {
604 /* NSC 87560 and maybe others */
606 temp
&= ~(RH_A_POTPGT
| RH_A_NPS
);
607 ohci_writel (ohci
, temp
, &ohci
->regs
->roothub
.a
);
608 } else if ((ohci
->flags
& OHCI_QUIRK_AMD756
) || distrust_firmware
) {
609 /* hub power always on; required for AMD-756 and some
610 * Mac platforms. ganged overcurrent reporting, if any.
613 ohci_writel (ohci
, temp
, &ohci
->regs
->roothub
.a
);
615 ohci_writel (ohci
, RH_HS_LPSC
, &ohci
->regs
->roothub
.status
);
616 ohci_writel (ohci
, (temp
& RH_A_NPS
) ? 0 : RH_B_PPCM
,
617 &ohci
->regs
->roothub
.b
);
618 // flush those writes
619 (void) ohci_readl (ohci
, &ohci
->regs
->control
);
621 ohci
->next_statechange
= jiffies
+ STATECHANGE_DELAY
;
622 spin_unlock_irq (&ohci
->lock
);
624 // POTPGT delay is bits 24-31, in 2 ms units.
625 mdelay ((temp
>> 23) & 0x1fe);
626 hcd
->state
= HC_STATE_RUNNING
;
633 /*-------------------------------------------------------------------------*/
635 /* an interrupt happens */
637 static irqreturn_t
ohci_irq (struct usb_hcd
*hcd
)
639 struct ohci_hcd
*ohci
= hcd_to_ohci (hcd
);
640 struct ohci_regs __iomem
*regs
= ohci
->regs
;
643 /* we can eliminate a (slow) ohci_readl()
644 if _only_ WDH caused this irq */
645 if ((ohci
->hcca
->done_head
!= 0)
646 && ! (hc32_to_cpup (ohci
, &ohci
->hcca
->done_head
)
648 ints
= OHCI_INTR_WDH
;
650 /* cardbus/... hardware gone before remove() */
651 } else if ((ints
= ohci_readl (ohci
, ®s
->intrstatus
)) == ~(u32
)0) {
653 ohci_dbg (ohci
, "device removed!\n");
656 /* interrupt for some other device? */
657 } else if ((ints
&= ohci_readl (ohci
, ®s
->intrenable
)) == 0) {
661 if (ints
& OHCI_INTR_UE
) {
663 ohci_err (ohci
, "OHCI Unrecoverable Error, disabled\n");
664 // e.g. due to PCI Master/Target Abort
667 ohci_usb_reset (ohci
);
670 if (ints
& OHCI_INTR_RHSC
) {
671 ohci_vdbg(ohci
, "rhsc\n");
672 ohci
->next_statechange
= jiffies
+ STATECHANGE_DELAY
;
673 ohci_writel(ohci
, OHCI_INTR_RD
| OHCI_INTR_RHSC
,
676 /* NOTE: Vendors didn't always make the same implementation
677 * choices for RHSC. Many followed the spec; RHSC triggers
678 * on an edge, like setting and maybe clearing a port status
679 * change bit. With others it's level-triggered, active
680 * until khubd clears all the port status change bits. We'll
681 * always disable it here and rely on polling until khubd
684 ohci_writel(ohci
, OHCI_INTR_RHSC
, ®s
->intrdisable
);
685 usb_hcd_poll_rh_status(hcd
);
688 /* For connect and disconnect events, we expect the controller
689 * to turn on RHSC along with RD. But for remote wakeup events
690 * this might not happen.
692 else if (ints
& OHCI_INTR_RD
) {
693 ohci_vdbg(ohci
, "resume detect\n");
694 ohci_writel(ohci
, OHCI_INTR_RD
, ®s
->intrstatus
);
696 if (ohci
->autostop
) {
697 spin_lock (&ohci
->lock
);
698 ohci_rh_resume (ohci
);
699 spin_unlock (&ohci
->lock
);
701 usb_hcd_resume_root_hub(hcd
);
704 if (ints
& OHCI_INTR_WDH
) {
705 if (HC_IS_RUNNING(hcd
->state
))
706 ohci_writel (ohci
, OHCI_INTR_WDH
, ®s
->intrdisable
);
707 spin_lock (&ohci
->lock
);
709 spin_unlock (&ohci
->lock
);
710 if (HC_IS_RUNNING(hcd
->state
))
711 ohci_writel (ohci
, OHCI_INTR_WDH
, ®s
->intrenable
);
714 /* could track INTR_SO to reduce available PCI/... bandwidth */
716 /* handle any pending URB/ED unlinks, leaving INTR_SF enabled
717 * when there's still unlinking to be done (next frame).
719 spin_lock (&ohci
->lock
);
720 if (ohci
->ed_rm_list
)
721 finish_unlinks (ohci
, ohci_frame_no(ohci
));
722 if ((ints
& OHCI_INTR_SF
) != 0 && !ohci
->ed_rm_list
723 && HC_IS_RUNNING(hcd
->state
))
724 ohci_writel (ohci
, OHCI_INTR_SF
, ®s
->intrdisable
);
725 spin_unlock (&ohci
->lock
);
727 if (HC_IS_RUNNING(hcd
->state
)) {
728 ohci_writel (ohci
, ints
, ®s
->intrstatus
);
729 ohci_writel (ohci
, OHCI_INTR_MIE
, ®s
->intrenable
);
730 // flush those writes
731 (void) ohci_readl (ohci
, &ohci
->regs
->control
);
737 /*-------------------------------------------------------------------------*/
739 static void ohci_stop (struct usb_hcd
*hcd
)
741 struct ohci_hcd
*ohci
= hcd_to_ohci (hcd
);
745 flush_scheduled_work();
747 ohci_usb_reset (ohci
);
748 ohci_writel (ohci
, OHCI_INTR_MIE
, &ohci
->regs
->intrdisable
);
749 free_irq(hcd
->irq
, hcd
);
752 remove_debug_files (ohci
);
753 ohci_mem_cleanup (ohci
);
755 dma_free_coherent (hcd
->self
.controller
,
757 ohci
->hcca
, ohci
->hcca_dma
);
763 /*-------------------------------------------------------------------------*/
765 /* must not be called from interrupt context */
769 static int ohci_restart (struct ohci_hcd
*ohci
)
773 struct urb_priv
*priv
;
775 /* mark any devices gone, so they do nothing till khubd disconnects.
776 * recycle any "live" eds/tds (and urbs) right away.
777 * later, khubd disconnect processing will recycle the other state,
778 * (either as disconnect/reconnect, or maybe someday as a reset).
780 spin_lock_irq(&ohci
->lock
);
782 usb_root_hub_lost_power(ohci_to_hcd(ohci
)->self
.root_hub
);
783 if (!list_empty (&ohci
->pending
))
784 ohci_dbg(ohci
, "abort schedule...\n");
785 list_for_each_entry (priv
, &ohci
->pending
, pending
) {
786 struct urb
*urb
= priv
->td
[0]->urb
;
787 struct ed
*ed
= priv
->ed
;
791 ed
->state
= ED_UNLINK
;
792 ed
->hwINFO
|= cpu_to_hc32(ohci
, ED_DEQUEUE
);
793 ed_deschedule (ohci
, ed
);
795 ed
->ed_next
= ohci
->ed_rm_list
;
797 ohci
->ed_rm_list
= ed
;
802 ohci_dbg(ohci
, "bogus ed %p state %d\n",
806 spin_lock (&urb
->lock
);
807 urb
->status
= -ESHUTDOWN
;
808 spin_unlock (&urb
->lock
);
810 finish_unlinks (ohci
, 0);
811 spin_unlock_irq(&ohci
->lock
);
813 /* paranoia, in case that didn't work: */
815 /* empty the interrupt branches */
816 for (i
= 0; i
< NUM_INTS
; i
++) ohci
->load
[i
] = 0;
817 for (i
= 0; i
< NUM_INTS
; i
++) ohci
->hcca
->int_table
[i
] = 0;
819 /* no EDs to remove */
820 ohci
->ed_rm_list
= NULL
;
822 /* empty control and bulk lists */
823 ohci
->ed_controltail
= NULL
;
824 ohci
->ed_bulktail
= NULL
;
826 if ((temp
= ohci_run (ohci
)) < 0) {
827 ohci_err (ohci
, "can't restart, %d\n", temp
);
830 /* here we "know" root ports should always stay powered,
831 * and that if we try to turn them back on the root hub
832 * will respond to CSC processing.
836 ohci_writel (ohci
, RH_PS_PSS
,
837 &ohci
->regs
->roothub
.portstatus
[i
]);
838 ohci_dbg (ohci
, "restart complete\n");
844 /*-------------------------------------------------------------------------*/
846 #define DRIVER_INFO DRIVER_VERSION " " DRIVER_DESC
848 MODULE_AUTHOR (DRIVER_AUTHOR
);
849 MODULE_DESCRIPTION (DRIVER_INFO
);
850 MODULE_LICENSE ("GPL");
853 #include "ohci-pci.c"
854 #define PCI_DRIVER ohci_pci_driver
858 #include "ohci-sa1111.c"
859 #define SA1111_DRIVER ohci_hcd_sa1111_driver
862 #ifdef CONFIG_ARCH_S3C2410
863 #include "ohci-s3c2410.c"
864 #define PLATFORM_DRIVER ohci_hcd_s3c2410_driver
867 #ifdef CONFIG_ARCH_OMAP
868 #include "ohci-omap.c"
869 #define PLATFORM_DRIVER ohci_hcd_omap_driver
872 #ifdef CONFIG_ARCH_LH7A404
873 #include "ohci-lh7a404.c"
874 #define PLATFORM_DRIVER ohci_hcd_lh7a404_driver
878 #include "ohci-pxa27x.c"
879 #define PLATFORM_DRIVER ohci_hcd_pxa27x_driver
882 #ifdef CONFIG_ARCH_EP93XX
883 #include "ohci-ep93xx.c"
884 #define PLATFORM_DRIVER ohci_hcd_ep93xx_driver
887 #ifdef CONFIG_SOC_AU1X00
888 #include "ohci-au1xxx.c"
889 #define PLATFORM_DRIVER ohci_hcd_au1xxx_driver
892 #ifdef CONFIG_PNX8550
893 #include "ohci-pnx8550.c"
894 #define PLATFORM_DRIVER ohci_hcd_pnx8550_driver
897 #ifdef CONFIG_USB_OHCI_HCD_PPC_SOC
898 #include "ohci-ppc-soc.c"
899 #define PLATFORM_DRIVER ohci_hcd_ppc_soc_driver
902 #ifdef CONFIG_ARCH_AT91
903 #include "ohci-at91.c"
904 #define PLATFORM_DRIVER ohci_hcd_at91_driver
907 #ifdef CONFIG_ARCH_PNX4008
908 #include "ohci-pnx4008.c"
909 #define PLATFORM_DRIVER usb_hcd_pnx4008_driver
913 #ifdef CONFIG_USB_OHCI_HCD_PPC_OF
914 #include "ohci-ppc-of.c"
915 #define OF_PLATFORM_DRIVER ohci_hcd_ppc_of_driver
918 #ifdef CONFIG_PPC_PS3
919 #include "ohci-ps3.c"
920 #define PS3_SYSTEM_BUS_DRIVER ps3_ohci_sb_driver
923 #if !defined(PCI_DRIVER) && \
924 !defined(PLATFORM_DRIVER) && \
925 !defined(OF_PLATFORM_DRIVER) && \
926 !defined(SA1111_DRIVER) && \
927 !defined(PS3_SYSTEM_BUS_DRIVER)
928 #error "missing bus glue for ohci-hcd"
931 static int __init
ohci_hcd_mod_init(void)
938 printk (KERN_DEBUG
"%s: " DRIVER_INFO
"\n", hcd_name
);
939 pr_debug ("%s: block sizes: ed %Zd td %Zd\n", hcd_name
,
940 sizeof (struct ed
), sizeof (struct td
));
942 #ifdef PS3_SYSTEM_BUS_DRIVER
943 if (firmware_has_feature(FW_FEATURE_PS3_LV1
)) {
944 retval
= ps3_system_bus_driver_register(
945 &PS3_SYSTEM_BUS_DRIVER
);
951 #ifdef PLATFORM_DRIVER
952 retval
= platform_driver_register(&PLATFORM_DRIVER
);
957 #ifdef OF_PLATFORM_DRIVER
958 retval
= of_register_platform_driver(&OF_PLATFORM_DRIVER
);
960 goto error_of_platform
;
964 retval
= sa1111_driver_register(&SA1111_DRIVER
);
970 retval
= pci_register_driver(&PCI_DRIVER
);
982 sa1111_driver_unregister(&SA1111_DRIVER
);
985 #ifdef OF_PLATFORM_DRIVER
986 of_unregister_platform_driver(&OF_PLATFORM_DRIVER
);
989 #ifdef PLATFORM_DRIVER
990 platform_driver_unregister(&PLATFORM_DRIVER
);
993 #ifdef PS3_SYSTEM_BUS_DRIVER
994 if (firmware_has_feature(FW_FEATURE_PS3_LV1
))
995 ps3_system_bus_driver_unregister(&PS3_SYSTEM_BUS_DRIVER
);
1000 module_init(ohci_hcd_mod_init
);
1002 static void __exit
ohci_hcd_mod_exit(void)
1005 pci_unregister_driver(&PCI_DRIVER
);
1007 #ifdef SA1111_DRIVER
1008 sa1111_driver_unregister(&SA1111_DRIVER
);
1010 #ifdef OF_PLATFORM_DRIVER
1011 of_unregister_platform_driver(&OF_PLATFORM_DRIVER
);
1013 #ifdef PLATFORM_DRIVER
1014 platform_driver_unregister(&PLATFORM_DRIVER
);
1016 #ifdef PS3_SYSTEM_BUS_DRIVER
1017 if (firmware_has_feature(FW_FEATURE_PS3_LV1
))
1018 ps3_system_bus_driver_unregister(&PS3_SYSTEM_BUS_DRIVER
);
1021 module_exit(ohci_hcd_mod_exit
);