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ibm_emac: improved PHY support
[linux-2.6.git] / drivers / net / epic100.c
blob5e517946f46a6c1deaee52eb25664467cd233528
1 /* epic100.c: A SMC 83c170 EPIC/100 Fast Ethernet driver for Linux. */
2 /*
3 Written/copyright 1997-2001 by Donald Becker.
4
5 This software may be used and distributed according to the terms of
6 the GNU General Public License (GPL), incorporated herein by reference.
7 Drivers based on or derived from this code fall under the GPL and must
8 retain the authorship, copyright and license notice. This file is not
9 a complete program and may only be used when the entire operating
10 system is licensed under the GPL.
11
12 This driver is for the SMC83c170/175 "EPIC" series, as used on the
13 SMC EtherPower II 9432 PCI adapter, and several CardBus cards.
14
15 The author may be reached as becker@scyld.com, or C/O
16 Scyld Computing Corporation
17 410 Severn Ave., Suite 210
18 Annapolis MD 21403
19
20 Information and updates available at
21 http://www.scyld.com/network/epic100.html
22 [this link no longer provides anything useful -jgarzik]
23
24 ---------------------------------------------------------------------
25
26 */
27
28 #define DRV_NAME "epic100"
29 #define DRV_VERSION "2.1"
30 #define DRV_RELDATE "Sept 11, 2006"
31
32 /* The user-configurable values.
33 These may be modified when a driver module is loaded.*/
34
35 static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
36
37 /* Used to pass the full-duplex flag, etc. */
38 #define MAX_UNITS 8 /* More are supported, limit only on options */
39 static int options[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
40 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
41
42 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
43 Setting to > 1518 effectively disables this feature. */
44 static int rx_copybreak;
45
46 /* Operational parameters that are set at compile time. */
47
48 /* Keep the ring sizes a power of two for operational efficiency.
49 The compiler will convert <unsigned>'%'<2^N> into a bit mask.
50 Making the Tx ring too large decreases the effectiveness of channel
51 bonding and packet priority.
52 There are no ill effects from too-large receive rings. */
53 #define TX_RING_SIZE 256
54 #define TX_QUEUE_LEN 240 /* Limit ring entries actually used. */
55 #define RX_RING_SIZE 256
56 #define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct epic_tx_desc)
57 #define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct epic_rx_desc)
58
59 /* Operational parameters that usually are not changed. */
60 /* Time in jiffies before concluding the transmitter is hung. */
61 #define TX_TIMEOUT (2*HZ)
62
63 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
64
65 /* Bytes transferred to chip before transmission starts. */
66 /* Initial threshold, increased on underflow, rounded down to 4 byte units. */
67 #define TX_FIFO_THRESH 256
68 #define RX_FIFO_THRESH 1 /* 0-3, 0==32, 64,96, or 3==128 bytes */
69
70 #include <linux/module.h>
71 #include <linux/kernel.h>
72 #include <linux/string.h>
73 #include <linux/timer.h>
74 #include <linux/errno.h>
75 #include <linux/ioport.h>
76 #include <linux/slab.h>
77 #include <linux/interrupt.h>
78 #include <linux/pci.h>
79 #include <linux/delay.h>
80 #include <linux/netdevice.h>
81 #include <linux/etherdevice.h>
82 #include <linux/skbuff.h>
83 #include <linux/init.h>
84 #include <linux/spinlock.h>
85 #include <linux/ethtool.h>
86 #include <linux/mii.h>
87 #include <linux/crc32.h>
88 #include <linux/bitops.h>
89 #include <asm/io.h>
90 #include <asm/uaccess.h>
91
92 /* These identify the driver base version and may not be removed. */
93 static char version[] __devinitdata =
94 DRV_NAME ".c:v1.11 1/7/2001 Written by Donald Becker <becker@scyld.com>\n";
95 static char version2[] __devinitdata =
96 " (unofficial 2.4.x kernel port, version " DRV_VERSION ", " DRV_RELDATE ")\n";
97
98 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
99 MODULE_DESCRIPTION("SMC 83c170 EPIC series Ethernet driver");
100 MODULE_LICENSE("GPL");
101
102 module_param(debug, int, 0);
103 module_param(rx_copybreak, int, 0);
104 module_param_array(options, int, NULL, 0);
105 module_param_array(full_duplex, int, NULL, 0);
106 MODULE_PARM_DESC(debug, "EPIC/100 debug level (0-5)");
107 MODULE_PARM_DESC(options, "EPIC/100: Bits 0-3: media type, bit 4: full duplex");
108 MODULE_PARM_DESC(rx_copybreak, "EPIC/100 copy breakpoint for copy-only-tiny-frames");
109 MODULE_PARM_DESC(full_duplex, "EPIC/100 full duplex setting(s) (1)");
110
111 /*
112 Theory of Operation
113
114 I. Board Compatibility
115
116 This device driver is designed for the SMC "EPIC/100", the SMC
117 single-chip Ethernet controllers for PCI. This chip is used on
118 the SMC EtherPower II boards.
119
120 II. Board-specific settings
121
122 PCI bus devices are configured by the system at boot time, so no jumpers
123 need to be set on the board. The system BIOS will assign the
124 PCI INTA signal to a (preferably otherwise unused) system IRQ line.
125 Note: Kernel versions earlier than 1.3.73 do not support shared PCI
126 interrupt lines.
127
128 III. Driver operation
129
130 IIIa. Ring buffers
131
132 IVb. References
133
134 http://www.smsc.com/main/datasheets/83c171.pdf
135 http://www.smsc.com/main/datasheets/83c175.pdf
136 http://scyld.com/expert/NWay.html
137 http://www.national.com/pf/DP/DP83840A.html
138
139 IVc. Errata
140
141 */
142
143
144 enum chip_capability_flags { MII_PWRDWN=1, TYPE2_INTR=2, NO_MII=4 };
145
146 #define EPIC_TOTAL_SIZE 0x100
147 #define USE_IO_OPS 1
148
149 typedef enum {
150 SMSC_83C170_0,
151 SMSC_83C170,
152 SMSC_83C175,
153 } chip_t;
154
155
156 struct epic_chip_info {
157 const char *name;
158 int drv_flags; /* Driver use, intended as capability flags. */
159 };
160
161
162 /* indexed by chip_t */
163 static const struct epic_chip_info pci_id_tbl[] = {
164 { "SMSC EPIC/100 83c170", TYPE2_INTR | NO_MII | MII_PWRDWN },
165 { "SMSC EPIC/100 83c170", TYPE2_INTR },
166 { "SMSC EPIC/C 83c175", TYPE2_INTR | MII_PWRDWN },
167 };
168
169
170 static struct pci_device_id epic_pci_tbl[] = {
171 { 0x10B8, 0x0005, 0x1092, 0x0AB4, 0, 0, SMSC_83C170_0 },
172 { 0x10B8, 0x0005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, SMSC_83C170 },
173 { 0x10B8, 0x0006, PCI_ANY_ID, PCI_ANY_ID,
174 PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, SMSC_83C175 },
175 { 0,}
176 };
177 MODULE_DEVICE_TABLE (pci, epic_pci_tbl);
178
179
180 #ifndef USE_IO_OPS
181 #undef inb
182 #undef inw
183 #undef inl
184 #undef outb
185 #undef outw
186 #undef outl
187 #define inb readb
188 #define inw readw
189 #define inl readl
190 #define outb writeb
191 #define outw writew
192 #define outl writel
193 #endif
194
195 /* Offsets to registers, using the (ugh) SMC names. */
196 enum epic_registers {
197 COMMAND=0, INTSTAT=4, INTMASK=8, GENCTL=0x0C, NVCTL=0x10, EECTL=0x14,
198 PCIBurstCnt=0x18,
199 TEST1=0x1C, CRCCNT=0x20, ALICNT=0x24, MPCNT=0x28, /* Rx error counters. */
200 MIICtrl=0x30, MIIData=0x34, MIICfg=0x38,
201 LAN0=64, /* MAC address. */
202 MC0=80, /* Multicast filter table. */
203 RxCtrl=96, TxCtrl=112, TxSTAT=0x74,
204 PRxCDAR=0x84, RxSTAT=0xA4, EarlyRx=0xB0, PTxCDAR=0xC4, TxThresh=0xDC,
205 };
206
207 /* Interrupt register bits, using my own meaningful names. */
208 enum IntrStatus {
209 TxIdle=0x40000, RxIdle=0x20000, IntrSummary=0x010000,
210 PCIBusErr170=0x7000, PCIBusErr175=0x1000, PhyEvent175=0x8000,
211 RxStarted=0x0800, RxEarlyWarn=0x0400, CntFull=0x0200, TxUnderrun=0x0100,
212 TxEmpty=0x0080, TxDone=0x0020, RxError=0x0010,
213 RxOverflow=0x0008, RxFull=0x0004, RxHeader=0x0002, RxDone=0x0001,
214 };
215 enum CommandBits {
216 StopRx=1, StartRx=2, TxQueued=4, RxQueued=8,
217 StopTxDMA=0x20, StopRxDMA=0x40, RestartTx=0x80,
218 };
219
220 #define EpicRemoved 0xffffffff /* Chip failed or removed (CardBus) */
221
222 #define EpicNapiEvent (TxEmpty | TxDone | \
223 RxDone | RxStarted | RxEarlyWarn | RxOverflow | RxFull)
224 #define EpicNormalEvent (0x0000ffff & ~EpicNapiEvent)
225
226 static const u16 media2miictl[16] = {
227 0, 0x0C00, 0x0C00, 0x2000, 0x0100, 0x2100, 0, 0,
228 0, 0, 0, 0, 0, 0, 0, 0 };
229
230 /* The EPIC100 Rx and Tx buffer descriptors. */
231
232 struct epic_tx_desc {
233 u32 txstatus;
234 u32 bufaddr;
235 u32 buflength;
236 u32 next;
237 };
238
239 struct epic_rx_desc {
240 u32 rxstatus;
241 u32 bufaddr;
242 u32 buflength;
243 u32 next;
244 };
245
246 enum desc_status_bits {
247 DescOwn=0x8000,
248 };
249
250 #define PRIV_ALIGN 15 /* Required alignment mask */
251 struct epic_private {
252 struct epic_rx_desc *rx_ring;
253 struct epic_tx_desc *tx_ring;
254 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
255 struct sk_buff* tx_skbuff[TX_RING_SIZE];
256 /* The addresses of receive-in-place skbuffs. */
257 struct sk_buff* rx_skbuff[RX_RING_SIZE];
258
259 dma_addr_t tx_ring_dma;
260 dma_addr_t rx_ring_dma;
261
262 /* Ring pointers. */
263 spinlock_t lock; /* Group with Tx control cache line. */
264 spinlock_t napi_lock;
265 unsigned int reschedule_in_poll;
266 unsigned int cur_tx, dirty_tx;
267
268 unsigned int cur_rx, dirty_rx;
269 u32 irq_mask;
270 unsigned int rx_buf_sz; /* Based on MTU+slack. */
271
272 struct pci_dev *pci_dev; /* PCI bus location. */
273 int chip_id, chip_flags;
274
275 struct net_device_stats stats;
276 struct timer_list timer; /* Media selection timer. */
277 int tx_threshold;
278 unsigned char mc_filter[8];
279 signed char phys[4]; /* MII device addresses. */
280 u16 advertising; /* NWay media advertisement */
281 int mii_phy_cnt;
282 struct mii_if_info mii;
283 unsigned int tx_full:1; /* The Tx queue is full. */
284 unsigned int default_port:4; /* Last dev->if_port value. */
285 };
286
287 static int epic_open(struct net_device *dev);
288 static int read_eeprom(long ioaddr, int location);
289 static int mdio_read(struct net_device *dev, int phy_id, int location);
290 static void mdio_write(struct net_device *dev, int phy_id, int loc, int val);
291 static void epic_restart(struct net_device *dev);
292 static void epic_timer(unsigned long data);
293 static void epic_tx_timeout(struct net_device *dev);
294 static void epic_init_ring(struct net_device *dev);
295 static int epic_start_xmit(struct sk_buff *skb, struct net_device *dev);
296 static int epic_rx(struct net_device *dev, int budget);
297 static int epic_poll(struct net_device *dev, int *budget);
298 static irqreturn_t epic_interrupt(int irq, void *dev_instance);
299 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
300 static const struct ethtool_ops netdev_ethtool_ops;
301 static int epic_close(struct net_device *dev);
302 static struct net_device_stats *epic_get_stats(struct net_device *dev);
303 static void set_rx_mode(struct net_device *dev);
304
305
306
307 static int __devinit epic_init_one (struct pci_dev *pdev,
308 const struct pci_device_id *ent)
309 {
310 static int card_idx = -1;
311 long ioaddr;
312 int chip_idx = (int) ent->driver_data;
313 int irq;
314 struct net_device *dev;
315 struct epic_private *ep;
316 int i, ret, option = 0, duplex = 0;
317 void *ring_space;
318 dma_addr_t ring_dma;
319
320 /* when built into the kernel, we only print version if device is found */
321 #ifndef MODULE
322 static int printed_version;
323 if (!printed_version++)
324 printk (KERN_INFO "%s" KERN_INFO "%s",
325 version, version2);
326 #endif
327
328 card_idx++;
329
330 ret = pci_enable_device(pdev);
331 if (ret)
332 goto out;
333 irq = pdev->irq;
334
335 if (pci_resource_len(pdev, 0) < EPIC_TOTAL_SIZE) {
336 dev_err(&pdev->dev, "no PCI region space\n");
337 ret = -ENODEV;
338 goto err_out_disable;
339 }
340
341 pci_set_master(pdev);
342
343 ret = pci_request_regions(pdev, DRV_NAME);
344 if (ret < 0)
345 goto err_out_disable;
346
347 ret = -ENOMEM;
348
349 dev = alloc_etherdev(sizeof (*ep));
350 if (!dev) {
351 dev_err(&pdev->dev, "no memory for eth device\n");
352 goto err_out_free_res;
353 }
354 SET_MODULE_OWNER(dev);
355 SET_NETDEV_DEV(dev, &pdev->dev);
356
357 #ifdef USE_IO_OPS
358 ioaddr = pci_resource_start (pdev, 0);
359 #else
360 ioaddr = pci_resource_start (pdev, 1);
361 ioaddr = (long) ioremap (ioaddr, pci_resource_len (pdev, 1));
362 if (!ioaddr) {
363 dev_err(&pdev->dev, "ioremap failed\n");
364 goto err_out_free_netdev;
365 }
366 #endif
367
368 pci_set_drvdata(pdev, dev);
369 ep = dev->priv;
370 ep->mii.dev = dev;
371 ep->mii.mdio_read = mdio_read;
372 ep->mii.mdio_write = mdio_write;
373 ep->mii.phy_id_mask = 0x1f;
374 ep->mii.reg_num_mask = 0x1f;
375
376 ring_space = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &ring_dma);
377 if (!ring_space)
378 goto err_out_iounmap;
379 ep->tx_ring = (struct epic_tx_desc *)ring_space;
380 ep->tx_ring_dma = ring_dma;
381
382 ring_space = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &ring_dma);
383 if (!ring_space)
384 goto err_out_unmap_tx;
385 ep->rx_ring = (struct epic_rx_desc *)ring_space;
386 ep->rx_ring_dma = ring_dma;
387
388 if (dev->mem_start) {
389 option = dev->mem_start;
390 duplex = (dev->mem_start & 16) ? 1 : 0;
391 } else if (card_idx >= 0 && card_idx < MAX_UNITS) {
392 if (options[card_idx] >= 0)
393 option = options[card_idx];
394 if (full_duplex[card_idx] >= 0)
395 duplex = full_duplex[card_idx];
396 }
397
398 dev->base_addr = ioaddr;
399 dev->irq = irq;
400
401 spin_lock_init(&ep->lock);
402 spin_lock_init(&ep->napi_lock);
403 ep->reschedule_in_poll = 0;
404
405 /* Bring the chip out of low-power mode. */
406 outl(0x4200, ioaddr + GENCTL);
407 /* Magic?! If we don't set this bit the MII interface won't work. */
408 /* This magic is documented in SMSC app note 7.15 */
409 for (i = 16; i > 0; i--)
410 outl(0x0008, ioaddr + TEST1);
411
412 /* Turn on the MII transceiver. */
413 outl(0x12, ioaddr + MIICfg);
414 if (chip_idx == 1)
415 outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
416 outl(0x0200, ioaddr + GENCTL);
417
418 /* Note: the '175 does not have a serial EEPROM. */
419 for (i = 0; i < 3; i++)
420 ((u16 *)dev->dev_addr)[i] = le16_to_cpu(inw(ioaddr + LAN0 + i*4));
421
422 if (debug > 2) {
423 dev_printk(KERN_DEBUG, &pdev->dev, "EEPROM contents:\n");
424 for (i = 0; i < 64; i++)
425 printk(" %4.4x%s", read_eeprom(ioaddr, i),
426 i % 16 == 15 ? "\n" : "");
427 }
428
429 ep->pci_dev = pdev;
430 ep->chip_id = chip_idx;
431 ep->chip_flags = pci_id_tbl[chip_idx].drv_flags;
432 ep->irq_mask =
433 (ep->chip_flags & TYPE2_INTR ? PCIBusErr175 : PCIBusErr170)
434 | CntFull | TxUnderrun | EpicNapiEvent;
435
436 /* Find the connected MII xcvrs.
437 Doing this in open() would allow detecting external xcvrs later, but
438 takes much time and no cards have external MII. */
439 {
440 int phy, phy_idx = 0;
441 for (phy = 1; phy < 32 && phy_idx < sizeof(ep->phys); phy++) {
442 int mii_status = mdio_read(dev, phy, MII_BMSR);
443 if (mii_status != 0xffff && mii_status != 0x0000) {
444 ep->phys[phy_idx++] = phy;
445 dev_info(&pdev->dev,
446 "MII transceiver #%d control "
447 "%4.4x status %4.4x.\n",
448 phy, mdio_read(dev, phy, 0), mii_status);
449 }
450 }
451 ep->mii_phy_cnt = phy_idx;
452 if (phy_idx != 0) {
453 phy = ep->phys[0];
454 ep->mii.advertising = mdio_read(dev, phy, MII_ADVERTISE);
455 dev_info(&pdev->dev,
456 "Autonegotiation advertising %4.4x link "
457 "partner %4.4x.\n",
458 ep->mii.advertising, mdio_read(dev, phy, 5));
459 } else if ( ! (ep->chip_flags & NO_MII)) {
460 dev_warn(&pdev->dev,
461 "***WARNING***: No MII transceiver found!\n");
462 /* Use the known PHY address of the EPII. */
463 ep->phys[0] = 3;
464 }
465 ep->mii.phy_id = ep->phys[0];
466 }
467
468 /* Turn off the MII xcvr (175 only!), leave the chip in low-power mode. */
469 if (ep->chip_flags & MII_PWRDWN)
470 outl(inl(ioaddr + NVCTL) & ~0x483C, ioaddr + NVCTL);
471 outl(0x0008, ioaddr + GENCTL);
472
473 /* The lower four bits are the media type. */
474 if (duplex) {
475 ep->mii.force_media = ep->mii.full_duplex = 1;
476 dev_info(&pdev->dev, "Forced full duplex requested.\n");
477 }
478 dev->if_port = ep->default_port = option;
479
480 /* The Epic-specific entries in the device structure. */
481 dev->open = &epic_open;
482 dev->hard_start_xmit = &epic_start_xmit;
483 dev->stop = &epic_close;
484 dev->get_stats = &epic_get_stats;
485 dev->set_multicast_list = &set_rx_mode;
486 dev->do_ioctl = &netdev_ioctl;
487 dev->ethtool_ops = &netdev_ethtool_ops;
488 dev->watchdog_timeo = TX_TIMEOUT;
489 dev->tx_timeout = &epic_tx_timeout;
490 dev->poll = epic_poll;
491 dev->weight = 64;
492
493 ret = register_netdev(dev);
494 if (ret < 0)
495 goto err_out_unmap_rx;
496
497 printk(KERN_INFO "%s: %s at %#lx, IRQ %d, ",
498 dev->name, pci_id_tbl[chip_idx].name, ioaddr, dev->irq);
499 for (i = 0; i < 5; i++)
500 printk("%2.2x:", dev->dev_addr[i]);
501 printk("%2.2x.\n", dev->dev_addr[i]);
502
503 out:
504 return ret;
505
506 err_out_unmap_rx:
507 pci_free_consistent(pdev, RX_TOTAL_SIZE, ep->rx_ring, ep->rx_ring_dma);
508 err_out_unmap_tx:
509 pci_free_consistent(pdev, TX_TOTAL_SIZE, ep->tx_ring, ep->tx_ring_dma);
510 err_out_iounmap:
511 #ifndef USE_IO_OPS
512 iounmap(ioaddr);
513 err_out_free_netdev:
514 #endif
515 free_netdev(dev);
516 err_out_free_res:
517 pci_release_regions(pdev);
518 err_out_disable:
519 pci_disable_device(pdev);
520 goto out;
521 }
522
523 /* Serial EEPROM section. */
524
525 /* EEPROM_Ctrl bits. */
526 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
527 #define EE_CS 0x02 /* EEPROM chip select. */
528 #define EE_DATA_WRITE 0x08 /* EEPROM chip data in. */
529 #define EE_WRITE_0 0x01
530 #define EE_WRITE_1 0x09
531 #define EE_DATA_READ 0x10 /* EEPROM chip data out. */
532 #define EE_ENB (0x0001 | EE_CS)
533
534 /* Delay between EEPROM clock transitions.
535 This serves to flush the operation to the PCI bus.
536 */
537
538 #define eeprom_delay() inl(ee_addr)
539
540 /* The EEPROM commands include the alway-set leading bit. */
541 #define EE_WRITE_CMD (5 << 6)
542 #define EE_READ64_CMD (6 << 6)
543 #define EE_READ256_CMD (6 << 8)
544 #define EE_ERASE_CMD (7 << 6)
545
546 static void epic_disable_int(struct net_device *dev, struct epic_private *ep)
547 {
548 long ioaddr = dev->base_addr;
549
550 outl(0x00000000, ioaddr + INTMASK);
551 }
552
553 static inline void __epic_pci_commit(long ioaddr)
554 {
555 #ifndef USE_IO_OPS
556 inl(ioaddr + INTMASK);
557 #endif
558 }
559
560 static inline void epic_napi_irq_off(struct net_device *dev,
561 struct epic_private *ep)
562 {
563 long ioaddr = dev->base_addr;
564
565 outl(ep->irq_mask & ~EpicNapiEvent, ioaddr + INTMASK);
566 __epic_pci_commit(ioaddr);
567 }
568
569 static inline void epic_napi_irq_on(struct net_device *dev,
570 struct epic_private *ep)
571 {
572 long ioaddr = dev->base_addr;
573
574 /* No need to commit possible posted write */
575 outl(ep->irq_mask | EpicNapiEvent, ioaddr + INTMASK);
576 }
577
578 static int __devinit read_eeprom(long ioaddr, int location)
579 {
580 int i;
581 int retval = 0;
582 long ee_addr = ioaddr + EECTL;
583 int read_cmd = location |
584 (inl(ee_addr) & 0x40 ? EE_READ64_CMD : EE_READ256_CMD);
585
586 outl(EE_ENB & ~EE_CS, ee_addr);
587 outl(EE_ENB, ee_addr);
588
589 /* Shift the read command bits out. */
590 for (i = 12; i >= 0; i--) {
591 short dataval = (read_cmd & (1 << i)) ? EE_WRITE_1 : EE_WRITE_0;
592 outl(EE_ENB | dataval, ee_addr);
593 eeprom_delay();
594 outl(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
595 eeprom_delay();
596 }
597 outl(EE_ENB, ee_addr);
598
599 for (i = 16; i > 0; i--) {
600 outl(EE_ENB | EE_SHIFT_CLK, ee_addr);
601 eeprom_delay();
602 retval = (retval << 1) | ((inl(ee_addr) & EE_DATA_READ) ? 1 : 0);
603 outl(EE_ENB, ee_addr);
604 eeprom_delay();
605 }
606
607 /* Terminate the EEPROM access. */
608 outl(EE_ENB & ~EE_CS, ee_addr);
609 return retval;
610 }
611
612 #define MII_READOP 1
613 #define MII_WRITEOP 2
614 static int mdio_read(struct net_device *dev, int phy_id, int location)
615 {
616 long ioaddr = dev->base_addr;
617 int read_cmd = (phy_id << 9) | (location << 4) | MII_READOP;
618 int i;
619
620 outl(read_cmd, ioaddr + MIICtrl);
621 /* Typical operation takes 25 loops. */
622 for (i = 400; i > 0; i--) {
623 barrier();
624 if ((inl(ioaddr + MIICtrl) & MII_READOP) == 0) {
625 /* Work around read failure bug. */
626 if (phy_id == 1 && location < 6
627 && inw(ioaddr + MIIData) == 0xffff) {
628 outl(read_cmd, ioaddr + MIICtrl);
629 continue;
630 }
631 return inw(ioaddr + MIIData);
632 }
633 }
634 return 0xffff;
635 }
636
637 static void mdio_write(struct net_device *dev, int phy_id, int loc, int value)
638 {
639 long ioaddr = dev->base_addr;
640 int i;
641
642 outw(value, ioaddr + MIIData);
643 outl((phy_id << 9) | (loc << 4) | MII_WRITEOP, ioaddr + MIICtrl);
644 for (i = 10000; i > 0; i--) {
645 barrier();
646 if ((inl(ioaddr + MIICtrl) & MII_WRITEOP) == 0)
647 break;
648 }
649 return;
650 }
651
652
653 static int epic_open(struct net_device *dev)
654 {
655 struct epic_private *ep = dev->priv;
656 long ioaddr = dev->base_addr;
657 int i;
658 int retval;
659
660 /* Soft reset the chip. */
661 outl(0x4001, ioaddr + GENCTL);
662
663 if ((retval = request_irq(dev->irq, &epic_interrupt, IRQF_SHARED, dev->name, dev)))
664 return retval;
665
666 epic_init_ring(dev);
667
668 outl(0x4000, ioaddr + GENCTL);
669 /* This magic is documented in SMSC app note 7.15 */
670 for (i = 16; i > 0; i--)
671 outl(0x0008, ioaddr + TEST1);
672
673 /* Pull the chip out of low-power mode, enable interrupts, and set for
674 PCI read multiple. The MIIcfg setting and strange write order are
675 required by the details of which bits are reset and the transceiver
676 wiring on the Ositech CardBus card.
677 */
678 #if 0
679 outl(dev->if_port == 1 ? 0x13 : 0x12, ioaddr + MIICfg);
680 #endif
681 if (ep->chip_flags & MII_PWRDWN)
682 outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
683
684 #if defined(__powerpc__) || defined(__sparc__) /* Big endian */
685 outl(0x4432 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
686 inl(ioaddr + GENCTL);
687 outl(0x0432 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
688 #else
689 outl(0x4412 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
690 inl(ioaddr + GENCTL);
691 outl(0x0412 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
692 #endif
693
694 udelay(20); /* Looks like EPII needs that if you want reliable RX init. FIXME: pci posting bug? */
695
696 for (i = 0; i < 3; i++)
697 outl(cpu_to_le16(((u16*)dev->dev_addr)[i]), ioaddr + LAN0 + i*4);
698
699 ep->tx_threshold = TX_FIFO_THRESH;
700 outl(ep->tx_threshold, ioaddr + TxThresh);
701
702 if (media2miictl[dev->if_port & 15]) {
703 if (ep->mii_phy_cnt)
704 mdio_write(dev, ep->phys[0], MII_BMCR, media2miictl[dev->if_port&15]);
705 if (dev->if_port == 1) {
706 if (debug > 1)
707 printk(KERN_INFO "%s: Using the 10base2 transceiver, MII "
708 "status %4.4x.\n",
709 dev->name, mdio_read(dev, ep->phys[0], MII_BMSR));
710 }
711 } else {
712 int mii_lpa = mdio_read(dev, ep->phys[0], MII_LPA);
713 if (mii_lpa != 0xffff) {
714 if ((mii_lpa & LPA_100FULL) || (mii_lpa & 0x01C0) == LPA_10FULL)
715 ep->mii.full_duplex = 1;
716 else if (! (mii_lpa & LPA_LPACK))
717 mdio_write(dev, ep->phys[0], MII_BMCR, BMCR_ANENABLE|BMCR_ANRESTART);
718 if (debug > 1)
719 printk(KERN_INFO "%s: Setting %s-duplex based on MII xcvr %d"
720 " register read of %4.4x.\n", dev->name,
721 ep->mii.full_duplex ? "full" : "half",
722 ep->phys[0], mii_lpa);
723 }
724 }
725
726 outl(ep->mii.full_duplex ? 0x7F : 0x79, ioaddr + TxCtrl);
727 outl(ep->rx_ring_dma, ioaddr + PRxCDAR);
728 outl(ep->tx_ring_dma, ioaddr + PTxCDAR);
729
730 /* Start the chip's Rx process. */
731 set_rx_mode(dev);
732 outl(StartRx | RxQueued, ioaddr + COMMAND);
733
734 netif_start_queue(dev);
735
736 /* Enable interrupts by setting the interrupt mask. */
737 outl((ep->chip_flags & TYPE2_INTR ? PCIBusErr175 : PCIBusErr170)
738 | CntFull | TxUnderrun
739 | RxError | RxHeader | EpicNapiEvent, ioaddr + INTMASK);
740
741 if (debug > 1)
742 printk(KERN_DEBUG "%s: epic_open() ioaddr %lx IRQ %d status %4.4x "
743 "%s-duplex.\n",
744 dev->name, ioaddr, dev->irq, (int)inl(ioaddr + GENCTL),
745 ep->mii.full_duplex ? "full" : "half");
746
747 /* Set the timer to switch to check for link beat and perhaps switch
748 to an alternate media type. */
749 init_timer(&ep->timer);
750 ep->timer.expires = jiffies + 3*HZ;
751 ep->timer.data = (unsigned long)dev;
752 ep->timer.function = &epic_timer; /* timer handler */
753 add_timer(&ep->timer);
754
755 return 0;
756 }
757
758 /* Reset the chip to recover from a PCI transaction error.
759 This may occur at interrupt time. */
760 static void epic_pause(struct net_device *dev)
761 {
762 long ioaddr = dev->base_addr;
763 struct epic_private *ep = dev->priv;
764
765 netif_stop_queue (dev);
766
767 /* Disable interrupts by clearing the interrupt mask. */
768 outl(0x00000000, ioaddr + INTMASK);
769 /* Stop the chip's Tx and Rx DMA processes. */
770 outw(StopRx | StopTxDMA | StopRxDMA, ioaddr + COMMAND);
771
772 /* Update the error counts. */
773 if (inw(ioaddr + COMMAND) != 0xffff) {
774 ep->stats.rx_missed_errors += inb(ioaddr + MPCNT);
775 ep->stats.rx_frame_errors += inb(ioaddr + ALICNT);
776 ep->stats.rx_crc_errors += inb(ioaddr + CRCCNT);
777 }
778
779 /* Remove the packets on the Rx queue. */
780 epic_rx(dev, RX_RING_SIZE);
781 }
782
783 static void epic_restart(struct net_device *dev)
784 {
785 long ioaddr = dev->base_addr;
786 struct epic_private *ep = dev->priv;
787 int i;
788
789 /* Soft reset the chip. */
790 outl(0x4001, ioaddr + GENCTL);
791
792 printk(KERN_DEBUG "%s: Restarting the EPIC chip, Rx %d/%d Tx %d/%d.\n",
793 dev->name, ep->cur_rx, ep->dirty_rx, ep->dirty_tx, ep->cur_tx);
794 udelay(1);
795
796 /* This magic is documented in SMSC app note 7.15 */
797 for (i = 16; i > 0; i--)
798 outl(0x0008, ioaddr + TEST1);
799
800 #if defined(__powerpc__) || defined(__sparc__) /* Big endian */
801 outl(0x0432 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
802 #else
803 outl(0x0412 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
804 #endif
805 outl(dev->if_port == 1 ? 0x13 : 0x12, ioaddr + MIICfg);
806 if (ep->chip_flags & MII_PWRDWN)
807 outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
808
809 for (i = 0; i < 3; i++)
810 outl(cpu_to_le16(((u16*)dev->dev_addr)[i]), ioaddr + LAN0 + i*4);
811
812 ep->tx_threshold = TX_FIFO_THRESH;
813 outl(ep->tx_threshold, ioaddr + TxThresh);
814 outl(ep->mii.full_duplex ? 0x7F : 0x79, ioaddr + TxCtrl);
815 outl(ep->rx_ring_dma + (ep->cur_rx%RX_RING_SIZE)*
816 sizeof(struct epic_rx_desc), ioaddr + PRxCDAR);
817 outl(ep->tx_ring_dma + (ep->dirty_tx%TX_RING_SIZE)*
818 sizeof(struct epic_tx_desc), ioaddr + PTxCDAR);
819
820 /* Start the chip's Rx process. */
821 set_rx_mode(dev);
822 outl(StartRx | RxQueued, ioaddr + COMMAND);
823
824 /* Enable interrupts by setting the interrupt mask. */
825 outl((ep->chip_flags & TYPE2_INTR ? PCIBusErr175 : PCIBusErr170)
826 | CntFull | TxUnderrun
827 | RxError | RxHeader | EpicNapiEvent, ioaddr + INTMASK);
828
829 printk(KERN_DEBUG "%s: epic_restart() done, cmd status %4.4x, ctl %4.4x"
830 " interrupt %4.4x.\n",
831 dev->name, (int)inl(ioaddr + COMMAND), (int)inl(ioaddr + GENCTL),
832 (int)inl(ioaddr + INTSTAT));
833 return;
834 }
835
836 static void check_media(struct net_device *dev)
837 {
838 struct epic_private *ep = dev->priv;
839 long ioaddr = dev->base_addr;
840 int mii_lpa = ep->mii_phy_cnt ? mdio_read(dev, ep->phys[0], MII_LPA) : 0;
841 int negotiated = mii_lpa & ep->mii.advertising;
842 int duplex = (negotiated & 0x0100) || (negotiated & 0x01C0) == 0x0040;
843
844 if (ep->mii.force_media)
845 return;
846 if (mii_lpa == 0xffff) /* Bogus read */
847 return;
848 if (ep->mii.full_duplex != duplex) {
849 ep->mii.full_duplex = duplex;
850 printk(KERN_INFO "%s: Setting %s-duplex based on MII #%d link"
851 " partner capability of %4.4x.\n", dev->name,
852 ep->mii.full_duplex ? "full" : "half", ep->phys[0], mii_lpa);
853 outl(ep->mii.full_duplex ? 0x7F : 0x79, ioaddr + TxCtrl);
854 }
855 }
856
857 static void epic_timer(unsigned long data)
858 {
859 struct net_device *dev = (struct net_device *)data;
860 struct epic_private *ep = dev->priv;
861 long ioaddr = dev->base_addr;
862 int next_tick = 5*HZ;
863
864 if (debug > 3) {
865 printk(KERN_DEBUG "%s: Media monitor tick, Tx status %8.8x.\n",
866 dev->name, (int)inl(ioaddr + TxSTAT));
867 printk(KERN_DEBUG "%s: Other registers are IntMask %4.4x "
868 "IntStatus %4.4x RxStatus %4.4x.\n",
869 dev->name, (int)inl(ioaddr + INTMASK),
870 (int)inl(ioaddr + INTSTAT), (int)inl(ioaddr + RxSTAT));
871 }
872
873 check_media(dev);
874
875 ep->timer.expires = jiffies + next_tick;
876 add_timer(&ep->timer);
877 }
878
879 static void epic_tx_timeout(struct net_device *dev)
880 {
881 struct epic_private *ep = dev->priv;
882 long ioaddr = dev->base_addr;
883
884 if (debug > 0) {
885 printk(KERN_WARNING "%s: Transmit timeout using MII device, "
886 "Tx status %4.4x.\n",
887 dev->name, (int)inw(ioaddr + TxSTAT));
888 if (debug > 1) {
889 printk(KERN_DEBUG "%s: Tx indices: dirty_tx %d, cur_tx %d.\n",
890 dev->name, ep->dirty_tx, ep->cur_tx);
891 }
892 }
893 if (inw(ioaddr + TxSTAT) & 0x10) { /* Tx FIFO underflow. */
894 ep->stats.tx_fifo_errors++;
895 outl(RestartTx, ioaddr + COMMAND);
896 } else {
897 epic_restart(dev);
898 outl(TxQueued, dev->base_addr + COMMAND);
899 }
900
901 dev->trans_start = jiffies;
902 ep->stats.tx_errors++;
903 if (!ep->tx_full)
904 netif_wake_queue(dev);
905 }
906
907 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
908 static void epic_init_ring(struct net_device *dev)
909 {
910 struct epic_private *ep = dev->priv;
911 int i;
912
913 ep->tx_full = 0;
914 ep->dirty_tx = ep->cur_tx = 0;
915 ep->cur_rx = ep->dirty_rx = 0;
916 ep->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
917
918 /* Initialize all Rx descriptors. */
919 for (i = 0; i < RX_RING_SIZE; i++) {
920 ep->rx_ring[i].rxstatus = 0;
921 ep->rx_ring[i].buflength = cpu_to_le32(ep->rx_buf_sz);
922 ep->rx_ring[i].next = ep->rx_ring_dma +
923 (i+1)*sizeof(struct epic_rx_desc);
924 ep->rx_skbuff[i] = NULL;
925 }
926 /* Mark the last entry as wrapping the ring. */
927 ep->rx_ring[i-1].next = ep->rx_ring_dma;
928
929 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
930 for (i = 0; i < RX_RING_SIZE; i++) {
931 struct sk_buff *skb = dev_alloc_skb(ep->rx_buf_sz);
932 ep->rx_skbuff[i] = skb;
933 if (skb == NULL)
934 break;
935 skb_reserve(skb, 2); /* 16 byte align the IP header. */
936 ep->rx_ring[i].bufaddr = pci_map_single(ep->pci_dev,
937 skb->data, ep->rx_buf_sz, PCI_DMA_FROMDEVICE);
938 ep->rx_ring[i].rxstatus = cpu_to_le32(DescOwn);
939 }
940 ep->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
941
942 /* The Tx buffer descriptor is filled in as needed, but we
943 do need to clear the ownership bit. */
944 for (i = 0; i < TX_RING_SIZE; i++) {
945 ep->tx_skbuff[i] = NULL;
946 ep->tx_ring[i].txstatus = 0x0000;
947 ep->tx_ring[i].next = ep->tx_ring_dma +
948 (i+1)*sizeof(struct epic_tx_desc);
949 }
950 ep->tx_ring[i-1].next = ep->tx_ring_dma;
951 return;
952 }
953
954 static int epic_start_xmit(struct sk_buff *skb, struct net_device *dev)
955 {
956 struct epic_private *ep = dev->priv;
957 int entry, free_count;
958 u32 ctrl_word;
959 unsigned long flags;
960
961 if (skb_padto(skb, ETH_ZLEN))
962 return 0;
963
964 /* Caution: the write order is important here, set the field with the
965 "ownership" bit last. */
966
967 /* Calculate the next Tx descriptor entry. */
968 spin_lock_irqsave(&ep->lock, flags);
969 free_count = ep->cur_tx - ep->dirty_tx;
970 entry = ep->cur_tx % TX_RING_SIZE;
971
972 ep->tx_skbuff[entry] = skb;
973 ep->tx_ring[entry].bufaddr = pci_map_single(ep->pci_dev, skb->data,
974 skb->len, PCI_DMA_TODEVICE);
975 if (free_count < TX_QUEUE_LEN/2) {/* Typical path */
976 ctrl_word = cpu_to_le32(0x100000); /* No interrupt */
977 } else if (free_count == TX_QUEUE_LEN/2) {
978 ctrl_word = cpu_to_le32(0x140000); /* Tx-done intr. */
979 } else if (free_count < TX_QUEUE_LEN - 1) {
980 ctrl_word = cpu_to_le32(0x100000); /* No Tx-done intr. */
981 } else {
982 /* Leave room for an additional entry. */
983 ctrl_word = cpu_to_le32(0x140000); /* Tx-done intr. */
984 ep->tx_full = 1;
985 }
986 ep->tx_ring[entry].buflength = ctrl_word | cpu_to_le32(skb->len);
987 ep->tx_ring[entry].txstatus =
988 ((skb->len >= ETH_ZLEN ? skb->len : ETH_ZLEN) << 16)
989 | cpu_to_le32(DescOwn);
990
991 ep->cur_tx++;
992 if (ep->tx_full)
993 netif_stop_queue(dev);
994
995 spin_unlock_irqrestore(&ep->lock, flags);
996 /* Trigger an immediate transmit demand. */
997 outl(TxQueued, dev->base_addr + COMMAND);
998
999 dev->trans_start = jiffies;
1000 if (debug > 4)
1001 printk(KERN_DEBUG "%s: Queued Tx packet size %d to slot %d, "
1002 "flag %2.2x Tx status %8.8x.\n",
1003 dev->name, (int)skb->len, entry, ctrl_word,
1004 (int)inl(dev->base_addr + TxSTAT));
1005
1006 return 0;
1007 }
1008
1009 static void epic_tx_error(struct net_device *dev, struct epic_private *ep,
1010 int status)
1011 {
1012 struct net_device_stats *stats = &ep->stats;
1013
1014 #ifndef final_version
1015 /* There was an major error, log it. */
1016 if (debug > 1)
1017 printk(KERN_DEBUG "%s: Transmit error, Tx status %8.8x.\n",
1018 dev->name, status);
1019 #endif
1020 stats->tx_errors++;
1021 if (status & 0x1050)
1022 stats->tx_aborted_errors++;
1023 if (status & 0x0008)
1024 stats->tx_carrier_errors++;
1025 if (status & 0x0040)
1026 stats->tx_window_errors++;
1027 if (status & 0x0010)
1028 stats->tx_fifo_errors++;
1029 }
1030
1031 static void epic_tx(struct net_device *dev, struct epic_private *ep)
1032 {
1033 unsigned int dirty_tx, cur_tx;
1034
1035 /*
1036 * Note: if this lock becomes a problem we can narrow the locked
1037 * region at the cost of occasionally grabbing the lock more times.
1038 */
1039 cur_tx = ep->cur_tx;
1040 for (dirty_tx = ep->dirty_tx; cur_tx - dirty_tx > 0; dirty_tx++) {
1041 struct sk_buff *skb;
1042 int entry = dirty_tx % TX_RING_SIZE;
1043 int txstatus = le32_to_cpu(ep->tx_ring[entry].txstatus);
1044
1045 if (txstatus & DescOwn)
1046 break; /* It still hasn't been Txed */
1047
1048 if (likely(txstatus & 0x0001)) {
1049 ep->stats.collisions += (txstatus >> 8) & 15;
1050 ep->stats.tx_packets++;
1051 ep->stats.tx_bytes += ep->tx_skbuff[entry]->len;
1052 } else
1053 epic_tx_error(dev, ep, txstatus);
1054
1055 /* Free the original skb. */
1056 skb = ep->tx_skbuff[entry];
1057 pci_unmap_single(ep->pci_dev, ep->tx_ring[entry].bufaddr,
1058 skb->len, PCI_DMA_TODEVICE);
1059 dev_kfree_skb_irq(skb);
1060 ep->tx_skbuff[entry] = NULL;
1061 }
1062
1063 #ifndef final_version
1064 if (cur_tx - dirty_tx > TX_RING_SIZE) {
1065 printk(KERN_WARNING
1066 "%s: Out-of-sync dirty pointer, %d vs. %d, full=%d.\n",
1067 dev->name, dirty_tx, cur_tx, ep->tx_full);
1068 dirty_tx += TX_RING_SIZE;
1069 }
1070 #endif
1071 ep->dirty_tx = dirty_tx;
1072 if (ep->tx_full && cur_tx - dirty_tx < TX_QUEUE_LEN - 4) {
1073 /* The ring is no longer full, allow new TX entries. */
1074 ep->tx_full = 0;
1075 netif_wake_queue(dev);
1076 }
1077 }
1078
1079 /* The interrupt handler does all of the Rx thread work and cleans up
1080 after the Tx thread. */
1081 static irqreturn_t epic_interrupt(int irq, void *dev_instance)
1082 {
1083 struct net_device *dev = dev_instance;
1084 struct epic_private *ep = dev->priv;
1085 long ioaddr = dev->base_addr;
1086 unsigned int handled = 0;
1087 int status;
1088
1089 status = inl(ioaddr + INTSTAT);
1090 /* Acknowledge all of the current interrupt sources ASAP. */
1091 outl(status & EpicNormalEvent, ioaddr + INTSTAT);
1092
1093 if (debug > 4) {
1094 printk(KERN_DEBUG "%s: Interrupt, status=%#8.8x new "
1095 "intstat=%#8.8x.\n", dev->name, status,
1096 (int)inl(ioaddr + INTSTAT));
1097 }
1098
1099 if ((status & IntrSummary) == 0)
1100 goto out;
1101
1102 handled = 1;
1103
1104 if ((status & EpicNapiEvent) && !ep->reschedule_in_poll) {
1105 spin_lock(&ep->napi_lock);
1106 if (netif_rx_schedule_prep(dev)) {
1107 epic_napi_irq_off(dev, ep);
1108 __netif_rx_schedule(dev);
1109 } else
1110 ep->reschedule_in_poll++;
1111 spin_unlock(&ep->napi_lock);
1112 }
1113 status &= ~EpicNapiEvent;
1114
1115 /* Check uncommon events all at once. */
1116 if (status & (CntFull | TxUnderrun | PCIBusErr170 | PCIBusErr175)) {
1117 if (status == EpicRemoved)
1118 goto out;
1119
1120 /* Always update the error counts to avoid overhead later. */
1121 ep->stats.rx_missed_errors += inb(ioaddr + MPCNT);
1122 ep->stats.rx_frame_errors += inb(ioaddr + ALICNT);
1123 ep->stats.rx_crc_errors += inb(ioaddr + CRCCNT);
1124
1125 if (status & TxUnderrun) { /* Tx FIFO underflow. */
1126 ep->stats.tx_fifo_errors++;
1127 outl(ep->tx_threshold += 128, ioaddr + TxThresh);
1128 /* Restart the transmit process. */
1129 outl(RestartTx, ioaddr + COMMAND);
1130 }
1131 if (status & PCIBusErr170) {
1132 printk(KERN_ERR "%s: PCI Bus Error! status %4.4x.\n",
1133 dev->name, status);
1134 epic_pause(dev);
1135 epic_restart(dev);
1136 }
1137 /* Clear all error sources. */
1138 outl(status & 0x7f18, ioaddr + INTSTAT);
1139 }
1140
1141 out:
1142 if (debug > 3) {
1143 printk(KERN_DEBUG "%s: exit interrupt, intr_status=%#4.4x.\n",
1144 dev->name, status);
1145 }
1146
1147 return IRQ_RETVAL(handled);
1148 }
1149
1150 static int epic_rx(struct net_device *dev, int budget)
1151 {
1152 struct epic_private *ep = dev->priv;
1153 int entry = ep->cur_rx % RX_RING_SIZE;
1154 int rx_work_limit = ep->dirty_rx + RX_RING_SIZE - ep->cur_rx;
1155 int work_done = 0;
1156
1157 if (debug > 4)
1158 printk(KERN_DEBUG " In epic_rx(), entry %d %8.8x.\n", entry,
1159 ep->rx_ring[entry].rxstatus);
1160
1161 if (rx_work_limit > budget)
1162 rx_work_limit = budget;
1163
1164 /* If we own the next entry, it's a new packet. Send it up. */
1165 while ((ep->rx_ring[entry].rxstatus & cpu_to_le32(DescOwn)) == 0) {
1166 int status = le32_to_cpu(ep->rx_ring[entry].rxstatus);
1167
1168 if (debug > 4)
1169 printk(KERN_DEBUG " epic_rx() status was %8.8x.\n", status);
1170 if (--rx_work_limit < 0)
1171 break;
1172 if (status & 0x2006) {
1173 if (debug > 2)
1174 printk(KERN_DEBUG "%s: epic_rx() error status was %8.8x.\n",
1175 dev->name, status);
1176 if (status & 0x2000) {
1177 printk(KERN_WARNING "%s: Oversized Ethernet frame spanned "
1178 "multiple buffers, status %4.4x!\n", dev->name, status);
1179 ep->stats.rx_length_errors++;
1180 } else if (status & 0x0006)
1181 /* Rx Frame errors are counted in hardware. */
1182 ep->stats.rx_errors++;
1183 } else {
1184 /* Malloc up new buffer, compatible with net-2e. */
1185 /* Omit the four octet CRC from the length. */
1186 short pkt_len = (status >> 16) - 4;
1187 struct sk_buff *skb;
1188
1189 if (pkt_len > PKT_BUF_SZ - 4) {
1190 printk(KERN_ERR "%s: Oversized Ethernet frame, status %x "
1191 "%d bytes.\n",
1192 dev->name, status, pkt_len);
1193 pkt_len = 1514;
1194 }
1195 /* Check if the packet is long enough to accept without copying
1196 to a minimally-sized skbuff. */
1197 if (pkt_len < rx_copybreak
1198 && (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1199 skb_reserve(skb, 2); /* 16 byte align the IP header */
1200 pci_dma_sync_single_for_cpu(ep->pci_dev,
1201 ep->rx_ring[entry].bufaddr,
1202 ep->rx_buf_sz,
1203 PCI_DMA_FROMDEVICE);
1204 eth_copy_and_sum(skb, ep->rx_skbuff[entry]->data, pkt_len, 0);
1205 skb_put(skb, pkt_len);
1206 pci_dma_sync_single_for_device(ep->pci_dev,
1207 ep->rx_ring[entry].bufaddr,
1208 ep->rx_buf_sz,
1209 PCI_DMA_FROMDEVICE);
1210 } else {
1211 pci_unmap_single(ep->pci_dev,
1212 ep->rx_ring[entry].bufaddr,
1213 ep->rx_buf_sz, PCI_DMA_FROMDEVICE);
1214 skb_put(skb = ep->rx_skbuff[entry], pkt_len);
1215 ep->rx_skbuff[entry] = NULL;
1216 }
1217 skb->protocol = eth_type_trans(skb, dev);
1218 netif_receive_skb(skb);
1219 dev->last_rx = jiffies;
1220 ep->stats.rx_packets++;
1221 ep->stats.rx_bytes += pkt_len;
1222 }
1223 work_done++;
1224 entry = (++ep->cur_rx) % RX_RING_SIZE;
1225 }
1226
1227 /* Refill the Rx ring buffers. */
1228 for (; ep->cur_rx - ep->dirty_rx > 0; ep->dirty_rx++) {
1229 entry = ep->dirty_rx % RX_RING_SIZE;
1230 if (ep->rx_skbuff[entry] == NULL) {
1231 struct sk_buff *skb;
1232 skb = ep->rx_skbuff[entry] = dev_alloc_skb(ep->rx_buf_sz);
1233 if (skb == NULL)
1234 break;
1235 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
1236 ep->rx_ring[entry].bufaddr = pci_map_single(ep->pci_dev,
1237 skb->data, ep->rx_buf_sz, PCI_DMA_FROMDEVICE);
1238 work_done++;
1239 }
1240 ep->rx_ring[entry].rxstatus = cpu_to_le32(DescOwn);
1241 }
1242 return work_done;
1243 }
1244
1245 static void epic_rx_err(struct net_device *dev, struct epic_private *ep)
1246 {
1247 long ioaddr = dev->base_addr;
1248 int status;
1249
1250 status = inl(ioaddr + INTSTAT);
1251
1252 if (status == EpicRemoved)
1253 return;
1254 if (status & RxOverflow) /* Missed a Rx frame. */
1255 ep->stats.rx_errors++;
1256 if (status & (RxOverflow | RxFull))
1257 outw(RxQueued, ioaddr + COMMAND);
1258 }
1259
1260 static int epic_poll(struct net_device *dev, int *budget)
1261 {
1262 struct epic_private *ep = dev->priv;
1263 int work_done = 0, orig_budget;
1264 long ioaddr = dev->base_addr;
1265
1266 orig_budget = (*budget > dev->quota) ? dev->quota : *budget;
1267
1268 rx_action:
1269
1270 epic_tx(dev, ep);
1271
1272 work_done += epic_rx(dev, *budget);
1273
1274 epic_rx_err(dev, ep);
1275
1276 *budget -= work_done;
1277 dev->quota -= work_done;
1278
1279 if (netif_running(dev) && (work_done < orig_budget)) {
1280 unsigned long flags;
1281 int more;
1282
1283 /* A bit baroque but it avoids a (space hungry) spin_unlock */
1284
1285 spin_lock_irqsave(&ep->napi_lock, flags);
1286
1287 more = ep->reschedule_in_poll;
1288 if (!more) {
1289 __netif_rx_complete(dev);
1290 outl(EpicNapiEvent, ioaddr + INTSTAT);
1291 epic_napi_irq_on(dev, ep);
1292 } else
1293 ep->reschedule_in_poll--;
1294
1295 spin_unlock_irqrestore(&ep->napi_lock, flags);
1296
1297 if (more)
1298 goto rx_action;
1299 }
1300
1301 return (work_done >= orig_budget);
1302 }
1303
1304 static int epic_close(struct net_device *dev)
1305 {
1306 long ioaddr = dev->base_addr;
1307 struct epic_private *ep = dev->priv;
1308 struct sk_buff *skb;
1309 int i;
1310
1311 netif_stop_queue(dev);
1312
1313 if (debug > 1)
1314 printk(KERN_DEBUG "%s: Shutting down ethercard, status was %2.2x.\n",
1315 dev->name, (int)inl(ioaddr + INTSTAT));
1316
1317 del_timer_sync(&ep->timer);
1318
1319 epic_disable_int(dev, ep);
1320
1321 free_irq(dev->irq, dev);
1322
1323 epic_pause(dev);
1324
1325 /* Free all the skbuffs in the Rx queue. */
1326 for (i = 0; i < RX_RING_SIZE; i++) {
1327 skb = ep->rx_skbuff[i];
1328 ep->rx_skbuff[i] = NULL;
1329 ep->rx_ring[i].rxstatus = 0; /* Not owned by Epic chip. */
1330 ep->rx_ring[i].buflength = 0;
1331 if (skb) {
1332 pci_unmap_single(ep->pci_dev, ep->rx_ring[i].bufaddr,
1333 ep->rx_buf_sz, PCI_DMA_FROMDEVICE);
1334 dev_kfree_skb(skb);
1335 }
1336 ep->rx_ring[i].bufaddr = 0xBADF00D0; /* An invalid address. */
1337 }
1338 for (i = 0; i < TX_RING_SIZE; i++) {
1339 skb = ep->tx_skbuff[i];
1340 ep->tx_skbuff[i] = NULL;
1341 if (!skb)
1342 continue;
1343 pci_unmap_single(ep->pci_dev, ep->tx_ring[i].bufaddr,
1344 skb->len, PCI_DMA_TODEVICE);
1345 dev_kfree_skb(skb);
1346 }
1347
1348 /* Green! Leave the chip in low-power mode. */
1349 outl(0x0008, ioaddr + GENCTL);
1350
1351 return 0;
1352 }
1353
1354 static struct net_device_stats *epic_get_stats(struct net_device *dev)
1355 {
1356 struct epic_private *ep = dev->priv;
1357 long ioaddr = dev->base_addr;
1358
1359 if (netif_running(dev)) {
1360 /* Update the error counts. */
1361 ep->stats.rx_missed_errors += inb(ioaddr + MPCNT);
1362 ep->stats.rx_frame_errors += inb(ioaddr + ALICNT);
1363 ep->stats.rx_crc_errors += inb(ioaddr + CRCCNT);
1364 }
1365
1366 return &ep->stats;
1367 }
1368
1369 /* Set or clear the multicast filter for this adaptor.
1370 Note that we only use exclusion around actually queueing the
1371 new frame, not around filling ep->setup_frame. This is non-deterministic
1372 when re-entered but still correct. */
1373
1374 static void set_rx_mode(struct net_device *dev)
1375 {
1376 long ioaddr = dev->base_addr;
1377 struct epic_private *ep = dev->priv;
1378 unsigned char mc_filter[8]; /* Multicast hash filter */
1379 int i;
1380
1381 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1382 outl(0x002C, ioaddr + RxCtrl);
1383 /* Unconditionally log net taps. */
1384 memset(mc_filter, 0xff, sizeof(mc_filter));
1385 } else if ((dev->mc_count > 0) || (dev->flags & IFF_ALLMULTI)) {
1386 /* There is apparently a chip bug, so the multicast filter
1387 is never enabled. */
1388 /* Too many to filter perfectly -- accept all multicasts. */
1389 memset(mc_filter, 0xff, sizeof(mc_filter));
1390 outl(0x000C, ioaddr + RxCtrl);
1391 } else if (dev->mc_count == 0) {
1392 outl(0x0004, ioaddr + RxCtrl);
1393 return;
1394 } else { /* Never executed, for now. */
1395 struct dev_mc_list *mclist;
1396
1397 memset(mc_filter, 0, sizeof(mc_filter));
1398 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1399 i++, mclist = mclist->next) {
1400 unsigned int bit_nr =
1401 ether_crc_le(ETH_ALEN, mclist->dmi_addr) & 0x3f;
1402 mc_filter[bit_nr >> 3] |= (1 << bit_nr);
1403 }
1404 }
1405 /* ToDo: perhaps we need to stop the Tx and Rx process here? */
1406 if (memcmp(mc_filter, ep->mc_filter, sizeof(mc_filter))) {
1407 for (i = 0; i < 4; i++)
1408 outw(((u16 *)mc_filter)[i], ioaddr + MC0 + i*4);
1409 memcpy(ep->mc_filter, mc_filter, sizeof(mc_filter));
1410 }
1411 return;
1412 }
1413
1414 static void netdev_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1415 {
1416 struct epic_private *np = dev->priv;
1417
1418 strcpy (info->driver, DRV_NAME);
1419 strcpy (info->version, DRV_VERSION);
1420 strcpy (info->bus_info, pci_name(np->pci_dev));
1421 }
1422
1423 static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1424 {
1425 struct epic_private *np = dev->priv;
1426 int rc;
1427
1428 spin_lock_irq(&np->lock);
1429 rc = mii_ethtool_gset(&np->mii, cmd);
1430 spin_unlock_irq(&np->lock);
1431
1432 return rc;
1433 }
1434
1435 static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1436 {
1437 struct epic_private *np = dev->priv;
1438 int rc;
1439
1440 spin_lock_irq(&np->lock);
1441 rc = mii_ethtool_sset(&np->mii, cmd);
1442 spin_unlock_irq(&np->lock);
1443
1444 return rc;
1445 }
1446
1447 static int netdev_nway_reset(struct net_device *dev)
1448 {
1449 struct epic_private *np = dev->priv;
1450 return mii_nway_restart(&np->mii);
1451 }
1452
1453 static u32 netdev_get_link(struct net_device *dev)
1454 {
1455 struct epic_private *np = dev->priv;
1456 return mii_link_ok(&np->mii);
1457 }
1458
1459 static u32 netdev_get_msglevel(struct net_device *dev)
1460 {
1461 return debug;
1462 }
1463
1464 static void netdev_set_msglevel(struct net_device *dev, u32 value)
1465 {
1466 debug = value;
1467 }
1468
1469 static int ethtool_begin(struct net_device *dev)
1470 {
1471 unsigned long ioaddr = dev->base_addr;
1472 /* power-up, if interface is down */
1473 if (! netif_running(dev)) {
1474 outl(0x0200, ioaddr + GENCTL);
1475 outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
1476 }
1477 return 0;
1478 }
1479
1480 static void ethtool_complete(struct net_device *dev)
1481 {
1482 unsigned long ioaddr = dev->base_addr;
1483 /* power-down, if interface is down */
1484 if (! netif_running(dev)) {
1485 outl(0x0008, ioaddr + GENCTL);
1486 outl((inl(ioaddr + NVCTL) & ~0x483C) | 0x0000, ioaddr + NVCTL);
1487 }
1488 }
1489
1490 static const struct ethtool_ops netdev_ethtool_ops = {
1491 .get_drvinfo = netdev_get_drvinfo,
1492 .get_settings = netdev_get_settings,
1493 .set_settings = netdev_set_settings,
1494 .nway_reset = netdev_nway_reset,
1495 .get_link = netdev_get_link,
1496 .get_msglevel = netdev_get_msglevel,
1497 .set_msglevel = netdev_set_msglevel,
1498 .get_sg = ethtool_op_get_sg,
1499 .get_tx_csum = ethtool_op_get_tx_csum,
1500 .begin = ethtool_begin,
1501 .complete = ethtool_complete
1502 };
1503
1504 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1505 {
1506 struct epic_private *np = dev->priv;
1507 long ioaddr = dev->base_addr;
1508 struct mii_ioctl_data *data = if_mii(rq);
1509 int rc;
1510
1511 /* power-up, if interface is down */
1512 if (! netif_running(dev)) {
1513 outl(0x0200, ioaddr + GENCTL);
1514 outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
1515 }
1516
1517 /* all non-ethtool ioctls (the SIOC[GS]MIIxxx ioctls) */
1518 spin_lock_irq(&np->lock);
1519 rc = generic_mii_ioctl(&np->mii, data, cmd, NULL);
1520 spin_unlock_irq(&np->lock);
1521
1522 /* power-down, if interface is down */
1523 if (! netif_running(dev)) {
1524 outl(0x0008, ioaddr + GENCTL);
1525 outl((inl(ioaddr + NVCTL) & ~0x483C) | 0x0000, ioaddr + NVCTL);
1526 }
1527 return rc;
1528 }
1529
1530
1531 static void __devexit epic_remove_one (struct pci_dev *pdev)
1532 {
1533 struct net_device *dev = pci_get_drvdata(pdev);
1534 struct epic_private *ep = dev->priv;
1535
1536 pci_free_consistent(pdev, TX_TOTAL_SIZE, ep->tx_ring, ep->tx_ring_dma);
1537 pci_free_consistent(pdev, RX_TOTAL_SIZE, ep->rx_ring, ep->rx_ring_dma);
1538 unregister_netdev(dev);
1539 #ifndef USE_IO_OPS
1540 iounmap((void*) dev->base_addr);
1541 #endif
1542 pci_release_regions(pdev);
1543 free_netdev(dev);
1544 pci_disable_device(pdev);
1545 pci_set_drvdata(pdev, NULL);
1546 /* pci_power_off(pdev, -1); */
1547 }
1548
1549
1550 #ifdef CONFIG_PM
1551
1552 static int epic_suspend (struct pci_dev *pdev, pm_message_t state)
1553 {
1554 struct net_device *dev = pci_get_drvdata(pdev);
1555 long ioaddr = dev->base_addr;
1556
1557 if (!netif_running(dev))
1558 return 0;
1559 epic_pause(dev);
1560 /* Put the chip into low-power mode. */
1561 outl(0x0008, ioaddr + GENCTL);
1562 /* pci_power_off(pdev, -1); */
1563 return 0;
1564 }
1565
1566
1567 static int epic_resume (struct pci_dev *pdev)
1568 {
1569 struct net_device *dev = pci_get_drvdata(pdev);
1570
1571 if (!netif_running(dev))
1572 return 0;
1573 epic_restart(dev);
1574 /* pci_power_on(pdev); */
1575 return 0;
1576 }
1577
1578 #endif /* CONFIG_PM */
1579
1580
1581 static struct pci_driver epic_driver = {
1582 .name = DRV_NAME,
1583 .id_table = epic_pci_tbl,
1584 .probe = epic_init_one,
1585 .remove = __devexit_p(epic_remove_one),
1586 #ifdef CONFIG_PM
1587 .suspend = epic_suspend,
1588 .resume = epic_resume,
1589 #endif /* CONFIG_PM */
1590 };
1591
1592
1593 static int __init epic_init (void)
1594 {
1595 /* when a module, this is printed whether or not devices are found in probe */
1596 #ifdef MODULE
1597 printk (KERN_INFO "%s" KERN_INFO "%s",
1598 version, version2);
1599 #endif
1600
1601 return pci_register_driver(&epic_driver);
1602 }
1603
1604
1605 static void __exit epic_cleanup (void)
1606 {
1607 pci_unregister_driver (&epic_driver);
1608 }
1609
1610
1611 module_init(epic_init);
1612 module_exit(epic_cleanup);
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