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sh_eth: add IRQ flags to 'struct sh_eth_cpu_data'
[linux-2.6.git] / drivers / net / ethernet / renesas / sh_eth.c
blobd0151d02416f38625d567cc9595aefbc333ba69c
1 /*
2 * SuperH Ethernet device driver
3 *
4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
5 * Copyright (C) 2008-2013 Renesas Solutions Corp.
6 * Copyright (C) 2013 Cogent Embedded, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * The full GNU General Public License is included in this distribution in
21 * the file called "COPYING".
22 */
23
24 #include <linux/init.h>
25 #include <linux/module.h>
26 #include <linux/kernel.h>
27 #include <linux/spinlock.h>
28 #include <linux/interrupt.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/etherdevice.h>
31 #include <linux/delay.h>
32 #include <linux/platform_device.h>
33 #include <linux/mdio-bitbang.h>
34 #include <linux/netdevice.h>
35 #include <linux/phy.h>
36 #include <linux/cache.h>
37 #include <linux/io.h>
38 #include <linux/pm_runtime.h>
39 #include <linux/slab.h>
40 #include <linux/ethtool.h>
41 #include <linux/if_vlan.h>
42 #include <linux/clk.h>
43 #include <linux/sh_eth.h>
44
45 #include "sh_eth.h"
46
47 #define SH_ETH_DEF_MSG_ENABLE \
48 (NETIF_MSG_LINK | \
49 NETIF_MSG_TIMER | \
50 NETIF_MSG_RX_ERR| \
51 NETIF_MSG_TX_ERR)
52
53 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
54 [EDSR] = 0x0000,
55 [EDMR] = 0x0400,
56 [EDTRR] = 0x0408,
57 [EDRRR] = 0x0410,
58 [EESR] = 0x0428,
59 [EESIPR] = 0x0430,
60 [TDLAR] = 0x0010,
61 [TDFAR] = 0x0014,
62 [TDFXR] = 0x0018,
63 [TDFFR] = 0x001c,
64 [RDLAR] = 0x0030,
65 [RDFAR] = 0x0034,
66 [RDFXR] = 0x0038,
67 [RDFFR] = 0x003c,
68 [TRSCER] = 0x0438,
69 [RMFCR] = 0x0440,
70 [TFTR] = 0x0448,
71 [FDR] = 0x0450,
72 [RMCR] = 0x0458,
73 [RPADIR] = 0x0460,
74 [FCFTR] = 0x0468,
75 [CSMR] = 0x04E4,
76
77 [ECMR] = 0x0500,
78 [ECSR] = 0x0510,
79 [ECSIPR] = 0x0518,
80 [PIR] = 0x0520,
81 [PSR] = 0x0528,
82 [PIPR] = 0x052c,
83 [RFLR] = 0x0508,
84 [APR] = 0x0554,
85 [MPR] = 0x0558,
86 [PFTCR] = 0x055c,
87 [PFRCR] = 0x0560,
88 [TPAUSER] = 0x0564,
89 [GECMR] = 0x05b0,
90 [BCULR] = 0x05b4,
91 [MAHR] = 0x05c0,
92 [MALR] = 0x05c8,
93 [TROCR] = 0x0700,
94 [CDCR] = 0x0708,
95 [LCCR] = 0x0710,
96 [CEFCR] = 0x0740,
97 [FRECR] = 0x0748,
98 [TSFRCR] = 0x0750,
99 [TLFRCR] = 0x0758,
100 [RFCR] = 0x0760,
101 [CERCR] = 0x0768,
102 [CEECR] = 0x0770,
103 [MAFCR] = 0x0778,
104 [RMII_MII] = 0x0790,
105
106 [ARSTR] = 0x0000,
107 [TSU_CTRST] = 0x0004,
108 [TSU_FWEN0] = 0x0010,
109 [TSU_FWEN1] = 0x0014,
110 [TSU_FCM] = 0x0018,
111 [TSU_BSYSL0] = 0x0020,
112 [TSU_BSYSL1] = 0x0024,
113 [TSU_PRISL0] = 0x0028,
114 [TSU_PRISL1] = 0x002c,
115 [TSU_FWSL0] = 0x0030,
116 [TSU_FWSL1] = 0x0034,
117 [TSU_FWSLC] = 0x0038,
118 [TSU_QTAG0] = 0x0040,
119 [TSU_QTAG1] = 0x0044,
120 [TSU_FWSR] = 0x0050,
121 [TSU_FWINMK] = 0x0054,
122 [TSU_ADQT0] = 0x0048,
123 [TSU_ADQT1] = 0x004c,
124 [TSU_VTAG0] = 0x0058,
125 [TSU_VTAG1] = 0x005c,
126 [TSU_ADSBSY] = 0x0060,
127 [TSU_TEN] = 0x0064,
128 [TSU_POST1] = 0x0070,
129 [TSU_POST2] = 0x0074,
130 [TSU_POST3] = 0x0078,
131 [TSU_POST4] = 0x007c,
132 [TSU_ADRH0] = 0x0100,
133 [TSU_ADRL0] = 0x0104,
134 [TSU_ADRH31] = 0x01f8,
135 [TSU_ADRL31] = 0x01fc,
136
137 [TXNLCR0] = 0x0080,
138 [TXALCR0] = 0x0084,
139 [RXNLCR0] = 0x0088,
140 [RXALCR0] = 0x008c,
141 [FWNLCR0] = 0x0090,
142 [FWALCR0] = 0x0094,
143 [TXNLCR1] = 0x00a0,
144 [TXALCR1] = 0x00a0,
145 [RXNLCR1] = 0x00a8,
146 [RXALCR1] = 0x00ac,
147 [FWNLCR1] = 0x00b0,
148 [FWALCR1] = 0x00b4,
149 };
150
151 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
152 [ECMR] = 0x0300,
153 [RFLR] = 0x0308,
154 [ECSR] = 0x0310,
155 [ECSIPR] = 0x0318,
156 [PIR] = 0x0320,
157 [PSR] = 0x0328,
158 [RDMLR] = 0x0340,
159 [IPGR] = 0x0350,
160 [APR] = 0x0354,
161 [MPR] = 0x0358,
162 [RFCF] = 0x0360,
163 [TPAUSER] = 0x0364,
164 [TPAUSECR] = 0x0368,
165 [MAHR] = 0x03c0,
166 [MALR] = 0x03c8,
167 [TROCR] = 0x03d0,
168 [CDCR] = 0x03d4,
169 [LCCR] = 0x03d8,
170 [CNDCR] = 0x03dc,
171 [CEFCR] = 0x03e4,
172 [FRECR] = 0x03e8,
173 [TSFRCR] = 0x03ec,
174 [TLFRCR] = 0x03f0,
175 [RFCR] = 0x03f4,
176 [MAFCR] = 0x03f8,
177
178 [EDMR] = 0x0200,
179 [EDTRR] = 0x0208,
180 [EDRRR] = 0x0210,
181 [TDLAR] = 0x0218,
182 [RDLAR] = 0x0220,
183 [EESR] = 0x0228,
184 [EESIPR] = 0x0230,
185 [TRSCER] = 0x0238,
186 [RMFCR] = 0x0240,
187 [TFTR] = 0x0248,
188 [FDR] = 0x0250,
189 [RMCR] = 0x0258,
190 [TFUCR] = 0x0264,
191 [RFOCR] = 0x0268,
192 [FCFTR] = 0x0270,
193 [TRIMD] = 0x027c,
194 };
195
196 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
197 [ECMR] = 0x0100,
198 [RFLR] = 0x0108,
199 [ECSR] = 0x0110,
200 [ECSIPR] = 0x0118,
201 [PIR] = 0x0120,
202 [PSR] = 0x0128,
203 [RDMLR] = 0x0140,
204 [IPGR] = 0x0150,
205 [APR] = 0x0154,
206 [MPR] = 0x0158,
207 [TPAUSER] = 0x0164,
208 [RFCF] = 0x0160,
209 [TPAUSECR] = 0x0168,
210 [BCFRR] = 0x016c,
211 [MAHR] = 0x01c0,
212 [MALR] = 0x01c8,
213 [TROCR] = 0x01d0,
214 [CDCR] = 0x01d4,
215 [LCCR] = 0x01d8,
216 [CNDCR] = 0x01dc,
217 [CEFCR] = 0x01e4,
218 [FRECR] = 0x01e8,
219 [TSFRCR] = 0x01ec,
220 [TLFRCR] = 0x01f0,
221 [RFCR] = 0x01f4,
222 [MAFCR] = 0x01f8,
223 [RTRATE] = 0x01fc,
224
225 [EDMR] = 0x0000,
226 [EDTRR] = 0x0008,
227 [EDRRR] = 0x0010,
228 [TDLAR] = 0x0018,
229 [RDLAR] = 0x0020,
230 [EESR] = 0x0028,
231 [EESIPR] = 0x0030,
232 [TRSCER] = 0x0038,
233 [RMFCR] = 0x0040,
234 [TFTR] = 0x0048,
235 [FDR] = 0x0050,
236 [RMCR] = 0x0058,
237 [TFUCR] = 0x0064,
238 [RFOCR] = 0x0068,
239 [FCFTR] = 0x0070,
240 [RPADIR] = 0x0078,
241 [TRIMD] = 0x007c,
242 [RBWAR] = 0x00c8,
243 [RDFAR] = 0x00cc,
244 [TBRAR] = 0x00d4,
245 [TDFAR] = 0x00d8,
246 };
247
248 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
249 [ECMR] = 0x0160,
250 [ECSR] = 0x0164,
251 [ECSIPR] = 0x0168,
252 [PIR] = 0x016c,
253 [MAHR] = 0x0170,
254 [MALR] = 0x0174,
255 [RFLR] = 0x0178,
256 [PSR] = 0x017c,
257 [TROCR] = 0x0180,
258 [CDCR] = 0x0184,
259 [LCCR] = 0x0188,
260 [CNDCR] = 0x018c,
261 [CEFCR] = 0x0194,
262 [FRECR] = 0x0198,
263 [TSFRCR] = 0x019c,
264 [TLFRCR] = 0x01a0,
265 [RFCR] = 0x01a4,
266 [MAFCR] = 0x01a8,
267 [IPGR] = 0x01b4,
268 [APR] = 0x01b8,
269 [MPR] = 0x01bc,
270 [TPAUSER] = 0x01c4,
271 [BCFR] = 0x01cc,
272
273 [ARSTR] = 0x0000,
274 [TSU_CTRST] = 0x0004,
275 [TSU_FWEN0] = 0x0010,
276 [TSU_FWEN1] = 0x0014,
277 [TSU_FCM] = 0x0018,
278 [TSU_BSYSL0] = 0x0020,
279 [TSU_BSYSL1] = 0x0024,
280 [TSU_PRISL0] = 0x0028,
281 [TSU_PRISL1] = 0x002c,
282 [TSU_FWSL0] = 0x0030,
283 [TSU_FWSL1] = 0x0034,
284 [TSU_FWSLC] = 0x0038,
285 [TSU_QTAGM0] = 0x0040,
286 [TSU_QTAGM1] = 0x0044,
287 [TSU_ADQT0] = 0x0048,
288 [TSU_ADQT1] = 0x004c,
289 [TSU_FWSR] = 0x0050,
290 [TSU_FWINMK] = 0x0054,
291 [TSU_ADSBSY] = 0x0060,
292 [TSU_TEN] = 0x0064,
293 [TSU_POST1] = 0x0070,
294 [TSU_POST2] = 0x0074,
295 [TSU_POST3] = 0x0078,
296 [TSU_POST4] = 0x007c,
297
298 [TXNLCR0] = 0x0080,
299 [TXALCR0] = 0x0084,
300 [RXNLCR0] = 0x0088,
301 [RXALCR0] = 0x008c,
302 [FWNLCR0] = 0x0090,
303 [FWALCR0] = 0x0094,
304 [TXNLCR1] = 0x00a0,
305 [TXALCR1] = 0x00a0,
306 [RXNLCR1] = 0x00a8,
307 [RXALCR1] = 0x00ac,
308 [FWNLCR1] = 0x00b0,
309 [FWALCR1] = 0x00b4,
310
311 [TSU_ADRH0] = 0x0100,
312 [TSU_ADRL0] = 0x0104,
313 [TSU_ADRL31] = 0x01fc,
314 };
315
316 #if defined(CONFIG_CPU_SUBTYPE_SH7734) || \
317 defined(CONFIG_CPU_SUBTYPE_SH7763) || \
318 defined(CONFIG_ARCH_R8A7740)
319 static void sh_eth_select_mii(struct net_device *ndev)
320 {
321 u32 value = 0x0;
322 struct sh_eth_private *mdp = netdev_priv(ndev);
323
324 switch (mdp->phy_interface) {
325 case PHY_INTERFACE_MODE_GMII:
326 value = 0x2;
327 break;
328 case PHY_INTERFACE_MODE_MII:
329 value = 0x1;
330 break;
331 case PHY_INTERFACE_MODE_RMII:
332 value = 0x0;
333 break;
334 default:
335 pr_warn("PHY interface mode was not setup. Set to MII.\n");
336 value = 0x1;
337 break;
338 }
339
340 sh_eth_write(ndev, value, RMII_MII);
341 }
342 #endif
343
344 static void __maybe_unused sh_eth_set_duplex(struct net_device *ndev)
345 {
346 struct sh_eth_private *mdp = netdev_priv(ndev);
347
348 if (mdp->duplex) /* Full */
349 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
350 else /* Half */
351 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
352 }
353
354 /* There is CPU dependent code */
355 #if defined(CONFIG_ARCH_R8A7778) || defined(CONFIG_ARCH_R8A7779)
356 #define SH_ETH_RESET_DEFAULT 1
357 static void sh_eth_set_rate(struct net_device *ndev)
358 {
359 struct sh_eth_private *mdp = netdev_priv(ndev);
360
361 switch (mdp->speed) {
362 case 10: /* 10BASE */
363 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_ELB, ECMR);
364 break;
365 case 100:/* 100BASE */
366 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_ELB, ECMR);
367 break;
368 default:
369 break;
370 }
371 }
372
373 /* R8A7778/9 */
374 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
375 .set_duplex = sh_eth_set_duplex,
376 .set_rate = sh_eth_set_rate,
377
378 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
379 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
380 .eesipr_value = 0x01ff009f,
381
382 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
383 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
384 EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
385 .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
386
387 .apr = 1,
388 .mpr = 1,
389 .tpauser = 1,
390 .hw_swap = 1,
391 };
392 #elif defined(CONFIG_CPU_SUBTYPE_SH7724)
393 #define SH_ETH_RESET_DEFAULT 1
394
395 static void sh_eth_set_rate(struct net_device *ndev)
396 {
397 struct sh_eth_private *mdp = netdev_priv(ndev);
398
399 switch (mdp->speed) {
400 case 10: /* 10BASE */
401 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);
402 break;
403 case 100:/* 100BASE */
404 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);
405 break;
406 default:
407 break;
408 }
409 }
410
411 /* SH7724 */
412 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
413 .set_duplex = sh_eth_set_duplex,
414 .set_rate = sh_eth_set_rate,
415
416 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
417 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
418 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x01ff009f,
419
420 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
421 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
422 EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
423 .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
424
425 .apr = 1,
426 .mpr = 1,
427 .tpauser = 1,
428 .hw_swap = 1,
429 .rpadir = 1,
430 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
431 };
432 #elif defined(CONFIG_CPU_SUBTYPE_SH7757)
433 #define SH_ETH_HAS_BOTH_MODULES 1
434 static int sh_eth_check_reset(struct net_device *ndev);
435
436 static void sh_eth_set_rate(struct net_device *ndev)
437 {
438 struct sh_eth_private *mdp = netdev_priv(ndev);
439
440 switch (mdp->speed) {
441 case 10: /* 10BASE */
442 sh_eth_write(ndev, 0, RTRATE);
443 break;
444 case 100:/* 100BASE */
445 sh_eth_write(ndev, 1, RTRATE);
446 break;
447 default:
448 break;
449 }
450 }
451
452 /* SH7757 */
453 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
454 .set_duplex = sh_eth_set_duplex,
455 .set_rate = sh_eth_set_rate,
456
457 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
458 .rmcr_value = 0x00000001,
459
460 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
461 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
462 EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
463 .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
464
465 .irq_flags = IRQF_SHARED,
466 .apr = 1,
467 .mpr = 1,
468 .tpauser = 1,
469 .hw_swap = 1,
470 .no_ade = 1,
471 .rpadir = 1,
472 .rpadir_value = 2 << 16,
473 };
474
475 #define SH_GIGA_ETH_BASE 0xfee00000
476 #define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
477 #define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
478 static void sh_eth_chip_reset_giga(struct net_device *ndev)
479 {
480 int i;
481 unsigned long mahr[2], malr[2];
482
483 /* save MAHR and MALR */
484 for (i = 0; i < 2; i++) {
485 malr[i] = ioread32((void *)GIGA_MALR(i));
486 mahr[i] = ioread32((void *)GIGA_MAHR(i));
487 }
488
489 /* reset device */
490 iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800));
491 mdelay(1);
492
493 /* restore MAHR and MALR */
494 for (i = 0; i < 2; i++) {
495 iowrite32(malr[i], (void *)GIGA_MALR(i));
496 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
497 }
498 }
499
500 static int sh_eth_is_gether(struct sh_eth_private *mdp);
501 static int sh_eth_reset(struct net_device *ndev)
502 {
503 struct sh_eth_private *mdp = netdev_priv(ndev);
504 int ret = 0;
505
506 if (sh_eth_is_gether(mdp)) {
507 sh_eth_write(ndev, EDSR_ENALL, EDSR);
508 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
509 EDMR);
510
511 ret = sh_eth_check_reset(ndev);
512 if (ret)
513 goto out;
514
515 /* Table Init */
516 sh_eth_write(ndev, 0x0, TDLAR);
517 sh_eth_write(ndev, 0x0, TDFAR);
518 sh_eth_write(ndev, 0x0, TDFXR);
519 sh_eth_write(ndev, 0x0, TDFFR);
520 sh_eth_write(ndev, 0x0, RDLAR);
521 sh_eth_write(ndev, 0x0, RDFAR);
522 sh_eth_write(ndev, 0x0, RDFXR);
523 sh_eth_write(ndev, 0x0, RDFFR);
524 } else {
525 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
526 EDMR);
527 mdelay(3);
528 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
529 EDMR);
530 }
531
532 out:
533 return ret;
534 }
535
536 static void sh_eth_set_rate_giga(struct net_device *ndev)
537 {
538 struct sh_eth_private *mdp = netdev_priv(ndev);
539
540 switch (mdp->speed) {
541 case 10: /* 10BASE */
542 sh_eth_write(ndev, 0x00000000, GECMR);
543 break;
544 case 100:/* 100BASE */
545 sh_eth_write(ndev, 0x00000010, GECMR);
546 break;
547 case 1000: /* 1000BASE */
548 sh_eth_write(ndev, 0x00000020, GECMR);
549 break;
550 default:
551 break;
552 }
553 }
554
555 /* SH7757(GETHERC) */
556 static struct sh_eth_cpu_data sh_eth_my_cpu_data_giga = {
557 .chip_reset = sh_eth_chip_reset_giga,
558 .set_duplex = sh_eth_set_duplex,
559 .set_rate = sh_eth_set_rate_giga,
560
561 .ecsr_value = ECSR_ICD | ECSR_MPD,
562 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
563 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
564
565 .tx_check = EESR_TC1 | EESR_FTC,
566 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
567 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
568 EESR_ECI,
569 .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
570 EESR_TFE,
571 .fdr_value = 0x0000072f,
572 .rmcr_value = 0x00000001,
573
574 .irq_flags = IRQF_SHARED,
575 .apr = 1,
576 .mpr = 1,
577 .tpauser = 1,
578 .bculr = 1,
579 .hw_swap = 1,
580 .rpadir = 1,
581 .rpadir_value = 2 << 16,
582 .no_trimd = 1,
583 .no_ade = 1,
584 .tsu = 1,
585 };
586
587 static struct sh_eth_cpu_data *sh_eth_get_cpu_data(struct sh_eth_private *mdp)
588 {
589 if (sh_eth_is_gether(mdp))
590 return &sh_eth_my_cpu_data_giga;
591 else
592 return &sh_eth_my_cpu_data;
593 }
594
595 #elif defined(CONFIG_CPU_SUBTYPE_SH7734) || defined(CONFIG_CPU_SUBTYPE_SH7763)
596 static int sh_eth_check_reset(struct net_device *ndev);
597 static void sh_eth_reset_hw_crc(struct net_device *ndev);
598
599 static void sh_eth_chip_reset(struct net_device *ndev)
600 {
601 struct sh_eth_private *mdp = netdev_priv(ndev);
602
603 /* reset device */
604 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
605 mdelay(1);
606 }
607
608 static void sh_eth_set_rate(struct net_device *ndev)
609 {
610 struct sh_eth_private *mdp = netdev_priv(ndev);
611
612 switch (mdp->speed) {
613 case 10: /* 10BASE */
614 sh_eth_write(ndev, GECMR_10, GECMR);
615 break;
616 case 100:/* 100BASE */
617 sh_eth_write(ndev, GECMR_100, GECMR);
618 break;
619 case 1000: /* 1000BASE */
620 sh_eth_write(ndev, GECMR_1000, GECMR);
621 break;
622 default:
623 break;
624 }
625 }
626
627 /* sh7763 */
628 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
629 .chip_reset = sh_eth_chip_reset,
630 .set_duplex = sh_eth_set_duplex,
631 .set_rate = sh_eth_set_rate,
632
633 .ecsr_value = ECSR_ICD | ECSR_MPD,
634 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
635 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
636
637 .tx_check = EESR_TC1 | EESR_FTC,
638 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
639 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
640 EESR_ECI,
641 .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
642 EESR_TFE,
643
644 .apr = 1,
645 .mpr = 1,
646 .tpauser = 1,
647 .bculr = 1,
648 .hw_swap = 1,
649 .no_trimd = 1,
650 .no_ade = 1,
651 .tsu = 1,
652 #if defined(CONFIG_CPU_SUBTYPE_SH7734)
653 .hw_crc = 1,
654 .select_mii = 1,
655 #else
656 .irq_flags = IRQF_SHARED,
657 #endif
658 };
659
660 static int sh_eth_reset(struct net_device *ndev)
661 {
662 int ret = 0;
663
664 sh_eth_write(ndev, EDSR_ENALL, EDSR);
665 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER, EDMR);
666
667 ret = sh_eth_check_reset(ndev);
668 if (ret)
669 goto out;
670
671 /* Table Init */
672 sh_eth_write(ndev, 0x0, TDLAR);
673 sh_eth_write(ndev, 0x0, TDFAR);
674 sh_eth_write(ndev, 0x0, TDFXR);
675 sh_eth_write(ndev, 0x0, TDFFR);
676 sh_eth_write(ndev, 0x0, RDLAR);
677 sh_eth_write(ndev, 0x0, RDFAR);
678 sh_eth_write(ndev, 0x0, RDFXR);
679 sh_eth_write(ndev, 0x0, RDFFR);
680
681 /* Reset HW CRC register */
682 sh_eth_reset_hw_crc(ndev);
683
684 /* Select MII mode */
685 if (sh_eth_my_cpu_data.select_mii)
686 sh_eth_select_mii(ndev);
687 out:
688 return ret;
689 }
690
691 static void sh_eth_reset_hw_crc(struct net_device *ndev)
692 {
693 if (sh_eth_my_cpu_data.hw_crc)
694 sh_eth_write(ndev, 0x0, CSMR);
695 }
696
697 #elif defined(CONFIG_ARCH_R8A7740)
698 static int sh_eth_check_reset(struct net_device *ndev);
699
700 static void sh_eth_chip_reset(struct net_device *ndev)
701 {
702 struct sh_eth_private *mdp = netdev_priv(ndev);
703
704 /* reset device */
705 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
706 mdelay(1);
707
708 sh_eth_select_mii(ndev);
709 }
710
711 static int sh_eth_reset(struct net_device *ndev)
712 {
713 int ret = 0;
714
715 sh_eth_write(ndev, EDSR_ENALL, EDSR);
716 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER, EDMR);
717
718 ret = sh_eth_check_reset(ndev);
719 if (ret)
720 goto out;
721
722 /* Table Init */
723 sh_eth_write(ndev, 0x0, TDLAR);
724 sh_eth_write(ndev, 0x0, TDFAR);
725 sh_eth_write(ndev, 0x0, TDFXR);
726 sh_eth_write(ndev, 0x0, TDFFR);
727 sh_eth_write(ndev, 0x0, RDLAR);
728 sh_eth_write(ndev, 0x0, RDFAR);
729 sh_eth_write(ndev, 0x0, RDFXR);
730 sh_eth_write(ndev, 0x0, RDFFR);
731
732 out:
733 return ret;
734 }
735
736 static void sh_eth_set_rate(struct net_device *ndev)
737 {
738 struct sh_eth_private *mdp = netdev_priv(ndev);
739
740 switch (mdp->speed) {
741 case 10: /* 10BASE */
742 sh_eth_write(ndev, GECMR_10, GECMR);
743 break;
744 case 100:/* 100BASE */
745 sh_eth_write(ndev, GECMR_100, GECMR);
746 break;
747 case 1000: /* 1000BASE */
748 sh_eth_write(ndev, GECMR_1000, GECMR);
749 break;
750 default:
751 break;
752 }
753 }
754
755 /* R8A7740 */
756 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
757 .chip_reset = sh_eth_chip_reset,
758 .set_duplex = sh_eth_set_duplex,
759 .set_rate = sh_eth_set_rate,
760
761 .ecsr_value = ECSR_ICD | ECSR_MPD,
762 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
763 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
764
765 .tx_check = EESR_TC1 | EESR_FTC,
766 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
767 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
768 EESR_ECI,
769 .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
770 EESR_TFE,
771
772 .apr = 1,
773 .mpr = 1,
774 .tpauser = 1,
775 .bculr = 1,
776 .hw_swap = 1,
777 .no_trimd = 1,
778 .no_ade = 1,
779 .tsu = 1,
780 .select_mii = 1,
781 };
782
783 #elif defined(CONFIG_CPU_SUBTYPE_SH7619)
784 #define SH_ETH_RESET_DEFAULT 1
785 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
786 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
787
788 .apr = 1,
789 .mpr = 1,
790 .tpauser = 1,
791 .hw_swap = 1,
792 };
793 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
794 #define SH_ETH_RESET_DEFAULT 1
795 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
796 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
797 .tsu = 1,
798 };
799 #endif
800
801 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
802 {
803 if (!cd->ecsr_value)
804 cd->ecsr_value = DEFAULT_ECSR_INIT;
805
806 if (!cd->ecsipr_value)
807 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
808
809 if (!cd->fcftr_value)
810 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF | \
811 DEFAULT_FIFO_F_D_RFD;
812
813 if (!cd->fdr_value)
814 cd->fdr_value = DEFAULT_FDR_INIT;
815
816 if (!cd->rmcr_value)
817 cd->rmcr_value = DEFAULT_RMCR_VALUE;
818
819 if (!cd->tx_check)
820 cd->tx_check = DEFAULT_TX_CHECK;
821
822 if (!cd->eesr_err_check)
823 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
824
825 if (!cd->tx_error_check)
826 cd->tx_error_check = DEFAULT_TX_ERROR_CHECK;
827 }
828
829 #if defined(SH_ETH_RESET_DEFAULT)
830 /* Chip Reset */
831 static int sh_eth_reset(struct net_device *ndev)
832 {
833 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER, EDMR);
834 mdelay(3);
835 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER, EDMR);
836
837 return 0;
838 }
839 #else
840 static int sh_eth_check_reset(struct net_device *ndev)
841 {
842 int ret = 0;
843 int cnt = 100;
844
845 while (cnt > 0) {
846 if (!(sh_eth_read(ndev, EDMR) & 0x3))
847 break;
848 mdelay(1);
849 cnt--;
850 }
851 if (cnt < 0) {
852 pr_err("Device reset fail\n");
853 ret = -ETIMEDOUT;
854 }
855 return ret;
856 }
857 #endif
858
859 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
860 static void sh_eth_set_receive_align(struct sk_buff *skb)
861 {
862 int reserve;
863
864 reserve = SH4_SKB_RX_ALIGN - ((u32)skb->data & (SH4_SKB_RX_ALIGN - 1));
865 if (reserve)
866 skb_reserve(skb, reserve);
867 }
868 #else
869 static void sh_eth_set_receive_align(struct sk_buff *skb)
870 {
871 skb_reserve(skb, SH2_SH3_SKB_RX_ALIGN);
872 }
873 #endif
874
875
876 /* CPU <-> EDMAC endian convert */
877 static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
878 {
879 switch (mdp->edmac_endian) {
880 case EDMAC_LITTLE_ENDIAN:
881 return cpu_to_le32(x);
882 case EDMAC_BIG_ENDIAN:
883 return cpu_to_be32(x);
884 }
885 return x;
886 }
887
888 static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
889 {
890 switch (mdp->edmac_endian) {
891 case EDMAC_LITTLE_ENDIAN:
892 return le32_to_cpu(x);
893 case EDMAC_BIG_ENDIAN:
894 return be32_to_cpu(x);
895 }
896 return x;
897 }
898
899 /*
900 * Program the hardware MAC address from dev->dev_addr.
901 */
902 static void update_mac_address(struct net_device *ndev)
903 {
904 sh_eth_write(ndev,
905 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
906 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
907 sh_eth_write(ndev,
908 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
909 }
910
911 /*
912 * Get MAC address from SuperH MAC address register
913 *
914 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
915 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
916 * When you want use this device, you must set MAC address in bootloader.
917 *
918 */
919 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
920 {
921 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
922 memcpy(ndev->dev_addr, mac, 6);
923 } else {
924 ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24);
925 ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF;
926 ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF;
927 ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF);
928 ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF;
929 ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF);
930 }
931 }
932
933 static int sh_eth_is_gether(struct sh_eth_private *mdp)
934 {
935 if (mdp->reg_offset == sh_eth_offset_gigabit)
936 return 1;
937 else
938 return 0;
939 }
940
941 static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
942 {
943 if (sh_eth_is_gether(mdp))
944 return EDTRR_TRNS_GETHER;
945 else
946 return EDTRR_TRNS_ETHER;
947 }
948
949 struct bb_info {
950 void (*set_gate)(void *addr);
951 struct mdiobb_ctrl ctrl;
952 void *addr;
953 u32 mmd_msk;/* MMD */
954 u32 mdo_msk;
955 u32 mdi_msk;
956 u32 mdc_msk;
957 };
958
959 /* PHY bit set */
960 static void bb_set(void *addr, u32 msk)
961 {
962 iowrite32(ioread32(addr) | msk, addr);
963 }
964
965 /* PHY bit clear */
966 static void bb_clr(void *addr, u32 msk)
967 {
968 iowrite32((ioread32(addr) & ~msk), addr);
969 }
970
971 /* PHY bit read */
972 static int bb_read(void *addr, u32 msk)
973 {
974 return (ioread32(addr) & msk) != 0;
975 }
976
977 /* Data I/O pin control */
978 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
979 {
980 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
981
982 if (bitbang->set_gate)
983 bitbang->set_gate(bitbang->addr);
984
985 if (bit)
986 bb_set(bitbang->addr, bitbang->mmd_msk);
987 else
988 bb_clr(bitbang->addr, bitbang->mmd_msk);
989 }
990
991 /* Set bit data*/
992 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
993 {
994 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
995
996 if (bitbang->set_gate)
997 bitbang->set_gate(bitbang->addr);
998
999 if (bit)
1000 bb_set(bitbang->addr, bitbang->mdo_msk);
1001 else
1002 bb_clr(bitbang->addr, bitbang->mdo_msk);
1003 }
1004
1005 /* Get bit data*/
1006 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1007 {
1008 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1009
1010 if (bitbang->set_gate)
1011 bitbang->set_gate(bitbang->addr);
1012
1013 return bb_read(bitbang->addr, bitbang->mdi_msk);
1014 }
1015
1016 /* MDC pin control */
1017 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1018 {
1019 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1020
1021 if (bitbang->set_gate)
1022 bitbang->set_gate(bitbang->addr);
1023
1024 if (bit)
1025 bb_set(bitbang->addr, bitbang->mdc_msk);
1026 else
1027 bb_clr(bitbang->addr, bitbang->mdc_msk);
1028 }
1029
1030 /* mdio bus control struct */
1031 static struct mdiobb_ops bb_ops = {
1032 .owner = THIS_MODULE,
1033 .set_mdc = sh_mdc_ctrl,
1034 .set_mdio_dir = sh_mmd_ctrl,
1035 .set_mdio_data = sh_set_mdio,
1036 .get_mdio_data = sh_get_mdio,
1037 };
1038
1039 /* free skb and descriptor buffer */
1040 static void sh_eth_ring_free(struct net_device *ndev)
1041 {
1042 struct sh_eth_private *mdp = netdev_priv(ndev);
1043 int i;
1044
1045 /* Free Rx skb ringbuffer */
1046 if (mdp->rx_skbuff) {
1047 for (i = 0; i < mdp->num_rx_ring; i++) {
1048 if (mdp->rx_skbuff[i])
1049 dev_kfree_skb(mdp->rx_skbuff[i]);
1050 }
1051 }
1052 kfree(mdp->rx_skbuff);
1053 mdp->rx_skbuff = NULL;
1054
1055 /* Free Tx skb ringbuffer */
1056 if (mdp->tx_skbuff) {
1057 for (i = 0; i < mdp->num_tx_ring; i++) {
1058 if (mdp->tx_skbuff[i])
1059 dev_kfree_skb(mdp->tx_skbuff[i]);
1060 }
1061 }
1062 kfree(mdp->tx_skbuff);
1063 mdp->tx_skbuff = NULL;
1064 }
1065
1066 /* format skb and descriptor buffer */
1067 static void sh_eth_ring_format(struct net_device *ndev)
1068 {
1069 struct sh_eth_private *mdp = netdev_priv(ndev);
1070 int i;
1071 struct sk_buff *skb;
1072 struct sh_eth_rxdesc *rxdesc = NULL;
1073 struct sh_eth_txdesc *txdesc = NULL;
1074 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1075 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
1076
1077 mdp->cur_rx = mdp->cur_tx = 0;
1078 mdp->dirty_rx = mdp->dirty_tx = 0;
1079
1080 memset(mdp->rx_ring, 0, rx_ringsize);
1081
1082 /* build Rx ring buffer */
1083 for (i = 0; i < mdp->num_rx_ring; i++) {
1084 /* skb */
1085 mdp->rx_skbuff[i] = NULL;
1086 skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
1087 mdp->rx_skbuff[i] = skb;
1088 if (skb == NULL)
1089 break;
1090 dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
1091 DMA_FROM_DEVICE);
1092 sh_eth_set_receive_align(skb);
1093
1094 /* RX descriptor */
1095 rxdesc = &mdp->rx_ring[i];
1096 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
1097 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1098
1099 /* The size of the buffer is 16 byte boundary. */
1100 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
1101 /* Rx descriptor address set */
1102 if (i == 0) {
1103 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
1104 if (sh_eth_is_gether(mdp))
1105 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
1106 }
1107 }
1108
1109 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
1110
1111 /* Mark the last entry as wrapping the ring. */
1112 rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL);
1113
1114 memset(mdp->tx_ring, 0, tx_ringsize);
1115
1116 /* build Tx ring buffer */
1117 for (i = 0; i < mdp->num_tx_ring; i++) {
1118 mdp->tx_skbuff[i] = NULL;
1119 txdesc = &mdp->tx_ring[i];
1120 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1121 txdesc->buffer_length = 0;
1122 if (i == 0) {
1123 /* Tx descriptor address set */
1124 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
1125 if (sh_eth_is_gether(mdp))
1126 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
1127 }
1128 }
1129
1130 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1131 }
1132
1133 /* Get skb and descriptor buffer */
1134 static int sh_eth_ring_init(struct net_device *ndev)
1135 {
1136 struct sh_eth_private *mdp = netdev_priv(ndev);
1137 int rx_ringsize, tx_ringsize, ret = 0;
1138
1139 /*
1140 * +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1141 * card needs room to do 8 byte alignment, +2 so we can reserve
1142 * the first 2 bytes, and +16 gets room for the status word from the
1143 * card.
1144 */
1145 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1146 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
1147 if (mdp->cd->rpadir)
1148 mdp->rx_buf_sz += NET_IP_ALIGN;
1149
1150 /* Allocate RX and TX skb rings */
1151 mdp->rx_skbuff = kmalloc_array(mdp->num_rx_ring,
1152 sizeof(*mdp->rx_skbuff), GFP_KERNEL);
1153 if (!mdp->rx_skbuff) {
1154 ret = -ENOMEM;
1155 return ret;
1156 }
1157
1158 mdp->tx_skbuff = kmalloc_array(mdp->num_tx_ring,
1159 sizeof(*mdp->tx_skbuff), GFP_KERNEL);
1160 if (!mdp->tx_skbuff) {
1161 ret = -ENOMEM;
1162 goto skb_ring_free;
1163 }
1164
1165 /* Allocate all Rx descriptors. */
1166 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1167 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
1168 GFP_KERNEL);
1169 if (!mdp->rx_ring) {
1170 ret = -ENOMEM;
1171 goto desc_ring_free;
1172 }
1173
1174 mdp->dirty_rx = 0;
1175
1176 /* Allocate all Tx descriptors. */
1177 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1178 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
1179 GFP_KERNEL);
1180 if (!mdp->tx_ring) {
1181 ret = -ENOMEM;
1182 goto desc_ring_free;
1183 }
1184 return ret;
1185
1186 desc_ring_free:
1187 /* free DMA buffer */
1188 dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma);
1189
1190 skb_ring_free:
1191 /* Free Rx and Tx skb ring buffer */
1192 sh_eth_ring_free(ndev);
1193 mdp->tx_ring = NULL;
1194 mdp->rx_ring = NULL;
1195
1196 return ret;
1197 }
1198
1199 static void sh_eth_free_dma_buffer(struct sh_eth_private *mdp)
1200 {
1201 int ringsize;
1202
1203 if (mdp->rx_ring) {
1204 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1205 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1206 mdp->rx_desc_dma);
1207 mdp->rx_ring = NULL;
1208 }
1209
1210 if (mdp->tx_ring) {
1211 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1212 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1213 mdp->tx_desc_dma);
1214 mdp->tx_ring = NULL;
1215 }
1216 }
1217
1218 static int sh_eth_dev_init(struct net_device *ndev, bool start)
1219 {
1220 int ret = 0;
1221 struct sh_eth_private *mdp = netdev_priv(ndev);
1222 u32 val;
1223
1224 /* Soft Reset */
1225 ret = sh_eth_reset(ndev);
1226 if (ret)
1227 goto out;
1228
1229 /* Descriptor format */
1230 sh_eth_ring_format(ndev);
1231 if (mdp->cd->rpadir)
1232 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
1233
1234 /* all sh_eth int mask */
1235 sh_eth_write(ndev, 0, EESIPR);
1236
1237 #if defined(__LITTLE_ENDIAN)
1238 if (mdp->cd->hw_swap)
1239 sh_eth_write(ndev, EDMR_EL, EDMR);
1240 else
1241 #endif
1242 sh_eth_write(ndev, 0, EDMR);
1243
1244 /* FIFO size set */
1245 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1246 sh_eth_write(ndev, 0, TFTR);
1247
1248 /* Frame recv control */
1249 sh_eth_write(ndev, mdp->cd->rmcr_value, RMCR);
1250
1251 sh_eth_write(ndev, DESC_I_RINT8 | DESC_I_RINT5 | DESC_I_TINT2, TRSCER);
1252
1253 if (mdp->cd->bculr)
1254 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */
1255
1256 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1257
1258 if (!mdp->cd->no_trimd)
1259 sh_eth_write(ndev, 0, TRIMD);
1260
1261 /* Recv frame limit set register */
1262 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1263 RFLR);
1264
1265 sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
1266 if (start)
1267 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1268
1269 /* PAUSE Prohibition */
1270 val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
1271 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
1272
1273 sh_eth_write(ndev, val, ECMR);
1274
1275 if (mdp->cd->set_rate)
1276 mdp->cd->set_rate(ndev);
1277
1278 /* E-MAC Status Register clear */
1279 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1280
1281 /* E-MAC Interrupt Enable register */
1282 if (start)
1283 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1284
1285 /* Set MAC address */
1286 update_mac_address(ndev);
1287
1288 /* mask reset */
1289 if (mdp->cd->apr)
1290 sh_eth_write(ndev, APR_AP, APR);
1291 if (mdp->cd->mpr)
1292 sh_eth_write(ndev, MPR_MP, MPR);
1293 if (mdp->cd->tpauser)
1294 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1295
1296 if (start) {
1297 /* Setting the Rx mode will start the Rx process. */
1298 sh_eth_write(ndev, EDRRR_R, EDRRR);
1299
1300 netif_start_queue(ndev);
1301 }
1302
1303 out:
1304 return ret;
1305 }
1306
1307 /* free Tx skb function */
1308 static int sh_eth_txfree(struct net_device *ndev)
1309 {
1310 struct sh_eth_private *mdp = netdev_priv(ndev);
1311 struct sh_eth_txdesc *txdesc;
1312 int freeNum = 0;
1313 int entry = 0;
1314
1315 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1316 entry = mdp->dirty_tx % mdp->num_tx_ring;
1317 txdesc = &mdp->tx_ring[entry];
1318 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
1319 break;
1320 /* Free the original skb. */
1321 if (mdp->tx_skbuff[entry]) {
1322 dma_unmap_single(&ndev->dev, txdesc->addr,
1323 txdesc->buffer_length, DMA_TO_DEVICE);
1324 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1325 mdp->tx_skbuff[entry] = NULL;
1326 freeNum++;
1327 }
1328 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1329 if (entry >= mdp->num_tx_ring - 1)
1330 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1331
1332 ndev->stats.tx_packets++;
1333 ndev->stats.tx_bytes += txdesc->buffer_length;
1334 }
1335 return freeNum;
1336 }
1337
1338 /* Packet receive function */
1339 static int sh_eth_rx(struct net_device *ndev, u32 intr_status)
1340 {
1341 struct sh_eth_private *mdp = netdev_priv(ndev);
1342 struct sh_eth_rxdesc *rxdesc;
1343
1344 int entry = mdp->cur_rx % mdp->num_rx_ring;
1345 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1346 struct sk_buff *skb;
1347 u16 pkt_len = 0;
1348 u32 desc_status;
1349
1350 rxdesc = &mdp->rx_ring[entry];
1351 while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
1352 desc_status = edmac_to_cpu(mdp, rxdesc->status);
1353 pkt_len = rxdesc->frame_length;
1354
1355 #if defined(CONFIG_ARCH_R8A7740)
1356 desc_status >>= 16;
1357 #endif
1358
1359 if (--boguscnt < 0)
1360 break;
1361
1362 if (!(desc_status & RDFEND))
1363 ndev->stats.rx_length_errors++;
1364
1365 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1366 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1367 ndev->stats.rx_errors++;
1368 if (desc_status & RD_RFS1)
1369 ndev->stats.rx_crc_errors++;
1370 if (desc_status & RD_RFS2)
1371 ndev->stats.rx_frame_errors++;
1372 if (desc_status & RD_RFS3)
1373 ndev->stats.rx_length_errors++;
1374 if (desc_status & RD_RFS4)
1375 ndev->stats.rx_length_errors++;
1376 if (desc_status & RD_RFS6)
1377 ndev->stats.rx_missed_errors++;
1378 if (desc_status & RD_RFS10)
1379 ndev->stats.rx_over_errors++;
1380 } else {
1381 if (!mdp->cd->hw_swap)
1382 sh_eth_soft_swap(
1383 phys_to_virt(ALIGN(rxdesc->addr, 4)),
1384 pkt_len + 2);
1385 skb = mdp->rx_skbuff[entry];
1386 mdp->rx_skbuff[entry] = NULL;
1387 if (mdp->cd->rpadir)
1388 skb_reserve(skb, NET_IP_ALIGN);
1389 skb_put(skb, pkt_len);
1390 skb->protocol = eth_type_trans(skb, ndev);
1391 netif_rx(skb);
1392 ndev->stats.rx_packets++;
1393 ndev->stats.rx_bytes += pkt_len;
1394 }
1395 rxdesc->status |= cpu_to_edmac(mdp, RD_RACT);
1396 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
1397 rxdesc = &mdp->rx_ring[entry];
1398 }
1399
1400 /* Refill the Rx ring buffers. */
1401 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1402 entry = mdp->dirty_rx % mdp->num_rx_ring;
1403 rxdesc = &mdp->rx_ring[entry];
1404 /* The size of the buffer is 16 byte boundary. */
1405 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
1406
1407 if (mdp->rx_skbuff[entry] == NULL) {
1408 skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
1409 mdp->rx_skbuff[entry] = skb;
1410 if (skb == NULL)
1411 break; /* Better luck next round. */
1412 dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
1413 DMA_FROM_DEVICE);
1414 sh_eth_set_receive_align(skb);
1415
1416 skb_checksum_none_assert(skb);
1417 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
1418 }
1419 if (entry >= mdp->num_rx_ring - 1)
1420 rxdesc->status |=
1421 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
1422 else
1423 rxdesc->status |=
1424 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1425 }
1426
1427 /* Restart Rx engine if stopped. */
1428 /* If we don't need to check status, don't. -KDU */
1429 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1430 /* fix the values for the next receiving if RDE is set */
1431 if (intr_status & EESR_RDE)
1432 mdp->cur_rx = mdp->dirty_rx =
1433 (sh_eth_read(ndev, RDFAR) -
1434 sh_eth_read(ndev, RDLAR)) >> 4;
1435 sh_eth_write(ndev, EDRRR_R, EDRRR);
1436 }
1437
1438 return 0;
1439 }
1440
1441 static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1442 {
1443 /* disable tx and rx */
1444 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
1445 ~(ECMR_RE | ECMR_TE), ECMR);
1446 }
1447
1448 static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1449 {
1450 /* enable tx and rx */
1451 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
1452 (ECMR_RE | ECMR_TE), ECMR);
1453 }
1454
1455 /* error control function */
1456 static void sh_eth_error(struct net_device *ndev, int intr_status)
1457 {
1458 struct sh_eth_private *mdp = netdev_priv(ndev);
1459 u32 felic_stat;
1460 u32 link_stat;
1461 u32 mask;
1462
1463 if (intr_status & EESR_ECI) {
1464 felic_stat = sh_eth_read(ndev, ECSR);
1465 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
1466 if (felic_stat & ECSR_ICD)
1467 ndev->stats.tx_carrier_errors++;
1468 if (felic_stat & ECSR_LCHNG) {
1469 /* Link Changed */
1470 if (mdp->cd->no_psr || mdp->no_ether_link) {
1471 goto ignore_link;
1472 } else {
1473 link_stat = (sh_eth_read(ndev, PSR));
1474 if (mdp->ether_link_active_low)
1475 link_stat = ~link_stat;
1476 }
1477 if (!(link_stat & PHY_ST_LINK))
1478 sh_eth_rcv_snd_disable(ndev);
1479 else {
1480 /* Link Up */
1481 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
1482 ~DMAC_M_ECI, EESIPR);
1483 /*clear int */
1484 sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
1485 ECSR);
1486 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
1487 DMAC_M_ECI, EESIPR);
1488 /* enable tx and rx */
1489 sh_eth_rcv_snd_enable(ndev);
1490 }
1491 }
1492 }
1493
1494 ignore_link:
1495 if (intr_status & EESR_TWB) {
1496 /* Write buck end. unused write back interrupt */
1497 if (intr_status & EESR_TABT) /* Transmit Abort int */
1498 ndev->stats.tx_aborted_errors++;
1499 if (netif_msg_tx_err(mdp))
1500 dev_err(&ndev->dev, "Transmit Abort\n");
1501 }
1502
1503 if (intr_status & EESR_RABT) {
1504 /* Receive Abort int */
1505 if (intr_status & EESR_RFRMER) {
1506 /* Receive Frame Overflow int */
1507 ndev->stats.rx_frame_errors++;
1508 if (netif_msg_rx_err(mdp))
1509 dev_err(&ndev->dev, "Receive Abort\n");
1510 }
1511 }
1512
1513 if (intr_status & EESR_TDE) {
1514 /* Transmit Descriptor Empty int */
1515 ndev->stats.tx_fifo_errors++;
1516 if (netif_msg_tx_err(mdp))
1517 dev_err(&ndev->dev, "Transmit Descriptor Empty\n");
1518 }
1519
1520 if (intr_status & EESR_TFE) {
1521 /* FIFO under flow */
1522 ndev->stats.tx_fifo_errors++;
1523 if (netif_msg_tx_err(mdp))
1524 dev_err(&ndev->dev, "Transmit FIFO Under flow\n");
1525 }
1526
1527 if (intr_status & EESR_RDE) {
1528 /* Receive Descriptor Empty int */
1529 ndev->stats.rx_over_errors++;
1530
1531 if (netif_msg_rx_err(mdp))
1532 dev_err(&ndev->dev, "Receive Descriptor Empty\n");
1533 }
1534
1535 if (intr_status & EESR_RFE) {
1536 /* Receive FIFO Overflow int */
1537 ndev->stats.rx_fifo_errors++;
1538 if (netif_msg_rx_err(mdp))
1539 dev_err(&ndev->dev, "Receive FIFO Overflow\n");
1540 }
1541
1542 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1543 /* Address Error */
1544 ndev->stats.tx_fifo_errors++;
1545 if (netif_msg_tx_err(mdp))
1546 dev_err(&ndev->dev, "Address Error\n");
1547 }
1548
1549 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1550 if (mdp->cd->no_ade)
1551 mask &= ~EESR_ADE;
1552 if (intr_status & mask) {
1553 /* Tx error */
1554 u32 edtrr = sh_eth_read(ndev, EDTRR);
1555 /* dmesg */
1556 dev_err(&ndev->dev, "TX error. status=%8.8x cur_tx=%8.8x ",
1557 intr_status, mdp->cur_tx);
1558 dev_err(&ndev->dev, "dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1559 mdp->dirty_tx, (u32) ndev->state, edtrr);
1560 /* dirty buffer free */
1561 sh_eth_txfree(ndev);
1562
1563 /* SH7712 BUG */
1564 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
1565 /* tx dma start */
1566 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1567 }
1568 /* wakeup */
1569 netif_wake_queue(ndev);
1570 }
1571 }
1572
1573 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1574 {
1575 struct net_device *ndev = netdev;
1576 struct sh_eth_private *mdp = netdev_priv(ndev);
1577 struct sh_eth_cpu_data *cd = mdp->cd;
1578 irqreturn_t ret = IRQ_NONE;
1579 unsigned long intr_status;
1580
1581 spin_lock(&mdp->lock);
1582
1583 /* Get interrupt status */
1584 intr_status = sh_eth_read(ndev, EESR);
1585 /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1586 * enabled since it's the one that comes thru regardless of the mask,
1587 * and we need to fully handle it in sh_eth_error() in order to quench
1588 * it as it doesn't get cleared by just writing 1 to the ECI bit...
1589 */
1590 intr_status &= sh_eth_read(ndev, EESIPR) | DMAC_M_ECI;
1591 /* Clear interrupt */
1592 if (intr_status & (EESR_FRC | EESR_RMAF | EESR_RRF |
1593 EESR_RTLF | EESR_RTSF | EESR_PRE | EESR_CERF |
1594 cd->tx_check | cd->eesr_err_check)) {
1595 sh_eth_write(ndev, intr_status, EESR);
1596 ret = IRQ_HANDLED;
1597 } else
1598 goto other_irq;
1599
1600 if (intr_status & (EESR_FRC | /* Frame recv*/
1601 EESR_RMAF | /* Multi cast address recv*/
1602 EESR_RRF | /* Bit frame recv */
1603 EESR_RTLF | /* Long frame recv*/
1604 EESR_RTSF | /* short frame recv */
1605 EESR_PRE | /* PHY-LSI recv error */
1606 EESR_CERF)){ /* recv frame CRC error */
1607 sh_eth_rx(ndev, intr_status);
1608 }
1609
1610 /* Tx Check */
1611 if (intr_status & cd->tx_check) {
1612 sh_eth_txfree(ndev);
1613 netif_wake_queue(ndev);
1614 }
1615
1616 if (intr_status & cd->eesr_err_check)
1617 sh_eth_error(ndev, intr_status);
1618
1619 other_irq:
1620 spin_unlock(&mdp->lock);
1621
1622 return ret;
1623 }
1624
1625 /* PHY state control function */
1626 static void sh_eth_adjust_link(struct net_device *ndev)
1627 {
1628 struct sh_eth_private *mdp = netdev_priv(ndev);
1629 struct phy_device *phydev = mdp->phydev;
1630 int new_state = 0;
1631
1632 if (phydev->link) {
1633 if (phydev->duplex != mdp->duplex) {
1634 new_state = 1;
1635 mdp->duplex = phydev->duplex;
1636 if (mdp->cd->set_duplex)
1637 mdp->cd->set_duplex(ndev);
1638 }
1639
1640 if (phydev->speed != mdp->speed) {
1641 new_state = 1;
1642 mdp->speed = phydev->speed;
1643 if (mdp->cd->set_rate)
1644 mdp->cd->set_rate(ndev);
1645 }
1646 if (!mdp->link) {
1647 sh_eth_write(ndev,
1648 (sh_eth_read(ndev, ECMR) & ~ECMR_TXF), ECMR);
1649 new_state = 1;
1650 mdp->link = phydev->link;
1651 if (mdp->cd->no_psr || mdp->no_ether_link)
1652 sh_eth_rcv_snd_enable(ndev);
1653 }
1654 } else if (mdp->link) {
1655 new_state = 1;
1656 mdp->link = 0;
1657 mdp->speed = 0;
1658 mdp->duplex = -1;
1659 if (mdp->cd->no_psr || mdp->no_ether_link)
1660 sh_eth_rcv_snd_disable(ndev);
1661 }
1662
1663 if (new_state && netif_msg_link(mdp))
1664 phy_print_status(phydev);
1665 }
1666
1667 /* PHY init function */
1668 static int sh_eth_phy_init(struct net_device *ndev)
1669 {
1670 struct sh_eth_private *mdp = netdev_priv(ndev);
1671 char phy_id[MII_BUS_ID_SIZE + 3];
1672 struct phy_device *phydev = NULL;
1673
1674 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1675 mdp->mii_bus->id , mdp->phy_id);
1676
1677 mdp->link = 0;
1678 mdp->speed = 0;
1679 mdp->duplex = -1;
1680
1681 /* Try connect to PHY */
1682 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1683 mdp->phy_interface);
1684 if (IS_ERR(phydev)) {
1685 dev_err(&ndev->dev, "phy_connect failed\n");
1686 return PTR_ERR(phydev);
1687 }
1688
1689 dev_info(&ndev->dev, "attached phy %i to driver %s\n",
1690 phydev->addr, phydev->drv->name);
1691
1692 mdp->phydev = phydev;
1693
1694 return 0;
1695 }
1696
1697 /* PHY control start function */
1698 static int sh_eth_phy_start(struct net_device *ndev)
1699 {
1700 struct sh_eth_private *mdp = netdev_priv(ndev);
1701 int ret;
1702
1703 ret = sh_eth_phy_init(ndev);
1704 if (ret)
1705 return ret;
1706
1707 /* reset phy - this also wakes it from PDOWN */
1708 phy_write(mdp->phydev, MII_BMCR, BMCR_RESET);
1709 phy_start(mdp->phydev);
1710
1711 return 0;
1712 }
1713
1714 static int sh_eth_get_settings(struct net_device *ndev,
1715 struct ethtool_cmd *ecmd)
1716 {
1717 struct sh_eth_private *mdp = netdev_priv(ndev);
1718 unsigned long flags;
1719 int ret;
1720
1721 spin_lock_irqsave(&mdp->lock, flags);
1722 ret = phy_ethtool_gset(mdp->phydev, ecmd);
1723 spin_unlock_irqrestore(&mdp->lock, flags);
1724
1725 return ret;
1726 }
1727
1728 static int sh_eth_set_settings(struct net_device *ndev,
1729 struct ethtool_cmd *ecmd)
1730 {
1731 struct sh_eth_private *mdp = netdev_priv(ndev);
1732 unsigned long flags;
1733 int ret;
1734
1735 spin_lock_irqsave(&mdp->lock, flags);
1736
1737 /* disable tx and rx */
1738 sh_eth_rcv_snd_disable(ndev);
1739
1740 ret = phy_ethtool_sset(mdp->phydev, ecmd);
1741 if (ret)
1742 goto error_exit;
1743
1744 if (ecmd->duplex == DUPLEX_FULL)
1745 mdp->duplex = 1;
1746 else
1747 mdp->duplex = 0;
1748
1749 if (mdp->cd->set_duplex)
1750 mdp->cd->set_duplex(ndev);
1751
1752 error_exit:
1753 mdelay(1);
1754
1755 /* enable tx and rx */
1756 sh_eth_rcv_snd_enable(ndev);
1757
1758 spin_unlock_irqrestore(&mdp->lock, flags);
1759
1760 return ret;
1761 }
1762
1763 static int sh_eth_nway_reset(struct net_device *ndev)
1764 {
1765 struct sh_eth_private *mdp = netdev_priv(ndev);
1766 unsigned long flags;
1767 int ret;
1768
1769 spin_lock_irqsave(&mdp->lock, flags);
1770 ret = phy_start_aneg(mdp->phydev);
1771 spin_unlock_irqrestore(&mdp->lock, flags);
1772
1773 return ret;
1774 }
1775
1776 static u32 sh_eth_get_msglevel(struct net_device *ndev)
1777 {
1778 struct sh_eth_private *mdp = netdev_priv(ndev);
1779 return mdp->msg_enable;
1780 }
1781
1782 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
1783 {
1784 struct sh_eth_private *mdp = netdev_priv(ndev);
1785 mdp->msg_enable = value;
1786 }
1787
1788 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
1789 "rx_current", "tx_current",
1790 "rx_dirty", "tx_dirty",
1791 };
1792 #define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
1793
1794 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
1795 {
1796 switch (sset) {
1797 case ETH_SS_STATS:
1798 return SH_ETH_STATS_LEN;
1799 default:
1800 return -EOPNOTSUPP;
1801 }
1802 }
1803
1804 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
1805 struct ethtool_stats *stats, u64 *data)
1806 {
1807 struct sh_eth_private *mdp = netdev_priv(ndev);
1808 int i = 0;
1809
1810 /* device-specific stats */
1811 data[i++] = mdp->cur_rx;
1812 data[i++] = mdp->cur_tx;
1813 data[i++] = mdp->dirty_rx;
1814 data[i++] = mdp->dirty_tx;
1815 }
1816
1817 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1818 {
1819 switch (stringset) {
1820 case ETH_SS_STATS:
1821 memcpy(data, *sh_eth_gstrings_stats,
1822 sizeof(sh_eth_gstrings_stats));
1823 break;
1824 }
1825 }
1826
1827 static void sh_eth_get_ringparam(struct net_device *ndev,
1828 struct ethtool_ringparam *ring)
1829 {
1830 struct sh_eth_private *mdp = netdev_priv(ndev);
1831
1832 ring->rx_max_pending = RX_RING_MAX;
1833 ring->tx_max_pending = TX_RING_MAX;
1834 ring->rx_pending = mdp->num_rx_ring;
1835 ring->tx_pending = mdp->num_tx_ring;
1836 }
1837
1838 static int sh_eth_set_ringparam(struct net_device *ndev,
1839 struct ethtool_ringparam *ring)
1840 {
1841 struct sh_eth_private *mdp = netdev_priv(ndev);
1842 int ret;
1843
1844 if (ring->tx_pending > TX_RING_MAX ||
1845 ring->rx_pending > RX_RING_MAX ||
1846 ring->tx_pending < TX_RING_MIN ||
1847 ring->rx_pending < RX_RING_MIN)
1848 return -EINVAL;
1849 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
1850 return -EINVAL;
1851
1852 if (netif_running(ndev)) {
1853 netif_tx_disable(ndev);
1854 /* Disable interrupts by clearing the interrupt mask. */
1855 sh_eth_write(ndev, 0x0000, EESIPR);
1856 /* Stop the chip's Tx and Rx processes. */
1857 sh_eth_write(ndev, 0, EDTRR);
1858 sh_eth_write(ndev, 0, EDRRR);
1859 synchronize_irq(ndev->irq);
1860 }
1861
1862 /* Free all the skbuffs in the Rx queue. */
1863 sh_eth_ring_free(ndev);
1864 /* Free DMA buffer */
1865 sh_eth_free_dma_buffer(mdp);
1866
1867 /* Set new parameters */
1868 mdp->num_rx_ring = ring->rx_pending;
1869 mdp->num_tx_ring = ring->tx_pending;
1870
1871 ret = sh_eth_ring_init(ndev);
1872 if (ret < 0) {
1873 dev_err(&ndev->dev, "%s: sh_eth_ring_init failed.\n", __func__);
1874 return ret;
1875 }
1876 ret = sh_eth_dev_init(ndev, false);
1877 if (ret < 0) {
1878 dev_err(&ndev->dev, "%s: sh_eth_dev_init failed.\n", __func__);
1879 return ret;
1880 }
1881
1882 if (netif_running(ndev)) {
1883 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1884 /* Setting the Rx mode will start the Rx process. */
1885 sh_eth_write(ndev, EDRRR_R, EDRRR);
1886 netif_wake_queue(ndev);
1887 }
1888
1889 return 0;
1890 }
1891
1892 static const struct ethtool_ops sh_eth_ethtool_ops = {
1893 .get_settings = sh_eth_get_settings,
1894 .set_settings = sh_eth_set_settings,
1895 .nway_reset = sh_eth_nway_reset,
1896 .get_msglevel = sh_eth_get_msglevel,
1897 .set_msglevel = sh_eth_set_msglevel,
1898 .get_link = ethtool_op_get_link,
1899 .get_strings = sh_eth_get_strings,
1900 .get_ethtool_stats = sh_eth_get_ethtool_stats,
1901 .get_sset_count = sh_eth_get_sset_count,
1902 .get_ringparam = sh_eth_get_ringparam,
1903 .set_ringparam = sh_eth_set_ringparam,
1904 };
1905
1906 /* network device open function */
1907 static int sh_eth_open(struct net_device *ndev)
1908 {
1909 int ret = 0;
1910 struct sh_eth_private *mdp = netdev_priv(ndev);
1911
1912 pm_runtime_get_sync(&mdp->pdev->dev);
1913
1914 ret = request_irq(ndev->irq, sh_eth_interrupt,
1915 mdp->cd->irq_flags, ndev->name, ndev);
1916 if (ret) {
1917 dev_err(&ndev->dev, "Can not assign IRQ number\n");
1918 return ret;
1919 }
1920
1921 /* Descriptor set */
1922 ret = sh_eth_ring_init(ndev);
1923 if (ret)
1924 goto out_free_irq;
1925
1926 /* device init */
1927 ret = sh_eth_dev_init(ndev, true);
1928 if (ret)
1929 goto out_free_irq;
1930
1931 /* PHY control start*/
1932 ret = sh_eth_phy_start(ndev);
1933 if (ret)
1934 goto out_free_irq;
1935
1936 return ret;
1937
1938 out_free_irq:
1939 free_irq(ndev->irq, ndev);
1940 pm_runtime_put_sync(&mdp->pdev->dev);
1941 return ret;
1942 }
1943
1944 /* Timeout function */
1945 static void sh_eth_tx_timeout(struct net_device *ndev)
1946 {
1947 struct sh_eth_private *mdp = netdev_priv(ndev);
1948 struct sh_eth_rxdesc *rxdesc;
1949 int i;
1950
1951 netif_stop_queue(ndev);
1952
1953 if (netif_msg_timer(mdp))
1954 dev_err(&ndev->dev, "%s: transmit timed out, status %8.8x,"
1955 " resetting...\n", ndev->name, (int)sh_eth_read(ndev, EESR));
1956
1957 /* tx_errors count up */
1958 ndev->stats.tx_errors++;
1959
1960 /* Free all the skbuffs in the Rx queue. */
1961 for (i = 0; i < mdp->num_rx_ring; i++) {
1962 rxdesc = &mdp->rx_ring[i];
1963 rxdesc->status = 0;
1964 rxdesc->addr = 0xBADF00D0;
1965 if (mdp->rx_skbuff[i])
1966 dev_kfree_skb(mdp->rx_skbuff[i]);
1967 mdp->rx_skbuff[i] = NULL;
1968 }
1969 for (i = 0; i < mdp->num_tx_ring; i++) {
1970 if (mdp->tx_skbuff[i])
1971 dev_kfree_skb(mdp->tx_skbuff[i]);
1972 mdp->tx_skbuff[i] = NULL;
1973 }
1974
1975 /* device init */
1976 sh_eth_dev_init(ndev, true);
1977 }
1978
1979 /* Packet transmit function */
1980 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1981 {
1982 struct sh_eth_private *mdp = netdev_priv(ndev);
1983 struct sh_eth_txdesc *txdesc;
1984 u32 entry;
1985 unsigned long flags;
1986
1987 spin_lock_irqsave(&mdp->lock, flags);
1988 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
1989 if (!sh_eth_txfree(ndev)) {
1990 if (netif_msg_tx_queued(mdp))
1991 dev_warn(&ndev->dev, "TxFD exhausted.\n");
1992 netif_stop_queue(ndev);
1993 spin_unlock_irqrestore(&mdp->lock, flags);
1994 return NETDEV_TX_BUSY;
1995 }
1996 }
1997 spin_unlock_irqrestore(&mdp->lock, flags);
1998
1999 entry = mdp->cur_tx % mdp->num_tx_ring;
2000 mdp->tx_skbuff[entry] = skb;
2001 txdesc = &mdp->tx_ring[entry];
2002 /* soft swap. */
2003 if (!mdp->cd->hw_swap)
2004 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
2005 skb->len + 2);
2006 txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len,
2007 DMA_TO_DEVICE);
2008 if (skb->len < ETHERSMALL)
2009 txdesc->buffer_length = ETHERSMALL;
2010 else
2011 txdesc->buffer_length = skb->len;
2012
2013 if (entry >= mdp->num_tx_ring - 1)
2014 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
2015 else
2016 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
2017
2018 mdp->cur_tx++;
2019
2020 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
2021 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
2022
2023 return NETDEV_TX_OK;
2024 }
2025
2026 /* device close function */
2027 static int sh_eth_close(struct net_device *ndev)
2028 {
2029 struct sh_eth_private *mdp = netdev_priv(ndev);
2030
2031 netif_stop_queue(ndev);
2032
2033 /* Disable interrupts by clearing the interrupt mask. */
2034 sh_eth_write(ndev, 0x0000, EESIPR);
2035
2036 /* Stop the chip's Tx and Rx processes. */
2037 sh_eth_write(ndev, 0, EDTRR);
2038 sh_eth_write(ndev, 0, EDRRR);
2039
2040 /* PHY Disconnect */
2041 if (mdp->phydev) {
2042 phy_stop(mdp->phydev);
2043 phy_disconnect(mdp->phydev);
2044 }
2045
2046 free_irq(ndev->irq, ndev);
2047
2048 /* Free all the skbuffs in the Rx queue. */
2049 sh_eth_ring_free(ndev);
2050
2051 /* free DMA buffer */
2052 sh_eth_free_dma_buffer(mdp);
2053
2054 pm_runtime_put_sync(&mdp->pdev->dev);
2055
2056 return 0;
2057 }
2058
2059 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2060 {
2061 struct sh_eth_private *mdp = netdev_priv(ndev);
2062
2063 pm_runtime_get_sync(&mdp->pdev->dev);
2064
2065 ndev->stats.tx_dropped += sh_eth_read(ndev, TROCR);
2066 sh_eth_write(ndev, 0, TROCR); /* (write clear) */
2067 ndev->stats.collisions += sh_eth_read(ndev, CDCR);
2068 sh_eth_write(ndev, 0, CDCR); /* (write clear) */
2069 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, LCCR);
2070 sh_eth_write(ndev, 0, LCCR); /* (write clear) */
2071 if (sh_eth_is_gether(mdp)) {
2072 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CERCR);
2073 sh_eth_write(ndev, 0, CERCR); /* (write clear) */
2074 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CEECR);
2075 sh_eth_write(ndev, 0, CEECR); /* (write clear) */
2076 } else {
2077 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CNDCR);
2078 sh_eth_write(ndev, 0, CNDCR); /* (write clear) */
2079 }
2080 pm_runtime_put_sync(&mdp->pdev->dev);
2081
2082 return &ndev->stats;
2083 }
2084
2085 /* ioctl to device function */
2086 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq,
2087 int cmd)
2088 {
2089 struct sh_eth_private *mdp = netdev_priv(ndev);
2090 struct phy_device *phydev = mdp->phydev;
2091
2092 if (!netif_running(ndev))
2093 return -EINVAL;
2094
2095 if (!phydev)
2096 return -ENODEV;
2097
2098 return phy_mii_ioctl(phydev, rq, cmd);
2099 }
2100
2101 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2102 static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2103 int entry)
2104 {
2105 return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2106 }
2107
2108 static u32 sh_eth_tsu_get_post_mask(int entry)
2109 {
2110 return 0x0f << (28 - ((entry % 8) * 4));
2111 }
2112
2113 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2114 {
2115 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2116 }
2117
2118 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2119 int entry)
2120 {
2121 struct sh_eth_private *mdp = netdev_priv(ndev);
2122 u32 tmp;
2123 void *reg_offset;
2124
2125 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2126 tmp = ioread32(reg_offset);
2127 iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2128 }
2129
2130 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2131 int entry)
2132 {
2133 struct sh_eth_private *mdp = netdev_priv(ndev);
2134 u32 post_mask, ref_mask, tmp;
2135 void *reg_offset;
2136
2137 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2138 post_mask = sh_eth_tsu_get_post_mask(entry);
2139 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2140
2141 tmp = ioread32(reg_offset);
2142 iowrite32(tmp & ~post_mask, reg_offset);
2143
2144 /* If other port enables, the function returns "true" */
2145 return tmp & ref_mask;
2146 }
2147
2148 static int sh_eth_tsu_busy(struct net_device *ndev)
2149 {
2150 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2151 struct sh_eth_private *mdp = netdev_priv(ndev);
2152
2153 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2154 udelay(10);
2155 timeout--;
2156 if (timeout <= 0) {
2157 dev_err(&ndev->dev, "%s: timeout\n", __func__);
2158 return -ETIMEDOUT;
2159 }
2160 }
2161
2162 return 0;
2163 }
2164
2165 static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2166 const u8 *addr)
2167 {
2168 u32 val;
2169
2170 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2171 iowrite32(val, reg);
2172 if (sh_eth_tsu_busy(ndev) < 0)
2173 return -EBUSY;
2174
2175 val = addr[4] << 8 | addr[5];
2176 iowrite32(val, reg + 4);
2177 if (sh_eth_tsu_busy(ndev) < 0)
2178 return -EBUSY;
2179
2180 return 0;
2181 }
2182
2183 static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2184 {
2185 u32 val;
2186
2187 val = ioread32(reg);
2188 addr[0] = (val >> 24) & 0xff;
2189 addr[1] = (val >> 16) & 0xff;
2190 addr[2] = (val >> 8) & 0xff;
2191 addr[3] = val & 0xff;
2192 val = ioread32(reg + 4);
2193 addr[4] = (val >> 8) & 0xff;
2194 addr[5] = val & 0xff;
2195 }
2196
2197
2198 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2199 {
2200 struct sh_eth_private *mdp = netdev_priv(ndev);
2201 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2202 int i;
2203 u8 c_addr[ETH_ALEN];
2204
2205 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2206 sh_eth_tsu_read_entry(reg_offset, c_addr);
2207 if (memcmp(addr, c_addr, ETH_ALEN) == 0)
2208 return i;
2209 }
2210
2211 return -ENOENT;
2212 }
2213
2214 static int sh_eth_tsu_find_empty(struct net_device *ndev)
2215 {
2216 u8 blank[ETH_ALEN];
2217 int entry;
2218
2219 memset(blank, 0, sizeof(blank));
2220 entry = sh_eth_tsu_find_entry(ndev, blank);
2221 return (entry < 0) ? -ENOMEM : entry;
2222 }
2223
2224 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2225 int entry)
2226 {
2227 struct sh_eth_private *mdp = netdev_priv(ndev);
2228 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2229 int ret;
2230 u8 blank[ETH_ALEN];
2231
2232 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2233 ~(1 << (31 - entry)), TSU_TEN);
2234
2235 memset(blank, 0, sizeof(blank));
2236 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2237 if (ret < 0)
2238 return ret;
2239 return 0;
2240 }
2241
2242 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2243 {
2244 struct sh_eth_private *mdp = netdev_priv(ndev);
2245 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2246 int i, ret;
2247
2248 if (!mdp->cd->tsu)
2249 return 0;
2250
2251 i = sh_eth_tsu_find_entry(ndev, addr);
2252 if (i < 0) {
2253 /* No entry found, create one */
2254 i = sh_eth_tsu_find_empty(ndev);
2255 if (i < 0)
2256 return -ENOMEM;
2257 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2258 if (ret < 0)
2259 return ret;
2260
2261 /* Enable the entry */
2262 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2263 (1 << (31 - i)), TSU_TEN);
2264 }
2265
2266 /* Entry found or created, enable POST */
2267 sh_eth_tsu_enable_cam_entry_post(ndev, i);
2268
2269 return 0;
2270 }
2271
2272 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2273 {
2274 struct sh_eth_private *mdp = netdev_priv(ndev);
2275 int i, ret;
2276
2277 if (!mdp->cd->tsu)
2278 return 0;
2279
2280 i = sh_eth_tsu_find_entry(ndev, addr);
2281 if (i) {
2282 /* Entry found */
2283 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2284 goto done;
2285
2286 /* Disable the entry if both ports was disabled */
2287 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2288 if (ret < 0)
2289 return ret;
2290 }
2291 done:
2292 return 0;
2293 }
2294
2295 static int sh_eth_tsu_purge_all(struct net_device *ndev)
2296 {
2297 struct sh_eth_private *mdp = netdev_priv(ndev);
2298 int i, ret;
2299
2300 if (unlikely(!mdp->cd->tsu))
2301 return 0;
2302
2303 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2304 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2305 continue;
2306
2307 /* Disable the entry if both ports was disabled */
2308 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2309 if (ret < 0)
2310 return ret;
2311 }
2312
2313 return 0;
2314 }
2315
2316 static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2317 {
2318 struct sh_eth_private *mdp = netdev_priv(ndev);
2319 u8 addr[ETH_ALEN];
2320 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2321 int i;
2322
2323 if (unlikely(!mdp->cd->tsu))
2324 return;
2325
2326 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2327 sh_eth_tsu_read_entry(reg_offset, addr);
2328 if (is_multicast_ether_addr(addr))
2329 sh_eth_tsu_del_entry(ndev, addr);
2330 }
2331 }
2332
2333 /* Multicast reception directions set */
2334 static void sh_eth_set_multicast_list(struct net_device *ndev)
2335 {
2336 struct sh_eth_private *mdp = netdev_priv(ndev);
2337 u32 ecmr_bits;
2338 int mcast_all = 0;
2339 unsigned long flags;
2340
2341 spin_lock_irqsave(&mdp->lock, flags);
2342 /*
2343 * Initial condition is MCT = 1, PRM = 0.
2344 * Depending on ndev->flags, set PRM or clear MCT
2345 */
2346 ecmr_bits = (sh_eth_read(ndev, ECMR) & ~ECMR_PRM) | ECMR_MCT;
2347
2348 if (!(ndev->flags & IFF_MULTICAST)) {
2349 sh_eth_tsu_purge_mcast(ndev);
2350 mcast_all = 1;
2351 }
2352 if (ndev->flags & IFF_ALLMULTI) {
2353 sh_eth_tsu_purge_mcast(ndev);
2354 ecmr_bits &= ~ECMR_MCT;
2355 mcast_all = 1;
2356 }
2357
2358 if (ndev->flags & IFF_PROMISC) {
2359 sh_eth_tsu_purge_all(ndev);
2360 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2361 } else if (mdp->cd->tsu) {
2362 struct netdev_hw_addr *ha;
2363 netdev_for_each_mc_addr(ha, ndev) {
2364 if (mcast_all && is_multicast_ether_addr(ha->addr))
2365 continue;
2366
2367 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2368 if (!mcast_all) {
2369 sh_eth_tsu_purge_mcast(ndev);
2370 ecmr_bits &= ~ECMR_MCT;
2371 mcast_all = 1;
2372 }
2373 }
2374 }
2375 } else {
2376 /* Normal, unicast/broadcast-only mode. */
2377 ecmr_bits = (ecmr_bits & ~ECMR_PRM) | ECMR_MCT;
2378 }
2379
2380 /* update the ethernet mode */
2381 sh_eth_write(ndev, ecmr_bits, ECMR);
2382
2383 spin_unlock_irqrestore(&mdp->lock, flags);
2384 }
2385
2386 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2387 {
2388 if (!mdp->port)
2389 return TSU_VTAG0;
2390 else
2391 return TSU_VTAG1;
2392 }
2393
2394 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2395 __be16 proto, u16 vid)
2396 {
2397 struct sh_eth_private *mdp = netdev_priv(ndev);
2398 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2399
2400 if (unlikely(!mdp->cd->tsu))
2401 return -EPERM;
2402
2403 /* No filtering if vid = 0 */
2404 if (!vid)
2405 return 0;
2406
2407 mdp->vlan_num_ids++;
2408
2409 /*
2410 * The controller has one VLAN tag HW filter. So, if the filter is
2411 * already enabled, the driver disables it and the filte
2412 */
2413 if (mdp->vlan_num_ids > 1) {
2414 /* disable VLAN filter */
2415 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2416 return 0;
2417 }
2418
2419 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2420 vtag_reg_index);
2421
2422 return 0;
2423 }
2424
2425 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2426 __be16 proto, u16 vid)
2427 {
2428 struct sh_eth_private *mdp = netdev_priv(ndev);
2429 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2430
2431 if (unlikely(!mdp->cd->tsu))
2432 return -EPERM;
2433
2434 /* No filtering if vid = 0 */
2435 if (!vid)
2436 return 0;
2437
2438 mdp->vlan_num_ids--;
2439 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2440
2441 return 0;
2442 }
2443
2444 /* SuperH's TSU register init function */
2445 static void sh_eth_tsu_init(struct sh_eth_private *mdp)
2446 {
2447 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
2448 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
2449 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
2450 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2451 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2452 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2453 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2454 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2455 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2456 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
2457 if (sh_eth_is_gether(mdp)) {
2458 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */
2459 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */
2460 } else {
2461 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
2462 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
2463 }
2464 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
2465 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
2466 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2467 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
2468 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
2469 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
2470 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
2471 }
2472
2473 /* MDIO bus release function */
2474 static int sh_mdio_release(struct net_device *ndev)
2475 {
2476 struct mii_bus *bus = dev_get_drvdata(&ndev->dev);
2477
2478 /* unregister mdio bus */
2479 mdiobus_unregister(bus);
2480
2481 /* remove mdio bus info from net_device */
2482 dev_set_drvdata(&ndev->dev, NULL);
2483
2484 /* free bitbang info */
2485 free_mdio_bitbang(bus);
2486
2487 return 0;
2488 }
2489
2490 /* MDIO bus init function */
2491 static int sh_mdio_init(struct net_device *ndev, int id,
2492 struct sh_eth_plat_data *pd)
2493 {
2494 int ret, i;
2495 struct bb_info *bitbang;
2496 struct sh_eth_private *mdp = netdev_priv(ndev);
2497
2498 /* create bit control struct for PHY */
2499 bitbang = devm_kzalloc(&ndev->dev, sizeof(struct bb_info),
2500 GFP_KERNEL);
2501 if (!bitbang) {
2502 ret = -ENOMEM;
2503 goto out;
2504 }
2505
2506 /* bitbang init */
2507 bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
2508 bitbang->set_gate = pd->set_mdio_gate;
2509 bitbang->mdi_msk = PIR_MDI;
2510 bitbang->mdo_msk = PIR_MDO;
2511 bitbang->mmd_msk = PIR_MMD;
2512 bitbang->mdc_msk = PIR_MDC;
2513 bitbang->ctrl.ops = &bb_ops;
2514
2515 /* MII controller setting */
2516 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
2517 if (!mdp->mii_bus) {
2518 ret = -ENOMEM;
2519 goto out;
2520 }
2521
2522 /* Hook up MII support for ethtool */
2523 mdp->mii_bus->name = "sh_mii";
2524 mdp->mii_bus->parent = &ndev->dev;
2525 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2526 mdp->pdev->name, id);
2527
2528 /* PHY IRQ */
2529 mdp->mii_bus->irq = devm_kzalloc(&ndev->dev,
2530 sizeof(int) * PHY_MAX_ADDR,
2531 GFP_KERNEL);
2532 if (!mdp->mii_bus->irq) {
2533 ret = -ENOMEM;
2534 goto out_free_bus;
2535 }
2536
2537 for (i = 0; i < PHY_MAX_ADDR; i++)
2538 mdp->mii_bus->irq[i] = PHY_POLL;
2539
2540 /* register mdio bus */
2541 ret = mdiobus_register(mdp->mii_bus);
2542 if (ret)
2543 goto out_free_bus;
2544
2545 dev_set_drvdata(&ndev->dev, mdp->mii_bus);
2546
2547 return 0;
2548
2549 out_free_bus:
2550 free_mdio_bitbang(mdp->mii_bus);
2551
2552 out:
2553 return ret;
2554 }
2555
2556 static const u16 *sh_eth_get_register_offset(int register_type)
2557 {
2558 const u16 *reg_offset = NULL;
2559
2560 switch (register_type) {
2561 case SH_ETH_REG_GIGABIT:
2562 reg_offset = sh_eth_offset_gigabit;
2563 break;
2564 case SH_ETH_REG_FAST_RCAR:
2565 reg_offset = sh_eth_offset_fast_rcar;
2566 break;
2567 case SH_ETH_REG_FAST_SH4:
2568 reg_offset = sh_eth_offset_fast_sh4;
2569 break;
2570 case SH_ETH_REG_FAST_SH3_SH2:
2571 reg_offset = sh_eth_offset_fast_sh3_sh2;
2572 break;
2573 default:
2574 pr_err("Unknown register type (%d)\n", register_type);
2575 break;
2576 }
2577
2578 return reg_offset;
2579 }
2580
2581 static struct net_device_ops sh_eth_netdev_ops = {
2582 .ndo_open = sh_eth_open,
2583 .ndo_stop = sh_eth_close,
2584 .ndo_start_xmit = sh_eth_start_xmit,
2585 .ndo_get_stats = sh_eth_get_stats,
2586 .ndo_tx_timeout = sh_eth_tx_timeout,
2587 .ndo_do_ioctl = sh_eth_do_ioctl,
2588 .ndo_validate_addr = eth_validate_addr,
2589 .ndo_set_mac_address = eth_mac_addr,
2590 .ndo_change_mtu = eth_change_mtu,
2591 };
2592
2593 static int sh_eth_drv_probe(struct platform_device *pdev)
2594 {
2595 int ret, devno = 0;
2596 struct resource *res;
2597 struct net_device *ndev = NULL;
2598 struct sh_eth_private *mdp = NULL;
2599 struct sh_eth_plat_data *pd = pdev->dev.platform_data;
2600
2601 /* get base addr */
2602 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2603 if (unlikely(res == NULL)) {
2604 dev_err(&pdev->dev, "invalid resource\n");
2605 ret = -EINVAL;
2606 goto out;
2607 }
2608
2609 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
2610 if (!ndev) {
2611 ret = -ENOMEM;
2612 goto out;
2613 }
2614
2615 /* The sh Ether-specific entries in the device structure. */
2616 ndev->base_addr = res->start;
2617 devno = pdev->id;
2618 if (devno < 0)
2619 devno = 0;
2620
2621 ndev->dma = -1;
2622 ret = platform_get_irq(pdev, 0);
2623 if (ret < 0) {
2624 ret = -ENODEV;
2625 goto out_release;
2626 }
2627 ndev->irq = ret;
2628
2629 SET_NETDEV_DEV(ndev, &pdev->dev);
2630
2631 /* Fill in the fields of the device structure with ethernet values. */
2632 ether_setup(ndev);
2633
2634 mdp = netdev_priv(ndev);
2635 mdp->num_tx_ring = TX_RING_SIZE;
2636 mdp->num_rx_ring = RX_RING_SIZE;
2637 mdp->addr = devm_ioremap_resource(&pdev->dev, res);
2638 if (IS_ERR(mdp->addr)) {
2639 ret = PTR_ERR(mdp->addr);
2640 goto out_release;
2641 }
2642
2643 spin_lock_init(&mdp->lock);
2644 mdp->pdev = pdev;
2645 pm_runtime_enable(&pdev->dev);
2646 pm_runtime_resume(&pdev->dev);
2647
2648 /* get PHY ID */
2649 mdp->phy_id = pd->phy;
2650 mdp->phy_interface = pd->phy_interface;
2651 /* EDMAC endian */
2652 mdp->edmac_endian = pd->edmac_endian;
2653 mdp->no_ether_link = pd->no_ether_link;
2654 mdp->ether_link_active_low = pd->ether_link_active_low;
2655 mdp->reg_offset = sh_eth_get_register_offset(pd->register_type);
2656
2657 /* set cpu data */
2658 #if defined(SH_ETH_HAS_BOTH_MODULES)
2659 mdp->cd = sh_eth_get_cpu_data(mdp);
2660 #else
2661 mdp->cd = &sh_eth_my_cpu_data;
2662 #endif
2663 sh_eth_set_default_cpu_data(mdp->cd);
2664
2665 /* set function */
2666 if (mdp->cd->tsu) {
2667 sh_eth_netdev_ops.ndo_set_rx_mode = sh_eth_set_multicast_list;
2668 sh_eth_netdev_ops.ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid;
2669 sh_eth_netdev_ops.ndo_vlan_rx_kill_vid =
2670 sh_eth_vlan_rx_kill_vid;
2671 }
2672
2673 ndev->netdev_ops = &sh_eth_netdev_ops;
2674 SET_ETHTOOL_OPS(ndev, &sh_eth_ethtool_ops);
2675 ndev->watchdog_timeo = TX_TIMEOUT;
2676
2677 /* debug message level */
2678 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
2679
2680 /* read and set MAC address */
2681 read_mac_address(ndev, pd->mac_addr);
2682 if (!is_valid_ether_addr(ndev->dev_addr)) {
2683 dev_warn(&pdev->dev,
2684 "no valid MAC address supplied, using a random one.\n");
2685 eth_hw_addr_random(ndev);
2686 }
2687
2688 /* ioremap the TSU registers */
2689 if (mdp->cd->tsu) {
2690 struct resource *rtsu;
2691 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2692 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
2693 if (IS_ERR(mdp->tsu_addr)) {
2694 ret = PTR_ERR(mdp->tsu_addr);
2695 goto out_release;
2696 }
2697 mdp->port = devno % 2;
2698 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
2699 }
2700
2701 /* initialize first or needed device */
2702 if (!devno || pd->needs_init) {
2703 if (mdp->cd->chip_reset)
2704 mdp->cd->chip_reset(ndev);
2705
2706 if (mdp->cd->tsu) {
2707 /* TSU init (Init only)*/
2708 sh_eth_tsu_init(mdp);
2709 }
2710 }
2711
2712 /* network device register */
2713 ret = register_netdev(ndev);
2714 if (ret)
2715 goto out_release;
2716
2717 /* mdio bus init */
2718 ret = sh_mdio_init(ndev, pdev->id, pd);
2719 if (ret)
2720 goto out_unregister;
2721
2722 /* print device information */
2723 pr_info("Base address at 0x%x, %pM, IRQ %d.\n",
2724 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
2725
2726 platform_set_drvdata(pdev, ndev);
2727
2728 return ret;
2729
2730 out_unregister:
2731 unregister_netdev(ndev);
2732
2733 out_release:
2734 /* net_dev free */
2735 if (ndev)
2736 free_netdev(ndev);
2737
2738 out:
2739 return ret;
2740 }
2741
2742 static int sh_eth_drv_remove(struct platform_device *pdev)
2743 {
2744 struct net_device *ndev = platform_get_drvdata(pdev);
2745
2746 sh_mdio_release(ndev);
2747 unregister_netdev(ndev);
2748 pm_runtime_disable(&pdev->dev);
2749 free_netdev(ndev);
2750
2751 return 0;
2752 }
2753
2754 static int sh_eth_runtime_nop(struct device *dev)
2755 {
2756 /*
2757 * Runtime PM callback shared between ->runtime_suspend()
2758 * and ->runtime_resume(). Simply returns success.
2759 *
2760 * This driver re-initializes all registers after
2761 * pm_runtime_get_sync() anyway so there is no need
2762 * to save and restore registers here.
2763 */
2764 return 0;
2765 }
2766
2767 static struct dev_pm_ops sh_eth_dev_pm_ops = {
2768 .runtime_suspend = sh_eth_runtime_nop,
2769 .runtime_resume = sh_eth_runtime_nop,
2770 };
2771
2772 static struct platform_driver sh_eth_driver = {
2773 .probe = sh_eth_drv_probe,
2774 .remove = sh_eth_drv_remove,
2775 .driver = {
2776 .name = CARDNAME,
2777 .pm = &sh_eth_dev_pm_ops,
2778 },
2779 };
2780
2781 module_platform_driver(sh_eth_driver);
2782
2783 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
2784 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
2785 MODULE_LICENSE("GPL v2");
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