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Blackfin arch: Modify some funtion names to more genernal ones
[linux-2.6.git] / drivers / serial / sh-sci.c
blob3df2aaec829fe874a633fecc3def9d5369e64446
1 /*
2 * drivers/serial/sh-sci.c
3 *
4 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
5 *
6 * Copyright (C) 2002 - 2006 Paul Mundt
7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
8 *
9 * based off of the old drivers/char/sh-sci.c by:
10 *
11 * Copyright (C) 1999, 2000 Niibe Yutaka
12 * Copyright (C) 2000 Sugioka Toshinobu
13 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
14 * Modified to support SecureEdge. David McCullough (2002)
15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
16 * Removed SH7300 support (Jul 2007).
17 *
18 * This file is subject to the terms and conditions of the GNU General Public
19 * License. See the file "COPYING" in the main directory of this archive
20 * for more details.
21 */
22 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
23 #define SUPPORT_SYSRQ
24 #endif
25
26 #undef DEBUG
27
28 #include <linux/module.h>
29 #include <linux/errno.h>
30 #include <linux/timer.h>
31 #include <linux/interrupt.h>
32 #include <linux/tty.h>
33 #include <linux/tty_flip.h>
34 #include <linux/serial.h>
35 #include <linux/major.h>
36 #include <linux/string.h>
37 #include <linux/sysrq.h>
38 #include <linux/ioport.h>
39 #include <linux/mm.h>
40 #include <linux/init.h>
41 #include <linux/delay.h>
42 #include <linux/console.h>
43 #include <linux/platform_device.h>
44 #include <linux/serial_sci.h>
45 #include <linux/notifier.h>
46 #include <linux/cpufreq.h>
47 #include <linux/clk.h>
48 #include <linux/ctype.h>
49
50 #ifdef CONFIG_SUPERH
51 #include <asm/clock.h>
52 #include <asm/sh_bios.h>
53 #include <asm/kgdb.h>
54 #endif
55
56 #include "sh-sci.h"
57
58 struct sci_port {
59 struct uart_port port;
60
61 /* Port type */
62 unsigned int type;
63
64 /* Port IRQs: ERI, RXI, TXI, BRI (optional) */
65 unsigned int irqs[SCIx_NR_IRQS];
66
67 /* Port pin configuration */
68 void (*init_pins)(struct uart_port *port,
69 unsigned int cflag);
70
71 /* Port enable callback */
72 void (*enable)(struct uart_port *port);
73
74 /* Port disable callback */
75 void (*disable)(struct uart_port *port);
76
77 /* Break timer */
78 struct timer_list break_timer;
79 int break_flag;
80
81 #ifdef CONFIG_SUPERH
82 /* Port clock */
83 struct clk *clk;
84 #endif
85 };
86
87 #ifdef CONFIG_SH_KGDB
88 static struct sci_port *kgdb_sci_port;
89 #endif
90
91 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
92 static struct sci_port *serial_console_port;
93 #endif
94
95 /* Function prototypes */
96 static void sci_stop_tx(struct uart_port *port);
97
98 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
99
100 static struct sci_port sci_ports[SCI_NPORTS];
101 static struct uart_driver sci_uart_driver;
102
103 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && \
104 defined(CONFIG_SH_STANDARD_BIOS) || defined(CONFIG_SH_KGDB)
105 static inline void handle_error(struct uart_port *port)
106 {
107 /* Clear error flags */
108 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
109 }
110
111 static int get_char(struct uart_port *port)
112 {
113 unsigned long flags;
114 unsigned short status;
115 int c;
116
117 spin_lock_irqsave(&port->lock, flags);
118 do {
119 status = sci_in(port, SCxSR);
120 if (status & SCxSR_ERRORS(port)) {
121 handle_error(port);
122 continue;
123 }
124 } while (!(status & SCxSR_RDxF(port)));
125 c = sci_in(port, SCxRDR);
126 sci_in(port, SCxSR); /* Dummy read */
127 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
128 spin_unlock_irqrestore(&port->lock, flags);
129
130 return c;
131 }
132 #endif /* CONFIG_SH_STANDARD_BIOS || CONFIG_SH_KGDB */
133
134 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || defined(CONFIG_SH_KGDB)
135 static void put_char(struct uart_port *port, char c)
136 {
137 unsigned long flags;
138 unsigned short status;
139
140 spin_lock_irqsave(&port->lock, flags);
141
142 do {
143 status = sci_in(port, SCxSR);
144 } while (!(status & SCxSR_TDxE(port)));
145
146 sci_out(port, SCxTDR, c);
147 sci_in(port, SCxSR); /* Dummy read */
148 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
149
150 spin_unlock_irqrestore(&port->lock, flags);
151 }
152 #endif
153
154 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
155 static void put_string(struct sci_port *sci_port, const char *buffer, int count)
156 {
157 struct uart_port *port = &sci_port->port;
158 const unsigned char *p = buffer;
159 int i;
160
161 #if defined(CONFIG_SH_STANDARD_BIOS) || defined(CONFIG_SH_KGDB)
162 int checksum;
163 int usegdb=0;
164
165 #ifdef CONFIG_SH_STANDARD_BIOS
166 /* This call only does a trap the first time it is
167 * called, and so is safe to do here unconditionally
168 */
169 usegdb |= sh_bios_in_gdb_mode();
170 #endif
171 #ifdef CONFIG_SH_KGDB
172 usegdb |= (kgdb_in_gdb_mode && (sci_port == kgdb_sci_port));
173 #endif
174
175 if (usegdb) {
176 /* $<packet info>#<checksum>. */
177 do {
178 unsigned char c;
179 put_char(port, '$');
180 put_char(port, 'O'); /* 'O'utput to console */
181 checksum = 'O';
182
183 for (i=0; i<count; i++) { /* Don't use run length encoding */
184 int h, l;
185
186 c = *p++;
187 h = hex_asc_hi(c);
188 l = hex_asc_lo(c);
189 put_char(port, h);
190 put_char(port, l);
191 checksum += h + l;
192 }
193 put_char(port, '#');
194 put_char(port, hex_asc_hi(checksum));
195 put_char(port, hex_asc_lo(checksum));
196 } while (get_char(port) != '+');
197 } else
198 #endif /* CONFIG_SH_STANDARD_BIOS || CONFIG_SH_KGDB */
199 for (i=0; i<count; i++) {
200 if (*p == 10)
201 put_char(port, '\r');
202 put_char(port, *p++);
203 }
204 }
205 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
206
207 #ifdef CONFIG_SH_KGDB
208 static int kgdb_sci_getchar(void)
209 {
210 int c;
211
212 /* Keep trying to read a character, this could be neater */
213 while ((c = get_char(&kgdb_sci_port->port)) < 0)
214 cpu_relax();
215
216 return c;
217 }
218
219 static inline void kgdb_sci_putchar(int c)
220 {
221 put_char(&kgdb_sci_port->port, c);
222 }
223 #endif /* CONFIG_SH_KGDB */
224
225 #if defined(__H8300S__)
226 enum { sci_disable, sci_enable };
227
228 static void h8300_sci_config(struct uart_port* port, unsigned int ctrl)
229 {
230 volatile unsigned char *mstpcrl=(volatile unsigned char *)MSTPCRL;
231 int ch = (port->mapbase - SMR0) >> 3;
232 unsigned char mask = 1 << (ch+1);
233
234 if (ctrl == sci_disable) {
235 *mstpcrl |= mask;
236 } else {
237 *mstpcrl &= ~mask;
238 }
239 }
240
241 static inline void h8300_sci_enable(struct uart_port *port)
242 {
243 h8300_sci_config(port, sci_enable);
244 }
245
246 static inline void h8300_sci_disable(struct uart_port *port)
247 {
248 h8300_sci_config(port, sci_disable);
249 }
250 #endif
251
252 #if defined(SCI_ONLY) || defined(SCI_AND_SCIF) && \
253 defined(__H8300H__) || defined(__H8300S__)
254 static void sci_init_pins_sci(struct uart_port* port, unsigned int cflag)
255 {
256 int ch = (port->mapbase - SMR0) >> 3;
257
258 /* set DDR regs */
259 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
260 h8300_sci_pins[ch].rx,
261 H8300_GPIO_INPUT);
262 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
263 h8300_sci_pins[ch].tx,
264 H8300_GPIO_OUTPUT);
265
266 /* tx mark output*/
267 H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx;
268 }
269 #else
270 #define sci_init_pins_sci NULL
271 #endif
272
273 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
274 static void sci_init_pins_irda(struct uart_port *port, unsigned int cflag)
275 {
276 unsigned int fcr_val = 0;
277
278 if (cflag & CRTSCTS)
279 fcr_val |= SCFCR_MCE;
280
281 sci_out(port, SCFCR, fcr_val);
282 }
283 #else
284 #define sci_init_pins_irda NULL
285 #endif
286
287 #ifdef SCI_ONLY
288 #define sci_init_pins_scif NULL
289 #endif
290
291 #if defined(SCIF_ONLY) || defined(SCI_AND_SCIF)
292 #if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
293 static void sci_init_pins_scif(struct uart_port* port, unsigned int cflag)
294 {
295 unsigned int fcr_val = 0;
296
297 set_sh771x_scif_pfc(port);
298 if (cflag & CRTSCTS) {
299 fcr_val |= SCFCR_MCE;
300 }
301 sci_out(port, SCFCR, fcr_val);
302 }
303 #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7721)
304 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
305 {
306 unsigned int fcr_val = 0;
307 unsigned short data;
308
309 if (cflag & CRTSCTS) {
310 /* enable RTS/CTS */
311 if (port->mapbase == 0xa4430000) { /* SCIF0 */
312 /* Clear PTCR bit 9-2; enable all scif pins but sck */
313 data = ctrl_inw(PORT_PTCR);
314 ctrl_outw((data & 0xfc03), PORT_PTCR);
315 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
316 /* Clear PVCR bit 9-2 */
317 data = ctrl_inw(PORT_PVCR);
318 ctrl_outw((data & 0xfc03), PORT_PVCR);
319 }
320 fcr_val |= SCFCR_MCE;
321 } else {
322 if (port->mapbase == 0xa4430000) { /* SCIF0 */
323 /* Clear PTCR bit 5-2; enable only tx and rx */
324 data = ctrl_inw(PORT_PTCR);
325 ctrl_outw((data & 0xffc3), PORT_PTCR);
326 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
327 /* Clear PVCR bit 5-2 */
328 data = ctrl_inw(PORT_PVCR);
329 ctrl_outw((data & 0xffc3), PORT_PVCR);
330 }
331 }
332 sci_out(port, SCFCR, fcr_val);
333 }
334 #elif defined(CONFIG_CPU_SH3)
335 /* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */
336 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
337 {
338 unsigned int fcr_val = 0;
339 unsigned short data;
340
341 /* We need to set SCPCR to enable RTS/CTS */
342 data = ctrl_inw(SCPCR);
343 /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/
344 ctrl_outw(data & 0x0fcf, SCPCR);
345
346 if (cflag & CRTSCTS)
347 fcr_val |= SCFCR_MCE;
348 else {
349 /* We need to set SCPCR to enable RTS/CTS */
350 data = ctrl_inw(SCPCR);
351 /* Clear out SCP7MD1,0, SCP4MD1,0,
352 Set SCP6MD1,0 = {01} (output) */
353 ctrl_outw((data & 0x0fcf) | 0x1000, SCPCR);
354
355 data = ctrl_inb(SCPDR);
356 /* Set /RTS2 (bit6) = 0 */
357 ctrl_outb(data & 0xbf, SCPDR);
358 }
359
360 sci_out(port, SCFCR, fcr_val);
361 }
362 #elif defined(CONFIG_CPU_SUBTYPE_SH7722)
363 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
364 {
365 unsigned int fcr_val = 0;
366 unsigned short data;
367
368 if (port->mapbase == 0xffe00000) {
369 data = ctrl_inw(PSCR);
370 data &= ~0x03cf;
371 if (cflag & CRTSCTS)
372 fcr_val |= SCFCR_MCE;
373 else
374 data |= 0x0340;
375
376 ctrl_outw(data, PSCR);
377 }
378 /* SCIF1 and SCIF2 should be setup by board code */
379
380 sci_out(port, SCFCR, fcr_val);
381 }
382 #elif defined(CONFIG_CPU_SUBTYPE_SH7723)
383 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
384 {
385 /* Nothing to do here.. */
386 sci_out(port, SCFCR, 0);
387 }
388 #else
389 /* For SH7750 */
390 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
391 {
392 unsigned int fcr_val = 0;
393
394 if (cflag & CRTSCTS) {
395 fcr_val |= SCFCR_MCE;
396 } else {
397 #if defined(CONFIG_CPU_SUBTYPE_SH7343) || defined(CONFIG_CPU_SUBTYPE_SH7366)
398 /* Nothing */
399 #elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
400 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
401 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
402 defined(CONFIG_CPU_SUBTYPE_SHX3)
403 ctrl_outw(0x0080, SCSPTR0); /* Set RTS = 1 */
404 #else
405 ctrl_outw(0x0080, SCSPTR2); /* Set RTS = 1 */
406 #endif
407 }
408 sci_out(port, SCFCR, fcr_val);
409 }
410 #endif
411
412 #if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
413 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
414 defined(CONFIG_CPU_SUBTYPE_SH7785)
415 static inline int scif_txroom(struct uart_port *port)
416 {
417 return SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0xff);
418 }
419
420 static inline int scif_rxroom(struct uart_port *port)
421 {
422 return sci_in(port, SCRFDR) & 0xff;
423 }
424 #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
425 static inline int scif_txroom(struct uart_port *port)
426 {
427 if((port->mapbase == 0xffe00000) || (port->mapbase == 0xffe08000)) /* SCIF0/1*/
428 return SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0xff);
429 else /* SCIF2 */
430 return SCIF2_TXROOM_MAX - (sci_in(port, SCFDR) >> 8);
431 }
432
433 static inline int scif_rxroom(struct uart_port *port)
434 {
435 if((port->mapbase == 0xffe00000) || (port->mapbase == 0xffe08000)) /* SCIF0/1*/
436 return sci_in(port, SCRFDR) & 0xff;
437 else /* SCIF2 */
438 return sci_in(port, SCFDR) & SCIF2_RFDC_MASK;
439 }
440 #else
441 static inline int scif_txroom(struct uart_port *port)
442 {
443 return SCIF_TXROOM_MAX - (sci_in(port, SCFDR) >> 8);
444 }
445
446 static inline int scif_rxroom(struct uart_port *port)
447 {
448 return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
449 }
450 #endif
451 #endif /* SCIF_ONLY || SCI_AND_SCIF */
452
453 static inline int sci_txroom(struct uart_port *port)
454 {
455 return ((sci_in(port, SCxSR) & SCI_TDRE) != 0);
456 }
457
458 static inline int sci_rxroom(struct uart_port *port)
459 {
460 return ((sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0);
461 }
462
463 /* ********************************************************************** *
464 * the interrupt related routines *
465 * ********************************************************************** */
466
467 static void sci_transmit_chars(struct uart_port *port)
468 {
469 struct circ_buf *xmit = &port->info->xmit;
470 unsigned int stopped = uart_tx_stopped(port);
471 unsigned short status;
472 unsigned short ctrl;
473 int count;
474
475 status = sci_in(port, SCxSR);
476 if (!(status & SCxSR_TDxE(port))) {
477 ctrl = sci_in(port, SCSCR);
478 if (uart_circ_empty(xmit)) {
479 ctrl &= ~SCI_CTRL_FLAGS_TIE;
480 } else {
481 ctrl |= SCI_CTRL_FLAGS_TIE;
482 }
483 sci_out(port, SCSCR, ctrl);
484 return;
485 }
486
487 #ifndef SCI_ONLY
488 if (port->type == PORT_SCIF)
489 count = scif_txroom(port);
490 else
491 #endif
492 count = sci_txroom(port);
493
494 do {
495 unsigned char c;
496
497 if (port->x_char) {
498 c = port->x_char;
499 port->x_char = 0;
500 } else if (!uart_circ_empty(xmit) && !stopped) {
501 c = xmit->buf[xmit->tail];
502 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
503 } else {
504 break;
505 }
506
507 sci_out(port, SCxTDR, c);
508
509 port->icount.tx++;
510 } while (--count > 0);
511
512 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
513
514 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
515 uart_write_wakeup(port);
516 if (uart_circ_empty(xmit)) {
517 sci_stop_tx(port);
518 } else {
519 ctrl = sci_in(port, SCSCR);
520
521 #if !defined(SCI_ONLY)
522 if (port->type == PORT_SCIF) {
523 sci_in(port, SCxSR); /* Dummy read */
524 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
525 }
526 #endif
527
528 ctrl |= SCI_CTRL_FLAGS_TIE;
529 sci_out(port, SCSCR, ctrl);
530 }
531 }
532
533 /* On SH3, SCIF may read end-of-break as a space->mark char */
534 #define STEPFN(c) ({int __c=(c); (((__c-1)|(__c)) == -1); })
535
536 static inline void sci_receive_chars(struct uart_port *port)
537 {
538 struct sci_port *sci_port = (struct sci_port *)port;
539 struct tty_struct *tty = port->info->port.tty;
540 int i, count, copied = 0;
541 unsigned short status;
542 unsigned char flag;
543
544 status = sci_in(port, SCxSR);
545 if (!(status & SCxSR_RDxF(port)))
546 return;
547
548 while (1) {
549 #if !defined(SCI_ONLY)
550 if (port->type == PORT_SCIF)
551 count = scif_rxroom(port);
552 else
553 #endif
554 count = sci_rxroom(port);
555
556 /* Don't copy more bytes than there is room for in the buffer */
557 count = tty_buffer_request_room(tty, count);
558
559 /* If for any reason we can't copy more data, we're done! */
560 if (count == 0)
561 break;
562
563 if (port->type == PORT_SCI) {
564 char c = sci_in(port, SCxRDR);
565 if (uart_handle_sysrq_char(port, c) || sci_port->break_flag)
566 count = 0;
567 else {
568 tty_insert_flip_char(tty, c, TTY_NORMAL);
569 }
570 } else {
571 for (i=0; i<count; i++) {
572 char c = sci_in(port, SCxRDR);
573 status = sci_in(port, SCxSR);
574 #if defined(CONFIG_CPU_SH3)
575 /* Skip "chars" during break */
576 if (sci_port->break_flag) {
577 if ((c == 0) &&
578 (status & SCxSR_FER(port))) {
579 count--; i--;
580 continue;
581 }
582
583 /* Nonzero => end-of-break */
584 pr_debug("scif: debounce<%02x>\n", c);
585 sci_port->break_flag = 0;
586
587 if (STEPFN(c)) {
588 count--; i--;
589 continue;
590 }
591 }
592 #endif /* CONFIG_CPU_SH3 */
593 if (uart_handle_sysrq_char(port, c)) {
594 count--; i--;
595 continue;
596 }
597
598 /* Store data and status */
599 if (status&SCxSR_FER(port)) {
600 flag = TTY_FRAME;
601 pr_debug("sci: frame error\n");
602 } else if (status&SCxSR_PER(port)) {
603 flag = TTY_PARITY;
604 pr_debug("sci: parity error\n");
605 } else
606 flag = TTY_NORMAL;
607 tty_insert_flip_char(tty, c, flag);
608 }
609 }
610
611 sci_in(port, SCxSR); /* dummy read */
612 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
613
614 copied += count;
615 port->icount.rx += count;
616 }
617
618 if (copied) {
619 /* Tell the rest of the system the news. New characters! */
620 tty_flip_buffer_push(tty);
621 } else {
622 sci_in(port, SCxSR); /* dummy read */
623 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
624 }
625 }
626
627 #define SCI_BREAK_JIFFIES (HZ/20)
628 /* The sci generates interrupts during the break,
629 * 1 per millisecond or so during the break period, for 9600 baud.
630 * So dont bother disabling interrupts.
631 * But dont want more than 1 break event.
632 * Use a kernel timer to periodically poll the rx line until
633 * the break is finished.
634 */
635 static void sci_schedule_break_timer(struct sci_port *port)
636 {
637 port->break_timer.expires = jiffies + SCI_BREAK_JIFFIES;
638 add_timer(&port->break_timer);
639 }
640 /* Ensure that two consecutive samples find the break over. */
641 static void sci_break_timer(unsigned long data)
642 {
643 struct sci_port *port = (struct sci_port *)data;
644
645 if (sci_rxd_in(&port->port) == 0) {
646 port->break_flag = 1;
647 sci_schedule_break_timer(port);
648 } else if (port->break_flag == 1) {
649 /* break is over. */
650 port->break_flag = 2;
651 sci_schedule_break_timer(port);
652 } else
653 port->break_flag = 0;
654 }
655
656 static inline int sci_handle_errors(struct uart_port *port)
657 {
658 int copied = 0;
659 unsigned short status = sci_in(port, SCxSR);
660 struct tty_struct *tty = port->info->port.tty;
661
662 if (status & SCxSR_ORER(port)) {
663 /* overrun error */
664 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN))
665 copied++;
666 pr_debug("sci: overrun error\n");
667 }
668
669 if (status & SCxSR_FER(port)) {
670 if (sci_rxd_in(port) == 0) {
671 /* Notify of BREAK */
672 struct sci_port *sci_port = (struct sci_port *)port;
673
674 if (!sci_port->break_flag) {
675 sci_port->break_flag = 1;
676 sci_schedule_break_timer(sci_port);
677
678 /* Do sysrq handling. */
679 if (uart_handle_break(port))
680 return 0;
681 pr_debug("sci: BREAK detected\n");
682 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
683 copied++;
684 }
685 } else {
686 /* frame error */
687 if (tty_insert_flip_char(tty, 0, TTY_FRAME))
688 copied++;
689 pr_debug("sci: frame error\n");
690 }
691 }
692
693 if (status & SCxSR_PER(port)) {
694 /* parity error */
695 if (tty_insert_flip_char(tty, 0, TTY_PARITY))
696 copied++;
697 pr_debug("sci: parity error\n");
698 }
699
700 if (copied)
701 tty_flip_buffer_push(tty);
702
703 return copied;
704 }
705
706 static inline int sci_handle_breaks(struct uart_port *port)
707 {
708 int copied = 0;
709 unsigned short status = sci_in(port, SCxSR);
710 struct tty_struct *tty = port->info->port.tty;
711 struct sci_port *s = &sci_ports[port->line];
712
713 if (uart_handle_break(port))
714 return 0;
715
716 if (!s->break_flag && status & SCxSR_BRK(port)) {
717 #if defined(CONFIG_CPU_SH3)
718 /* Debounce break */
719 s->break_flag = 1;
720 #endif
721 /* Notify of BREAK */
722 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
723 copied++;
724 pr_debug("sci: BREAK detected\n");
725 }
726
727 #if defined(SCIF_ORER)
728 /* XXX: Handle SCIF overrun error */
729 if (port->type == PORT_SCIF && (sci_in(port, SCLSR) & SCIF_ORER) != 0) {
730 sci_out(port, SCLSR, 0);
731 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN)) {
732 copied++;
733 pr_debug("sci: overrun error\n");
734 }
735 }
736 #endif
737
738 if (copied)
739 tty_flip_buffer_push(tty);
740
741 return copied;
742 }
743
744 static irqreturn_t sci_rx_interrupt(int irq, void *port)
745 {
746 /* I think sci_receive_chars has to be called irrespective
747 * of whether the I_IXOFF is set, otherwise, how is the interrupt
748 * to be disabled?
749 */
750 sci_receive_chars(port);
751
752 return IRQ_HANDLED;
753 }
754
755 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
756 {
757 struct uart_port *port = ptr;
758
759 spin_lock_irq(&port->lock);
760 sci_transmit_chars(port);
761 spin_unlock_irq(&port->lock);
762
763 return IRQ_HANDLED;
764 }
765
766 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
767 {
768 struct uart_port *port = ptr;
769
770 /* Handle errors */
771 if (port->type == PORT_SCI) {
772 if (sci_handle_errors(port)) {
773 /* discard character in rx buffer */
774 sci_in(port, SCxSR);
775 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
776 }
777 } else {
778 #if defined(SCIF_ORER)
779 if((sci_in(port, SCLSR) & SCIF_ORER) != 0) {
780 struct tty_struct *tty = port->info->port.tty;
781
782 sci_out(port, SCLSR, 0);
783 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
784 tty_flip_buffer_push(tty);
785 pr_debug("scif: overrun error\n");
786 }
787 #endif
788 sci_rx_interrupt(irq, ptr);
789 }
790
791 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
792
793 /* Kick the transmission */
794 sci_tx_interrupt(irq, ptr);
795
796 return IRQ_HANDLED;
797 }
798
799 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
800 {
801 struct uart_port *port = ptr;
802
803 /* Handle BREAKs */
804 sci_handle_breaks(port);
805 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
806
807 return IRQ_HANDLED;
808 }
809
810 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
811 {
812 unsigned short ssr_status, scr_status;
813 struct uart_port *port = ptr;
814
815 ssr_status = sci_in(port,SCxSR);
816 scr_status = sci_in(port,SCSCR);
817
818 /* Tx Interrupt */
819 if ((ssr_status & 0x0020) && (scr_status & 0x0080))
820 sci_tx_interrupt(irq, ptr);
821 /* Rx Interrupt */
822 if ((ssr_status & 0x0002) && (scr_status & 0x0040))
823 sci_rx_interrupt(irq, ptr);
824 /* Error Interrupt */
825 if ((ssr_status & 0x0080) && (scr_status & 0x0400))
826 sci_er_interrupt(irq, ptr);
827 /* Break Interrupt */
828 if ((ssr_status & 0x0010) && (scr_status & 0x0200))
829 sci_br_interrupt(irq, ptr);
830
831 return IRQ_HANDLED;
832 }
833
834 #ifdef CONFIG_CPU_FREQ
835 /*
836 * Here we define a transistion notifier so that we can update all of our
837 * ports' baud rate when the peripheral clock changes.
838 */
839 static int sci_notifier(struct notifier_block *self,
840 unsigned long phase, void *p)
841 {
842 struct cpufreq_freqs *freqs = p;
843 int i;
844
845 if ((phase == CPUFREQ_POSTCHANGE) ||
846 (phase == CPUFREQ_RESUMECHANGE)){
847 for (i = 0; i < SCI_NPORTS; i++) {
848 struct uart_port *port = &sci_ports[i].port;
849 struct clk *clk;
850
851 /*
852 * Update the uartclk per-port if frequency has
853 * changed, since it will no longer necessarily be
854 * consistent with the old frequency.
855 *
856 * Really we want to be able to do something like
857 * uart_change_speed() or something along those lines
858 * here to implicitly reset the per-port baud rate..
859 *
860 * Clean this up later..
861 */
862 clk = clk_get(NULL, "module_clk");
863 port->uartclk = clk_get_rate(clk) * 16;
864 clk_put(clk);
865 }
866
867 printk(KERN_INFO "%s: got a postchange notification "
868 "for cpu %d (old %d, new %d)\n",
869 __func__, freqs->cpu, freqs->old, freqs->new);
870 }
871
872 return NOTIFY_OK;
873 }
874
875 static struct notifier_block sci_nb = { &sci_notifier, NULL, 0 };
876 #endif /* CONFIG_CPU_FREQ */
877
878 static int sci_request_irq(struct sci_port *port)
879 {
880 int i;
881 irqreturn_t (*handlers[4])(int irq, void *ptr) = {
882 sci_er_interrupt, sci_rx_interrupt, sci_tx_interrupt,
883 sci_br_interrupt,
884 };
885 const char *desc[] = { "SCI Receive Error", "SCI Receive Data Full",
886 "SCI Transmit Data Empty", "SCI Break" };
887
888 if (port->irqs[0] == port->irqs[1]) {
889 if (!port->irqs[0]) {
890 printk(KERN_ERR "sci: Cannot allocate irq.(IRQ=0)\n");
891 return -ENODEV;
892 }
893
894 if (request_irq(port->irqs[0], sci_mpxed_interrupt,
895 IRQF_DISABLED, "sci", port)) {
896 printk(KERN_ERR "sci: Cannot allocate irq.\n");
897 return -ENODEV;
898 }
899 } else {
900 for (i = 0; i < ARRAY_SIZE(handlers); i++) {
901 if (!port->irqs[i])
902 continue;
903 if (request_irq(port->irqs[i], handlers[i],
904 IRQF_DISABLED, desc[i], port)) {
905 printk(KERN_ERR "sci: Cannot allocate irq.\n");
906 return -ENODEV;
907 }
908 }
909 }
910
911 return 0;
912 }
913
914 static void sci_free_irq(struct sci_port *port)
915 {
916 int i;
917
918 if (port->irqs[0] == port->irqs[1]) {
919 if (!port->irqs[0])
920 printk("sci: sci_free_irq error\n");
921 else
922 free_irq(port->irqs[0], port);
923 } else {
924 for (i = 0; i < ARRAY_SIZE(port->irqs); i++) {
925 if (!port->irqs[i])
926 continue;
927
928 free_irq(port->irqs[i], port);
929 }
930 }
931 }
932
933 static unsigned int sci_tx_empty(struct uart_port *port)
934 {
935 /* Can't detect */
936 return TIOCSER_TEMT;
937 }
938
939 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
940 {
941 /* This routine is used for seting signals of: DTR, DCD, CTS/RTS */
942 /* We use SCIF's hardware for CTS/RTS, so don't need any for that. */
943 /* If you have signals for DTR and DCD, please implement here. */
944 }
945
946 static unsigned int sci_get_mctrl(struct uart_port *port)
947 {
948 /* This routine is used for geting signals of: DTR, DCD, DSR, RI,
949 and CTS/RTS */
950
951 return TIOCM_DTR | TIOCM_RTS | TIOCM_DSR;
952 }
953
954 static void sci_start_tx(struct uart_port *port)
955 {
956 unsigned short ctrl;
957
958 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
959 ctrl = sci_in(port, SCSCR);
960 ctrl |= SCI_CTRL_FLAGS_TIE;
961 sci_out(port, SCSCR, ctrl);
962 }
963
964 static void sci_stop_tx(struct uart_port *port)
965 {
966 unsigned short ctrl;
967
968 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
969 ctrl = sci_in(port, SCSCR);
970 ctrl &= ~SCI_CTRL_FLAGS_TIE;
971 sci_out(port, SCSCR, ctrl);
972 }
973
974 static void sci_start_rx(struct uart_port *port, unsigned int tty_start)
975 {
976 unsigned short ctrl;
977
978 /* Set RIE (Receive Interrupt Enable) bit in SCSCR */
979 ctrl = sci_in(port, SCSCR);
980 ctrl |= SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE;
981 sci_out(port, SCSCR, ctrl);
982 }
983
984 static void sci_stop_rx(struct uart_port *port)
985 {
986 unsigned short ctrl;
987
988 /* Clear RIE (Receive Interrupt Enable) bit in SCSCR */
989 ctrl = sci_in(port, SCSCR);
990 ctrl &= ~(SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE);
991 sci_out(port, SCSCR, ctrl);
992 }
993
994 static void sci_enable_ms(struct uart_port *port)
995 {
996 /* Nothing here yet .. */
997 }
998
999 static void sci_break_ctl(struct uart_port *port, int break_state)
1000 {
1001 /* Nothing here yet .. */
1002 }
1003
1004 static int sci_startup(struct uart_port *port)
1005 {
1006 struct sci_port *s = &sci_ports[port->line];
1007
1008 if (s->enable)
1009 s->enable(port);
1010
1011 #if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
1012 s->clk = clk_get(NULL, "module_clk");
1013 #endif
1014
1015 sci_request_irq(s);
1016 sci_start_tx(port);
1017 sci_start_rx(port, 1);
1018
1019 return 0;
1020 }
1021
1022 static void sci_shutdown(struct uart_port *port)
1023 {
1024 struct sci_port *s = &sci_ports[port->line];
1025
1026 sci_stop_rx(port);
1027 sci_stop_tx(port);
1028 sci_free_irq(s);
1029
1030 if (s->disable)
1031 s->disable(port);
1032
1033 #if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
1034 clk_put(s->clk);
1035 s->clk = NULL;
1036 #endif
1037 }
1038
1039 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1040 struct ktermios *old)
1041 {
1042 struct sci_port *s = &sci_ports[port->line];
1043 unsigned int status, baud, smr_val;
1044 int t;
1045
1046 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
1047
1048 switch (baud) {
1049 case 0:
1050 t = -1;
1051 break;
1052 default:
1053 {
1054 #if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
1055 t = SCBRR_VALUE(baud, clk_get_rate(s->clk));
1056 #else
1057 t = SCBRR_VALUE(baud);
1058 #endif
1059 break;
1060 }
1061 }
1062
1063 do {
1064 status = sci_in(port, SCxSR);
1065 } while (!(status & SCxSR_TEND(port)));
1066
1067 sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1068
1069 #if !defined(SCI_ONLY)
1070 if (port->type == PORT_SCIF)
1071 sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1072 #endif
1073
1074 smr_val = sci_in(port, SCSMR) & 3;
1075 if ((termios->c_cflag & CSIZE) == CS7)
1076 smr_val |= 0x40;
1077 if (termios->c_cflag & PARENB)
1078 smr_val |= 0x20;
1079 if (termios->c_cflag & PARODD)
1080 smr_val |= 0x30;
1081 if (termios->c_cflag & CSTOPB)
1082 smr_val |= 0x08;
1083
1084 uart_update_timeout(port, termios->c_cflag, baud);
1085
1086 sci_out(port, SCSMR, smr_val);
1087
1088 if (t > 0) {
1089 if(t >= 256) {
1090 sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1);
1091 t >>= 2;
1092 } else {
1093 sci_out(port, SCSMR, sci_in(port, SCSMR) & ~3);
1094 }
1095 sci_out(port, SCBRR, t);
1096 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
1097 }
1098
1099 if (likely(s->init_pins))
1100 s->init_pins(port, termios->c_cflag);
1101
1102 sci_out(port, SCSCR, SCSCR_INIT(port));
1103
1104 if ((termios->c_cflag & CREAD) != 0)
1105 sci_start_rx(port,0);
1106 }
1107
1108 static const char *sci_type(struct uart_port *port)
1109 {
1110 switch (port->type) {
1111 case PORT_SCI: return "sci";
1112 case PORT_SCIF: return "scif";
1113 case PORT_IRDA: return "irda";
1114 }
1115
1116 return 0;
1117 }
1118
1119 static void sci_release_port(struct uart_port *port)
1120 {
1121 /* Nothing here yet .. */
1122 }
1123
1124 static int sci_request_port(struct uart_port *port)
1125 {
1126 /* Nothing here yet .. */
1127 return 0;
1128 }
1129
1130 static void sci_config_port(struct uart_port *port, int flags)
1131 {
1132 struct sci_port *s = &sci_ports[port->line];
1133
1134 port->type = s->type;
1135
1136 switch (port->type) {
1137 case PORT_SCI:
1138 s->init_pins = sci_init_pins_sci;
1139 break;
1140 case PORT_SCIF:
1141 s->init_pins = sci_init_pins_scif;
1142 break;
1143 case PORT_IRDA:
1144 s->init_pins = sci_init_pins_irda;
1145 break;
1146 }
1147
1148 #if defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
1149 if (port->mapbase == 0)
1150 port->mapbase = onchip_remap(SCIF_ADDR_SH5, 1024, "SCIF");
1151
1152 port->membase = (void __iomem *)port->mapbase;
1153 #endif
1154 }
1155
1156 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
1157 {
1158 struct sci_port *s = &sci_ports[port->line];
1159
1160 if (ser->irq != s->irqs[SCIx_TXI_IRQ] || ser->irq > NR_IRQS)
1161 return -EINVAL;
1162 if (ser->baud_base < 2400)
1163 /* No paper tape reader for Mitch.. */
1164 return -EINVAL;
1165
1166 return 0;
1167 }
1168
1169 static struct uart_ops sci_uart_ops = {
1170 .tx_empty = sci_tx_empty,
1171 .set_mctrl = sci_set_mctrl,
1172 .get_mctrl = sci_get_mctrl,
1173 .start_tx = sci_start_tx,
1174 .stop_tx = sci_stop_tx,
1175 .stop_rx = sci_stop_rx,
1176 .enable_ms = sci_enable_ms,
1177 .break_ctl = sci_break_ctl,
1178 .startup = sci_startup,
1179 .shutdown = sci_shutdown,
1180 .set_termios = sci_set_termios,
1181 .type = sci_type,
1182 .release_port = sci_release_port,
1183 .request_port = sci_request_port,
1184 .config_port = sci_config_port,
1185 .verify_port = sci_verify_port,
1186 };
1187
1188 static void __init sci_init_ports(void)
1189 {
1190 static int first = 1;
1191 int i;
1192
1193 if (!first)
1194 return;
1195
1196 first = 0;
1197
1198 for (i = 0; i < SCI_NPORTS; i++) {
1199 sci_ports[i].port.ops = &sci_uart_ops;
1200 sci_ports[i].port.iotype = UPIO_MEM;
1201 sci_ports[i].port.line = i;
1202 sci_ports[i].port.fifosize = 1;
1203
1204 #if defined(__H8300H__) || defined(__H8300S__)
1205 #ifdef __H8300S__
1206 sci_ports[i].enable = h8300_sci_enable;
1207 sci_ports[i].disable = h8300_sci_disable;
1208 #endif
1209 sci_ports[i].port.uartclk = CONFIG_CPU_CLOCK;
1210 #elif defined(CONFIG_SUPERH64)
1211 sci_ports[i].port.uartclk = current_cpu_data.module_clock * 16;
1212 #else
1213 /*
1214 * XXX: We should use a proper SCI/SCIF clock
1215 */
1216 {
1217 struct clk *clk = clk_get(NULL, "module_clk");
1218 sci_ports[i].port.uartclk = clk_get_rate(clk) * 16;
1219 clk_put(clk);
1220 }
1221 #endif
1222
1223 sci_ports[i].break_timer.data = (unsigned long)&sci_ports[i];
1224 sci_ports[i].break_timer.function = sci_break_timer;
1225
1226 init_timer(&sci_ports[i].break_timer);
1227 }
1228 }
1229
1230 int __init early_sci_setup(struct uart_port *port)
1231 {
1232 if (unlikely(port->line > SCI_NPORTS))
1233 return -ENODEV;
1234
1235 sci_init_ports();
1236
1237 sci_ports[port->line].port.membase = port->membase;
1238 sci_ports[port->line].port.mapbase = port->mapbase;
1239 sci_ports[port->line].port.type = port->type;
1240
1241 return 0;
1242 }
1243
1244 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
1245 /*
1246 * Print a string to the serial port trying not to disturb
1247 * any possible real use of the port...
1248 */
1249 static void serial_console_write(struct console *co, const char *s,
1250 unsigned count)
1251 {
1252 put_string(serial_console_port, s, count);
1253 }
1254
1255 static int __init serial_console_setup(struct console *co, char *options)
1256 {
1257 struct uart_port *port;
1258 int baud = 115200;
1259 int bits = 8;
1260 int parity = 'n';
1261 int flow = 'n';
1262 int ret;
1263
1264 /*
1265 * Check whether an invalid uart number has been specified, and
1266 * if so, search for the first available port that does have
1267 * console support.
1268 */
1269 if (co->index >= SCI_NPORTS)
1270 co->index = 0;
1271
1272 serial_console_port = &sci_ports[co->index];
1273 port = &serial_console_port->port;
1274
1275 /*
1276 * Also need to check port->type, we don't actually have any
1277 * UPIO_PORT ports, but uart_report_port() handily misreports
1278 * it anyways if we don't have a port available by the time this is
1279 * called.
1280 */
1281 if (!port->type)
1282 return -ENODEV;
1283 if (!port->membase || !port->mapbase)
1284 return -ENODEV;
1285
1286 port->type = serial_console_port->type;
1287
1288 #if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
1289 if (!serial_console_port->clk)
1290 serial_console_port->clk = clk_get(NULL, "module_clk");
1291 #endif
1292
1293 if (port->flags & UPF_IOREMAP)
1294 sci_config_port(port, 0);
1295
1296 if (serial_console_port->enable)
1297 serial_console_port->enable(port);
1298
1299 if (options)
1300 uart_parse_options(options, &baud, &parity, &bits, &flow);
1301
1302 ret = uart_set_options(port, co, baud, parity, bits, flow);
1303 #if defined(__H8300H__) || defined(__H8300S__)
1304 /* disable rx interrupt */
1305 if (ret == 0)
1306 sci_stop_rx(port);
1307 #endif
1308 return ret;
1309 }
1310
1311 static struct console serial_console = {
1312 .name = "ttySC",
1313 .device = uart_console_device,
1314 .write = serial_console_write,
1315 .setup = serial_console_setup,
1316 .flags = CON_PRINTBUFFER,
1317 .index = -1,
1318 .data = &sci_uart_driver,
1319 };
1320
1321 static int __init sci_console_init(void)
1322 {
1323 sci_init_ports();
1324 register_console(&serial_console);
1325 return 0;
1326 }
1327 console_initcall(sci_console_init);
1328 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1329
1330 #ifdef CONFIG_SH_KGDB_CONSOLE
1331 /*
1332 * FIXME: Most of this can go away.. at the moment, we rely on
1333 * arch/sh/kernel/setup.c to do the command line parsing for kgdb, though
1334 * most of that can easily be done here instead.
1335 *
1336 * For the time being, just accept the values that were parsed earlier..
1337 */
1338 static void __init kgdb_console_get_options(struct uart_port *port, int *baud,
1339 int *parity, int *bits)
1340 {
1341 *baud = kgdb_baud;
1342 *parity = tolower(kgdb_parity);
1343 *bits = kgdb_bits - '0';
1344 }
1345
1346 /*
1347 * The naming here is somewhat misleading, since kgdb_console_setup() takes
1348 * care of the early-on initialization for kgdb, regardless of whether we
1349 * actually use kgdb as a console or not.
1350 *
1351 * On the plus side, this lets us kill off the old kgdb_sci_setup() nonsense.
1352 */
1353 int __init kgdb_console_setup(struct console *co, char *options)
1354 {
1355 struct uart_port *port = &sci_ports[kgdb_portnum].port;
1356 int baud = 38400;
1357 int bits = 8;
1358 int parity = 'n';
1359 int flow = 'n';
1360
1361 if (co->index != kgdb_portnum)
1362 co->index = kgdb_portnum;
1363
1364 kgdb_sci_port = &sci_ports[co->index];
1365 port = &kgdb_sci_port->port;
1366
1367 /*
1368 * Also need to check port->type, we don't actually have any
1369 * UPIO_PORT ports, but uart_report_port() handily misreports
1370 * it anyways if we don't have a port available by the time this is
1371 * called.
1372 */
1373 if (!port->type)
1374 return -ENODEV;
1375 if (!port->membase || !port->mapbase)
1376 return -ENODEV;
1377
1378 if (options)
1379 uart_parse_options(options, &baud, &parity, &bits, &flow);
1380 else
1381 kgdb_console_get_options(port, &baud, &parity, &bits);
1382
1383 kgdb_getchar = kgdb_sci_getchar;
1384 kgdb_putchar = kgdb_sci_putchar;
1385
1386 return uart_set_options(port, co, baud, parity, bits, flow);
1387 }
1388
1389 static struct console kgdb_console = {
1390 .name = "ttySC",
1391 .device = uart_console_device,
1392 .write = kgdb_console_write,
1393 .setup = kgdb_console_setup,
1394 .flags = CON_PRINTBUFFER,
1395 .index = -1,
1396 .data = &sci_uart_driver,
1397 };
1398
1399 /* Register the KGDB console so we get messages (d'oh!) */
1400 static int __init kgdb_console_init(void)
1401 {
1402 sci_init_ports();
1403 register_console(&kgdb_console);
1404 return 0;
1405 }
1406 console_initcall(kgdb_console_init);
1407 #endif /* CONFIG_SH_KGDB_CONSOLE */
1408
1409 #if defined(CONFIG_SH_KGDB_CONSOLE)
1410 #define SCI_CONSOLE &kgdb_console
1411 #elif defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1412 #define SCI_CONSOLE &serial_console
1413 #else
1414 #define SCI_CONSOLE 0
1415 #endif
1416
1417 static char banner[] __initdata =
1418 KERN_INFO "SuperH SCI(F) driver initialized\n";
1419
1420 static struct uart_driver sci_uart_driver = {
1421 .owner = THIS_MODULE,
1422 .driver_name = "sci",
1423 .dev_name = "ttySC",
1424 .major = SCI_MAJOR,
1425 .minor = SCI_MINOR_START,
1426 .nr = SCI_NPORTS,
1427 .cons = SCI_CONSOLE,
1428 };
1429
1430 /*
1431 * Register a set of serial devices attached to a platform device. The
1432 * list is terminated with a zero flags entry, which means we expect
1433 * all entries to have at least UPF_BOOT_AUTOCONF set. Platforms that need
1434 * remapping (such as sh64) should also set UPF_IOREMAP.
1435 */
1436 static int __devinit sci_probe(struct platform_device *dev)
1437 {
1438 struct plat_sci_port *p = dev->dev.platform_data;
1439 int i;
1440
1441 for (i = 0; p && p->flags != 0; p++, i++) {
1442 struct sci_port *sciport = &sci_ports[i];
1443
1444 /* Sanity check */
1445 if (unlikely(i == SCI_NPORTS)) {
1446 dev_notice(&dev->dev, "Attempting to register port "
1447 "%d when only %d are available.\n",
1448 i+1, SCI_NPORTS);
1449 dev_notice(&dev->dev, "Consider bumping "
1450 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
1451 break;
1452 }
1453
1454 sciport->port.mapbase = p->mapbase;
1455
1456 /*
1457 * For the simple (and majority of) cases where we don't need
1458 * to do any remapping, just cast the cookie directly.
1459 */
1460 if (p->mapbase && !p->membase && !(p->flags & UPF_IOREMAP))
1461 p->membase = (void __iomem *)p->mapbase;
1462
1463 sciport->port.membase = p->membase;
1464
1465 sciport->port.irq = p->irqs[SCIx_TXI_IRQ];
1466 sciport->port.flags = p->flags;
1467 sciport->port.dev = &dev->dev;
1468
1469 sciport->type = sciport->port.type = p->type;
1470
1471 memcpy(&sciport->irqs, &p->irqs, sizeof(p->irqs));
1472
1473 uart_add_one_port(&sci_uart_driver, &sciport->port);
1474 }
1475
1476 #if defined(CONFIG_SH_KGDB) && !defined(CONFIG_SH_KGDB_CONSOLE)
1477 kgdb_sci_port = &sci_ports[kgdb_portnum];
1478 kgdb_getchar = kgdb_sci_getchar;
1479 kgdb_putchar = kgdb_sci_putchar;
1480 #endif
1481
1482 #ifdef CONFIG_CPU_FREQ
1483 cpufreq_register_notifier(&sci_nb, CPUFREQ_TRANSITION_NOTIFIER);
1484 dev_info(&dev->dev, "CPU frequency notifier registered\n");
1485 #endif
1486
1487 #ifdef CONFIG_SH_STANDARD_BIOS
1488 sh_bios_gdb_detach();
1489 #endif
1490
1491 return 0;
1492 }
1493
1494 static int __devexit sci_remove(struct platform_device *dev)
1495 {
1496 int i;
1497
1498 for (i = 0; i < SCI_NPORTS; i++)
1499 uart_remove_one_port(&sci_uart_driver, &sci_ports[i].port);
1500
1501 return 0;
1502 }
1503
1504 static int sci_suspend(struct platform_device *dev, pm_message_t state)
1505 {
1506 int i;
1507
1508 for (i = 0; i < SCI_NPORTS; i++) {
1509 struct sci_port *p = &sci_ports[i];
1510
1511 if (p->type != PORT_UNKNOWN && p->port.dev == &dev->dev)
1512 uart_suspend_port(&sci_uart_driver, &p->port);
1513 }
1514
1515 return 0;
1516 }
1517
1518 static int sci_resume(struct platform_device *dev)
1519 {
1520 int i;
1521
1522 for (i = 0; i < SCI_NPORTS; i++) {
1523 struct sci_port *p = &sci_ports[i];
1524
1525 if (p->type != PORT_UNKNOWN && p->port.dev == &dev->dev)
1526 uart_resume_port(&sci_uart_driver, &p->port);
1527 }
1528
1529 return 0;
1530 }
1531
1532 static struct platform_driver sci_driver = {
1533 .probe = sci_probe,
1534 .remove = __devexit_p(sci_remove),
1535 .suspend = sci_suspend,
1536 .resume = sci_resume,
1537 .driver = {
1538 .name = "sh-sci",
1539 .owner = THIS_MODULE,
1540 },
1541 };
1542
1543 static int __init sci_init(void)
1544 {
1545 int ret;
1546
1547 printk(banner);
1548
1549 sci_init_ports();
1550
1551 ret = uart_register_driver(&sci_uart_driver);
1552 if (likely(ret == 0)) {
1553 ret = platform_driver_register(&sci_driver);
1554 if (unlikely(ret))
1555 uart_unregister_driver(&sci_uart_driver);
1556 }
1557
1558 return ret;
1559 }
1560
1561 static void __exit sci_exit(void)
1562 {
1563 platform_driver_unregister(&sci_driver);
1564 uart_unregister_driver(&sci_uart_driver);
1565 }
1566
1567 module_init(sci_init);
1568 module_exit(sci_exit);
1569
1570 MODULE_LICENSE("GPL");
1571 MODULE_ALIAS("platform:sh-sci");
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