2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include "radeon_drm.h"
31 #include <asm/div64.h>
33 #include "drm_crtc_helper.h"
36 static int radeon_ddc_dump(struct drm_connector
*connector
);
38 static void avivo_crtc_load_lut(struct drm_crtc
*crtc
)
40 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
41 struct drm_device
*dev
= crtc
->dev
;
42 struct radeon_device
*rdev
= dev
->dev_private
;
45 DRM_DEBUG("%d\n", radeon_crtc
->crtc_id
);
46 WREG32(AVIVO_DC_LUTA_CONTROL
+ radeon_crtc
->crtc_offset
, 0);
48 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE
+ radeon_crtc
->crtc_offset
, 0);
49 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN
+ radeon_crtc
->crtc_offset
, 0);
50 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED
+ radeon_crtc
->crtc_offset
, 0);
52 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE
+ radeon_crtc
->crtc_offset
, 0xffff);
53 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN
+ radeon_crtc
->crtc_offset
, 0xffff);
54 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED
+ radeon_crtc
->crtc_offset
, 0xffff);
56 WREG32(AVIVO_DC_LUT_RW_SELECT
, radeon_crtc
->crtc_id
);
57 WREG32(AVIVO_DC_LUT_RW_MODE
, 0);
58 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK
, 0x0000003f);
60 WREG8(AVIVO_DC_LUT_RW_INDEX
, 0);
61 for (i
= 0; i
< 256; i
++) {
62 WREG32(AVIVO_DC_LUT_30_COLOR
,
63 (radeon_crtc
->lut_r
[i
] << 20) |
64 (radeon_crtc
->lut_g
[i
] << 10) |
65 (radeon_crtc
->lut_b
[i
] << 0));
68 WREG32(AVIVO_D1GRPH_LUT_SEL
+ radeon_crtc
->crtc_offset
, radeon_crtc
->crtc_id
);
71 static void legacy_crtc_load_lut(struct drm_crtc
*crtc
)
73 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
74 struct drm_device
*dev
= crtc
->dev
;
75 struct radeon_device
*rdev
= dev
->dev_private
;
79 dac2_cntl
= RREG32(RADEON_DAC_CNTL2
);
80 if (radeon_crtc
->crtc_id
== 0)
81 dac2_cntl
&= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL
;
83 dac2_cntl
|= RADEON_DAC2_PALETTE_ACC_CTL
;
84 WREG32(RADEON_DAC_CNTL2
, dac2_cntl
);
86 WREG8(RADEON_PALETTE_INDEX
, 0);
87 for (i
= 0; i
< 256; i
++) {
88 WREG32(RADEON_PALETTE_30_DATA
,
89 (radeon_crtc
->lut_r
[i
] << 20) |
90 (radeon_crtc
->lut_g
[i
] << 10) |
91 (radeon_crtc
->lut_b
[i
] << 0));
95 void radeon_crtc_load_lut(struct drm_crtc
*crtc
)
97 struct drm_device
*dev
= crtc
->dev
;
98 struct radeon_device
*rdev
= dev
->dev_private
;
103 if (ASIC_IS_AVIVO(rdev
))
104 avivo_crtc_load_lut(crtc
);
106 legacy_crtc_load_lut(crtc
);
109 /** Sets the color ramps on behalf of fbcon */
110 void radeon_crtc_fb_gamma_set(struct drm_crtc
*crtc
, u16 red
, u16 green
,
113 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
115 radeon_crtc
->lut_r
[regno
] = red
>> 6;
116 radeon_crtc
->lut_g
[regno
] = green
>> 6;
117 radeon_crtc
->lut_b
[regno
] = blue
>> 6;
120 /** Gets the color ramps on behalf of fbcon */
121 void radeon_crtc_fb_gamma_get(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
122 u16
*blue
, int regno
)
124 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
126 *red
= radeon_crtc
->lut_r
[regno
] << 6;
127 *green
= radeon_crtc
->lut_g
[regno
] << 6;
128 *blue
= radeon_crtc
->lut_b
[regno
] << 6;
131 static void radeon_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
132 u16
*blue
, uint32_t size
)
134 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
141 /* userspace palettes are always correct as is */
142 for (i
= 0; i
< 256; i
++) {
143 radeon_crtc
->lut_r
[i
] = red
[i
] >> 6;
144 radeon_crtc
->lut_g
[i
] = green
[i
] >> 6;
145 radeon_crtc
->lut_b
[i
] = blue
[i
] >> 6;
147 radeon_crtc_load_lut(crtc
);
150 static void radeon_crtc_destroy(struct drm_crtc
*crtc
)
152 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
154 drm_crtc_cleanup(crtc
);
158 static const struct drm_crtc_funcs radeon_crtc_funcs
= {
159 .cursor_set
= radeon_crtc_cursor_set
,
160 .cursor_move
= radeon_crtc_cursor_move
,
161 .gamma_set
= radeon_crtc_gamma_set
,
162 .set_config
= drm_crtc_helper_set_config
,
163 .destroy
= radeon_crtc_destroy
,
166 static void radeon_crtc_init(struct drm_device
*dev
, int index
)
168 struct radeon_device
*rdev
= dev
->dev_private
;
169 struct radeon_crtc
*radeon_crtc
;
172 radeon_crtc
= kzalloc(sizeof(struct radeon_crtc
) + (RADEONFB_CONN_LIMIT
* sizeof(struct drm_connector
*)), GFP_KERNEL
);
173 if (radeon_crtc
== NULL
)
176 drm_crtc_init(dev
, &radeon_crtc
->base
, &radeon_crtc_funcs
);
178 drm_mode_crtc_set_gamma_size(&radeon_crtc
->base
, 256);
179 radeon_crtc
->crtc_id
= index
;
180 rdev
->mode_info
.crtcs
[index
] = radeon_crtc
;
183 radeon_crtc
->mode_set
.crtc
= &radeon_crtc
->base
;
184 radeon_crtc
->mode_set
.connectors
= (struct drm_connector
**)(radeon_crtc
+ 1);
185 radeon_crtc
->mode_set
.num_connectors
= 0;
188 for (i
= 0; i
< 256; i
++) {
189 radeon_crtc
->lut_r
[i
] = i
<< 2;
190 radeon_crtc
->lut_g
[i
] = i
<< 2;
191 radeon_crtc
->lut_b
[i
] = i
<< 2;
194 if (rdev
->is_atom_bios
&& (ASIC_IS_AVIVO(rdev
) || radeon_r4xx_atom
))
195 radeon_atombios_init_crtc(dev
, radeon_crtc
);
197 radeon_legacy_init_crtc(dev
, radeon_crtc
);
200 static const char *encoder_names
[34] = {
220 "INTERNAL_KLDSCP_TMDS1",
221 "INTERNAL_KLDSCP_DVO1",
222 "INTERNAL_KLDSCP_DAC1",
223 "INTERNAL_KLDSCP_DAC2",
232 "INTERNAL_KLDSCP_LVTMA",
237 static const char *connector_names
[15] = {
255 static const char *hpd_names
[7] = {
265 static void radeon_print_display_setup(struct drm_device
*dev
)
267 struct drm_connector
*connector
;
268 struct radeon_connector
*radeon_connector
;
269 struct drm_encoder
*encoder
;
270 struct radeon_encoder
*radeon_encoder
;
274 DRM_INFO("Radeon Display Connectors\n");
275 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
276 radeon_connector
= to_radeon_connector(connector
);
277 DRM_INFO("Connector %d:\n", i
);
278 DRM_INFO(" %s\n", connector_names
[connector
->connector_type
]);
279 if (radeon_connector
->hpd
.hpd
!= RADEON_HPD_NONE
)
280 DRM_INFO(" %s\n", hpd_names
[radeon_connector
->hpd
.hpd
]);
281 if (radeon_connector
->ddc_bus
)
282 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
283 radeon_connector
->ddc_bus
->rec
.mask_clk_reg
,
284 radeon_connector
->ddc_bus
->rec
.mask_data_reg
,
285 radeon_connector
->ddc_bus
->rec
.a_clk_reg
,
286 radeon_connector
->ddc_bus
->rec
.a_data_reg
,
287 radeon_connector
->ddc_bus
->rec
.en_clk_reg
,
288 radeon_connector
->ddc_bus
->rec
.en_data_reg
,
289 radeon_connector
->ddc_bus
->rec
.y_clk_reg
,
290 radeon_connector
->ddc_bus
->rec
.y_data_reg
);
291 DRM_INFO(" Encoders:\n");
292 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
293 radeon_encoder
= to_radeon_encoder(encoder
);
294 devices
= radeon_encoder
->devices
& radeon_connector
->devices
;
296 if (devices
& ATOM_DEVICE_CRT1_SUPPORT
)
297 DRM_INFO(" CRT1: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
298 if (devices
& ATOM_DEVICE_CRT2_SUPPORT
)
299 DRM_INFO(" CRT2: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
300 if (devices
& ATOM_DEVICE_LCD1_SUPPORT
)
301 DRM_INFO(" LCD1: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
302 if (devices
& ATOM_DEVICE_DFP1_SUPPORT
)
303 DRM_INFO(" DFP1: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
304 if (devices
& ATOM_DEVICE_DFP2_SUPPORT
)
305 DRM_INFO(" DFP2: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
306 if (devices
& ATOM_DEVICE_DFP3_SUPPORT
)
307 DRM_INFO(" DFP3: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
308 if (devices
& ATOM_DEVICE_DFP4_SUPPORT
)
309 DRM_INFO(" DFP4: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
310 if (devices
& ATOM_DEVICE_DFP5_SUPPORT
)
311 DRM_INFO(" DFP5: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
312 if (devices
& ATOM_DEVICE_TV1_SUPPORT
)
313 DRM_INFO(" TV1: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
314 if (devices
& ATOM_DEVICE_CV_SUPPORT
)
315 DRM_INFO(" CV: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
322 static bool radeon_setup_enc_conn(struct drm_device
*dev
)
324 struct radeon_device
*rdev
= dev
->dev_private
;
325 struct drm_connector
*drm_connector
;
329 if (rdev
->is_atom_bios
) {
330 if (rdev
->family
>= CHIP_R600
)
331 ret
= radeon_get_atom_connector_info_from_object_table(dev
);
333 ret
= radeon_get_atom_connector_info_from_supported_devices_table(dev
);
335 ret
= radeon_get_legacy_connector_info_from_bios(dev
);
337 ret
= radeon_get_legacy_connector_info_from_table(dev
);
340 if (!ASIC_IS_AVIVO(rdev
))
341 ret
= radeon_get_legacy_connector_info_from_table(dev
);
344 radeon_setup_encoder_clones(dev
);
345 radeon_print_display_setup(dev
);
346 list_for_each_entry(drm_connector
, &dev
->mode_config
.connector_list
, head
)
347 radeon_ddc_dump(drm_connector
);
353 int radeon_ddc_get_modes(struct radeon_connector
*radeon_connector
)
357 if ((radeon_connector
->base
.connector_type
== DRM_MODE_CONNECTOR_DisplayPort
) ||
358 (radeon_connector
->base
.connector_type
== DRM_MODE_CONNECTOR_eDP
)) {
359 struct radeon_connector_atom_dig
*dig
= radeon_connector
->con_priv
;
360 if ((dig
->dp_sink_type
== CONNECTOR_OBJECT_ID_DISPLAYPORT
||
361 dig
->dp_sink_type
== CONNECTOR_OBJECT_ID_eDP
) && dig
->dp_i2c_bus
)
362 radeon_connector
->edid
= drm_get_edid(&radeon_connector
->base
, &dig
->dp_i2c_bus
->adapter
);
364 if (!radeon_connector
->ddc_bus
)
366 if (!radeon_connector
->edid
) {
367 radeon_connector
->edid
= drm_get_edid(&radeon_connector
->base
, &radeon_connector
->ddc_bus
->adapter
);
370 if (radeon_connector
->edid
) {
371 drm_mode_connector_update_edid_property(&radeon_connector
->base
, radeon_connector
->edid
);
372 ret
= drm_add_edid_modes(&radeon_connector
->base
, radeon_connector
->edid
);
375 drm_mode_connector_update_edid_property(&radeon_connector
->base
, NULL
);
379 static int radeon_ddc_dump(struct drm_connector
*connector
)
382 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
385 if (!radeon_connector
->ddc_bus
)
387 edid
= drm_get_edid(connector
, &radeon_connector
->ddc_bus
->adapter
);
394 static inline uint32_t radeon_div(uint64_t n
, uint32_t d
)
404 void radeon_compute_pll(struct radeon_pll
*pll
,
406 uint32_t *dot_clock_p
,
408 uint32_t *frac_fb_div_p
,
410 uint32_t *post_div_p
)
412 uint32_t min_ref_div
= pll
->min_ref_div
;
413 uint32_t max_ref_div
= pll
->max_ref_div
;
414 uint32_t min_post_div
= pll
->min_post_div
;
415 uint32_t max_post_div
= pll
->max_post_div
;
416 uint32_t min_fractional_feed_div
= 0;
417 uint32_t max_fractional_feed_div
= 0;
418 uint32_t best_vco
= pll
->best_vco
;
419 uint32_t best_post_div
= 1;
420 uint32_t best_ref_div
= 1;
421 uint32_t best_feedback_div
= 1;
422 uint32_t best_frac_feedback_div
= 0;
423 uint32_t best_freq
= -1;
424 uint32_t best_error
= 0xffffffff;
425 uint32_t best_vco_diff
= 1;
428 DRM_DEBUG("PLL freq %llu %u %u\n", freq
, pll
->min_ref_div
, pll
->max_ref_div
);
431 if (pll
->flags
& RADEON_PLL_USE_REF_DIV
)
432 min_ref_div
= max_ref_div
= pll
->reference_div
;
434 while (min_ref_div
< max_ref_div
-1) {
435 uint32_t mid
= (min_ref_div
+ max_ref_div
) / 2;
436 uint32_t pll_in
= pll
->reference_freq
/ mid
;
437 if (pll_in
< pll
->pll_in_min
)
439 else if (pll_in
> pll
->pll_in_max
)
446 if (pll
->flags
& RADEON_PLL_USE_POST_DIV
)
447 min_post_div
= max_post_div
= pll
->post_div
;
449 if (pll
->flags
& RADEON_PLL_USE_FRAC_FB_DIV
) {
450 min_fractional_feed_div
= pll
->min_frac_feedback_div
;
451 max_fractional_feed_div
= pll
->max_frac_feedback_div
;
454 for (post_div
= min_post_div
; post_div
<= max_post_div
; ++post_div
) {
457 if ((pll
->flags
& RADEON_PLL_NO_ODD_POST_DIV
) && (post_div
& 1))
460 /* legacy radeons only have a few post_divs */
461 if (pll
->flags
& RADEON_PLL_LEGACY
) {
462 if ((post_div
== 5) ||
473 for (ref_div
= min_ref_div
; ref_div
<= max_ref_div
; ++ref_div
) {
474 uint32_t feedback_div
, current_freq
= 0, error
, vco_diff
;
475 uint32_t pll_in
= pll
->reference_freq
/ ref_div
;
476 uint32_t min_feed_div
= pll
->min_feedback_div
;
477 uint32_t max_feed_div
= pll
->max_feedback_div
+ 1;
479 if (pll_in
< pll
->pll_in_min
|| pll_in
> pll
->pll_in_max
)
482 while (min_feed_div
< max_feed_div
) {
484 uint32_t min_frac_feed_div
= min_fractional_feed_div
;
485 uint32_t max_frac_feed_div
= max_fractional_feed_div
+ 1;
486 uint32_t frac_feedback_div
;
489 feedback_div
= (min_feed_div
+ max_feed_div
) / 2;
491 tmp
= (uint64_t)pll
->reference_freq
* feedback_div
;
492 vco
= radeon_div(tmp
, ref_div
);
494 if (vco
< pll
->pll_out_min
) {
495 min_feed_div
= feedback_div
+ 1;
497 } else if (vco
> pll
->pll_out_max
) {
498 max_feed_div
= feedback_div
;
502 while (min_frac_feed_div
< max_frac_feed_div
) {
503 frac_feedback_div
= (min_frac_feed_div
+ max_frac_feed_div
) / 2;
504 tmp
= (uint64_t)pll
->reference_freq
* 10000 * feedback_div
;
505 tmp
+= (uint64_t)pll
->reference_freq
* 1000 * frac_feedback_div
;
506 current_freq
= radeon_div(tmp
, ref_div
* post_div
);
508 if (pll
->flags
& RADEON_PLL_PREFER_CLOSEST_LOWER
) {
509 error
= freq
- current_freq
;
510 error
= error
< 0 ? 0xffffffff : error
;
512 error
= abs(current_freq
- freq
);
513 vco_diff
= abs(vco
- best_vco
);
515 if ((best_vco
== 0 && error
< best_error
) ||
517 (error
< best_error
- 100 ||
518 (abs(error
- best_error
) < 100 && vco_diff
< best_vco_diff
)))) {
519 best_post_div
= post_div
;
520 best_ref_div
= ref_div
;
521 best_feedback_div
= feedback_div
;
522 best_frac_feedback_div
= frac_feedback_div
;
523 best_freq
= current_freq
;
525 best_vco_diff
= vco_diff
;
526 } else if (current_freq
== freq
) {
527 if (best_freq
== -1) {
528 best_post_div
= post_div
;
529 best_ref_div
= ref_div
;
530 best_feedback_div
= feedback_div
;
531 best_frac_feedback_div
= frac_feedback_div
;
532 best_freq
= current_freq
;
534 best_vco_diff
= vco_diff
;
535 } else if (((pll
->flags
& RADEON_PLL_PREFER_LOW_REF_DIV
) && (ref_div
< best_ref_div
)) ||
536 ((pll
->flags
& RADEON_PLL_PREFER_HIGH_REF_DIV
) && (ref_div
> best_ref_div
)) ||
537 ((pll
->flags
& RADEON_PLL_PREFER_LOW_FB_DIV
) && (feedback_div
< best_feedback_div
)) ||
538 ((pll
->flags
& RADEON_PLL_PREFER_HIGH_FB_DIV
) && (feedback_div
> best_feedback_div
)) ||
539 ((pll
->flags
& RADEON_PLL_PREFER_LOW_POST_DIV
) && (post_div
< best_post_div
)) ||
540 ((pll
->flags
& RADEON_PLL_PREFER_HIGH_POST_DIV
) && (post_div
> best_post_div
))) {
541 best_post_div
= post_div
;
542 best_ref_div
= ref_div
;
543 best_feedback_div
= feedback_div
;
544 best_frac_feedback_div
= frac_feedback_div
;
545 best_freq
= current_freq
;
547 best_vco_diff
= vco_diff
;
550 if (current_freq
< freq
)
551 min_frac_feed_div
= frac_feedback_div
+ 1;
553 max_frac_feed_div
= frac_feedback_div
;
555 if (current_freq
< freq
)
556 min_feed_div
= feedback_div
+ 1;
558 max_feed_div
= feedback_div
;
563 *dot_clock_p
= best_freq
/ 10000;
564 *fb_div_p
= best_feedback_div
;
565 *frac_fb_div_p
= best_frac_feedback_div
;
566 *ref_div_p
= best_ref_div
;
567 *post_div_p
= best_post_div
;
570 void radeon_compute_pll_avivo(struct radeon_pll
*pll
,
572 uint32_t *dot_clock_p
,
574 uint32_t *frac_fb_div_p
,
576 uint32_t *post_div_p
)
578 fixed20_12 m
, n
, frac_n
, p
, f_vco
, f_pclk
, best_freq
;
579 fixed20_12 pll_out_max
, pll_out_min
;
580 fixed20_12 pll_in_max
, pll_in_min
;
581 fixed20_12 reference_freq
;
582 fixed20_12 error
, ffreq
, a
, b
;
584 pll_out_max
.full
= rfixed_const(pll
->pll_out_max
);
585 pll_out_min
.full
= rfixed_const(pll
->pll_out_min
);
586 pll_in_max
.full
= rfixed_const(pll
->pll_in_max
);
587 pll_in_min
.full
= rfixed_const(pll
->pll_in_min
);
588 reference_freq
.full
= rfixed_const(pll
->reference_freq
);
590 ffreq
.full
= rfixed_const(freq
);
591 error
.full
= rfixed_const(100 * 100);
594 p
.full
= rfixed_div(pll_out_max
, ffreq
);
595 p
.full
= rfixed_floor(p
);
598 m
.full
= rfixed_div(reference_freq
, pll_in_max
);
599 m
.full
= rfixed_ceil(m
);
602 n
.full
= rfixed_div(ffreq
, reference_freq
);
603 n
.full
= rfixed_mul(n
, m
);
604 n
.full
= rfixed_mul(n
, p
);
606 f_vco
.full
= rfixed_div(n
, m
);
607 f_vco
.full
= rfixed_mul(f_vco
, reference_freq
);
609 f_pclk
.full
= rfixed_div(f_vco
, p
);
611 if (f_pclk
.full
> ffreq
.full
)
612 error
.full
= f_pclk
.full
- ffreq
.full
;
614 error
.full
= ffreq
.full
- f_pclk
.full
;
615 error
.full
= rfixed_div(error
, f_pclk
);
616 a
.full
= rfixed_const(100 * 100);
617 error
.full
= rfixed_mul(error
, a
);
619 a
.full
= rfixed_mul(m
, p
);
620 a
.full
= rfixed_div(n
, a
);
621 best_freq
.full
= rfixed_mul(reference_freq
, a
);
623 if (rfixed_trunc(error
) < 25)
626 a
.full
= rfixed_const(1);
627 m
.full
= m
.full
+ a
.full
;
628 a
.full
= rfixed_div(reference_freq
, m
);
629 if (a
.full
>= pll_in_min
.full
)
632 m
.full
= rfixed_div(reference_freq
, pll_in_max
);
633 m
.full
= rfixed_ceil(m
);
634 a
.full
= rfixed_const(1);
635 p
.full
= p
.full
- a
.full
;
636 a
.full
= rfixed_mul(p
, ffreq
);
637 if (a
.full
>= pll_out_min
.full
)
640 DRM_ERROR("Unable to find pll dividers\n");
645 a
.full
= rfixed_const(10);
646 b
.full
= rfixed_mul(n
, a
);
648 frac_n
.full
= rfixed_floor(n
);
649 frac_n
.full
= rfixed_mul(frac_n
, a
);
650 frac_n
.full
= b
.full
- frac_n
.full
;
652 *dot_clock_p
= rfixed_trunc(best_freq
);
653 *fb_div_p
= rfixed_trunc(n
);
654 *frac_fb_div_p
= rfixed_trunc(frac_n
);
655 *ref_div_p
= rfixed_trunc(m
);
656 *post_div_p
= rfixed_trunc(p
);
658 DRM_DEBUG("%u %d.%d, %d, %d\n", *dot_clock_p
* 10, *fb_div_p
, *frac_fb_div_p
, *ref_div_p
, *post_div_p
);
661 static void radeon_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
663 struct radeon_framebuffer
*radeon_fb
= to_radeon_framebuffer(fb
);
664 struct drm_device
*dev
= fb
->dev
;
667 radeonfb_remove(dev
, fb
);
669 if (radeon_fb
->obj
) {
670 mutex_lock(&dev
->struct_mutex
);
671 drm_gem_object_unreference(radeon_fb
->obj
);
672 mutex_unlock(&dev
->struct_mutex
);
674 drm_framebuffer_cleanup(fb
);
678 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
679 struct drm_file
*file_priv
,
680 unsigned int *handle
)
682 struct radeon_framebuffer
*radeon_fb
= to_radeon_framebuffer(fb
);
684 return drm_gem_handle_create(file_priv
, radeon_fb
->obj
, handle
);
687 static const struct drm_framebuffer_funcs radeon_fb_funcs
= {
688 .destroy
= radeon_user_framebuffer_destroy
,
689 .create_handle
= radeon_user_framebuffer_create_handle
,
692 struct drm_framebuffer
*
693 radeon_framebuffer_create(struct drm_device
*dev
,
694 struct drm_mode_fb_cmd
*mode_cmd
,
695 struct drm_gem_object
*obj
)
697 struct radeon_framebuffer
*radeon_fb
;
699 radeon_fb
= kzalloc(sizeof(*radeon_fb
), GFP_KERNEL
);
700 if (radeon_fb
== NULL
) {
703 drm_framebuffer_init(dev
, &radeon_fb
->base
, &radeon_fb_funcs
);
704 drm_helper_mode_fill_fb_struct(&radeon_fb
->base
, mode_cmd
);
705 radeon_fb
->obj
= obj
;
706 return &radeon_fb
->base
;
709 static struct drm_framebuffer
*
710 radeon_user_framebuffer_create(struct drm_device
*dev
,
711 struct drm_file
*file_priv
,
712 struct drm_mode_fb_cmd
*mode_cmd
)
714 struct drm_gem_object
*obj
;
716 obj
= drm_gem_object_lookup(dev
, file_priv
, mode_cmd
->handle
);
718 dev_err(&dev
->pdev
->dev
, "No GEM object associated to handle 0x%08X, "
719 "can't create framebuffer\n", mode_cmd
->handle
);
722 return radeon_framebuffer_create(dev
, mode_cmd
, obj
);
725 static const struct drm_mode_config_funcs radeon_mode_funcs
= {
726 .fb_create
= radeon_user_framebuffer_create
,
727 .fb_changed
= radeonfb_probe
,
730 struct drm_prop_enum_list
{
735 static struct drm_prop_enum_list radeon_tmds_pll_enum_list
[] =
740 static struct drm_prop_enum_list radeon_tv_std_enum_list
[] =
741 { { TV_STD_NTSC
, "ntsc" },
742 { TV_STD_PAL
, "pal" },
743 { TV_STD_PAL_M
, "pal-m" },
744 { TV_STD_PAL_60
, "pal-60" },
745 { TV_STD_NTSC_J
, "ntsc-j" },
746 { TV_STD_SCART_PAL
, "scart-pal" },
747 { TV_STD_PAL_CN
, "pal-cn" },
748 { TV_STD_SECAM
, "secam" },
751 static int radeon_modeset_create_props(struct radeon_device
*rdev
)
755 if (rdev
->is_atom_bios
) {
756 rdev
->mode_info
.coherent_mode_property
=
757 drm_property_create(rdev
->ddev
,
760 if (!rdev
->mode_info
.coherent_mode_property
)
763 rdev
->mode_info
.coherent_mode_property
->values
[0] = 0;
764 rdev
->mode_info
.coherent_mode_property
->values
[1] = 1;
767 if (!ASIC_IS_AVIVO(rdev
)) {
768 sz
= ARRAY_SIZE(radeon_tmds_pll_enum_list
);
769 rdev
->mode_info
.tmds_pll_property
=
770 drm_property_create(rdev
->ddev
,
773 for (i
= 0; i
< sz
; i
++) {
774 drm_property_add_enum(rdev
->mode_info
.tmds_pll_property
,
776 radeon_tmds_pll_enum_list
[i
].type
,
777 radeon_tmds_pll_enum_list
[i
].name
);
781 rdev
->mode_info
.load_detect_property
=
782 drm_property_create(rdev
->ddev
,
784 "load detection", 2);
785 if (!rdev
->mode_info
.load_detect_property
)
787 rdev
->mode_info
.load_detect_property
->values
[0] = 0;
788 rdev
->mode_info
.load_detect_property
->values
[1] = 1;
790 drm_mode_create_scaling_mode_property(rdev
->ddev
);
792 sz
= ARRAY_SIZE(radeon_tv_std_enum_list
);
793 rdev
->mode_info
.tv_std_property
=
794 drm_property_create(rdev
->ddev
,
797 for (i
= 0; i
< sz
; i
++) {
798 drm_property_add_enum(rdev
->mode_info
.tv_std_property
,
800 radeon_tv_std_enum_list
[i
].type
,
801 radeon_tv_std_enum_list
[i
].name
);
807 int radeon_modeset_init(struct radeon_device
*rdev
)
812 drm_mode_config_init(rdev
->ddev
);
813 rdev
->mode_info
.mode_config_initialized
= true;
815 rdev
->ddev
->mode_config
.funcs
= (void *)&radeon_mode_funcs
;
817 if (ASIC_IS_AVIVO(rdev
)) {
818 rdev
->ddev
->mode_config
.max_width
= 8192;
819 rdev
->ddev
->mode_config
.max_height
= 8192;
821 rdev
->ddev
->mode_config
.max_width
= 4096;
822 rdev
->ddev
->mode_config
.max_height
= 4096;
825 rdev
->ddev
->mode_config
.fb_base
= rdev
->mc
.aper_base
;
827 ret
= radeon_modeset_create_props(rdev
);
832 if (rdev
->flags
& RADEON_SINGLE_CRTC
)
836 for (i
= 0; i
< num_crtc
; i
++) {
837 radeon_crtc_init(rdev
->ddev
, i
);
840 /* okay we should have all the bios connectors */
841 ret
= radeon_setup_enc_conn(rdev
->ddev
);
846 radeon_hpd_init(rdev
);
847 drm_helper_initial_config(rdev
->ddev
);
851 void radeon_modeset_fini(struct radeon_device
*rdev
)
853 if (rdev
->mode_info
.mode_config_initialized
) {
854 radeon_hpd_fini(rdev
);
855 drm_mode_config_cleanup(rdev
->ddev
);
856 rdev
->mode_info
.mode_config_initialized
= false;
860 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc
*crtc
,
861 struct drm_display_mode
*mode
,
862 struct drm_display_mode
*adjusted_mode
)
864 struct drm_device
*dev
= crtc
->dev
;
865 struct drm_encoder
*encoder
;
866 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
867 struct radeon_encoder
*radeon_encoder
;
870 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
871 radeon_encoder
= to_radeon_encoder(encoder
);
872 if (encoder
->crtc
!= crtc
)
876 if (radeon_encoder
->rmx_type
== RMX_OFF
)
877 radeon_crtc
->rmx_type
= RMX_OFF
;
878 else if (mode
->hdisplay
< radeon_encoder
->native_mode
.hdisplay
||
879 mode
->vdisplay
< radeon_encoder
->native_mode
.vdisplay
)
880 radeon_crtc
->rmx_type
= radeon_encoder
->rmx_type
;
882 radeon_crtc
->rmx_type
= RMX_OFF
;
883 /* copy native mode */
884 memcpy(&radeon_crtc
->native_mode
,
885 &radeon_encoder
->native_mode
,
886 sizeof(struct drm_display_mode
));
889 if (radeon_crtc
->rmx_type
!= radeon_encoder
->rmx_type
) {
890 /* WARNING: Right now this can't happen but
891 * in the future we need to check that scaling
892 * are consistent accross different encoder
893 * (ie all encoder can work with the same
896 DRM_ERROR("Scaling not consistent accross encoder.\n");
901 if (radeon_crtc
->rmx_type
!= RMX_OFF
) {
903 a
.full
= rfixed_const(crtc
->mode
.vdisplay
);
904 b
.full
= rfixed_const(radeon_crtc
->native_mode
.hdisplay
);
905 radeon_crtc
->vsc
.full
= rfixed_div(a
, b
);
906 a
.full
= rfixed_const(crtc
->mode
.hdisplay
);
907 b
.full
= rfixed_const(radeon_crtc
->native_mode
.vdisplay
);
908 radeon_crtc
->hsc
.full
= rfixed_div(a
, b
);
910 radeon_crtc
->vsc
.full
= rfixed_const(1);
911 radeon_crtc
->hsc
.full
= rfixed_const(1);