2 * sata_promise.c - Promise SATA
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Mikael Pettersson <mikpe@it.uu.se>
6 * Please ALWAYS copy linux-ide@vger.kernel.org
9 * Copyright 2003-2004 Red Hat, Inc.
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
30 * Hardware information only available under NDA.
34 #include <linux/kernel.h>
35 #include <linux/module.h>
36 #include <linux/pci.h>
37 #include <linux/init.h>
38 #include <linux/blkdev.h>
39 #include <linux/delay.h>
40 #include <linux/interrupt.h>
41 #include <linux/device.h>
42 #include <scsi/scsi.h>
43 #include <scsi/scsi_host.h>
44 #include <scsi/scsi_cmnd.h>
45 #include <linux/libata.h>
46 #include "sata_promise.h"
48 #define DRV_NAME "sata_promise"
49 #define DRV_VERSION "2.12"
54 PDC_MAX_PRD
= LIBATA_MAX_PRD
- 1, /* -1 for ASIC PRD bug workaround */
56 /* register offsets */
57 PDC_FEATURE
= 0x04, /* Feature/Error reg (per port) */
58 PDC_SECTOR_COUNT
= 0x08, /* Sector count reg (per port) */
59 PDC_SECTOR_NUMBER
= 0x0C, /* Sector number reg (per port) */
60 PDC_CYLINDER_LOW
= 0x10, /* Cylinder low reg (per port) */
61 PDC_CYLINDER_HIGH
= 0x14, /* Cylinder high reg (per port) */
62 PDC_DEVICE
= 0x18, /* Device/Head reg (per port) */
63 PDC_COMMAND
= 0x1C, /* Command/status reg (per port) */
64 PDC_ALTSTATUS
= 0x38, /* Alternate-status/device-control reg (per port) */
65 PDC_PKT_SUBMIT
= 0x40, /* Command packet pointer addr */
66 PDC_INT_SEQMASK
= 0x40, /* Mask of asserted SEQ INTs */
67 PDC_FLASH_CTL
= 0x44, /* Flash control register */
68 PDC_GLOBAL_CTL
= 0x48, /* Global control/status (per port) */
69 PDC_CTLSTAT
= 0x60, /* IDE control and status (per port) */
70 PDC_SATA_PLUG_CSR
= 0x6C, /* SATA Plug control/status reg */
71 PDC2_SATA_PLUG_CSR
= 0x60, /* SATAII Plug control/status reg */
72 PDC_TBG_MODE
= 0x41C, /* TBG mode (not SATAII) */
73 PDC_SLEW_CTL
= 0x470, /* slew rate control reg (not SATAII) */
75 /* PDC_GLOBAL_CTL bit definitions */
76 PDC_PH_ERR
= (1 << 8), /* PCI error while loading packet */
77 PDC_SH_ERR
= (1 << 9), /* PCI error while loading S/G table */
78 PDC_DH_ERR
= (1 << 10), /* PCI error while loading data */
79 PDC2_HTO_ERR
= (1 << 12), /* host bus timeout */
80 PDC2_ATA_HBA_ERR
= (1 << 13), /* error during SATA DATA FIS transmission */
81 PDC2_ATA_DMA_CNT_ERR
= (1 << 14), /* DMA DATA FIS size differs from S/G count */
82 PDC_OVERRUN_ERR
= (1 << 19), /* S/G byte count larger than HD requires */
83 PDC_UNDERRUN_ERR
= (1 << 20), /* S/G byte count less than HD requires */
84 PDC_DRIVE_ERR
= (1 << 21), /* drive error */
85 PDC_PCI_SYS_ERR
= (1 << 22), /* PCI system error */
86 PDC1_PCI_PARITY_ERR
= (1 << 23), /* PCI parity error (from SATA150 driver) */
87 PDC1_ERR_MASK
= PDC1_PCI_PARITY_ERR
,
88 PDC2_ERR_MASK
= PDC2_HTO_ERR
| PDC2_ATA_HBA_ERR
|
90 PDC_ERR_MASK
= PDC_PH_ERR
| PDC_SH_ERR
| PDC_DH_ERR
|
91 PDC_OVERRUN_ERR
| PDC_UNDERRUN_ERR
|
92 PDC_DRIVE_ERR
| PDC_PCI_SYS_ERR
|
93 PDC1_ERR_MASK
| PDC2_ERR_MASK
,
95 board_2037x
= 0, /* FastTrak S150 TX2plus */
96 board_2037x_pata
= 1, /* FastTrak S150 TX2plus PATA port */
97 board_20319
= 2, /* FastTrak S150 TX4 */
98 board_20619
= 3, /* FastTrak TX4000 */
99 board_2057x
= 4, /* SATAII150 Tx2plus */
100 board_2057x_pata
= 5, /* SATAII150 Tx2plus PATA port */
101 board_40518
= 6, /* SATAII150 Tx4 */
103 PDC_HAS_PATA
= (1 << 1), /* PDC20375/20575 has PATA */
105 /* Sequence counter control registers bit definitions */
106 PDC_SEQCNTRL_INT_MASK
= (1 << 5), /* Sequence Interrupt Mask */
108 /* Feature register values */
109 PDC_FEATURE_ATAPI_PIO
= 0x00, /* ATAPI data xfer by PIO */
110 PDC_FEATURE_ATAPI_DMA
= 0x01, /* ATAPI data xfer by DMA */
112 /* Device/Head register values */
113 PDC_DEVICE_SATA
= 0xE0, /* Device/Head value for SATA devices */
115 /* PDC_CTLSTAT bit definitions */
116 PDC_DMA_ENABLE
= (1 << 7),
117 PDC_IRQ_DISABLE
= (1 << 10),
118 PDC_RESET
= (1 << 11), /* HDMA reset */
120 PDC_COMMON_FLAGS
= ATA_FLAG_NO_LEGACY
|
122 ATA_FLAG_PIO_POLLING
,
125 PDC_FLAG_GEN_II
= (1 << 24),
126 PDC_FLAG_SATA_PATA
= (1 << 25), /* supports SATA + PATA */
127 PDC_FLAG_4_PORTS
= (1 << 26), /* 4 ports */
130 struct pdc_port_priv
{
135 static int pdc_sata_scr_read(struct ata_port
*ap
, unsigned int sc_reg
, u32
*val
);
136 static int pdc_sata_scr_write(struct ata_port
*ap
, unsigned int sc_reg
, u32 val
);
137 static int pdc_ata_init_one (struct pci_dev
*pdev
, const struct pci_device_id
*ent
);
138 static int pdc_common_port_start(struct ata_port
*ap
);
139 static int pdc_sata_port_start(struct ata_port
*ap
);
140 static void pdc_qc_prep(struct ata_queued_cmd
*qc
);
141 static void pdc_tf_load_mmio(struct ata_port
*ap
, const struct ata_taskfile
*tf
);
142 static void pdc_exec_command_mmio(struct ata_port
*ap
, const struct ata_taskfile
*tf
);
143 static int pdc_check_atapi_dma(struct ata_queued_cmd
*qc
);
144 static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd
*qc
);
145 static void pdc_irq_clear(struct ata_port
*ap
);
146 static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd
*qc
);
147 static void pdc_freeze(struct ata_port
*ap
);
148 static void pdc_sata_freeze(struct ata_port
*ap
);
149 static void pdc_thaw(struct ata_port
*ap
);
150 static void pdc_sata_thaw(struct ata_port
*ap
);
151 static void pdc_pata_error_handler(struct ata_port
*ap
);
152 static void pdc_sata_error_handler(struct ata_port
*ap
);
153 static void pdc_post_internal_cmd(struct ata_queued_cmd
*qc
);
154 static int pdc_pata_cable_detect(struct ata_port
*ap
);
155 static int pdc_sata_cable_detect(struct ata_port
*ap
);
157 static struct scsi_host_template pdc_ata_sht
= {
158 .module
= THIS_MODULE
,
160 .ioctl
= ata_scsi_ioctl
,
161 .queuecommand
= ata_scsi_queuecmd
,
162 .can_queue
= ATA_DEF_QUEUE
,
163 .this_id
= ATA_SHT_THIS_ID
,
164 .sg_tablesize
= PDC_MAX_PRD
,
165 .cmd_per_lun
= ATA_SHT_CMD_PER_LUN
,
166 .emulated
= ATA_SHT_EMULATED
,
167 .use_clustering
= ATA_SHT_USE_CLUSTERING
,
168 .proc_name
= DRV_NAME
,
169 .dma_boundary
= ATA_DMA_BOUNDARY
,
170 .slave_configure
= ata_scsi_slave_config
,
171 .slave_destroy
= ata_scsi_slave_destroy
,
172 .bios_param
= ata_std_bios_param
,
175 static const struct ata_port_operations pdc_sata_ops
= {
176 .tf_load
= pdc_tf_load_mmio
,
177 .tf_read
= ata_tf_read
,
178 .check_status
= ata_check_status
,
179 .exec_command
= pdc_exec_command_mmio
,
180 .dev_select
= ata_std_dev_select
,
181 .check_atapi_dma
= pdc_check_atapi_dma
,
183 .qc_prep
= pdc_qc_prep
,
184 .qc_issue
= pdc_qc_issue_prot
,
185 .freeze
= pdc_sata_freeze
,
186 .thaw
= pdc_sata_thaw
,
187 .error_handler
= pdc_sata_error_handler
,
188 .post_internal_cmd
= pdc_post_internal_cmd
,
189 .cable_detect
= pdc_sata_cable_detect
,
190 .data_xfer
= ata_data_xfer
,
191 .irq_clear
= pdc_irq_clear
,
192 .irq_on
= ata_irq_on
,
194 .scr_read
= pdc_sata_scr_read
,
195 .scr_write
= pdc_sata_scr_write
,
196 .port_start
= pdc_sata_port_start
,
199 /* First-generation chips need a more restrictive ->check_atapi_dma op */
200 static const struct ata_port_operations pdc_old_sata_ops
= {
201 .tf_load
= pdc_tf_load_mmio
,
202 .tf_read
= ata_tf_read
,
203 .check_status
= ata_check_status
,
204 .exec_command
= pdc_exec_command_mmio
,
205 .dev_select
= ata_std_dev_select
,
206 .check_atapi_dma
= pdc_old_sata_check_atapi_dma
,
208 .qc_prep
= pdc_qc_prep
,
209 .qc_issue
= pdc_qc_issue_prot
,
210 .freeze
= pdc_sata_freeze
,
211 .thaw
= pdc_sata_thaw
,
212 .error_handler
= pdc_sata_error_handler
,
213 .post_internal_cmd
= pdc_post_internal_cmd
,
214 .cable_detect
= pdc_sata_cable_detect
,
215 .data_xfer
= ata_data_xfer
,
216 .irq_clear
= pdc_irq_clear
,
217 .irq_on
= ata_irq_on
,
219 .scr_read
= pdc_sata_scr_read
,
220 .scr_write
= pdc_sata_scr_write
,
221 .port_start
= pdc_sata_port_start
,
224 static const struct ata_port_operations pdc_pata_ops
= {
225 .tf_load
= pdc_tf_load_mmio
,
226 .tf_read
= ata_tf_read
,
227 .check_status
= ata_check_status
,
228 .exec_command
= pdc_exec_command_mmio
,
229 .dev_select
= ata_std_dev_select
,
230 .check_atapi_dma
= pdc_check_atapi_dma
,
232 .qc_prep
= pdc_qc_prep
,
233 .qc_issue
= pdc_qc_issue_prot
,
234 .freeze
= pdc_freeze
,
236 .error_handler
= pdc_pata_error_handler
,
237 .post_internal_cmd
= pdc_post_internal_cmd
,
238 .cable_detect
= pdc_pata_cable_detect
,
239 .data_xfer
= ata_data_xfer
,
240 .irq_clear
= pdc_irq_clear
,
241 .irq_on
= ata_irq_on
,
243 .port_start
= pdc_common_port_start
,
246 static const struct ata_port_info pdc_port_info
[] = {
249 .flags
= PDC_COMMON_FLAGS
| ATA_FLAG_SATA
|
251 .pio_mask
= 0x1f, /* pio0-4 */
252 .mwdma_mask
= 0x07, /* mwdma0-2 */
253 .udma_mask
= ATA_UDMA6
,
254 .port_ops
= &pdc_old_sata_ops
,
259 .flags
= PDC_COMMON_FLAGS
| ATA_FLAG_SLAVE_POSS
,
260 .pio_mask
= 0x1f, /* pio0-4 */
261 .mwdma_mask
= 0x07, /* mwdma0-2 */
262 .udma_mask
= ATA_UDMA6
,
263 .port_ops
= &pdc_pata_ops
,
268 .flags
= PDC_COMMON_FLAGS
| ATA_FLAG_SATA
|
270 .pio_mask
= 0x1f, /* pio0-4 */
271 .mwdma_mask
= 0x07, /* mwdma0-2 */
272 .udma_mask
= ATA_UDMA6
,
273 .port_ops
= &pdc_old_sata_ops
,
278 .flags
= PDC_COMMON_FLAGS
| ATA_FLAG_SLAVE_POSS
|
280 .pio_mask
= 0x1f, /* pio0-4 */
281 .mwdma_mask
= 0x07, /* mwdma0-2 */
282 .udma_mask
= ATA_UDMA6
,
283 .port_ops
= &pdc_pata_ops
,
288 .flags
= PDC_COMMON_FLAGS
| ATA_FLAG_SATA
|
289 PDC_FLAG_GEN_II
| PDC_FLAG_SATA_PATA
,
290 .pio_mask
= 0x1f, /* pio0-4 */
291 .mwdma_mask
= 0x07, /* mwdma0-2 */
292 .udma_mask
= ATA_UDMA6
,
293 .port_ops
= &pdc_sata_ops
,
298 .flags
= PDC_COMMON_FLAGS
| ATA_FLAG_SLAVE_POSS
|
300 .pio_mask
= 0x1f, /* pio0-4 */
301 .mwdma_mask
= 0x07, /* mwdma0-2 */
302 .udma_mask
= ATA_UDMA6
,
303 .port_ops
= &pdc_pata_ops
,
308 .flags
= PDC_COMMON_FLAGS
| ATA_FLAG_SATA
|
309 PDC_FLAG_GEN_II
| PDC_FLAG_4_PORTS
,
310 .pio_mask
= 0x1f, /* pio0-4 */
311 .mwdma_mask
= 0x07, /* mwdma0-2 */
312 .udma_mask
= ATA_UDMA6
,
313 .port_ops
= &pdc_sata_ops
,
317 static const struct pci_device_id pdc_ata_pci_tbl
[] = {
318 { PCI_VDEVICE(PROMISE
, 0x3371), board_2037x
},
319 { PCI_VDEVICE(PROMISE
, 0x3373), board_2037x
},
320 { PCI_VDEVICE(PROMISE
, 0x3375), board_2037x
},
321 { PCI_VDEVICE(PROMISE
, 0x3376), board_2037x
},
322 { PCI_VDEVICE(PROMISE
, 0x3570), board_2057x
},
323 { PCI_VDEVICE(PROMISE
, 0x3571), board_2057x
},
324 { PCI_VDEVICE(PROMISE
, 0x3574), board_2057x
},
325 { PCI_VDEVICE(PROMISE
, 0x3577), board_2057x
},
326 { PCI_VDEVICE(PROMISE
, 0x3d73), board_2057x
},
327 { PCI_VDEVICE(PROMISE
, 0x3d75), board_2057x
},
329 { PCI_VDEVICE(PROMISE
, 0x3318), board_20319
},
330 { PCI_VDEVICE(PROMISE
, 0x3319), board_20319
},
331 { PCI_VDEVICE(PROMISE
, 0x3515), board_40518
},
332 { PCI_VDEVICE(PROMISE
, 0x3519), board_40518
},
333 { PCI_VDEVICE(PROMISE
, 0x3d17), board_40518
},
334 { PCI_VDEVICE(PROMISE
, 0x3d18), board_40518
},
336 { PCI_VDEVICE(PROMISE
, 0x6629), board_20619
},
338 { } /* terminate list */
341 static struct pci_driver pdc_ata_pci_driver
= {
343 .id_table
= pdc_ata_pci_tbl
,
344 .probe
= pdc_ata_init_one
,
345 .remove
= ata_pci_remove_one
,
348 static int pdc_common_port_start(struct ata_port
*ap
)
350 struct device
*dev
= ap
->host
->dev
;
351 struct pdc_port_priv
*pp
;
354 rc
= ata_port_start(ap
);
358 pp
= devm_kzalloc(dev
, sizeof(*pp
), GFP_KERNEL
);
362 pp
->pkt
= dmam_alloc_coherent(dev
, 128, &pp
->pkt_dma
, GFP_KERNEL
);
366 ap
->private_data
= pp
;
371 static int pdc_sata_port_start(struct ata_port
*ap
)
375 rc
= pdc_common_port_start(ap
);
379 /* fix up PHYMODE4 align timing */
380 if (ap
->flags
& PDC_FLAG_GEN_II
) {
381 void __iomem
*mmio
= ap
->ioaddr
.scr_addr
;
384 tmp
= readl(mmio
+ 0x014);
385 tmp
= (tmp
& ~3) | 1; /* set bits 1:0 = 0:1 */
386 writel(tmp
, mmio
+ 0x014);
392 static void pdc_reset_port(struct ata_port
*ap
)
394 void __iomem
*mmio
= ap
->ioaddr
.cmd_addr
+ PDC_CTLSTAT
;
398 for (i
= 11; i
> 0; i
--) {
411 readl(mmio
); /* flush */
414 static int pdc_pata_cable_detect(struct ata_port
*ap
)
417 void __iomem
*mmio
= ap
->ioaddr
.cmd_addr
+ PDC_CTLSTAT
+ 0x03;
421 return ATA_CBL_PATA40
;
422 return ATA_CBL_PATA80
;
425 static int pdc_sata_cable_detect(struct ata_port
*ap
)
430 static int pdc_sata_scr_read(struct ata_port
*ap
, unsigned int sc_reg
, u32
*val
)
432 if (sc_reg
> SCR_CONTROL
)
434 *val
= readl(ap
->ioaddr
.scr_addr
+ (sc_reg
* 4));
438 static int pdc_sata_scr_write(struct ata_port
*ap
, unsigned int sc_reg
, u32 val
)
440 if (sc_reg
> SCR_CONTROL
)
442 writel(val
, ap
->ioaddr
.scr_addr
+ (sc_reg
* 4));
446 static void pdc_atapi_pkt(struct ata_queued_cmd
*qc
)
448 struct ata_port
*ap
= qc
->ap
;
449 dma_addr_t sg_table
= ap
->prd_dma
;
450 unsigned int cdb_len
= qc
->dev
->cdb_len
;
452 struct pdc_port_priv
*pp
= ap
->private_data
;
454 u32
*buf32
= (u32
*) buf
;
455 unsigned int dev_sel
, feature
;
457 /* set control bits (byte 0), zero delay seq id (byte 3),
458 * and seq id (byte 2)
460 switch (qc
->tf
.protocol
) {
462 if (!(qc
->tf
.flags
& ATA_TFLAG_WRITE
))
463 buf32
[0] = cpu_to_le32(PDC_PKT_READ
);
467 case ATAPI_PROT_NODATA
:
468 buf32
[0] = cpu_to_le32(PDC_PKT_NODATA
);
474 buf32
[1] = cpu_to_le32(sg_table
); /* S/G table addr */
475 buf32
[2] = 0; /* no next-packet */
478 if (sata_scr_valid(&ap
->link
))
479 dev_sel
= PDC_DEVICE_SATA
;
481 dev_sel
= qc
->tf
.device
;
483 buf
[12] = (1 << 5) | ATA_REG_DEVICE
;
485 buf
[14] = (1 << 5) | ATA_REG_DEVICE
| PDC_PKT_CLEAR_BSY
;
486 buf
[15] = dev_sel
; /* once more, waiting for BSY to clear */
488 buf
[16] = (1 << 5) | ATA_REG_NSECT
;
489 buf
[17] = qc
->tf
.nsect
;
490 buf
[18] = (1 << 5) | ATA_REG_LBAL
;
491 buf
[19] = qc
->tf
.lbal
;
493 /* set feature and byte counter registers */
494 if (qc
->tf
.protocol
!= ATAPI_PROT_DMA
)
495 feature
= PDC_FEATURE_ATAPI_PIO
;
497 feature
= PDC_FEATURE_ATAPI_DMA
;
499 buf
[20] = (1 << 5) | ATA_REG_FEATURE
;
501 buf
[22] = (1 << 5) | ATA_REG_BYTEL
;
502 buf
[23] = qc
->tf
.lbam
;
503 buf
[24] = (1 << 5) | ATA_REG_BYTEH
;
504 buf
[25] = qc
->tf
.lbah
;
506 /* send ATAPI packet command 0xA0 */
507 buf
[26] = (1 << 5) | ATA_REG_CMD
;
508 buf
[27] = qc
->tf
.command
;
510 /* select drive and check DRQ */
511 buf
[28] = (1 << 5) | ATA_REG_DEVICE
| PDC_PKT_WAIT_DRDY
;
514 /* we can represent cdb lengths 2/4/6/8/10/12/14/16 */
515 BUG_ON(cdb_len
& ~0x1E);
517 /* append the CDB as the final part */
518 buf
[30] = (((cdb_len
>> 1) & 7) << 5) | ATA_REG_DATA
| PDC_LAST_REG
;
519 memcpy(buf
+31, cdb
, cdb_len
);
523 * pdc_fill_sg - Fill PCI IDE PRD table
524 * @qc: Metadata associated with taskfile to be transferred
526 * Fill PCI IDE PRD (scatter-gather) table with segments
527 * associated with the current disk command.
528 * Make sure hardware does not choke on it.
531 * spin_lock_irqsave(host lock)
534 static void pdc_fill_sg(struct ata_queued_cmd
*qc
)
536 struct ata_port
*ap
= qc
->ap
;
537 struct scatterlist
*sg
;
538 const u32 SG_COUNT_ASIC_BUG
= 41*4;
539 unsigned int si
, idx
;
542 if (!(qc
->flags
& ATA_QCFLAG_DMAMAP
))
546 for_each_sg(qc
->sg
, sg
, qc
->n_elem
, si
) {
550 /* determine if physical DMA addr spans 64K boundary.
551 * Note h/w doesn't support 64-bit, so we unconditionally
552 * truncate dma_addr_t to u32.
554 addr
= (u32
) sg_dma_address(sg
);
555 sg_len
= sg_dma_len(sg
);
558 offset
= addr
& 0xffff;
560 if ((offset
+ sg_len
) > 0x10000)
561 len
= 0x10000 - offset
;
563 ap
->prd
[idx
].addr
= cpu_to_le32(addr
);
564 ap
->prd
[idx
].flags_len
= cpu_to_le32(len
& 0xffff);
565 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx
, addr
, len
);
573 len
= le32_to_cpu(ap
->prd
[idx
- 1].flags_len
);
575 if (len
> SG_COUNT_ASIC_BUG
) {
578 VPRINTK("Splitting last PRD.\n");
580 addr
= le32_to_cpu(ap
->prd
[idx
- 1].addr
);
581 ap
->prd
[idx
- 1].flags_len
= cpu_to_le32(len
- SG_COUNT_ASIC_BUG
);
582 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx
- 1, addr
, SG_COUNT_ASIC_BUG
);
584 addr
= addr
+ len
- SG_COUNT_ASIC_BUG
;
585 len
= SG_COUNT_ASIC_BUG
;
586 ap
->prd
[idx
].addr
= cpu_to_le32(addr
);
587 ap
->prd
[idx
].flags_len
= cpu_to_le32(len
);
588 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx
, addr
, len
);
593 ap
->prd
[idx
- 1].flags_len
|= cpu_to_le32(ATA_PRD_EOT
);
596 static void pdc_qc_prep(struct ata_queued_cmd
*qc
)
598 struct pdc_port_priv
*pp
= qc
->ap
->private_data
;
603 switch (qc
->tf
.protocol
) {
608 case ATA_PROT_NODATA
:
609 i
= pdc_pkt_header(&qc
->tf
, qc
->ap
->prd_dma
,
610 qc
->dev
->devno
, pp
->pkt
);
612 if (qc
->tf
.flags
& ATA_TFLAG_LBA48
)
613 i
= pdc_prep_lba48(&qc
->tf
, pp
->pkt
, i
);
615 i
= pdc_prep_lba28(&qc
->tf
, pp
->pkt
, i
);
617 pdc_pkt_footer(&qc
->tf
, pp
->pkt
, i
);
627 case ATAPI_PROT_NODATA
:
636 static int pdc_is_sataii_tx4(unsigned long flags
)
638 const unsigned long mask
= PDC_FLAG_GEN_II
| PDC_FLAG_4_PORTS
;
639 return (flags
& mask
) == mask
;
642 static unsigned int pdc_port_no_to_ata_no(unsigned int port_no
,
645 static const unsigned char sataii_tx4_port_remap
[4] = { 3, 1, 0, 2};
646 return is_sataii_tx4
? sataii_tx4_port_remap
[port_no
] : port_no
;
649 static unsigned int pdc_sata_nr_ports(const struct ata_port
*ap
)
651 return (ap
->flags
& PDC_FLAG_4_PORTS
) ? 4 : 2;
654 static unsigned int pdc_sata_ata_port_to_ata_no(const struct ata_port
*ap
)
656 const struct ata_host
*host
= ap
->host
;
657 unsigned int nr_ports
= pdc_sata_nr_ports(ap
);
660 for(i
= 0; i
< nr_ports
&& host
->ports
[i
] != ap
; ++i
)
662 BUG_ON(i
>= nr_ports
);
663 return pdc_port_no_to_ata_no(i
, pdc_is_sataii_tx4(ap
->flags
));
666 static unsigned int pdc_sata_hotplug_offset(const struct ata_port
*ap
)
668 return (ap
->flags
& PDC_FLAG_GEN_II
) ? PDC2_SATA_PLUG_CSR
: PDC_SATA_PLUG_CSR
;
671 static void pdc_freeze(struct ata_port
*ap
)
673 void __iomem
*mmio
= ap
->ioaddr
.cmd_addr
;
676 tmp
= readl(mmio
+ PDC_CTLSTAT
);
677 tmp
|= PDC_IRQ_DISABLE
;
678 tmp
&= ~PDC_DMA_ENABLE
;
679 writel(tmp
, mmio
+ PDC_CTLSTAT
);
680 readl(mmio
+ PDC_CTLSTAT
); /* flush */
683 static void pdc_sata_freeze(struct ata_port
*ap
)
685 struct ata_host
*host
= ap
->host
;
686 void __iomem
*host_mmio
= host
->iomap
[PDC_MMIO_BAR
];
687 unsigned int hotplug_offset
= pdc_sata_hotplug_offset(ap
);
688 unsigned int ata_no
= pdc_sata_ata_port_to_ata_no(ap
);
691 /* Disable hotplug events on this port.
694 * 1) hotplug register accesses must be serialised via host->lock
695 * 2) ap->lock == &ap->host->lock
696 * 3) ->freeze() and ->thaw() are called with ap->lock held
698 hotplug_status
= readl(host_mmio
+ hotplug_offset
);
699 hotplug_status
|= 0x11 << (ata_no
+ 16);
700 writel(hotplug_status
, host_mmio
+ hotplug_offset
);
701 readl(host_mmio
+ hotplug_offset
); /* flush */
706 static void pdc_thaw(struct ata_port
*ap
)
708 void __iomem
*mmio
= ap
->ioaddr
.cmd_addr
;
712 readl(mmio
+ PDC_INT_SEQMASK
);
714 /* turn IRQ back on */
715 tmp
= readl(mmio
+ PDC_CTLSTAT
);
716 tmp
&= ~PDC_IRQ_DISABLE
;
717 writel(tmp
, mmio
+ PDC_CTLSTAT
);
718 readl(mmio
+ PDC_CTLSTAT
); /* flush */
721 static void pdc_sata_thaw(struct ata_port
*ap
)
723 struct ata_host
*host
= ap
->host
;
724 void __iomem
*host_mmio
= host
->iomap
[PDC_MMIO_BAR
];
725 unsigned int hotplug_offset
= pdc_sata_hotplug_offset(ap
);
726 unsigned int ata_no
= pdc_sata_ata_port_to_ata_no(ap
);
731 /* Enable hotplug events on this port.
732 * Locking: see pdc_sata_freeze().
734 hotplug_status
= readl(host_mmio
+ hotplug_offset
);
735 hotplug_status
|= 0x11 << ata_no
;
736 hotplug_status
&= ~(0x11 << (ata_no
+ 16));
737 writel(hotplug_status
, host_mmio
+ hotplug_offset
);
738 readl(host_mmio
+ hotplug_offset
); /* flush */
741 static void pdc_common_error_handler(struct ata_port
*ap
, ata_reset_fn_t hardreset
)
743 if (!(ap
->pflags
& ATA_PFLAG_FROZEN
))
746 /* perform recovery */
747 ata_do_eh(ap
, ata_std_prereset
, ata_std_softreset
, hardreset
,
751 static void pdc_pata_error_handler(struct ata_port
*ap
)
753 pdc_common_error_handler(ap
, NULL
);
756 static void pdc_sata_error_handler(struct ata_port
*ap
)
758 pdc_common_error_handler(ap
, sata_std_hardreset
);
761 static void pdc_post_internal_cmd(struct ata_queued_cmd
*qc
)
763 struct ata_port
*ap
= qc
->ap
;
765 /* make DMA engine forget about the failed command */
766 if (qc
->flags
& ATA_QCFLAG_FAILED
)
770 static void pdc_error_intr(struct ata_port
*ap
, struct ata_queued_cmd
*qc
,
771 u32 port_status
, u32 err_mask
)
773 struct ata_eh_info
*ehi
= &ap
->link
.eh_info
;
774 unsigned int ac_err_mask
= 0;
776 ata_ehi_clear_desc(ehi
);
777 ata_ehi_push_desc(ehi
, "port_status 0x%08x", port_status
);
778 port_status
&= err_mask
;
780 if (port_status
& PDC_DRIVE_ERR
)
781 ac_err_mask
|= AC_ERR_DEV
;
782 if (port_status
& (PDC_OVERRUN_ERR
| PDC_UNDERRUN_ERR
))
783 ac_err_mask
|= AC_ERR_HSM
;
784 if (port_status
& (PDC2_ATA_HBA_ERR
| PDC2_ATA_DMA_CNT_ERR
))
785 ac_err_mask
|= AC_ERR_ATA_BUS
;
786 if (port_status
& (PDC_PH_ERR
| PDC_SH_ERR
| PDC_DH_ERR
| PDC2_HTO_ERR
787 | PDC_PCI_SYS_ERR
| PDC1_PCI_PARITY_ERR
))
788 ac_err_mask
|= AC_ERR_HOST_BUS
;
790 if (sata_scr_valid(&ap
->link
)) {
793 pdc_sata_scr_read(ap
, SCR_ERROR
, &serror
);
794 ehi
->serror
|= serror
;
797 qc
->err_mask
|= ac_err_mask
;
804 static inline unsigned int pdc_host_intr(struct ata_port
*ap
,
805 struct ata_queued_cmd
*qc
)
807 unsigned int handled
= 0;
808 void __iomem
*port_mmio
= ap
->ioaddr
.cmd_addr
;
809 u32 port_status
, err_mask
;
811 err_mask
= PDC_ERR_MASK
;
812 if (ap
->flags
& PDC_FLAG_GEN_II
)
813 err_mask
&= ~PDC1_ERR_MASK
;
815 err_mask
&= ~PDC2_ERR_MASK
;
816 port_status
= readl(port_mmio
+ PDC_GLOBAL_CTL
);
817 if (unlikely(port_status
& err_mask
)) {
818 pdc_error_intr(ap
, qc
, port_status
, err_mask
);
822 switch (qc
->tf
.protocol
) {
824 case ATA_PROT_NODATA
:
826 case ATAPI_PROT_NODATA
:
827 qc
->err_mask
|= ac_err_mask(ata_wait_idle(ap
));
833 ap
->stats
.idle_irq
++;
840 static void pdc_irq_clear(struct ata_port
*ap
)
842 struct ata_host
*host
= ap
->host
;
843 void __iomem
*mmio
= host
->iomap
[PDC_MMIO_BAR
];
845 readl(mmio
+ PDC_INT_SEQMASK
);
848 static irqreturn_t
pdc_interrupt(int irq
, void *dev_instance
)
850 struct ata_host
*host
= dev_instance
;
854 unsigned int handled
= 0;
855 void __iomem
*mmio_base
;
856 unsigned int hotplug_offset
, ata_no
;
862 if (!host
|| !host
->iomap
[PDC_MMIO_BAR
]) {
863 VPRINTK("QUICK EXIT\n");
867 mmio_base
= host
->iomap
[PDC_MMIO_BAR
];
869 spin_lock(&host
->lock
);
871 /* read and clear hotplug flags for all ports */
872 if (host
->ports
[0]->flags
& PDC_FLAG_GEN_II
)
873 hotplug_offset
= PDC2_SATA_PLUG_CSR
;
875 hotplug_offset
= PDC_SATA_PLUG_CSR
;
876 hotplug_status
= readl(mmio_base
+ hotplug_offset
);
877 if (hotplug_status
& 0xff)
878 writel(hotplug_status
| 0xff, mmio_base
+ hotplug_offset
);
879 hotplug_status
&= 0xff; /* clear uninteresting bits */
881 /* reading should also clear interrupts */
882 mask
= readl(mmio_base
+ PDC_INT_SEQMASK
);
884 if (mask
== 0xffffffff && hotplug_status
== 0) {
885 VPRINTK("QUICK EXIT 2\n");
889 mask
&= 0xffff; /* only 16 tags possible */
890 if (mask
== 0 && hotplug_status
== 0) {
891 VPRINTK("QUICK EXIT 3\n");
895 writel(mask
, mmio_base
+ PDC_INT_SEQMASK
);
897 is_sataii_tx4
= pdc_is_sataii_tx4(host
->ports
[0]->flags
);
899 for (i
= 0; i
< host
->n_ports
; i
++) {
900 VPRINTK("port %u\n", i
);
903 /* check for a plug or unplug event */
904 ata_no
= pdc_port_no_to_ata_no(i
, is_sataii_tx4
);
905 tmp
= hotplug_status
& (0x11 << ata_no
);
907 !(ap
->flags
& ATA_FLAG_DISABLED
)) {
908 struct ata_eh_info
*ehi
= &ap
->link
.eh_info
;
909 ata_ehi_clear_desc(ehi
);
910 ata_ehi_hotplugged(ehi
);
911 ata_ehi_push_desc(ehi
, "hotplug_status %#x", tmp
);
917 /* check for a packet interrupt */
918 tmp
= mask
& (1 << (i
+ 1));
920 !(ap
->flags
& ATA_FLAG_DISABLED
)) {
921 struct ata_queued_cmd
*qc
;
923 qc
= ata_qc_from_tag(ap
, ap
->link
.active_tag
);
924 if (qc
&& (!(qc
->tf
.flags
& ATA_TFLAG_POLLING
)))
925 handled
+= pdc_host_intr(ap
, qc
);
932 spin_unlock(&host
->lock
);
933 return IRQ_RETVAL(handled
);
936 static inline void pdc_packet_start(struct ata_queued_cmd
*qc
)
938 struct ata_port
*ap
= qc
->ap
;
939 struct pdc_port_priv
*pp
= ap
->private_data
;
940 void __iomem
*mmio
= ap
->host
->iomap
[PDC_MMIO_BAR
];
941 unsigned int port_no
= ap
->port_no
;
942 u8 seq
= (u8
) (port_no
+ 1);
944 VPRINTK("ENTER, ap %p\n", ap
);
946 writel(0x00000001, mmio
+ (seq
* 4));
947 readl(mmio
+ (seq
* 4)); /* flush */
950 wmb(); /* flush PRD, pkt writes */
951 writel(pp
->pkt_dma
, ap
->ioaddr
.cmd_addr
+ PDC_PKT_SUBMIT
);
952 readl(ap
->ioaddr
.cmd_addr
+ PDC_PKT_SUBMIT
); /* flush */
955 static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd
*qc
)
957 switch (qc
->tf
.protocol
) {
958 case ATAPI_PROT_NODATA
:
959 if (qc
->dev
->flags
& ATA_DFLAG_CDB_INTR
)
962 case ATA_PROT_NODATA
:
963 if (qc
->tf
.flags
& ATA_TFLAG_POLLING
)
968 pdc_packet_start(qc
);
975 return ata_qc_issue_prot(qc
);
978 static void pdc_tf_load_mmio(struct ata_port
*ap
, const struct ata_taskfile
*tf
)
980 WARN_ON(tf
->protocol
== ATA_PROT_DMA
|| tf
->protocol
== ATAPI_PROT_DMA
);
984 static void pdc_exec_command_mmio(struct ata_port
*ap
,
985 const struct ata_taskfile
*tf
)
987 WARN_ON(tf
->protocol
== ATA_PROT_DMA
|| tf
->protocol
== ATAPI_PROT_DMA
);
988 ata_exec_command(ap
, tf
);
991 static int pdc_check_atapi_dma(struct ata_queued_cmd
*qc
)
993 u8
*scsicmd
= qc
->scsicmd
->cmnd
;
994 int pio
= 1; /* atapi dma off by default */
996 /* Whitelist commands that may use DMA. */
997 switch (scsicmd
[0]) {
1004 case 0xad: /* READ_DVD_STRUCTURE */
1005 case 0xbe: /* READ_CD */
1008 /* -45150 (FFFF4FA2) to -1 (FFFFFFFF) shall use PIO mode */
1009 if (scsicmd
[0] == WRITE_10
) {
1011 (scsicmd
[2] << 24) |
1012 (scsicmd
[3] << 16) |
1015 if (lba
>= 0xFFFF4FA2)
1021 static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd
*qc
)
1023 /* First generation chips cannot use ATAPI DMA on SATA ports */
1027 static void pdc_ata_setup_port(struct ata_port
*ap
,
1028 void __iomem
*base
, void __iomem
*scr_addr
)
1030 ap
->ioaddr
.cmd_addr
= base
;
1031 ap
->ioaddr
.data_addr
= base
;
1032 ap
->ioaddr
.feature_addr
=
1033 ap
->ioaddr
.error_addr
= base
+ 0x4;
1034 ap
->ioaddr
.nsect_addr
= base
+ 0x8;
1035 ap
->ioaddr
.lbal_addr
= base
+ 0xc;
1036 ap
->ioaddr
.lbam_addr
= base
+ 0x10;
1037 ap
->ioaddr
.lbah_addr
= base
+ 0x14;
1038 ap
->ioaddr
.device_addr
= base
+ 0x18;
1039 ap
->ioaddr
.command_addr
=
1040 ap
->ioaddr
.status_addr
= base
+ 0x1c;
1041 ap
->ioaddr
.altstatus_addr
=
1042 ap
->ioaddr
.ctl_addr
= base
+ 0x38;
1043 ap
->ioaddr
.scr_addr
= scr_addr
;
1046 static void pdc_host_init(struct ata_host
*host
)
1048 void __iomem
*mmio
= host
->iomap
[PDC_MMIO_BAR
];
1049 int is_gen2
= host
->ports
[0]->flags
& PDC_FLAG_GEN_II
;
1054 hotplug_offset
= PDC2_SATA_PLUG_CSR
;
1056 hotplug_offset
= PDC_SATA_PLUG_CSR
;
1059 * Except for the hotplug stuff, this is voodoo from the
1060 * Promise driver. Label this entire section
1061 * "TODO: figure out why we do this"
1064 /* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */
1065 tmp
= readl(mmio
+ PDC_FLASH_CTL
);
1066 tmp
|= 0x02000; /* bit 13 (enable bmr burst) */
1068 tmp
|= 0x10000; /* bit 16 (fifo threshold at 8 dw) */
1069 writel(tmp
, mmio
+ PDC_FLASH_CTL
);
1071 /* clear plug/unplug flags for all ports */
1072 tmp
= readl(mmio
+ hotplug_offset
);
1073 writel(tmp
| 0xff, mmio
+ hotplug_offset
);
1075 /* unmask plug/unplug ints */
1076 tmp
= readl(mmio
+ hotplug_offset
);
1077 writel(tmp
& ~0xff0000, mmio
+ hotplug_offset
);
1079 /* don't initialise TBG or SLEW on 2nd generation chips */
1083 /* reduce TBG clock to 133 Mhz. */
1084 tmp
= readl(mmio
+ PDC_TBG_MODE
);
1085 tmp
&= ~0x30000; /* clear bit 17, 16*/
1086 tmp
|= 0x10000; /* set bit 17:16 = 0:1 */
1087 writel(tmp
, mmio
+ PDC_TBG_MODE
);
1089 readl(mmio
+ PDC_TBG_MODE
); /* flush */
1092 /* adjust slew rate control register. */
1093 tmp
= readl(mmio
+ PDC_SLEW_CTL
);
1094 tmp
&= 0xFFFFF03F; /* clear bit 11 ~ 6 */
1095 tmp
|= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
1096 writel(tmp
, mmio
+ PDC_SLEW_CTL
);
1099 static int pdc_ata_init_one(struct pci_dev
*pdev
,
1100 const struct pci_device_id
*ent
)
1102 static int printed_version
;
1103 const struct ata_port_info
*pi
= &pdc_port_info
[ent
->driver_data
];
1104 const struct ata_port_info
*ppi
[PDC_MAX_PORTS
];
1105 struct ata_host
*host
;
1110 if (!printed_version
++)
1111 dev_printk(KERN_DEBUG
, &pdev
->dev
, "version " DRV_VERSION
"\n");
1113 /* enable and acquire resources */
1114 rc
= pcim_enable_device(pdev
);
1118 rc
= pcim_iomap_regions(pdev
, 1 << PDC_MMIO_BAR
, DRV_NAME
);
1120 pcim_pin_device(pdev
);
1123 base
= pcim_iomap_table(pdev
)[PDC_MMIO_BAR
];
1125 /* determine port configuration and setup host */
1127 if (pi
->flags
& PDC_FLAG_4_PORTS
)
1129 for (i
= 0; i
< n_ports
; i
++)
1132 if (pi
->flags
& PDC_FLAG_SATA_PATA
) {
1133 u8 tmp
= readb(base
+ PDC_FLASH_CTL
+1);
1135 ppi
[n_ports
++] = pi
+ 1;
1138 host
= ata_host_alloc_pinfo(&pdev
->dev
, ppi
, n_ports
);
1140 dev_printk(KERN_ERR
, &pdev
->dev
, "failed to allocate host\n");
1143 host
->iomap
= pcim_iomap_table(pdev
);
1145 is_sataii_tx4
= pdc_is_sataii_tx4(pi
->flags
);
1146 for (i
= 0; i
< host
->n_ports
; i
++) {
1147 struct ata_port
*ap
= host
->ports
[i
];
1148 unsigned int ata_no
= pdc_port_no_to_ata_no(i
, is_sataii_tx4
);
1149 unsigned int port_offset
= 0x200 + ata_no
* 0x80;
1150 unsigned int scr_offset
= 0x400 + ata_no
* 0x100;
1152 pdc_ata_setup_port(ap
, base
+ port_offset
, base
+ scr_offset
);
1154 ata_port_pbar_desc(ap
, PDC_MMIO_BAR
, -1, "mmio");
1155 ata_port_pbar_desc(ap
, PDC_MMIO_BAR
, port_offset
, "port");
1158 /* initialize adapter */
1159 pdc_host_init(host
);
1161 rc
= pci_set_dma_mask(pdev
, ATA_DMA_MASK
);
1164 rc
= pci_set_consistent_dma_mask(pdev
, ATA_DMA_MASK
);
1168 /* start host, request IRQ and attach */
1169 pci_set_master(pdev
);
1170 return ata_host_activate(host
, pdev
->irq
, pdc_interrupt
, IRQF_SHARED
,
1174 static int __init
pdc_ata_init(void)
1176 return pci_register_driver(&pdc_ata_pci_driver
);
1179 static void __exit
pdc_ata_exit(void)
1181 pci_unregister_driver(&pdc_ata_pci_driver
);
1184 MODULE_AUTHOR("Jeff Garzik");
1185 MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver");
1186 MODULE_LICENSE("GPL");
1187 MODULE_DEVICE_TABLE(pci
, pdc_ata_pci_tbl
);
1188 MODULE_VERSION(DRV_VERSION
);
1190 module_init(pdc_ata_init
);
1191 module_exit(pdc_ata_exit
);