arch/arm/include/asm/cacheflush.h

   1 /*
   2  *  arch/arm/include/asm/cacheflush.h
   3  *
   4  *  Copyright (C) 1999-2002 Russell King
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 #ifndef _ASMARM_CACHEFLUSH_H
  11 #define _ASMARM_CACHEFLUSH_H
  12
  13 #include <linux/mm.h>
  14
  15 #include <asm/glue.h>
  16 #include <asm/shmparam.h>
  17 #include <asm/cachetype.h>
  18
  19 #define CACHE_COLOUR(vaddr)     ((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT)
  20
  21 /*
  22  *      Cache Model
  23  *      ===========
  24  */
  25 #undef _CACHE
  26 #undef MULTI_CACHE
  27
  28 #if defined(CONFIG_CPU_CACHE_V3)
  29 # ifdef _CACHE
  30 #  define MULTI_CACHE 1
  31 # else
  32 #  define _CACHE v3
  33 # endif
  34 #endif
  35
  36 #if defined(CONFIG_CPU_CACHE_V4)
  37 # ifdef _CACHE
  38 #  define MULTI_CACHE 1
  39 # else
  40 #  define _CACHE v4
  41 # endif
  42 #endif
  43
  44 #if defined(CONFIG_CPU_ARM920T) || defined(CONFIG_CPU_ARM922T) || \
  45     defined(CONFIG_CPU_ARM925T) || defined(CONFIG_CPU_ARM1020)
  46 # define MULTI_CACHE 1
  47 #endif
  48
  49 #if defined(CONFIG_CPU_FA526)
  50 # ifdef _CACHE
  51 #  define MULTI_CACHE 1
  52 # else
  53 #  define _CACHE fa
  54 # endif
  55 #endif
  56
  57 #if defined(CONFIG_CPU_ARM926T)
  58 # ifdef _CACHE
  59 #  define MULTI_CACHE 1
  60 # else
  61 #  define _CACHE arm926
  62 # endif
  63 #endif
  64
  65 #if defined(CONFIG_CPU_ARM940T)
  66 # ifdef _CACHE
  67 #  define MULTI_CACHE 1
  68 # else
  69 #  define _CACHE arm940
  70 # endif
  71 #endif
  72
  73 #if defined(CONFIG_CPU_ARM946E)
  74 # ifdef _CACHE
  75 #  define MULTI_CACHE 1
  76 # else
  77 #  define _CACHE arm946
  78 # endif
  79 #endif
  80
  81 #if defined(CONFIG_CPU_CACHE_V4WB)
  82 # ifdef _CACHE
  83 #  define MULTI_CACHE 1
  84 # else
  85 #  define _CACHE v4wb
  86 # endif
  87 #endif
  88
  89 #if defined(CONFIG_CPU_XSCALE)
  90 # ifdef _CACHE
  91 #  define MULTI_CACHE 1
  92 # else
  93 #  define _CACHE xscale
  94 # endif
  95 #endif
  96
  97 #if defined(CONFIG_CPU_XSC3)
  98 # ifdef _CACHE
  99 #  define MULTI_CACHE 1
 100 # else
 101 #  define _CACHE xsc3
 102 # endif
 103 #endif
 104
 105 #if defined(CONFIG_CPU_MOHAWK)
 106 # ifdef _CACHE
 107 #  define MULTI_CACHE 1
 108 # else
 109 #  define _CACHE mohawk
 110 # endif
 111 #endif
 112
 113 #if defined(CONFIG_CPU_FEROCEON)
 114 # define MULTI_CACHE 1
 115 #endif
 116
 117 #if defined(CONFIG_CPU_V6)
 118 //# ifdef _CACHE
 119 #  define MULTI_CACHE 1
 120 //# else
 121 //#  define _CACHE v6
 122 //# endif
 123 #endif
 124
 125 #if defined(CONFIG_CPU_V7)
 126 //# ifdef _CACHE
 127 #  define MULTI_CACHE 1
 128 //# else
 129 //#  define _CACHE v7
 130 //# endif
 131 #endif
 132
 133 #if !defined(_CACHE) && !defined(MULTI_CACHE)
 134 #error Unknown cache maintainence model
 135 #endif
 136
 137 /*
 138  * This flag is used to indicate that the page pointed to by a pte
 139  * is dirty and requires cleaning before returning it to the user.
 140  */
 141 #define PG_dcache_dirty PG_arch_1
 142
 143 /*
 144  *      MM Cache Management
 145  *      ===================
 146  *
 147  *      The arch/arm/mm/cache-*.S and arch/arm/mm/proc-*.S files
 148  *      implement these methods.
 149  *
 150  *      Start addresses are inclusive and end addresses are exclusive;
 151  *      start addresses should be rounded down, end addresses up.
 152  *
 153  *      See Documentation/cachetlb.txt for more information.
 154  *      Please note that the implementation of these, and the required
 155  *      effects are cache-type (VIVT/VIPT/PIPT) specific.
 156  *
 157  *      flush_cache_kern_all()
 158  *
 159  *              Unconditionally clean and invalidate the entire cache.
 160  *
 161  *      flush_cache_user_mm(mm)
 162  *
 163  *              Clean and invalidate all user space cache entries
 164  *              before a change of page tables.
 165  *
 166  *      flush_cache_user_range(start, end, flags)
 167  *
 168  *              Clean and invalidate a range of cache entries in the
 169  *              specified address space before a change of page tables.
 170  *              - start - user start address (inclusive, page aligned)
 171  *              - end   - user end address   (exclusive, page aligned)
 172  *              - flags - vma->vm_flags field
 173  *
 174  *      coherent_kern_range(start, end)
 175  *
 176  *              Ensure coherency between the Icache and the Dcache in the
 177  *              region described by start, end.  If you have non-snooping
 178  *              Harvard caches, you need to implement this function.
 179  *              - start  - virtual start address
 180  *              - end    - virtual end address
 181  *
 182  *      DMA Cache Coherency
 183  *      ===================
 184  *
 185  *      dma_inv_range(start, end)
 186  *
 187  *              Invalidate (discard) the specified virtual address range.
 188  *              May not write back any entries.  If 'start' or 'end'
 189  *              are not cache line aligned, those lines must be written
 190  *              back.
 191  *              - start  - virtual start address
 192  *              - end    - virtual end address
 193  *
 194  *      dma_clean_range(start, end)
 195  *
 196  *              Clean (write back) the specified virtual address range.
 197  *              - start  - virtual start address
 198  *              - end    - virtual end address
 199  *
 200  *      dma_flush_range(start, end)
 201  *
 202  *              Clean and invalidate the specified virtual address range.
 203  *              - start  - virtual start address
 204  *              - end    - virtual end address
 205  */
 206
 207 struct cpu_cache_fns {
 208         void (*flush_kern_all)(void);
 209         void (*flush_user_all)(void);
 210         void (*flush_user_range)(unsigned long, unsigned long, unsigned int);
 211
 212         void (*coherent_kern_range)(unsigned long, unsigned long);
 213         void (*coherent_user_range)(unsigned long, unsigned long);
 214         void (*flush_kern_dcache_page)(void *);
 215
 216         void (*dma_inv_range)(const void *, const void *);
 217         void (*dma_clean_range)(const void *, const void *);
 218         void (*dma_flush_range)(const void *, const void *);
 219 };
 220
 221 struct outer_cache_fns {
 222         void (*inv_range)(unsigned long, unsigned long);
 223         void (*clean_range)(unsigned long, unsigned long);
 224         void (*flush_range)(unsigned long, unsigned long);
 225 };
 226
 227 /*
 228  * Select the calling method
 229  */
 230 #ifdef MULTI_CACHE
 231
 232 extern struct cpu_cache_fns cpu_cache;
 233
 234 #define __cpuc_flush_kern_all           cpu_cache.flush_kern_all
 235 #define __cpuc_flush_user_all           cpu_cache.flush_user_all
 236 #define __cpuc_flush_user_range         cpu_cache.flush_user_range
 237 #define __cpuc_coherent_kern_range      cpu_cache.coherent_kern_range
 238 #define __cpuc_coherent_user_range      cpu_cache.coherent_user_range
 239 #define __cpuc_flush_dcache_page        cpu_cache.flush_kern_dcache_page
 240
 241 /*
 242  * These are private to the dma-mapping API.  Do not use directly.
 243  * Their sole purpose is to ensure that data held in the cache
 244  * is visible to DMA, or data written by DMA to system memory is
 245  * visible to the CPU.
 246  */
 247 #define dmac_inv_range                  cpu_cache.dma_inv_range
 248 #define dmac_clean_range                cpu_cache.dma_clean_range
 249 #define dmac_flush_range                cpu_cache.dma_flush_range
 250
 251 #else
 252
 253 #define __cpuc_flush_kern_all           __glue(_CACHE,_flush_kern_cache_all)
 254 #define __cpuc_flush_user_all           __glue(_CACHE,_flush_user_cache_all)
 255 #define __cpuc_flush_user_range         __glue(_CACHE,_flush_user_cache_range)
 256 #define __cpuc_coherent_kern_range      __glue(_CACHE,_coherent_kern_range)
 257 #define __cpuc_coherent_user_range      __glue(_CACHE,_coherent_user_range)
 258 #define __cpuc_flush_dcache_page        __glue(_CACHE,_flush_kern_dcache_page)
 259
 260 extern void __cpuc_flush_kern_all(void);
 261 extern void __cpuc_flush_user_all(void);
 262 extern void __cpuc_flush_user_range(unsigned long, unsigned long, unsigned int);
 263 extern void __cpuc_coherent_kern_range(unsigned long, unsigned long);
 264 extern void __cpuc_coherent_user_range(unsigned long, unsigned long);
 265 extern void __cpuc_flush_dcache_page(void *);
 266
 267 /*
 268  * These are private to the dma-mapping API.  Do not use directly.
 269  * Their sole purpose is to ensure that data held in the cache
 270  * is visible to DMA, or data written by DMA to system memory is
 271  * visible to the CPU.
 272  */
 273 #define dmac_inv_range                  __glue(_CACHE,_dma_inv_range)
 274 #define dmac_clean_range                __glue(_CACHE,_dma_clean_range)
 275 #define dmac_flush_range                __glue(_CACHE,_dma_flush_range)
 276
 277 extern void dmac_inv_range(const void *, const void *);
 278 extern void dmac_clean_range(const void *, const void *);
 279 extern void dmac_flush_range(const void *, const void *);
 280
 281 #endif
 282
 283 #ifdef CONFIG_OUTER_CACHE
 284
 285 extern struct outer_cache_fns outer_cache;
 286
 287 static inline void outer_inv_range(unsigned long start, unsigned long end)
 288 {
 289         if (outer_cache.inv_range)
 290                 outer_cache.inv_range(start, end);
 291 }
 292 static inline void outer_clean_range(unsigned long start, unsigned long end)
 293 {
 294         if (outer_cache.clean_range)
 295                 outer_cache.clean_range(start, end);
 296 }
 297 static inline void outer_flush_range(unsigned long start, unsigned long end)
 298 {
 299         if (outer_cache.flush_range)
 300                 outer_cache.flush_range(start, end);
 301 }
 302
 303 #else
 304
 305 static inline void outer_inv_range(unsigned long start, unsigned long end)
 306 { }
 307 static inline void outer_clean_range(unsigned long start, unsigned long end)
 308 { }
 309 static inline void outer_flush_range(unsigned long start, unsigned long end)
 310 { }
 311
 312 #endif
 313
 314 /*
 315  * Copy user data from/to a page which is mapped into a different
 316  * processes address space.  Really, we want to allow our "user
 317  * space" model to handle this.
 318  */
 319 #define copy_to_user_page(vma, page, vaddr, dst, src, len) \
 320         do {                                                    \
 321                 memcpy(dst, src, len);                          \
 322                 flush_ptrace_access(vma, page, vaddr, dst, len, 1);\
 323         } while (0)
 324
 325 #define copy_from_user_page(vma, page, vaddr, dst, src, len) \
 326         do {                                                    \
 327                 memcpy(dst, src, len);                          \
 328         } while (0)
 329
 330 /*
 331  * Convert calls to our calling convention.
 332  */
 333 #define flush_cache_all()               __cpuc_flush_kern_all()
 334 #ifndef CONFIG_CPU_CACHE_VIPT
 335 static inline void flush_cache_mm(struct mm_struct *mm)
 336 {
 337         if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(mm)))
 338                 __cpuc_flush_user_all();
 339 }
 340
 341 static inline void
 342 flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
 343 {
 344         if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm)))
 345                 __cpuc_flush_user_range(start & PAGE_MASK, PAGE_ALIGN(end),
 346                                         vma->vm_flags);
 347 }
 348
 349 static inline void
 350 flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn)
 351 {
 352         if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) {
 353                 unsigned long addr = user_addr & PAGE_MASK;
 354                 __cpuc_flush_user_range(addr, addr + PAGE_SIZE, vma->vm_flags);
 355         }
 356 }
 357
 358 static inline void
 359 flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
 360                          unsigned long uaddr, void *kaddr,
 361                          unsigned long len, int write)
 362 {
 363         if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) {
 364                 unsigned long addr = (unsigned long)kaddr;
 365                 __cpuc_coherent_kern_range(addr, addr + len);
 366         }
 367 }
 368 #else
 369 extern void flush_cache_mm(struct mm_struct *mm);
 370 extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
 371 extern void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn);
 372 extern void flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
 373                                 unsigned long uaddr, void *kaddr,
 374                                 unsigned long len, int write);
 375 #endif
 376
 377 #define flush_cache_dup_mm(mm) flush_cache_mm(mm)
 378
 379 /*
 380  * flush_cache_user_range is used when we want to ensure that the
 381  * Harvard caches are synchronised for the user space address range.
 382  * This is used for the ARM private sys_cacheflush system call.
 383  */
 384 #define flush_cache_user_range(vma,start,end) \
 385         __cpuc_coherent_user_range((start) & PAGE_MASK, PAGE_ALIGN(end))
 386
 387 /*
 388  * Perform necessary cache operations to ensure that data previously
 389  * stored within this range of addresses can be executed by the CPU.
 390  */
 391 #define flush_icache_range(s,e)         __cpuc_coherent_kern_range(s,e)
 392
 393 /*
 394  * Perform necessary cache operations to ensure that the TLB will
 395  * see data written in the specified area.
 396  */
 397 #define clean_dcache_area(start,size)   cpu_dcache_clean_area(start, size)
 398
 399 /*
 400  * flush_dcache_page is used when the kernel has written to the page
 401  * cache page at virtual address page->virtual.
 402  *
 403  * If this page isn't mapped (ie, page_mapping == NULL), or it might
 404  * have userspace mappings, then we _must_ always clean + invalidate
 405  * the dcache entries associated with the kernel mapping.
 406  *
 407  * Otherwise we can defer the operation, and clean the cache when we are
 408  * about to change to user space.  This is the same method as used on SPARC64.
 409  * See update_mmu_cache for the user space part.
 410  */
 411 extern void flush_dcache_page(struct page *);
 412
 413 extern void __flush_dcache_page(struct address_space *mapping, struct page *page);
 414
 415 static inline void __flush_icache_all(void)
 416 {
 417         asm("mcr        p15, 0, %0, c7, c5, 0   @ invalidate I-cache\n"
 418             :
 419             : "r" (0));
 420 }
 421
 422 #define ARCH_HAS_FLUSH_ANON_PAGE
 423 static inline void flush_anon_page(struct vm_area_struct *vma,
 424                          struct page *page, unsigned long vmaddr)
 425 {
 426         extern void __flush_anon_page(struct vm_area_struct *vma,
 427                                 struct page *, unsigned long);
 428         if (PageAnon(page))
 429                 __flush_anon_page(vma, page, vmaddr);
 430 }
 431
 432 #define ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE
 433 static inline void flush_kernel_dcache_page(struct page *page)
 434 {
 435         /* highmem pages are always flushed upon kunmap already */
 436         if ((cache_is_vivt() || cache_is_vipt_aliasing()) && !PageHighMem(page))
 437                 __cpuc_flush_dcache_page(page_address(page));
 438 }
 439
 440 #define flush_dcache_mmap_lock(mapping) \
 441         spin_lock_irq(&(mapping)->tree_lock)
 442 #define flush_dcache_mmap_unlock(mapping) \
 443         spin_unlock_irq(&(mapping)->tree_lock)
 444
 445 #define flush_icache_user_range(vma,page,addr,len) \
 446         flush_dcache_page(page)
 447
 448 /*
 449  * We don't appear to need to do anything here.  In fact, if we did, we'd
 450  * duplicate cache flushing elsewhere performed by flush_dcache_page().
 451  */
 452 #define flush_icache_page(vma,page)     do { } while (0)
 453
 454 static inline void flush_ioremap_region(unsigned long phys, void __iomem *virt,
 455         unsigned offset, size_t size)
 456 {
 457         const void *start = (void __force *)virt + offset;
 458         dmac_inv_range(start, start + size);
 459 }
 460
 461 /*
 462  * flush_cache_vmap() is used when creating mappings (eg, via vmap,
 463  * vmalloc, ioremap etc) in kernel space for pages.  On non-VIPT
 464  * caches, since the direct-mappings of these pages may contain cached
 465  * data, we need to do a full cache flush to ensure that writebacks
 466  * don't corrupt data placed into these pages via the new mappings.
 467  */
 468 static inline void flush_cache_vmap(unsigned long start, unsigned long end)
 469 {
 470         if (!cache_is_vipt_nonaliasing())
 471                 flush_cache_all();
 472         else
 473                 /*
 474                  * set_pte_at() called from vmap_pte_range() does not
 475                  * have a DSB after cleaning the cache line.
 476                  */
 477                 dsb();
 478 }
 479
 480 static inline void flush_cache_vunmap(unsigned long start, unsigned long end)
 481 {
 482         if (!cache_is_vipt_nonaliasing())
 483                 flush_cache_all();
 484 }
 485
 486 #endif