arch/arm/mach-lpc32xx/timer.c

   1 /*
   2  * arch/arm/mach-lpc32xx/timer.c
   3  *
   4  * Author: Kevin Wells <kevin.wells@nxp.com>
   5  *
   6  * Copyright (C) 2009 - 2010 NXP Semiconductors
   7  * Copyright (C) 2009 Fontys University of Applied Sciences, Eindhoven
   8  *                    Ed Schouten <e.schouten@fontys.nl>
   9  *                    Laurens Timmermans <l.timmermans@fontys.nl>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  */
  21
  22 #include <linux/interrupt.h>
  23 #include <linux/irq.h>
  24 #include <linux/time.h>
  25 #include <linux/err.h>
  26 #include <linux/clockchips.h>
  27
  28 #include <asm/mach/time.h>
  29
  30 #include <mach/hardware.h>
  31 #include <mach/platform.h>
  32 #include "common.h"
  33
  34 static cycle_t lpc32xx_clksrc_read(struct clocksource *cs)
  35 {
  36         return (cycle_t)__raw_readl(LCP32XX_TIMER_TC(LPC32XX_TIMER1_BASE));
  37 }
  38
  39 static struct clocksource lpc32xx_clksrc = {
  40         .name   = "lpc32xx_clksrc",
  41         .rating = 300,
  42         .read   = lpc32xx_clksrc_read,
  43         .mask   = CLOCKSOURCE_MASK(32),
  44         .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
  45 };
  46
  47 static int lpc32xx_clkevt_next_event(unsigned long delta,
  48     struct clock_event_device *dev)
  49 {
  50         __raw_writel(LCP32XX_TIMER_CNTR_TCR_RESET,
  51                 LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
  52         __raw_writel(delta, LCP32XX_TIMER_PR(LPC32XX_TIMER0_BASE));
  53         __raw_writel(LCP32XX_TIMER_CNTR_TCR_EN,
  54                 LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
  55
  56         return 0;
  57 }
  58
  59 static void lpc32xx_clkevt_mode(enum clock_event_mode mode,
  60     struct clock_event_device *dev)
  61 {
  62         switch (mode) {
  63         case CLOCK_EVT_MODE_PERIODIC:
  64                 WARN_ON(1);
  65                 break;
  66
  67         case CLOCK_EVT_MODE_ONESHOT:
  68         case CLOCK_EVT_MODE_SHUTDOWN:
  69                 /*
  70                  * Disable the timer. When using oneshot, we must also
  71                  * disable the timer to wait for the first call to
  72                  * set_next_event().
  73                  */
  74                 __raw_writel(0, LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
  75                 break;
  76
  77         case CLOCK_EVT_MODE_UNUSED:
  78         case CLOCK_EVT_MODE_RESUME:
  79                 break;
  80         }
  81 }
  82
  83 static struct clock_event_device lpc32xx_clkevt = {
  84         .name           = "lpc32xx_clkevt",
  85         .features       = CLOCK_EVT_FEAT_ONESHOT,
  86         .shift          = 32,
  87         .rating         = 300,
  88         .set_next_event = lpc32xx_clkevt_next_event,
  89         .set_mode       = lpc32xx_clkevt_mode,
  90 };
  91
  92 static irqreturn_t lpc32xx_timer_interrupt(int irq, void *dev_id)
  93 {
  94         struct clock_event_device *evt = &lpc32xx_clkevt;
  95
  96         /* Clear match */
  97         __raw_writel(LCP32XX_TIMER_CNTR_MTCH_BIT(0),
  98                 LCP32XX_TIMER_IR(LPC32XX_TIMER0_BASE));
  99
 100         evt->event_handler(evt);
 101
 102         return IRQ_HANDLED;
 103 }
 104
 105 static struct irqaction lpc32xx_timer_irq = {
 106         .name           = "LPC32XX Timer Tick",
 107         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 108         .handler        = lpc32xx_timer_interrupt,
 109 };
 110
 111 /*
 112  * The clock management driver isn't initialized at this point, so the
 113  * clocks need to be enabled here manually and then tagged as used in
 114  * the clock driver initialization
 115  */
 116 static void __init lpc32xx_timer_init(void)
 117 {
 118         u32 clkrate, pllreg;
 119
 120         /* Enable timer clock */
 121         __raw_writel(LPC32XX_CLKPWR_TMRPWMCLK_TIMER0_EN |
 122                 LPC32XX_CLKPWR_TMRPWMCLK_TIMER1_EN,
 123                 LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1);
 124
 125         /*
 126          * The clock driver isn't initialized at this point. So determine if
 127          * the SYSCLK is driven from the PLL397 or main oscillator and then use
 128          * it to compute the PLL frequency and the PCLK divider to get the base
 129          * timer rates. This rate is needed to compute the tick rate.
 130          */
 131         if (clk_is_sysclk_mainosc() != 0)
 132                 clkrate = LPC32XX_MAIN_OSC_FREQ;
 133         else
 134                 clkrate = 397 * LPC32XX_CLOCK_OSC_FREQ;
 135
 136         /* Get ARM HCLKPLL register and convert it into a frequency */
 137         pllreg = __raw_readl(LPC32XX_CLKPWR_HCLKPLL_CTRL) & 0x1FFFF;
 138         clkrate = clk_get_pllrate_from_reg(clkrate, pllreg);
 139
 140         /* Get PCLK divider and divide ARM PLL clock by it to get timer rate */
 141         clkrate = clkrate / clk_get_pclk_div();
 142
 143         /* Initial timer setup */
 144         __raw_writel(0, LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
 145         __raw_writel(LCP32XX_TIMER_CNTR_MTCH_BIT(0),
 146                 LCP32XX_TIMER_IR(LPC32XX_TIMER0_BASE));
 147         __raw_writel(1, LCP32XX_TIMER_MR0(LPC32XX_TIMER0_BASE));
 148         __raw_writel(LCP32XX_TIMER_CNTR_MCR_MTCH(0) |
 149                 LCP32XX_TIMER_CNTR_MCR_STOP(0) |
 150                 LCP32XX_TIMER_CNTR_MCR_RESET(0),
 151                 LCP32XX_TIMER_MCR(LPC32XX_TIMER0_BASE));
 152
 153         /* Setup tick interrupt */
 154         setup_irq(IRQ_LPC32XX_TIMER0, &lpc32xx_timer_irq);
 155
 156         /* Setup the clockevent structure. */
 157         lpc32xx_clkevt.mult = div_sc(clkrate, NSEC_PER_SEC,
 158                 lpc32xx_clkevt.shift);
 159         lpc32xx_clkevt.max_delta_ns = clockevent_delta2ns(-1,
 160                 &lpc32xx_clkevt);
 161         lpc32xx_clkevt.min_delta_ns = clockevent_delta2ns(1,
 162                 &lpc32xx_clkevt) + 1;
 163         lpc32xx_clkevt.cpumask = cpumask_of(0);
 164         clockevents_register_device(&lpc32xx_clkevt);
 165
 166         /* Use timer1 as clock source. */
 167         __raw_writel(LCP32XX_TIMER_CNTR_TCR_RESET,
 168                 LCP32XX_TIMER_TCR(LPC32XX_TIMER1_BASE));
 169         __raw_writel(0, LCP32XX_TIMER_PR(LPC32XX_TIMER1_BASE));
 170         __raw_writel(0, LCP32XX_TIMER_MCR(LPC32XX_TIMER1_BASE));
 171         __raw_writel(LCP32XX_TIMER_CNTR_TCR_EN,
 172                 LCP32XX_TIMER_TCR(LPC32XX_TIMER1_BASE));
 173         clocksource_register_hz(&lpc32xx_clksrc, clkrate);
 174 }
 175
 176 struct sys_timer lpc32xx_timer = {
 177         .init           = &lpc32xx_timer_init,
 178 };
 179