drivers/tty/serial/mxs-auart.c

   1 /*
   2  * Freescale STMP37XX/STMP378X Application UART driver
   3  *
   4  * Author: dmitry pervushin <dimka@embeddedalley.com>
   5  *
   6  * Copyright 2008-2010 Freescale Semiconductor, Inc.
   7  * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
   8  *
   9  * The code contained herein is licensed under the GNU General Public
  10  * License. You may obtain a copy of the GNU General Public License
  11  * Version 2 or later at the following locations:
  12  *
  13  * http://www.opensource.org/licenses/gpl-license.html
  14  * http://www.gnu.org/copyleft/gpl.html
  15  */
  16
  17 #include <linux/kernel.h>
  18 #include <linux/errno.h>
  19 #include <linux/init.h>
  20 #include <linux/console.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/module.h>
  23 #include <linux/slab.h>
  24 #include <linux/wait.h>
  25 #include <linux/tty.h>
  26 #include <linux/tty_driver.h>
  27 #include <linux/tty_flip.h>
  28 #include <linux/serial.h>
  29 #include <linux/serial_core.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/device.h>
  32 #include <linux/clk.h>
  33 #include <linux/delay.h>
  34 #include <linux/io.h>
  35 #include <linux/pinctrl/consumer.h>
  36
  37 #include <asm/cacheflush.h>
  38
  39 #define MXS_AUART_PORTS 5
  40
  41 #define AUART_CTRL0                     0x00000000
  42 #define AUART_CTRL0_SET                 0x00000004
  43 #define AUART_CTRL0_CLR                 0x00000008
  44 #define AUART_CTRL0_TOG                 0x0000000c
  45 #define AUART_CTRL1                     0x00000010
  46 #define AUART_CTRL1_SET                 0x00000014
  47 #define AUART_CTRL1_CLR                 0x00000018
  48 #define AUART_CTRL1_TOG                 0x0000001c
  49 #define AUART_CTRL2                     0x00000020
  50 #define AUART_CTRL2_SET                 0x00000024
  51 #define AUART_CTRL2_CLR                 0x00000028
  52 #define AUART_CTRL2_TOG                 0x0000002c
  53 #define AUART_LINECTRL                  0x00000030
  54 #define AUART_LINECTRL_SET              0x00000034
  55 #define AUART_LINECTRL_CLR              0x00000038
  56 #define AUART_LINECTRL_TOG              0x0000003c
  57 #define AUART_LINECTRL2                 0x00000040
  58 #define AUART_LINECTRL2_SET             0x00000044
  59 #define AUART_LINECTRL2_CLR             0x00000048
  60 #define AUART_LINECTRL2_TOG             0x0000004c
  61 #define AUART_INTR                      0x00000050
  62 #define AUART_INTR_SET                  0x00000054
  63 #define AUART_INTR_CLR                  0x00000058
  64 #define AUART_INTR_TOG                  0x0000005c
  65 #define AUART_DATA                      0x00000060
  66 #define AUART_STAT                      0x00000070
  67 #define AUART_DEBUG                     0x00000080
  68 #define AUART_VERSION                   0x00000090
  69 #define AUART_AUTOBAUD                  0x000000a0
  70
  71 #define AUART_CTRL0_SFTRST                      (1 << 31)
  72 #define AUART_CTRL0_CLKGATE                     (1 << 30)
  73
  74 #define AUART_CTRL2_CTSEN                       (1 << 15)
  75 #define AUART_CTRL2_RTS                         (1 << 11)
  76 #define AUART_CTRL2_RXE                         (1 << 9)
  77 #define AUART_CTRL2_TXE                         (1 << 8)
  78 #define AUART_CTRL2_UARTEN                      (1 << 0)
  79
  80 #define AUART_LINECTRL_BAUD_DIVINT_SHIFT        16
  81 #define AUART_LINECTRL_BAUD_DIVINT_MASK         0xffff0000
  82 #define AUART_LINECTRL_BAUD_DIVINT(v)           (((v) & 0xffff) << 16)
  83 #define AUART_LINECTRL_BAUD_DIVFRAC_SHIFT       8
  84 #define AUART_LINECTRL_BAUD_DIVFRAC_MASK        0x00003f00
  85 #define AUART_LINECTRL_BAUD_DIVFRAC(v)          (((v) & 0x3f) << 8)
  86 #define AUART_LINECTRL_WLEN_MASK                0x00000060
  87 #define AUART_LINECTRL_WLEN(v)                  (((v) & 0x3) << 5)
  88 #define AUART_LINECTRL_FEN                      (1 << 4)
  89 #define AUART_LINECTRL_STP2                     (1 << 3)
  90 #define AUART_LINECTRL_EPS                      (1 << 2)
  91 #define AUART_LINECTRL_PEN                      (1 << 1)
  92 #define AUART_LINECTRL_BRK                      (1 << 0)
  93
  94 #define AUART_INTR_RTIEN                        (1 << 22)
  95 #define AUART_INTR_TXIEN                        (1 << 21)
  96 #define AUART_INTR_RXIEN                        (1 << 20)
  97 #define AUART_INTR_CTSMIEN                      (1 << 17)
  98 #define AUART_INTR_RTIS                         (1 << 6)
  99 #define AUART_INTR_TXIS                         (1 << 5)
 100 #define AUART_INTR_RXIS                         (1 << 4)
 101 #define AUART_INTR_CTSMIS                       (1 << 1)
 102
 103 #define AUART_STAT_BUSY                         (1 << 29)
 104 #define AUART_STAT_CTS                          (1 << 28)
 105 #define AUART_STAT_TXFE                         (1 << 27)
 106 #define AUART_STAT_TXFF                         (1 << 25)
 107 #define AUART_STAT_RXFE                         (1 << 24)
 108 #define AUART_STAT_OERR                         (1 << 19)
 109 #define AUART_STAT_BERR                         (1 << 18)
 110 #define AUART_STAT_PERR                         (1 << 17)
 111 #define AUART_STAT_FERR                         (1 << 16)
 112
 113 static struct uart_driver auart_driver;
 114
 115 struct mxs_auart_port {
 116         struct uart_port port;
 117
 118         unsigned int flags;
 119         unsigned int ctrl;
 120
 121         unsigned int irq;
 122
 123         struct clk *clk;
 124         struct device *dev;
 125 };
 126
 127 static void mxs_auart_stop_tx(struct uart_port *u);
 128
 129 #define to_auart_port(u) container_of(u, struct mxs_auart_port, port)
 130
 131 static inline void mxs_auart_tx_chars(struct mxs_auart_port *s)
 132 {
 133         struct circ_buf *xmit = &s->port.state->xmit;
 134
 135         while (!(readl(s->port.membase + AUART_STAT) &
 136                  AUART_STAT_TXFF)) {
 137                 if (s->port.x_char) {
 138                         s->port.icount.tx++;
 139                         writel(s->port.x_char,
 140                                      s->port.membase + AUART_DATA);
 141                         s->port.x_char = 0;
 142                         continue;
 143                 }
 144                 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) {
 145                         s->port.icount.tx++;
 146                         writel(xmit->buf[xmit->tail],
 147                                      s->port.membase + AUART_DATA);
 148                         xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 149                 } else
 150                         break;
 151         }
 152         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 153                 uart_write_wakeup(&s->port);
 154
 155         if (uart_circ_empty(&(s->port.state->xmit)))
 156                 writel(AUART_INTR_TXIEN,
 157                              s->port.membase + AUART_INTR_CLR);
 158         else
 159                 writel(AUART_INTR_TXIEN,
 160                              s->port.membase + AUART_INTR_SET);
 161
 162         if (uart_tx_stopped(&s->port))
 163                 mxs_auart_stop_tx(&s->port);
 164 }
 165
 166 static void mxs_auart_rx_char(struct mxs_auart_port *s)
 167 {
 168         int flag;
 169         u32 stat;
 170         u8 c;
 171
 172         c = readl(s->port.membase + AUART_DATA);
 173         stat = readl(s->port.membase + AUART_STAT);
 174
 175         flag = TTY_NORMAL;
 176         s->port.icount.rx++;
 177
 178         if (stat & AUART_STAT_BERR) {
 179                 s->port.icount.brk++;
 180                 if (uart_handle_break(&s->port))
 181                         goto out;
 182         } else if (stat & AUART_STAT_PERR) {
 183                 s->port.icount.parity++;
 184         } else if (stat & AUART_STAT_FERR) {
 185                 s->port.icount.frame++;
 186         }
 187
 188         /*
 189          * Mask off conditions which should be ingored.
 190          */
 191         stat &= s->port.read_status_mask;
 192
 193         if (stat & AUART_STAT_BERR) {
 194                 flag = TTY_BREAK;
 195         } else if (stat & AUART_STAT_PERR)
 196                 flag = TTY_PARITY;
 197         else if (stat & AUART_STAT_FERR)
 198                 flag = TTY_FRAME;
 199
 200         if (stat & AUART_STAT_OERR)
 201                 s->port.icount.overrun++;
 202
 203         if (uart_handle_sysrq_char(&s->port, c))
 204                 goto out;
 205
 206         uart_insert_char(&s->port, stat, AUART_STAT_OERR, c, flag);
 207 out:
 208         writel(stat, s->port.membase + AUART_STAT);
 209 }
 210
 211 static void mxs_auart_rx_chars(struct mxs_auart_port *s)
 212 {
 213         struct tty_struct *tty = s->port.state->port.tty;
 214         u32 stat = 0;
 215
 216         for (;;) {
 217                 stat = readl(s->port.membase + AUART_STAT);
 218                 if (stat & AUART_STAT_RXFE)
 219                         break;
 220                 mxs_auart_rx_char(s);
 221         }
 222
 223         writel(stat, s->port.membase + AUART_STAT);
 224         tty_flip_buffer_push(tty);
 225 }
 226
 227 static int mxs_auart_request_port(struct uart_port *u)
 228 {
 229         return 0;
 230 }
 231
 232 static int mxs_auart_verify_port(struct uart_port *u,
 233                                     struct serial_struct *ser)
 234 {
 235         if (u->type != PORT_UNKNOWN && u->type != PORT_IMX)
 236                 return -EINVAL;
 237         return 0;
 238 }
 239
 240 static void mxs_auart_config_port(struct uart_port *u, int flags)
 241 {
 242 }
 243
 244 static const char *mxs_auart_type(struct uart_port *u)
 245 {
 246         struct mxs_auart_port *s = to_auart_port(u);
 247
 248         return dev_name(s->dev);
 249 }
 250
 251 static void mxs_auart_release_port(struct uart_port *u)
 252 {
 253 }
 254
 255 static void mxs_auart_set_mctrl(struct uart_port *u, unsigned mctrl)
 256 {
 257         struct mxs_auart_port *s = to_auart_port(u);
 258
 259         u32 ctrl = readl(u->membase + AUART_CTRL2);
 260
 261         ctrl &= ~AUART_CTRL2_RTS;
 262         if (mctrl & TIOCM_RTS)
 263                 ctrl |= AUART_CTRL2_RTS;
 264         s->ctrl = mctrl;
 265         writel(ctrl, u->membase + AUART_CTRL2);
 266 }
 267
 268 static u32 mxs_auart_get_mctrl(struct uart_port *u)
 269 {
 270         struct mxs_auart_port *s = to_auart_port(u);
 271         u32 stat = readl(u->membase + AUART_STAT);
 272         int ctrl2 = readl(u->membase + AUART_CTRL2);
 273         u32 mctrl = s->ctrl;
 274
 275         mctrl &= ~TIOCM_CTS;
 276         if (stat & AUART_STAT_CTS)
 277                 mctrl |= TIOCM_CTS;
 278
 279         if (ctrl2 & AUART_CTRL2_RTS)
 280                 mctrl |= TIOCM_RTS;
 281
 282         return mctrl;
 283 }
 284
 285 static void mxs_auart_settermios(struct uart_port *u,
 286                                  struct ktermios *termios,
 287                                  struct ktermios *old)
 288 {
 289         u32 bm, ctrl, ctrl2, div;
 290         unsigned int cflag, baud;
 291
 292         cflag = termios->c_cflag;
 293
 294         ctrl = AUART_LINECTRL_FEN;
 295         ctrl2 = readl(u->membase + AUART_CTRL2);
 296
 297         /* byte size */
 298         switch (cflag & CSIZE) {
 299         case CS5:
 300                 bm = 0;
 301                 break;
 302         case CS6:
 303                 bm = 1;
 304                 break;
 305         case CS7:
 306                 bm = 2;
 307                 break;
 308         case CS8:
 309                 bm = 3;
 310                 break;
 311         default:
 312                 return;
 313         }
 314
 315         ctrl |= AUART_LINECTRL_WLEN(bm);
 316
 317         /* parity */
 318         if (cflag & PARENB) {
 319                 ctrl |= AUART_LINECTRL_PEN;
 320                 if ((cflag & PARODD) == 0)
 321                         ctrl |= AUART_LINECTRL_EPS;
 322         }
 323
 324         u->read_status_mask = 0;
 325
 326         if (termios->c_iflag & INPCK)
 327                 u->read_status_mask |= AUART_STAT_PERR;
 328         if (termios->c_iflag & (BRKINT | PARMRK))
 329                 u->read_status_mask |= AUART_STAT_BERR;
 330
 331         /*
 332          * Characters to ignore
 333          */
 334         u->ignore_status_mask = 0;
 335         if (termios->c_iflag & IGNPAR)
 336                 u->ignore_status_mask |= AUART_STAT_PERR;
 337         if (termios->c_iflag & IGNBRK) {
 338                 u->ignore_status_mask |= AUART_STAT_BERR;
 339                 /*
 340                  * If we're ignoring parity and break indicators,
 341                  * ignore overruns too (for real raw support).
 342                  */
 343                 if (termios->c_iflag & IGNPAR)
 344                         u->ignore_status_mask |= AUART_STAT_OERR;
 345         }
 346
 347         /*
 348          * ignore all characters if CREAD is not set
 349          */
 350         if (cflag & CREAD)
 351                 ctrl2 |= AUART_CTRL2_RXE;
 352         else
 353                 ctrl2 &= ~AUART_CTRL2_RXE;
 354
 355         /* figure out the stop bits requested */
 356         if (cflag & CSTOPB)
 357                 ctrl |= AUART_LINECTRL_STP2;
 358
 359         /* figure out the hardware flow control settings */
 360         if (cflag & CRTSCTS)
 361                 ctrl2 |= AUART_CTRL2_CTSEN;
 362         else
 363                 ctrl2 &= ~AUART_CTRL2_CTSEN;
 364
 365         /* set baud rate */
 366         baud = uart_get_baud_rate(u, termios, old, 0, u->uartclk);
 367         div = u->uartclk * 32 / baud;
 368         ctrl |= AUART_LINECTRL_BAUD_DIVFRAC(div & 0x3F);
 369         ctrl |= AUART_LINECTRL_BAUD_DIVINT(div >> 6);
 370
 371         writel(ctrl, u->membase + AUART_LINECTRL);
 372         writel(ctrl2, u->membase + AUART_CTRL2);
 373
 374         uart_update_timeout(u, termios->c_cflag, baud);
 375 }
 376
 377 static irqreturn_t mxs_auart_irq_handle(int irq, void *context)
 378 {
 379         u32 istatus, istat;
 380         struct mxs_auart_port *s = context;
 381         u32 stat = readl(s->port.membase + AUART_STAT);
 382
 383         istatus = istat = readl(s->port.membase + AUART_INTR);
 384
 385         if (istat & AUART_INTR_CTSMIS) {
 386                 uart_handle_cts_change(&s->port, stat & AUART_STAT_CTS);
 387                 writel(AUART_INTR_CTSMIS,
 388                                 s->port.membase + AUART_INTR_CLR);
 389                 istat &= ~AUART_INTR_CTSMIS;
 390         }
 391
 392         if (istat & (AUART_INTR_RTIS | AUART_INTR_RXIS)) {
 393                 mxs_auart_rx_chars(s);
 394                 istat &= ~(AUART_INTR_RTIS | AUART_INTR_RXIS);
 395         }
 396
 397         if (istat & AUART_INTR_TXIS) {
 398                 mxs_auart_tx_chars(s);
 399                 istat &= ~AUART_INTR_TXIS;
 400         }
 401
 402         writel(istatus & (AUART_INTR_RTIS
 403                 | AUART_INTR_TXIS
 404                 | AUART_INTR_RXIS
 405                 | AUART_INTR_CTSMIS),
 406                         s->port.membase + AUART_INTR_CLR);
 407
 408         return IRQ_HANDLED;
 409 }
 410
 411 static void mxs_auart_reset(struct uart_port *u)
 412 {
 413         int i;
 414         unsigned int reg;
 415
 416         writel(AUART_CTRL0_SFTRST, u->membase + AUART_CTRL0_CLR);
 417
 418         for (i = 0; i < 10000; i++) {
 419                 reg = readl(u->membase + AUART_CTRL0);
 420                 if (!(reg & AUART_CTRL0_SFTRST))
 421                         break;
 422                 udelay(3);
 423         }
 424         writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_CLR);
 425 }
 426
 427 static int mxs_auart_startup(struct uart_port *u)
 428 {
 429         struct mxs_auart_port *s = to_auart_port(u);
 430
 431         clk_prepare_enable(s->clk);
 432
 433         writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_CLR);
 434
 435         writel(AUART_CTRL2_UARTEN, u->membase + AUART_CTRL2_SET);
 436
 437         writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN,
 438                         u->membase + AUART_INTR);
 439
 440         /*
 441          * Enable fifo so all four bytes of a DMA word are written to
 442          * output (otherwise, only the LSB is written, ie. 1 in 4 bytes)
 443          */
 444         writel(AUART_LINECTRL_FEN, u->membase + AUART_LINECTRL_SET);
 445
 446         return 0;
 447 }
 448
 449 static void mxs_auart_shutdown(struct uart_port *u)
 450 {
 451         struct mxs_auart_port *s = to_auart_port(u);
 452
 453         writel(AUART_CTRL2_UARTEN, u->membase + AUART_CTRL2_CLR);
 454
 455         writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_SET);
 456
 457         writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN,
 458                         u->membase + AUART_INTR_CLR);
 459
 460         clk_disable_unprepare(s->clk);
 461 }
 462
 463 static unsigned int mxs_auart_tx_empty(struct uart_port *u)
 464 {
 465         if (readl(u->membase + AUART_STAT) & AUART_STAT_TXFE)
 466                 return TIOCSER_TEMT;
 467         else
 468                 return 0;
 469 }
 470
 471 static void mxs_auart_start_tx(struct uart_port *u)
 472 {
 473         struct mxs_auart_port *s = to_auart_port(u);
 474
 475         /* enable transmitter */
 476         writel(AUART_CTRL2_TXE, u->membase + AUART_CTRL2_SET);
 477
 478         mxs_auart_tx_chars(s);
 479 }
 480
 481 static void mxs_auart_stop_tx(struct uart_port *u)
 482 {
 483         writel(AUART_CTRL2_TXE, u->membase + AUART_CTRL2_CLR);
 484 }
 485
 486 static void mxs_auart_stop_rx(struct uart_port *u)
 487 {
 488         writel(AUART_CTRL2_RXE, u->membase + AUART_CTRL2_CLR);
 489 }
 490
 491 static void mxs_auart_break_ctl(struct uart_port *u, int ctl)
 492 {
 493         if (ctl)
 494                 writel(AUART_LINECTRL_BRK,
 495                              u->membase + AUART_LINECTRL_SET);
 496         else
 497                 writel(AUART_LINECTRL_BRK,
 498                              u->membase + AUART_LINECTRL_CLR);
 499 }
 500
 501 static void mxs_auart_enable_ms(struct uart_port *port)
 502 {
 503         /* just empty */
 504 }
 505
 506 static struct uart_ops mxs_auart_ops = {
 507         .tx_empty       = mxs_auart_tx_empty,
 508         .start_tx       = mxs_auart_start_tx,
 509         .stop_tx        = mxs_auart_stop_tx,
 510         .stop_rx        = mxs_auart_stop_rx,
 511         .enable_ms      = mxs_auart_enable_ms,
 512         .break_ctl      = mxs_auart_break_ctl,
 513         .set_mctrl      = mxs_auart_set_mctrl,
 514         .get_mctrl      = mxs_auart_get_mctrl,
 515         .startup        = mxs_auart_startup,
 516         .shutdown       = mxs_auart_shutdown,
 517         .set_termios    = mxs_auart_settermios,
 518         .type           = mxs_auart_type,
 519         .release_port   = mxs_auart_release_port,
 520         .request_port   = mxs_auart_request_port,
 521         .config_port    = mxs_auart_config_port,
 522         .verify_port    = mxs_auart_verify_port,
 523 };
 524
 525 static struct mxs_auart_port *auart_port[MXS_AUART_PORTS];
 526
 527 #ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
 528 static void mxs_auart_console_putchar(struct uart_port *port, int ch)
 529 {
 530         unsigned int to = 1000;
 531
 532         while (readl(port->membase + AUART_STAT) & AUART_STAT_TXFF) {
 533                 if (!to--)
 534                         break;
 535                 udelay(1);
 536         }
 537
 538         writel(ch, port->membase + AUART_DATA);
 539 }
 540
 541 static void
 542 auart_console_write(struct console *co, const char *str, unsigned int count)
 543 {
 544         struct mxs_auart_port *s;
 545         struct uart_port *port;
 546         unsigned int old_ctrl0, old_ctrl2;
 547         unsigned int to = 1000;
 548
 549         if (co->index > MXS_AUART_PORTS || co->index < 0)
 550                 return;
 551
 552         s = auart_port[co->index];
 553         port = &s->port;
 554
 555         clk_enable(s->clk);
 556
 557         /* First save the CR then disable the interrupts */
 558         old_ctrl2 = readl(port->membase + AUART_CTRL2);
 559         old_ctrl0 = readl(port->membase + AUART_CTRL0);
 560
 561         writel(AUART_CTRL0_CLKGATE,
 562                      port->membase + AUART_CTRL0_CLR);
 563         writel(AUART_CTRL2_UARTEN | AUART_CTRL2_TXE,
 564                      port->membase + AUART_CTRL2_SET);
 565
 566         uart_console_write(port, str, count, mxs_auart_console_putchar);
 567
 568         /*
 569          * Finally, wait for transmitter to become empty
 570          * and restore the TCR
 571          */
 572         while (readl(port->membase + AUART_STAT) & AUART_STAT_BUSY) {
 573                 if (!to--)
 574                         break;
 575                 udelay(1);
 576         }
 577
 578         writel(old_ctrl0, port->membase + AUART_CTRL0);
 579         writel(old_ctrl2, port->membase + AUART_CTRL2);
 580
 581         clk_disable(s->clk);
 582 }
 583
 584 static void __init
 585 auart_console_get_options(struct uart_port *port, int *baud,
 586                           int *parity, int *bits)
 587 {
 588         unsigned int lcr_h, quot;
 589
 590         if (!(readl(port->membase + AUART_CTRL2) & AUART_CTRL2_UARTEN))
 591                 return;
 592
 593         lcr_h = readl(port->membase + AUART_LINECTRL);
 594
 595         *parity = 'n';
 596         if (lcr_h & AUART_LINECTRL_PEN) {
 597                 if (lcr_h & AUART_LINECTRL_EPS)
 598                         *parity = 'e';
 599                 else
 600                         *parity = 'o';
 601         }
 602
 603         if ((lcr_h & AUART_LINECTRL_WLEN_MASK) == AUART_LINECTRL_WLEN(2))
 604                 *bits = 7;
 605         else
 606                 *bits = 8;
 607
 608         quot = ((readl(port->membase + AUART_LINECTRL)
 609                         & AUART_LINECTRL_BAUD_DIVINT_MASK))
 610                             >> (AUART_LINECTRL_BAUD_DIVINT_SHIFT - 6);
 611         quot |= ((readl(port->membase + AUART_LINECTRL)
 612                         & AUART_LINECTRL_BAUD_DIVFRAC_MASK))
 613                                 >> AUART_LINECTRL_BAUD_DIVFRAC_SHIFT;
 614         if (quot == 0)
 615                 quot = 1;
 616
 617         *baud = (port->uartclk << 2) / quot;
 618 }
 619
 620 static int __init
 621 auart_console_setup(struct console *co, char *options)
 622 {
 623         struct mxs_auart_port *s;
 624         int baud = 9600;
 625         int bits = 8;
 626         int parity = 'n';
 627         int flow = 'n';
 628         int ret;
 629
 630         /*
 631          * Check whether an invalid uart number has been specified, and
 632          * if so, search for the first available port that does have
 633          * console support.
 634          */
 635         if (co->index == -1 || co->index >= ARRAY_SIZE(auart_port))
 636                 co->index = 0;
 637         s = auart_port[co->index];
 638         if (!s)
 639                 return -ENODEV;
 640
 641         clk_prepare_enable(s->clk);
 642
 643         if (options)
 644                 uart_parse_options(options, &baud, &parity, &bits, &flow);
 645         else
 646                 auart_console_get_options(&s->port, &baud, &parity, &bits);
 647
 648         ret = uart_set_options(&s->port, co, baud, parity, bits, flow);
 649
 650         clk_disable_unprepare(s->clk);
 651
 652         return ret;
 653 }
 654
 655 static struct console auart_console = {
 656         .name           = "ttyAPP",
 657         .write          = auart_console_write,
 658         .device         = uart_console_device,
 659         .setup          = auart_console_setup,
 660         .flags          = CON_PRINTBUFFER,
 661         .index          = -1,
 662         .data           = &auart_driver,
 663 };
 664 #endif
 665
 666 static struct uart_driver auart_driver = {
 667         .owner          = THIS_MODULE,
 668         .driver_name    = "ttyAPP",
 669         .dev_name       = "ttyAPP",
 670         .major          = 0,
 671         .minor          = 0,
 672         .nr             = MXS_AUART_PORTS,
 673 #ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
 674         .cons =         &auart_console,
 675 #endif
 676 };
 677
 678 static int __devinit mxs_auart_probe(struct platform_device *pdev)
 679 {
 680         struct mxs_auart_port *s;
 681         u32 version;
 682         int ret = 0;
 683         struct resource *r;
 684         struct pinctrl *pinctrl;
 685
 686         s = kzalloc(sizeof(struct mxs_auart_port), GFP_KERNEL);
 687         if (!s) {
 688                 ret = -ENOMEM;
 689                 goto out;
 690         }
 691
 692         pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
 693         if (IS_ERR(pinctrl)) {
 694                 ret = PTR_ERR(pinctrl);
 695                 goto out_free;
 696         }
 697
 698         s->clk = clk_get(&pdev->dev, NULL);
 699         if (IS_ERR(s->clk)) {
 700                 ret = PTR_ERR(s->clk);
 701                 goto out_free;
 702         }
 703
 704         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 705         if (!r) {
 706                 ret = -ENXIO;
 707                 goto out_free_clk;
 708         }
 709
 710         s->port.mapbase = r->start;
 711         s->port.membase = ioremap(r->start, resource_size(r));
 712         s->port.ops = &mxs_auart_ops;
 713         s->port.iotype = UPIO_MEM;
 714         s->port.line = pdev->id < 0 ? 0 : pdev->id;
 715         s->port.fifosize = 16;
 716         s->port.uartclk = clk_get_rate(s->clk);
 717         s->port.type = PORT_IMX;
 718         s->port.dev = s->dev = get_device(&pdev->dev);
 719
 720         s->flags = 0;
 721         s->ctrl = 0;
 722
 723         s->irq = platform_get_irq(pdev, 0);
 724         s->port.irq = s->irq;
 725         ret = request_irq(s->irq, mxs_auart_irq_handle, 0, dev_name(&pdev->dev), s);
 726         if (ret)
 727                 goto out_free_clk;
 728
 729         platform_set_drvdata(pdev, s);
 730
 731         auart_port[pdev->id] = s;
 732
 733         mxs_auart_reset(&s->port);
 734
 735         ret = uart_add_one_port(&auart_driver, &s->port);
 736         if (ret)
 737                 goto out_free_irq;
 738
 739         version = readl(s->port.membase + AUART_VERSION);
 740         dev_info(&pdev->dev, "Found APPUART %d.%d.%d\n",
 741                (version >> 24) & 0xff,
 742                (version >> 16) & 0xff, version & 0xffff);
 743
 744         return 0;
 745
 746 out_free_irq:
 747         auart_port[pdev->id] = NULL;
 748         free_irq(s->irq, s);
 749 out_free_clk:
 750         clk_put(s->clk);
 751 out_free:
 752         kfree(s);
 753 out:
 754         return ret;
 755 }
 756
 757 static int __devexit mxs_auart_remove(struct platform_device *pdev)
 758 {
 759         struct mxs_auart_port *s = platform_get_drvdata(pdev);
 760
 761         uart_remove_one_port(&auart_driver, &s->port);
 762
 763         auart_port[pdev->id] = NULL;
 764
 765         clk_put(s->clk);
 766         free_irq(s->irq, s);
 767         kfree(s);
 768
 769         return 0;
 770 }
 771
 772 static struct platform_driver mxs_auart_driver = {
 773         .probe = mxs_auart_probe,
 774         .remove = __devexit_p(mxs_auart_remove),
 775         .driver = {
 776                 .name = "mxs-auart",
 777                 .owner = THIS_MODULE,
 778         },
 779 };
 780
 781 static int __init mxs_auart_init(void)
 782 {
 783         int r;
 784
 785         r = uart_register_driver(&auart_driver);
 786         if (r)
 787                 goto out;
 788
 789         r = platform_driver_register(&mxs_auart_driver);
 790         if (r)
 791                 goto out_err;
 792
 793         return 0;
 794 out_err:
 795         uart_unregister_driver(&auart_driver);
 796 out:
 797         return r;
 798 }
 799
 800 static void __exit mxs_auart_exit(void)
 801 {
 802         platform_driver_unregister(&mxs_auart_driver);
 803         uart_unregister_driver(&auart_driver);
 804 }
 805
 806 module_init(mxs_auart_init);
 807 module_exit(mxs_auart_exit);
 808 MODULE_LICENSE("GPL");
 809 MODULE_DESCRIPTION("Freescale MXS application uart driver");