arch/arm/mach-pxa/irq.c

   1 /*
   2  *  linux/arch/arm/mach-pxa/irq.c
   3  *
   4  *  Generic PXA IRQ handling, GPIO IRQ demultiplexing, etc.
   5  *
   6  *  Author:     Nicolas Pitre
   7  *  Created:    Jun 15, 2001
   8  *  Copyright:  MontaVista Software Inc.
   9  *
  10  *  This program is free software; you can redistribute it and/or modify
  11  *  it under the terms of the GNU General Public License version 2 as
  12  *  published by the Free Software Foundation.
  13  */
  14
  15 #include <linux/init.h>
  16 #include <linux/module.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/ptrace.h>
  19
  20 #include <asm/hardware.h>
  21 #include <asm/irq.h>
  22 #include <asm/mach/irq.h>
  23 #include <asm/arch/pxa-regs.h>
  24
  25 #include "generic.h"
  26
  27
  28 /*
  29  * This is for peripheral IRQs internal to the PXA chip.
  30  */
  31
  32 static void pxa_mask_low_irq(unsigned int irq)
  33 {
  34         ICMR &= ~(1 << (irq + PXA_IRQ_SKIP));
  35 }
  36
  37 static void pxa_unmask_low_irq(unsigned int irq)
  38 {
  39         ICMR |= (1 << (irq + PXA_IRQ_SKIP));
  40 }
  41
  42 static struct irq_chip pxa_internal_chip_low = {
  43         .name           = "SC",
  44         .ack            = pxa_mask_low_irq,
  45         .mask           = pxa_mask_low_irq,
  46         .unmask         = pxa_unmask_low_irq,
  47 };
  48
  49 #if PXA_INTERNAL_IRQS > 32
  50
  51 /*
  52  * This is for the second set of internal IRQs as found on the PXA27x.
  53  */
  54
  55 static void pxa_mask_high_irq(unsigned int irq)
  56 {
  57         ICMR2 &= ~(1 << (irq - 32 + PXA_IRQ_SKIP));
  58 }
  59
  60 static void pxa_unmask_high_irq(unsigned int irq)
  61 {
  62         ICMR2 |= (1 << (irq - 32 + PXA_IRQ_SKIP));
  63 }
  64
  65 static struct irq_chip pxa_internal_chip_high = {
  66         .name           = "SC-hi",
  67         .ack            = pxa_mask_high_irq,
  68         .mask           = pxa_mask_high_irq,
  69         .unmask         = pxa_unmask_high_irq,
  70 };
  71
  72 #endif
  73
  74 /*
  75  * PXA GPIO edge detection for IRQs:
  76  * IRQs are generated on Falling-Edge, Rising-Edge, or both.
  77  * Use this instead of directly setting GRER/GFER.
  78  */
  79
  80 static long GPIO_IRQ_rising_edge[4];
  81 static long GPIO_IRQ_falling_edge[4];
  82 static long GPIO_IRQ_mask[4];
  83
  84 static int pxa_gpio_irq_type(unsigned int irq, unsigned int type)
  85 {
  86         int gpio, idx;
  87
  88         gpio = IRQ_TO_GPIO(irq);
  89         idx = gpio >> 5;
  90
  91         if (type == IRQT_PROBE) {
  92             /* Don't mess with enabled GPIOs using preconfigured edges or
  93                GPIOs set to alternate function or to output during probe */
  94                 if ((GPIO_IRQ_rising_edge[idx] | GPIO_IRQ_falling_edge[idx] | GPDR(gpio)) &
  95                     GPIO_bit(gpio))
  96                         return 0;
  97                 if (GAFR(gpio) & (0x3 << (((gpio) & 0xf)*2)))
  98                         return 0;
  99                 type = __IRQT_RISEDGE | __IRQT_FALEDGE;
 100         }
 101
 102         /* printk(KERN_DEBUG "IRQ%d (GPIO%d): ", irq, gpio); */
 103
 104         pxa_gpio_mode(gpio | GPIO_IN);
 105
 106         if (type & __IRQT_RISEDGE) {
 107                 /* printk("rising "); */
 108                 __set_bit (gpio, GPIO_IRQ_rising_edge);
 109         } else
 110                 __clear_bit (gpio, GPIO_IRQ_rising_edge);
 111
 112         if (type & __IRQT_FALEDGE) {
 113                 /* printk("falling "); */
 114                 __set_bit (gpio, GPIO_IRQ_falling_edge);
 115         } else
 116                 __clear_bit (gpio, GPIO_IRQ_falling_edge);
 117
 118         /* printk("edges\n"); */
 119
 120         GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx];
 121         GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx];
 122         return 0;
 123 }
 124
 125 /*
 126  * GPIO IRQs must be acknowledged.  This is for GPIO 0 and 1.
 127  */
 128
 129 static void pxa_ack_low_gpio(unsigned int irq)
 130 {
 131         GEDR0 = (1 << (irq - IRQ_GPIO0));
 132 }
 133
 134 static struct irq_chip pxa_low_gpio_chip = {
 135         .name           = "GPIO-l",
 136         .ack            = pxa_ack_low_gpio,
 137         .mask           = pxa_mask_low_irq,
 138         .unmask         = pxa_unmask_low_irq,
 139         .set_type       = pxa_gpio_irq_type,
 140 };
 141
 142 /*
 143  * Demux handler for GPIO>=2 edge detect interrupts
 144  */
 145
 146 static void pxa_gpio_demux_handler(unsigned int irq, struct irqdesc *desc,
 147                                    struct pt_regs *regs)
 148 {
 149         unsigned int mask;
 150         int loop;
 151
 152         do {
 153                 loop = 0;
 154
 155                 mask = GEDR0 & ~3;
 156                 if (mask) {
 157                         GEDR0 = mask;
 158                         irq = IRQ_GPIO(2);
 159                         desc = irq_desc + irq;
 160                         mask >>= 2;
 161                         do {
 162                                 if (mask & 1)
 163                                         desc_handle_irq(irq, desc, regs);
 164                                 irq++;
 165                                 desc++;
 166                                 mask >>= 1;
 167                         } while (mask);
 168                         loop = 1;
 169                 }
 170
 171                 mask = GEDR1;
 172                 if (mask) {
 173                         GEDR1 = mask;
 174                         irq = IRQ_GPIO(32);
 175                         desc = irq_desc + irq;
 176                         do {
 177                                 if (mask & 1)
 178                                         desc_handle_irq(irq, desc, regs);
 179                                 irq++;
 180                                 desc++;
 181                                 mask >>= 1;
 182                         } while (mask);
 183                         loop = 1;
 184                 }
 185
 186                 mask = GEDR2;
 187                 if (mask) {
 188                         GEDR2 = mask;
 189                         irq = IRQ_GPIO(64);
 190                         desc = irq_desc + irq;
 191                         do {
 192                                 if (mask & 1)
 193                                         desc_handle_irq(irq, desc, regs);
 194                                 irq++;
 195                                 desc++;
 196                                 mask >>= 1;
 197                         } while (mask);
 198                         loop = 1;
 199                 }
 200
 201 #if PXA_LAST_GPIO >= 96
 202                 mask = GEDR3;
 203                 if (mask) {
 204                         GEDR3 = mask;
 205                         irq = IRQ_GPIO(96);
 206                         desc = irq_desc + irq;
 207                         do {
 208                                 if (mask & 1)
 209                                         desc_handle_irq(irq, desc, regs);
 210                                 irq++;
 211                                 desc++;
 212                                 mask >>= 1;
 213                         } while (mask);
 214                         loop = 1;
 215                 }
 216 #endif
 217         } while (loop);
 218 }
 219
 220 static void pxa_ack_muxed_gpio(unsigned int irq)
 221 {
 222         int gpio = irq - IRQ_GPIO(2) + 2;
 223         GEDR(gpio) = GPIO_bit(gpio);
 224 }
 225
 226 static void pxa_mask_muxed_gpio(unsigned int irq)
 227 {
 228         int gpio = irq - IRQ_GPIO(2) + 2;
 229         __clear_bit(gpio, GPIO_IRQ_mask);
 230         GRER(gpio) &= ~GPIO_bit(gpio);
 231         GFER(gpio) &= ~GPIO_bit(gpio);
 232 }
 233
 234 static void pxa_unmask_muxed_gpio(unsigned int irq)
 235 {
 236         int gpio = irq - IRQ_GPIO(2) + 2;
 237         int idx = gpio >> 5;
 238         __set_bit(gpio, GPIO_IRQ_mask);
 239         GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx];
 240         GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx];
 241 }
 242
 243 static struct irq_chip pxa_muxed_gpio_chip = {
 244         .name           = "GPIO",
 245         .ack            = pxa_ack_muxed_gpio,
 246         .mask           = pxa_mask_muxed_gpio,
 247         .unmask         = pxa_unmask_muxed_gpio,
 248         .set_type       = pxa_gpio_irq_type,
 249 };
 250
 251
 252 void __init pxa_init_irq(void)
 253 {
 254         int irq;
 255
 256         /* disable all IRQs */
 257         ICMR = 0;
 258
 259         /* all IRQs are IRQ, not FIQ */
 260         ICLR = 0;
 261
 262         /* clear all GPIO edge detects */
 263         GFER0 = 0;
 264         GFER1 = 0;
 265         GFER2 = 0;
 266         GRER0 = 0;
 267         GRER1 = 0;
 268         GRER2 = 0;
 269         GEDR0 = GEDR0;
 270         GEDR1 = GEDR1;
 271         GEDR2 = GEDR2;
 272
 273 #ifdef CONFIG_PXA27x
 274         /* And similarly for the extra regs on the PXA27x */
 275         ICMR2 = 0;
 276         ICLR2 = 0;
 277         GFER3 = 0;
 278         GRER3 = 0;
 279         GEDR3 = GEDR3;
 280 #endif
 281
 282         /* only unmasked interrupts kick us out of idle */
 283         ICCR = 1;
 284
 285         /* GPIO 0 and 1 must have their mask bit always set */
 286         GPIO_IRQ_mask[0] = 3;
 287
 288         for (irq = PXA_IRQ(PXA_IRQ_SKIP); irq <= PXA_IRQ(31); irq++) {
 289                 set_irq_chip(irq, &pxa_internal_chip_low);
 290                 set_irq_handler(irq, do_level_IRQ);
 291                 set_irq_flags(irq, IRQF_VALID);
 292         }
 293
 294 #if PXA_INTERNAL_IRQS > 32
 295         for (irq = PXA_IRQ(32); irq < PXA_IRQ(PXA_INTERNAL_IRQS); irq++) {
 296                 set_irq_chip(irq, &pxa_internal_chip_high);
 297                 set_irq_handler(irq, do_level_IRQ);
 298                 set_irq_flags(irq, IRQF_VALID);
 299         }
 300 #endif
 301
 302         for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) {
 303                 set_irq_chip(irq, &pxa_low_gpio_chip);
 304                 set_irq_handler(irq, do_edge_IRQ);
 305                 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
 306         }
 307
 308         for (irq = IRQ_GPIO(2); irq <= IRQ_GPIO(PXA_LAST_GPIO); irq++) {
 309                 set_irq_chip(irq, &pxa_muxed_gpio_chip);
 310                 set_irq_handler(irq, do_edge_IRQ);
 311                 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
 312         }
 313
 314         /* Install handler for GPIO>=2 edge detect interrupts */
 315         set_irq_chip(IRQ_GPIO_2_x, &pxa_internal_chip_low);
 316         set_irq_chained_handler(IRQ_GPIO_2_x, pxa_gpio_demux_handler);
 317 }