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drm/i915: Delay DP i2c initialization until panel power timings are computed
[linux-2.6.git] / drivers / gpu / drm / i915 / intel_dp.c
blob0c19b39b7cb8647a1ccf08b388d85bd5fdd85b1d
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include "drmP.h"
31 #include "drm.h"
32 #include "drm_crtc.h"
33 #include "drm_crtc_helper.h"
34 #include "intel_drv.h"
35 #include "i915_drm.h"
36 #include "i915_drv.h"
37 #include "drm_dp_helper.h"
38
39
40 #define DP_LINK_STATUS_SIZE 6
41 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42
43 #define DP_LINK_CONFIGURATION_SIZE 9
44
45 struct intel_dp {
46 struct intel_encoder base;
47 uint32_t output_reg;
48 uint32_t DP;
49 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
50 bool has_audio;
51 int force_audio;
52 uint32_t color_range;
53 int dpms_mode;
54 uint8_t link_bw;
55 uint8_t lane_count;
56 uint8_t dpcd[8];
57 struct i2c_adapter adapter;
58 struct i2c_algo_dp_aux_data algo;
59 bool is_pch_edp;
60 uint8_t train_set[4];
61 uint8_t link_status[DP_LINK_STATUS_SIZE];
62 };
63
64 /**
65 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
66 * @intel_dp: DP struct
67 *
68 * If a CPU or PCH DP output is attached to an eDP panel, this function
69 * will return true, and false otherwise.
70 */
71 static bool is_edp(struct intel_dp *intel_dp)
72 {
73 return intel_dp->base.type == INTEL_OUTPUT_EDP;
74 }
75
76 /**
77 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
78 * @intel_dp: DP struct
79 *
80 * Returns true if the given DP struct corresponds to a PCH DP port attached
81 * to an eDP panel, false otherwise. Helpful for determining whether we
82 * may need FDI resources for a given DP output or not.
83 */
84 static bool is_pch_edp(struct intel_dp *intel_dp)
85 {
86 return intel_dp->is_pch_edp;
87 }
88
89 static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
90 {
91 return container_of(encoder, struct intel_dp, base.base);
92 }
93
94 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
95 {
96 return container_of(intel_attached_encoder(connector),
97 struct intel_dp, base);
98 }
99
100 /**
101 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
102 * @encoder: DRM encoder
103 *
104 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
105 * by intel_display.c.
106 */
107 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
108 {
109 struct intel_dp *intel_dp;
110
111 if (!encoder)
112 return false;
113
114 intel_dp = enc_to_intel_dp(encoder);
115
116 return is_pch_edp(intel_dp);
117 }
118
119 static void intel_dp_start_link_train(struct intel_dp *intel_dp);
120 static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
121 static void intel_dp_link_down(struct intel_dp *intel_dp);
122
123 void
124 intel_edp_link_config (struct intel_encoder *intel_encoder,
125 int *lane_num, int *link_bw)
126 {
127 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
128
129 *lane_num = intel_dp->lane_count;
130 if (intel_dp->link_bw == DP_LINK_BW_1_62)
131 *link_bw = 162000;
132 else if (intel_dp->link_bw == DP_LINK_BW_2_7)
133 *link_bw = 270000;
134 }
135
136 static int
137 intel_dp_max_lane_count(struct intel_dp *intel_dp)
138 {
139 int max_lane_count = 4;
140
141 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
142 max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
143 switch (max_lane_count) {
144 case 1: case 2: case 4:
145 break;
146 default:
147 max_lane_count = 4;
148 }
149 }
150 return max_lane_count;
151 }
152
153 static int
154 intel_dp_max_link_bw(struct intel_dp *intel_dp)
155 {
156 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
157
158 switch (max_link_bw) {
159 case DP_LINK_BW_1_62:
160 case DP_LINK_BW_2_7:
161 break;
162 default:
163 max_link_bw = DP_LINK_BW_1_62;
164 break;
165 }
166 return max_link_bw;
167 }
168
169 static int
170 intel_dp_link_clock(uint8_t link_bw)
171 {
172 if (link_bw == DP_LINK_BW_2_7)
173 return 270000;
174 else
175 return 162000;
176 }
177
178 /* I think this is a fiction */
179 static int
180 intel_dp_link_required(struct drm_device *dev, struct intel_dp *intel_dp, int pixel_clock)
181 {
182 struct drm_crtc *crtc = intel_dp->base.base.crtc;
183 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
184 int bpp = 24;
185
186 if (intel_crtc)
187 bpp = intel_crtc->bpp;
188
189 return (pixel_clock * bpp + 7) / 8;
190 }
191
192 static int
193 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
194 {
195 return (max_link_clock * max_lanes * 8) / 10;
196 }
197
198 static int
199 intel_dp_mode_valid(struct drm_connector *connector,
200 struct drm_display_mode *mode)
201 {
202 struct intel_dp *intel_dp = intel_attached_dp(connector);
203 struct drm_device *dev = connector->dev;
204 struct drm_i915_private *dev_priv = dev->dev_private;
205 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
206 int max_lanes = intel_dp_max_lane_count(intel_dp);
207
208 if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) {
209 if (mode->hdisplay > dev_priv->panel_fixed_mode->hdisplay)
210 return MODE_PANEL;
211
212 if (mode->vdisplay > dev_priv->panel_fixed_mode->vdisplay)
213 return MODE_PANEL;
214 }
215
216 /* only refuse the mode on non eDP since we have seen some weird eDP panels
217 which are outside spec tolerances but somehow work by magic */
218 if (!is_edp(intel_dp) &&
219 (intel_dp_link_required(connector->dev, intel_dp, mode->clock)
220 > intel_dp_max_data_rate(max_link_clock, max_lanes)))
221 return MODE_CLOCK_HIGH;
222
223 if (mode->clock < 10000)
224 return MODE_CLOCK_LOW;
225
226 return MODE_OK;
227 }
228
229 static uint32_t
230 pack_aux(uint8_t *src, int src_bytes)
231 {
232 int i;
233 uint32_t v = 0;
234
235 if (src_bytes > 4)
236 src_bytes = 4;
237 for (i = 0; i < src_bytes; i++)
238 v |= ((uint32_t) src[i]) << ((3-i) * 8);
239 return v;
240 }
241
242 static void
243 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
244 {
245 int i;
246 if (dst_bytes > 4)
247 dst_bytes = 4;
248 for (i = 0; i < dst_bytes; i++)
249 dst[i] = src >> ((3-i) * 8);
250 }
251
252 /* hrawclock is 1/4 the FSB frequency */
253 static int
254 intel_hrawclk(struct drm_device *dev)
255 {
256 struct drm_i915_private *dev_priv = dev->dev_private;
257 uint32_t clkcfg;
258
259 clkcfg = I915_READ(CLKCFG);
260 switch (clkcfg & CLKCFG_FSB_MASK) {
261 case CLKCFG_FSB_400:
262 return 100;
263 case CLKCFG_FSB_533:
264 return 133;
265 case CLKCFG_FSB_667:
266 return 166;
267 case CLKCFG_FSB_800:
268 return 200;
269 case CLKCFG_FSB_1067:
270 return 266;
271 case CLKCFG_FSB_1333:
272 return 333;
273 /* these two are just a guess; one of them might be right */
274 case CLKCFG_FSB_1600:
275 case CLKCFG_FSB_1600_ALT:
276 return 400;
277 default:
278 return 133;
279 }
280 }
281
282 static void
283 intel_dp_check_edp(struct intel_dp *intel_dp)
284 {
285 struct drm_device *dev = intel_dp->base.base.dev;
286 struct drm_i915_private *dev_priv = dev->dev_private;
287 u32 pp_status, pp_control;
288 if (!is_edp(intel_dp))
289 return;
290 pp_status = I915_READ(PCH_PP_STATUS);
291 pp_control = I915_READ(PCH_PP_CONTROL);
292 if ((pp_status & PP_ON) == 0 && (pp_control & EDP_FORCE_VDD) == 0) {
293 WARN(1, "eDP powered off while attempting aux channel communication.\n");
294 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
295 pp_status,
296 I915_READ(PCH_PP_CONTROL));
297 }
298 }
299
300 static int
301 intel_dp_aux_ch(struct intel_dp *intel_dp,
302 uint8_t *send, int send_bytes,
303 uint8_t *recv, int recv_size)
304 {
305 uint32_t output_reg = intel_dp->output_reg;
306 struct drm_device *dev = intel_dp->base.base.dev;
307 struct drm_i915_private *dev_priv = dev->dev_private;
308 uint32_t ch_ctl = output_reg + 0x10;
309 uint32_t ch_data = ch_ctl + 4;
310 int i;
311 int recv_bytes;
312 uint32_t status;
313 uint32_t aux_clock_divider;
314 int try, precharge;
315
316 intel_dp_check_edp(intel_dp);
317 /* The clock divider is based off the hrawclk,
318 * and would like to run at 2MHz. So, take the
319 * hrawclk value and divide by 2 and use that
320 *
321 * Note that PCH attached eDP panels should use a 125MHz input
322 * clock divider.
323 */
324 if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) {
325 if (IS_GEN6(dev))
326 aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */
327 else
328 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
329 } else if (HAS_PCH_SPLIT(dev))
330 aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */
331 else
332 aux_clock_divider = intel_hrawclk(dev) / 2;
333
334 if (IS_GEN6(dev))
335 precharge = 3;
336 else
337 precharge = 5;
338
339 /* Try to wait for any previous AUX channel activity */
340 for (try = 0; try < 3; try++) {
341 status = I915_READ(ch_ctl);
342 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
343 break;
344 msleep(1);
345 }
346
347 if (try == 3) {
348 WARN(1, "dp_aux_ch not started status 0x%08x\n",
349 I915_READ(ch_ctl));
350 return -EBUSY;
351 }
352
353 /* Must try at least 3 times according to DP spec */
354 for (try = 0; try < 5; try++) {
355 /* Load the send data into the aux channel data registers */
356 for (i = 0; i < send_bytes; i += 4)
357 I915_WRITE(ch_data + i,
358 pack_aux(send + i, send_bytes - i));
359
360 /* Send the command and wait for it to complete */
361 I915_WRITE(ch_ctl,
362 DP_AUX_CH_CTL_SEND_BUSY |
363 DP_AUX_CH_CTL_TIME_OUT_400us |
364 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
365 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
366 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
367 DP_AUX_CH_CTL_DONE |
368 DP_AUX_CH_CTL_TIME_OUT_ERROR |
369 DP_AUX_CH_CTL_RECEIVE_ERROR);
370 for (;;) {
371 status = I915_READ(ch_ctl);
372 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
373 break;
374 udelay(100);
375 }
376
377 /* Clear done status and any errors */
378 I915_WRITE(ch_ctl,
379 status |
380 DP_AUX_CH_CTL_DONE |
381 DP_AUX_CH_CTL_TIME_OUT_ERROR |
382 DP_AUX_CH_CTL_RECEIVE_ERROR);
383 if (status & DP_AUX_CH_CTL_DONE)
384 break;
385 }
386
387 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
388 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
389 return -EBUSY;
390 }
391
392 /* Check for timeout or receive error.
393 * Timeouts occur when the sink is not connected
394 */
395 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
396 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
397 return -EIO;
398 }
399
400 /* Timeouts occur when the device isn't connected, so they're
401 * "normal" -- don't fill the kernel log with these */
402 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
403 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
404 return -ETIMEDOUT;
405 }
406
407 /* Unload any bytes sent back from the other side */
408 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
409 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
410 if (recv_bytes > recv_size)
411 recv_bytes = recv_size;
412
413 for (i = 0; i < recv_bytes; i += 4)
414 unpack_aux(I915_READ(ch_data + i),
415 recv + i, recv_bytes - i);
416
417 return recv_bytes;
418 }
419
420 /* Write data to the aux channel in native mode */
421 static int
422 intel_dp_aux_native_write(struct intel_dp *intel_dp,
423 uint16_t address, uint8_t *send, int send_bytes)
424 {
425 int ret;
426 uint8_t msg[20];
427 int msg_bytes;
428 uint8_t ack;
429
430 intel_dp_check_edp(intel_dp);
431 if (send_bytes > 16)
432 return -1;
433 msg[0] = AUX_NATIVE_WRITE << 4;
434 msg[1] = address >> 8;
435 msg[2] = address & 0xff;
436 msg[3] = send_bytes - 1;
437 memcpy(&msg[4], send, send_bytes);
438 msg_bytes = send_bytes + 4;
439 for (;;) {
440 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
441 if (ret < 0)
442 return ret;
443 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
444 break;
445 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
446 udelay(100);
447 else
448 return -EIO;
449 }
450 return send_bytes;
451 }
452
453 /* Write a single byte to the aux channel in native mode */
454 static int
455 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
456 uint16_t address, uint8_t byte)
457 {
458 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
459 }
460
461 /* read bytes from a native aux channel */
462 static int
463 intel_dp_aux_native_read(struct intel_dp *intel_dp,
464 uint16_t address, uint8_t *recv, int recv_bytes)
465 {
466 uint8_t msg[4];
467 int msg_bytes;
468 uint8_t reply[20];
469 int reply_bytes;
470 uint8_t ack;
471 int ret;
472
473 intel_dp_check_edp(intel_dp);
474 msg[0] = AUX_NATIVE_READ << 4;
475 msg[1] = address >> 8;
476 msg[2] = address & 0xff;
477 msg[3] = recv_bytes - 1;
478
479 msg_bytes = 4;
480 reply_bytes = recv_bytes + 1;
481
482 for (;;) {
483 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
484 reply, reply_bytes);
485 if (ret == 0)
486 return -EPROTO;
487 if (ret < 0)
488 return ret;
489 ack = reply[0];
490 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
491 memcpy(recv, reply + 1, ret - 1);
492 return ret - 1;
493 }
494 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
495 udelay(100);
496 else
497 return -EIO;
498 }
499 }
500
501 static int
502 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
503 uint8_t write_byte, uint8_t *read_byte)
504 {
505 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
506 struct intel_dp *intel_dp = container_of(adapter,
507 struct intel_dp,
508 adapter);
509 uint16_t address = algo_data->address;
510 uint8_t msg[5];
511 uint8_t reply[2];
512 unsigned retry;
513 int msg_bytes;
514 int reply_bytes;
515 int ret;
516
517 intel_dp_check_edp(intel_dp);
518 /* Set up the command byte */
519 if (mode & MODE_I2C_READ)
520 msg[0] = AUX_I2C_READ << 4;
521 else
522 msg[0] = AUX_I2C_WRITE << 4;
523
524 if (!(mode & MODE_I2C_STOP))
525 msg[0] |= AUX_I2C_MOT << 4;
526
527 msg[1] = address >> 8;
528 msg[2] = address;
529
530 switch (mode) {
531 case MODE_I2C_WRITE:
532 msg[3] = 0;
533 msg[4] = write_byte;
534 msg_bytes = 5;
535 reply_bytes = 1;
536 break;
537 case MODE_I2C_READ:
538 msg[3] = 0;
539 msg_bytes = 4;
540 reply_bytes = 2;
541 break;
542 default:
543 msg_bytes = 3;
544 reply_bytes = 1;
545 break;
546 }
547
548 for (retry = 0; retry < 5; retry++) {
549 ret = intel_dp_aux_ch(intel_dp,
550 msg, msg_bytes,
551 reply, reply_bytes);
552 if (ret < 0) {
553 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
554 return ret;
555 }
556
557 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
558 case AUX_NATIVE_REPLY_ACK:
559 /* I2C-over-AUX Reply field is only valid
560 * when paired with AUX ACK.
561 */
562 break;
563 case AUX_NATIVE_REPLY_NACK:
564 DRM_DEBUG_KMS("aux_ch native nack\n");
565 return -EREMOTEIO;
566 case AUX_NATIVE_REPLY_DEFER:
567 udelay(100);
568 continue;
569 default:
570 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
571 reply[0]);
572 return -EREMOTEIO;
573 }
574
575 switch (reply[0] & AUX_I2C_REPLY_MASK) {
576 case AUX_I2C_REPLY_ACK:
577 if (mode == MODE_I2C_READ) {
578 *read_byte = reply[1];
579 }
580 return reply_bytes - 1;
581 case AUX_I2C_REPLY_NACK:
582 DRM_DEBUG_KMS("aux_i2c nack\n");
583 return -EREMOTEIO;
584 case AUX_I2C_REPLY_DEFER:
585 DRM_DEBUG_KMS("aux_i2c defer\n");
586 udelay(100);
587 break;
588 default:
589 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
590 return -EREMOTEIO;
591 }
592 }
593
594 DRM_ERROR("too many retries, giving up\n");
595 return -EREMOTEIO;
596 }
597
598 static int
599 intel_dp_i2c_init(struct intel_dp *intel_dp,
600 struct intel_connector *intel_connector, const char *name)
601 {
602 DRM_DEBUG_KMS("i2c_init %s\n", name);
603 intel_dp->algo.running = false;
604 intel_dp->algo.address = 0;
605 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
606
607 memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter));
608 intel_dp->adapter.owner = THIS_MODULE;
609 intel_dp->adapter.class = I2C_CLASS_DDC;
610 strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
611 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
612 intel_dp->adapter.algo_data = &intel_dp->algo;
613 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
614
615 return i2c_dp_aux_add_bus(&intel_dp->adapter);
616 }
617
618 static bool
619 intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
620 struct drm_display_mode *adjusted_mode)
621 {
622 struct drm_device *dev = encoder->dev;
623 struct drm_i915_private *dev_priv = dev->dev_private;
624 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
625 int lane_count, clock;
626 int max_lane_count = intel_dp_max_lane_count(intel_dp);
627 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
628 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
629
630 if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) {
631 intel_fixed_panel_mode(dev_priv->panel_fixed_mode, adjusted_mode);
632 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
633 mode, adjusted_mode);
634 /*
635 * the mode->clock is used to calculate the Data&Link M/N
636 * of the pipe. For the eDP the fixed clock should be used.
637 */
638 mode->clock = dev_priv->panel_fixed_mode->clock;
639 }
640
641 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
642 for (clock = 0; clock <= max_clock; clock++) {
643 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
644
645 if (intel_dp_link_required(encoder->dev, intel_dp, mode->clock)
646 <= link_avail) {
647 intel_dp->link_bw = bws[clock];
648 intel_dp->lane_count = lane_count;
649 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
650 DRM_DEBUG_KMS("Display port link bw %02x lane "
651 "count %d clock %d\n",
652 intel_dp->link_bw, intel_dp->lane_count,
653 adjusted_mode->clock);
654 return true;
655 }
656 }
657 }
658
659 if (is_edp(intel_dp)) {
660 /* okay we failed just pick the highest */
661 intel_dp->lane_count = max_lane_count;
662 intel_dp->link_bw = bws[max_clock];
663 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
664 DRM_DEBUG_KMS("Force picking display port link bw %02x lane "
665 "count %d clock %d\n",
666 intel_dp->link_bw, intel_dp->lane_count,
667 adjusted_mode->clock);
668
669 return true;
670 }
671
672 return false;
673 }
674
675 struct intel_dp_m_n {
676 uint32_t tu;
677 uint32_t gmch_m;
678 uint32_t gmch_n;
679 uint32_t link_m;
680 uint32_t link_n;
681 };
682
683 static void
684 intel_reduce_ratio(uint32_t *num, uint32_t *den)
685 {
686 while (*num > 0xffffff || *den > 0xffffff) {
687 *num >>= 1;
688 *den >>= 1;
689 }
690 }
691
692 static void
693 intel_dp_compute_m_n(int bpp,
694 int nlanes,
695 int pixel_clock,
696 int link_clock,
697 struct intel_dp_m_n *m_n)
698 {
699 m_n->tu = 64;
700 m_n->gmch_m = (pixel_clock * bpp) >> 3;
701 m_n->gmch_n = link_clock * nlanes;
702 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
703 m_n->link_m = pixel_clock;
704 m_n->link_n = link_clock;
705 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
706 }
707
708 void
709 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
710 struct drm_display_mode *adjusted_mode)
711 {
712 struct drm_device *dev = crtc->dev;
713 struct drm_mode_config *mode_config = &dev->mode_config;
714 struct drm_encoder *encoder;
715 struct drm_i915_private *dev_priv = dev->dev_private;
716 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
717 int lane_count = 4;
718 struct intel_dp_m_n m_n;
719 int pipe = intel_crtc->pipe;
720
721 /*
722 * Find the lane count in the intel_encoder private
723 */
724 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
725 struct intel_dp *intel_dp;
726
727 if (encoder->crtc != crtc)
728 continue;
729
730 intel_dp = enc_to_intel_dp(encoder);
731 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) {
732 lane_count = intel_dp->lane_count;
733 break;
734 } else if (is_edp(intel_dp)) {
735 lane_count = dev_priv->edp.lanes;
736 break;
737 }
738 }
739
740 /*
741 * Compute the GMCH and Link ratios. The '3' here is
742 * the number of bytes_per_pixel post-LUT, which we always
743 * set up for 8-bits of R/G/B, or 3 bytes total.
744 */
745 intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
746 mode->clock, adjusted_mode->clock, &m_n);
747
748 if (HAS_PCH_SPLIT(dev)) {
749 I915_WRITE(TRANSDATA_M1(pipe),
750 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
751 m_n.gmch_m);
752 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
753 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
754 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
755 } else {
756 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
757 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
758 m_n.gmch_m);
759 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
760 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
761 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
762 }
763 }
764
765 static void
766 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
767 struct drm_display_mode *adjusted_mode)
768 {
769 struct drm_device *dev = encoder->dev;
770 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
771 struct drm_crtc *crtc = intel_dp->base.base.crtc;
772 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
773
774 intel_dp->DP = DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
775 intel_dp->DP |= intel_dp->color_range;
776
777 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
778 intel_dp->DP |= DP_SYNC_HS_HIGH;
779 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
780 intel_dp->DP |= DP_SYNC_VS_HIGH;
781
782 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
783 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
784 else
785 intel_dp->DP |= DP_LINK_TRAIN_OFF;
786
787 switch (intel_dp->lane_count) {
788 case 1:
789 intel_dp->DP |= DP_PORT_WIDTH_1;
790 break;
791 case 2:
792 intel_dp->DP |= DP_PORT_WIDTH_2;
793 break;
794 case 4:
795 intel_dp->DP |= DP_PORT_WIDTH_4;
796 break;
797 }
798 if (intel_dp->has_audio)
799 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
800
801 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
802 intel_dp->link_configuration[0] = intel_dp->link_bw;
803 intel_dp->link_configuration[1] = intel_dp->lane_count;
804 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
805
806 /*
807 * Check for DPCD version > 1.1 and enhanced framing support
808 */
809 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
810 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
811 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
812 intel_dp->DP |= DP_ENHANCED_FRAMING;
813 }
814
815 /* CPT DP's pipe select is decided in TRANS_DP_CTL */
816 if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev))
817 intel_dp->DP |= DP_PIPEB_SELECT;
818
819 if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) {
820 /* don't miss out required setting for eDP */
821 intel_dp->DP |= DP_PLL_ENABLE;
822 if (adjusted_mode->clock < 200000)
823 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
824 else
825 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
826 }
827 }
828
829 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
830 {
831 struct drm_device *dev = intel_dp->base.base.dev;
832 struct drm_i915_private *dev_priv = dev->dev_private;
833 u32 pp;
834
835 if (!is_edp(intel_dp))
836 return;
837 /*
838 * If the panel wasn't on, make sure there's not a currently
839 * active PP sequence before enabling AUX VDD.
840 */
841 if (!(I915_READ(PCH_PP_STATUS) & PP_ON))
842 msleep(dev_priv->panel_t3);
843
844 pp = I915_READ(PCH_PP_CONTROL);
845 pp &= ~PANEL_UNLOCK_MASK;
846 pp |= PANEL_UNLOCK_REGS;
847 pp |= EDP_FORCE_VDD;
848 I915_WRITE(PCH_PP_CONTROL, pp);
849 POSTING_READ(PCH_PP_CONTROL);
850 }
851
852 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp)
853 {
854 struct drm_device *dev = intel_dp->base.base.dev;
855 struct drm_i915_private *dev_priv = dev->dev_private;
856 u32 pp;
857
858 if (!is_edp(intel_dp))
859 return;
860 pp = I915_READ(PCH_PP_CONTROL);
861 pp &= ~PANEL_UNLOCK_MASK;
862 pp |= PANEL_UNLOCK_REGS;
863 pp &= ~EDP_FORCE_VDD;
864 I915_WRITE(PCH_PP_CONTROL, pp);
865 POSTING_READ(PCH_PP_CONTROL);
866
867 /* Make sure sequencer is idle before allowing subsequent activity */
868 msleep(dev_priv->panel_t12);
869 }
870
871 /* Returns true if the panel was already on when called */
872 static bool ironlake_edp_panel_on (struct intel_dp *intel_dp)
873 {
874 struct drm_device *dev = intel_dp->base.base.dev;
875 struct drm_i915_private *dev_priv = dev->dev_private;
876 u32 pp, idle_on_mask = PP_ON | PP_SEQUENCE_STATE_ON_IDLE;
877
878 if (!is_edp(intel_dp))
879 return;
880 if (I915_READ(PCH_PP_STATUS) & PP_ON)
881 return true;
882
883 pp = I915_READ(PCH_PP_CONTROL);
884 pp &= ~PANEL_UNLOCK_MASK;
885 pp |= PANEL_UNLOCK_REGS;
886
887 /* ILK workaround: disable reset around power sequence */
888 pp &= ~PANEL_POWER_RESET;
889 I915_WRITE(PCH_PP_CONTROL, pp);
890 POSTING_READ(PCH_PP_CONTROL);
891
892 pp |= POWER_TARGET_ON;
893 I915_WRITE(PCH_PP_CONTROL, pp);
894 POSTING_READ(PCH_PP_CONTROL);
895
896 if (wait_for((I915_READ(PCH_PP_STATUS) & idle_on_mask) == idle_on_mask,
897 5000))
898 DRM_ERROR("panel on wait timed out: 0x%08x\n",
899 I915_READ(PCH_PP_STATUS));
900
901 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
902 I915_WRITE(PCH_PP_CONTROL, pp);
903 POSTING_READ(PCH_PP_CONTROL);
904
905 return false;
906 }
907
908 static void ironlake_edp_panel_off (struct drm_device *dev)
909 {
910 struct drm_i915_private *dev_priv = dev->dev_private;
911 u32 pp, idle_off_mask = PP_ON | PP_SEQUENCE_MASK |
912 PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK;
913
914 if (!is_edp(intel_dp))
915 return;
916 pp = I915_READ(PCH_PP_CONTROL);
917 pp &= ~PANEL_UNLOCK_MASK;
918 pp |= PANEL_UNLOCK_REGS;
919
920 /* ILK workaround: disable reset around power sequence */
921 pp &= ~PANEL_POWER_RESET;
922 I915_WRITE(PCH_PP_CONTROL, pp);
923 POSTING_READ(PCH_PP_CONTROL);
924
925 pp &= ~POWER_TARGET_ON;
926 I915_WRITE(PCH_PP_CONTROL, pp);
927 POSTING_READ(PCH_PP_CONTROL);
928
929 if (wait_for((I915_READ(PCH_PP_STATUS) & idle_off_mask) == 0, 5000))
930 DRM_ERROR("panel off wait timed out: 0x%08x\n",
931 I915_READ(PCH_PP_STATUS));
932
933 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
934 I915_WRITE(PCH_PP_CONTROL, pp);
935 POSTING_READ(PCH_PP_CONTROL);
936 }
937
938 static void ironlake_edp_backlight_on (struct drm_device *dev)
939 {
940 struct drm_i915_private *dev_priv = dev->dev_private;
941 u32 pp;
942
943 DRM_DEBUG_KMS("\n");
944 /*
945 * If we enable the backlight right away following a panel power
946 * on, we may see slight flicker as the panel syncs with the eDP
947 * link. So delay a bit to make sure the image is solid before
948 * allowing it to appear.
949 */
950 msleep(300);
951 pp = I915_READ(PCH_PP_CONTROL);
952 pp &= ~PANEL_UNLOCK_MASK;
953 pp |= PANEL_UNLOCK_REGS;
954 pp |= EDP_BLC_ENABLE;
955 I915_WRITE(PCH_PP_CONTROL, pp);
956 }
957
958 static void ironlake_edp_backlight_off (struct drm_device *dev)
959 {
960 struct drm_i915_private *dev_priv = dev->dev_private;
961 u32 pp;
962
963 DRM_DEBUG_KMS("\n");
964 pp = I915_READ(PCH_PP_CONTROL);
965 pp &= ~PANEL_UNLOCK_MASK;
966 pp |= PANEL_UNLOCK_REGS;
967 pp &= ~EDP_BLC_ENABLE;
968 I915_WRITE(PCH_PP_CONTROL, pp);
969 }
970
971 static void ironlake_edp_pll_on(struct drm_encoder *encoder)
972 {
973 struct drm_device *dev = encoder->dev;
974 struct drm_i915_private *dev_priv = dev->dev_private;
975 u32 dpa_ctl;
976
977 DRM_DEBUG_KMS("\n");
978 dpa_ctl = I915_READ(DP_A);
979 dpa_ctl |= DP_PLL_ENABLE;
980 I915_WRITE(DP_A, dpa_ctl);
981 POSTING_READ(DP_A);
982 udelay(200);
983 }
984
985 static void ironlake_edp_pll_off(struct drm_encoder *encoder)
986 {
987 struct drm_device *dev = encoder->dev;
988 struct drm_i915_private *dev_priv = dev->dev_private;
989 u32 dpa_ctl;
990
991 dpa_ctl = I915_READ(DP_A);
992 dpa_ctl &= ~DP_PLL_ENABLE;
993 I915_WRITE(DP_A, dpa_ctl);
994 POSTING_READ(DP_A);
995 udelay(200);
996 }
997
998 /* If the sink supports it, try to set the power state appropriately */
999 static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1000 {
1001 int ret, i;
1002
1003 /* Should have a valid DPCD by this point */
1004 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1005 return;
1006
1007 if (mode != DRM_MODE_DPMS_ON) {
1008 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1009 DP_SET_POWER_D3);
1010 if (ret != 1)
1011 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1012 } else {
1013 /*
1014 * When turning on, we need to retry for 1ms to give the sink
1015 * time to wake up.
1016 */
1017 for (i = 0; i < 3; i++) {
1018 ret = intel_dp_aux_native_write_1(intel_dp,
1019 DP_SET_POWER,
1020 DP_SET_POWER_D0);
1021 if (ret == 1)
1022 break;
1023 msleep(1);
1024 }
1025 }
1026 }
1027
1028 static void intel_dp_prepare(struct drm_encoder *encoder)
1029 {
1030 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1031 struct drm_device *dev = encoder->dev;
1032
1033 /* Wake up the sink first */
1034 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1035
1036 if (is_edp(intel_dp)) {
1037 ironlake_edp_backlight_off(dev);
1038 ironlake_edp_panel_off(dev);
1039 if (!is_pch_edp(intel_dp))
1040 ironlake_edp_pll_on(encoder);
1041 else
1042 ironlake_edp_pll_off(encoder);
1043 }
1044 intel_dp_link_down(intel_dp);
1045 }
1046
1047 static void intel_dp_commit(struct drm_encoder *encoder)
1048 {
1049 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1050 struct drm_device *dev = encoder->dev;
1051
1052 ironlake_edp_panel_vdd_on(intel_dp);
1053
1054 intel_dp_start_link_train(intel_dp);
1055
1056 ironlake_edp_panel_on(intel_dp);
1057 ironlake_edp_panel_vdd_off(intel_dp);
1058
1059 intel_dp_complete_link_train(intel_dp);
1060
1061 if (is_edp(intel_dp))
1062 ironlake_edp_backlight_on(dev);
1063
1064 intel_dp->dpms_mode = DRM_MODE_DPMS_ON;
1065 }
1066
1067 static void
1068 intel_dp_dpms(struct drm_encoder *encoder, int mode)
1069 {
1070 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1071 struct drm_device *dev = encoder->dev;
1072 struct drm_i915_private *dev_priv = dev->dev_private;
1073 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1074
1075 if (mode != DRM_MODE_DPMS_ON) {
1076 ironlake_edp_panel_vdd_on(intel_dp);
1077 if (is_edp(intel_dp))
1078 ironlake_edp_backlight_off(dev);
1079 intel_dp_sink_dpms(intel_dp, mode);
1080 intel_dp_link_down(intel_dp);
1081 ironlake_edp_panel_off(dev);
1082 if (is_edp(intel_dp) && !is_pch_edp(intel_dp))
1083 ironlake_edp_pll_off(encoder);
1084 ironlake_edp_panel_vdd_off(intel_dp);
1085 } else {
1086 ironlake_edp_panel_vdd_on(intel_dp);
1087 intel_dp_sink_dpms(intel_dp, mode);
1088 if (!(dp_reg & DP_PORT_EN)) {
1089 intel_dp_start_link_train(intel_dp);
1090 ironlake_edp_panel_on(intel_dp);
1091 ironlake_edp_panel_vdd_off(intel_dp);
1092 intel_dp_complete_link_train(intel_dp);
1093 } else
1094 ironlake_edp_panel_vdd_off(intel_dp);
1095 if (is_edp(intel_dp))
1096 ironlake_edp_backlight_on(dev);
1097 }
1098 intel_dp->dpms_mode = mode;
1099 }
1100
1101 /*
1102 * Native read with retry for link status and receiver capability reads for
1103 * cases where the sink may still be asleep.
1104 */
1105 static bool
1106 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1107 uint8_t *recv, int recv_bytes)
1108 {
1109 int ret, i;
1110
1111 /*
1112 * Sinks are *supposed* to come up within 1ms from an off state,
1113 * but we're also supposed to retry 3 times per the spec.
1114 */
1115 for (i = 0; i < 3; i++) {
1116 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1117 recv_bytes);
1118 if (ret == recv_bytes)
1119 return true;
1120 msleep(1);
1121 }
1122
1123 return false;
1124 }
1125
1126 /*
1127 * Fetch AUX CH registers 0x202 - 0x207 which contain
1128 * link status information
1129 */
1130 static bool
1131 intel_dp_get_link_status(struct intel_dp *intel_dp)
1132 {
1133 return intel_dp_aux_native_read_retry(intel_dp,
1134 DP_LANE0_1_STATUS,
1135 intel_dp->link_status,
1136 DP_LINK_STATUS_SIZE);
1137 }
1138
1139 static uint8_t
1140 intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1141 int r)
1142 {
1143 return link_status[r - DP_LANE0_1_STATUS];
1144 }
1145
1146 static uint8_t
1147 intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
1148 int lane)
1149 {
1150 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1151 int s = ((lane & 1) ?
1152 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1153 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
1154 uint8_t l = intel_dp_link_status(link_status, i);
1155
1156 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1157 }
1158
1159 static uint8_t
1160 intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
1161 int lane)
1162 {
1163 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1164 int s = ((lane & 1) ?
1165 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1166 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
1167 uint8_t l = intel_dp_link_status(link_status, i);
1168
1169 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1170 }
1171
1172
1173 #if 0
1174 static char *voltage_names[] = {
1175 "0.4V", "0.6V", "0.8V", "1.2V"
1176 };
1177 static char *pre_emph_names[] = {
1178 "0dB", "3.5dB", "6dB", "9.5dB"
1179 };
1180 static char *link_train_names[] = {
1181 "pattern 1", "pattern 2", "idle", "off"
1182 };
1183 #endif
1184
1185 /*
1186 * These are source-specific values; current Intel hardware supports
1187 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1188 */
1189 #define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800
1190
1191 static uint8_t
1192 intel_dp_pre_emphasis_max(uint8_t voltage_swing)
1193 {
1194 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1195 case DP_TRAIN_VOLTAGE_SWING_400:
1196 return DP_TRAIN_PRE_EMPHASIS_6;
1197 case DP_TRAIN_VOLTAGE_SWING_600:
1198 return DP_TRAIN_PRE_EMPHASIS_6;
1199 case DP_TRAIN_VOLTAGE_SWING_800:
1200 return DP_TRAIN_PRE_EMPHASIS_3_5;
1201 case DP_TRAIN_VOLTAGE_SWING_1200:
1202 default:
1203 return DP_TRAIN_PRE_EMPHASIS_0;
1204 }
1205 }
1206
1207 static void
1208 intel_get_adjust_train(struct intel_dp *intel_dp)
1209 {
1210 uint8_t v = 0;
1211 uint8_t p = 0;
1212 int lane;
1213
1214 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1215 uint8_t this_v = intel_get_adjust_request_voltage(intel_dp->link_status, lane);
1216 uint8_t this_p = intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane);
1217
1218 if (this_v > v)
1219 v = this_v;
1220 if (this_p > p)
1221 p = this_p;
1222 }
1223
1224 if (v >= I830_DP_VOLTAGE_MAX)
1225 v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
1226
1227 if (p >= intel_dp_pre_emphasis_max(v))
1228 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1229
1230 for (lane = 0; lane < 4; lane++)
1231 intel_dp->train_set[lane] = v | p;
1232 }
1233
1234 static uint32_t
1235 intel_dp_signal_levels(uint8_t train_set, int lane_count)
1236 {
1237 uint32_t signal_levels = 0;
1238
1239 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1240 case DP_TRAIN_VOLTAGE_SWING_400:
1241 default:
1242 signal_levels |= DP_VOLTAGE_0_4;
1243 break;
1244 case DP_TRAIN_VOLTAGE_SWING_600:
1245 signal_levels |= DP_VOLTAGE_0_6;
1246 break;
1247 case DP_TRAIN_VOLTAGE_SWING_800:
1248 signal_levels |= DP_VOLTAGE_0_8;
1249 break;
1250 case DP_TRAIN_VOLTAGE_SWING_1200:
1251 signal_levels |= DP_VOLTAGE_1_2;
1252 break;
1253 }
1254 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1255 case DP_TRAIN_PRE_EMPHASIS_0:
1256 default:
1257 signal_levels |= DP_PRE_EMPHASIS_0;
1258 break;
1259 case DP_TRAIN_PRE_EMPHASIS_3_5:
1260 signal_levels |= DP_PRE_EMPHASIS_3_5;
1261 break;
1262 case DP_TRAIN_PRE_EMPHASIS_6:
1263 signal_levels |= DP_PRE_EMPHASIS_6;
1264 break;
1265 case DP_TRAIN_PRE_EMPHASIS_9_5:
1266 signal_levels |= DP_PRE_EMPHASIS_9_5;
1267 break;
1268 }
1269 return signal_levels;
1270 }
1271
1272 /* Gen6's DP voltage swing and pre-emphasis control */
1273 static uint32_t
1274 intel_gen6_edp_signal_levels(uint8_t train_set)
1275 {
1276 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1277 DP_TRAIN_PRE_EMPHASIS_MASK);
1278 switch (signal_levels) {
1279 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1280 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1281 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1282 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1283 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1284 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1285 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1286 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1287 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1288 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1289 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1290 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1291 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1292 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1293 default:
1294 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1295 "0x%x\n", signal_levels);
1296 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1297 }
1298 }
1299
1300 static uint8_t
1301 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1302 int lane)
1303 {
1304 int i = DP_LANE0_1_STATUS + (lane >> 1);
1305 int s = (lane & 1) * 4;
1306 uint8_t l = intel_dp_link_status(link_status, i);
1307
1308 return (l >> s) & 0xf;
1309 }
1310
1311 /* Check for clock recovery is done on all channels */
1312 static bool
1313 intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1314 {
1315 int lane;
1316 uint8_t lane_status;
1317
1318 for (lane = 0; lane < lane_count; lane++) {
1319 lane_status = intel_get_lane_status(link_status, lane);
1320 if ((lane_status & DP_LANE_CR_DONE) == 0)
1321 return false;
1322 }
1323 return true;
1324 }
1325
1326 /* Check to see if channel eq is done on all channels */
1327 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1328 DP_LANE_CHANNEL_EQ_DONE|\
1329 DP_LANE_SYMBOL_LOCKED)
1330 static bool
1331 intel_channel_eq_ok(struct intel_dp *intel_dp)
1332 {
1333 uint8_t lane_align;
1334 uint8_t lane_status;
1335 int lane;
1336
1337 lane_align = intel_dp_link_status(intel_dp->link_status,
1338 DP_LANE_ALIGN_STATUS_UPDATED);
1339 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1340 return false;
1341 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1342 lane_status = intel_get_lane_status(intel_dp->link_status, lane);
1343 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1344 return false;
1345 }
1346 return true;
1347 }
1348
1349 static bool
1350 intel_dp_set_link_train(struct intel_dp *intel_dp,
1351 uint32_t dp_reg_value,
1352 uint8_t dp_train_pat)
1353 {
1354 struct drm_device *dev = intel_dp->base.base.dev;
1355 struct drm_i915_private *dev_priv = dev->dev_private;
1356 int ret;
1357
1358 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1359 POSTING_READ(intel_dp->output_reg);
1360
1361 intel_dp_aux_native_write_1(intel_dp,
1362 DP_TRAINING_PATTERN_SET,
1363 dp_train_pat);
1364
1365 ret = intel_dp_aux_native_write(intel_dp,
1366 DP_TRAINING_LANE0_SET,
1367 intel_dp->train_set, 4);
1368 if (ret != 4)
1369 return false;
1370
1371 return true;
1372 }
1373
1374 /* Enable corresponding port and start training pattern 1 */
1375 static void
1376 intel_dp_start_link_train(struct intel_dp *intel_dp)
1377 {
1378 struct drm_device *dev = intel_dp->base.base.dev;
1379 struct drm_i915_private *dev_priv = dev->dev_private;
1380 struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
1381 int i;
1382 uint8_t voltage;
1383 bool clock_recovery = false;
1384 int tries;
1385 u32 reg;
1386 uint32_t DP = intel_dp->DP;
1387
1388 /*
1389 * On CPT we have to enable the port in training pattern 1, which
1390 * will happen below in intel_dp_set_link_train. Otherwise, enable
1391 * the port and wait for it to become active.
1392 */
1393 if (!HAS_PCH_CPT(dev)) {
1394 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
1395 POSTING_READ(intel_dp->output_reg);
1396 intel_wait_for_vblank(dev, intel_crtc->pipe);
1397 }
1398
1399 /* Write the link configuration data */
1400 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1401 intel_dp->link_configuration,
1402 DP_LINK_CONFIGURATION_SIZE);
1403
1404 DP |= DP_PORT_EN;
1405 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1406 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1407 else
1408 DP &= ~DP_LINK_TRAIN_MASK;
1409 memset(intel_dp->train_set, 0, 4);
1410 voltage = 0xff;
1411 tries = 0;
1412 clock_recovery = false;
1413 for (;;) {
1414 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1415 uint32_t signal_levels;
1416 if (IS_GEN6(dev) && is_edp(intel_dp)) {
1417 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1418 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1419 } else {
1420 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);
1421 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1422 }
1423
1424 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1425 reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1426 else
1427 reg = DP | DP_LINK_TRAIN_PAT_1;
1428
1429 if (!intel_dp_set_link_train(intel_dp, reg,
1430 DP_TRAINING_PATTERN_1 |
1431 DP_LINK_SCRAMBLING_DISABLE))
1432 break;
1433 /* Set training pattern 1 */
1434
1435 udelay(100);
1436 if (!intel_dp_get_link_status(intel_dp))
1437 break;
1438
1439 if (intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
1440 clock_recovery = true;
1441 break;
1442 }
1443
1444 /* Check to see if we've tried the max voltage */
1445 for (i = 0; i < intel_dp->lane_count; i++)
1446 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1447 break;
1448 if (i == intel_dp->lane_count)
1449 break;
1450
1451 /* Check to see if we've tried the same voltage 5 times */
1452 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1453 ++tries;
1454 if (tries == 5)
1455 break;
1456 } else
1457 tries = 0;
1458 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1459
1460 /* Compute new intel_dp->train_set as requested by target */
1461 intel_get_adjust_train(intel_dp);
1462 }
1463
1464 intel_dp->DP = DP;
1465 }
1466
1467 static void
1468 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1469 {
1470 struct drm_device *dev = intel_dp->base.base.dev;
1471 struct drm_i915_private *dev_priv = dev->dev_private;
1472 bool channel_eq = false;
1473 int tries, cr_tries;
1474 u32 reg;
1475 uint32_t DP = intel_dp->DP;
1476
1477 /* channel equalization */
1478 tries = 0;
1479 cr_tries = 0;
1480 channel_eq = false;
1481 for (;;) {
1482 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1483 uint32_t signal_levels;
1484
1485 if (cr_tries > 5) {
1486 DRM_ERROR("failed to train DP, aborting\n");
1487 intel_dp_link_down(intel_dp);
1488 break;
1489 }
1490
1491 if (IS_GEN6(dev) && is_edp(intel_dp)) {
1492 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1493 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1494 } else {
1495 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);
1496 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1497 }
1498
1499 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1500 reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1501 else
1502 reg = DP | DP_LINK_TRAIN_PAT_2;
1503
1504 /* channel eq pattern */
1505 if (!intel_dp_set_link_train(intel_dp, reg,
1506 DP_TRAINING_PATTERN_2 |
1507 DP_LINK_SCRAMBLING_DISABLE))
1508 break;
1509
1510 udelay(400);
1511 if (!intel_dp_get_link_status(intel_dp))
1512 break;
1513
1514 /* Make sure clock is still ok */
1515 if (!intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
1516 intel_dp_start_link_train(intel_dp);
1517 cr_tries++;
1518 continue;
1519 }
1520
1521 if (intel_channel_eq_ok(intel_dp)) {
1522 channel_eq = true;
1523 break;
1524 }
1525
1526 /* Try 5 times, then try clock recovery if that fails */
1527 if (tries > 5) {
1528 intel_dp_link_down(intel_dp);
1529 intel_dp_start_link_train(intel_dp);
1530 tries = 0;
1531 cr_tries++;
1532 continue;
1533 }
1534
1535 /* Compute new intel_dp->train_set as requested by target */
1536 intel_get_adjust_train(intel_dp);
1537 ++tries;
1538 }
1539
1540 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1541 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1542 else
1543 reg = DP | DP_LINK_TRAIN_OFF;
1544
1545 I915_WRITE(intel_dp->output_reg, reg);
1546 POSTING_READ(intel_dp->output_reg);
1547 intel_dp_aux_native_write_1(intel_dp,
1548 DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1549 }
1550
1551 static void
1552 intel_dp_link_down(struct intel_dp *intel_dp)
1553 {
1554 struct drm_device *dev = intel_dp->base.base.dev;
1555 struct drm_i915_private *dev_priv = dev->dev_private;
1556 uint32_t DP = intel_dp->DP;
1557
1558 if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
1559 return;
1560
1561 DRM_DEBUG_KMS("\n");
1562
1563 if (is_edp(intel_dp)) {
1564 DP &= ~DP_PLL_ENABLE;
1565 I915_WRITE(intel_dp->output_reg, DP);
1566 POSTING_READ(intel_dp->output_reg);
1567 udelay(100);
1568 }
1569
1570 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) {
1571 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1572 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1573 } else {
1574 DP &= ~DP_LINK_TRAIN_MASK;
1575 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1576 }
1577 POSTING_READ(intel_dp->output_reg);
1578
1579 msleep(17);
1580
1581 if (is_edp(intel_dp))
1582 DP |= DP_LINK_TRAIN_OFF;
1583
1584 if (!HAS_PCH_CPT(dev) &&
1585 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
1586 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1587
1588 /* Hardware workaround: leaving our transcoder select
1589 * set to transcoder B while it's off will prevent the
1590 * corresponding HDMI output on transcoder A.
1591 *
1592 * Combine this with another hardware workaround:
1593 * transcoder select bit can only be cleared while the
1594 * port is enabled.
1595 */
1596 DP &= ~DP_PIPEB_SELECT;
1597 I915_WRITE(intel_dp->output_reg, DP);
1598
1599 /* Changes to enable or select take place the vblank
1600 * after being written.
1601 */
1602 if (crtc == NULL) {
1603 /* We can arrive here never having been attached
1604 * to a CRTC, for instance, due to inheriting
1605 * random state from the BIOS.
1606 *
1607 * If the pipe is not running, play safe and
1608 * wait for the clocks to stabilise before
1609 * continuing.
1610 */
1611 POSTING_READ(intel_dp->output_reg);
1612 msleep(50);
1613 } else
1614 intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
1615 }
1616
1617 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1618 POSTING_READ(intel_dp->output_reg);
1619 }
1620
1621 static bool
1622 intel_dp_get_dpcd(struct intel_dp *intel_dp)
1623 {
1624 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
1625 sizeof (intel_dp->dpcd)) &&
1626 (intel_dp->dpcd[DP_DPCD_REV] != 0)) {
1627 return true;
1628 }
1629
1630 return false;
1631 }
1632
1633 /*
1634 * According to DP spec
1635 * 5.1.2:
1636 * 1. Read DPCD
1637 * 2. Configure link according to Receiver Capabilities
1638 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
1639 * 4. Check link status on receipt of hot-plug interrupt
1640 */
1641
1642 static void
1643 intel_dp_check_link_status(struct intel_dp *intel_dp)
1644 {
1645 if (intel_dp->dpms_mode != DRM_MODE_DPMS_ON)
1646 return;
1647
1648 if (!intel_dp->base.base.crtc)
1649 return;
1650
1651 /* Try to read receiver status if the link appears to be up */
1652 if (!intel_dp_get_link_status(intel_dp)) {
1653 intel_dp_link_down(intel_dp);
1654 return;
1655 }
1656
1657 /* Now read the DPCD to see if it's actually running */
1658 if (!intel_dp_get_dpcd(intel_dp)) {
1659 intel_dp_link_down(intel_dp);
1660 return;
1661 }
1662
1663 if (!intel_channel_eq_ok(intel_dp)) {
1664 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
1665 drm_get_encoder_name(&intel_dp->base.base));
1666 intel_dp_start_link_train(intel_dp);
1667 intel_dp_complete_link_train(intel_dp);
1668 }
1669 }
1670
1671 static enum drm_connector_status
1672 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
1673 {
1674 if (intel_dp_get_dpcd(intel_dp))
1675 return connector_status_connected;
1676 return connector_status_disconnected;
1677 }
1678
1679 static enum drm_connector_status
1680 ironlake_dp_detect(struct intel_dp *intel_dp)
1681 {
1682 enum drm_connector_status status;
1683
1684 /* Can't disconnect eDP, but you can close the lid... */
1685 if (is_edp(intel_dp)) {
1686 status = intel_panel_detect(intel_dp->base.base.dev);
1687 if (status == connector_status_unknown)
1688 status = connector_status_connected;
1689 return status;
1690 }
1691
1692 return intel_dp_detect_dpcd(intel_dp);
1693 }
1694
1695 static enum drm_connector_status
1696 g4x_dp_detect(struct intel_dp *intel_dp)
1697 {
1698 struct drm_device *dev = intel_dp->base.base.dev;
1699 struct drm_i915_private *dev_priv = dev->dev_private;
1700 uint32_t temp, bit;
1701
1702 switch (intel_dp->output_reg) {
1703 case DP_B:
1704 bit = DPB_HOTPLUG_INT_STATUS;
1705 break;
1706 case DP_C:
1707 bit = DPC_HOTPLUG_INT_STATUS;
1708 break;
1709 case DP_D:
1710 bit = DPD_HOTPLUG_INT_STATUS;
1711 break;
1712 default:
1713 return connector_status_unknown;
1714 }
1715
1716 temp = I915_READ(PORT_HOTPLUG_STAT);
1717
1718 if ((temp & bit) == 0)
1719 return connector_status_disconnected;
1720
1721 return intel_dp_detect_dpcd(intel_dp);
1722 }
1723
1724 /**
1725 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1726 *
1727 * \return true if DP port is connected.
1728 * \return false if DP port is disconnected.
1729 */
1730 static enum drm_connector_status
1731 intel_dp_detect(struct drm_connector *connector, bool force)
1732 {
1733 struct intel_dp *intel_dp = intel_attached_dp(connector);
1734 struct drm_device *dev = intel_dp->base.base.dev;
1735 enum drm_connector_status status;
1736 struct edid *edid = NULL;
1737
1738 intel_dp->has_audio = false;
1739
1740 if (HAS_PCH_SPLIT(dev))
1741 status = ironlake_dp_detect(intel_dp);
1742 else
1743 status = g4x_dp_detect(intel_dp);
1744
1745 DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
1746 intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
1747 intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
1748 intel_dp->dpcd[6], intel_dp->dpcd[7]);
1749
1750 if (status != connector_status_connected)
1751 return status;
1752
1753 if (intel_dp->force_audio) {
1754 intel_dp->has_audio = intel_dp->force_audio > 0;
1755 } else {
1756 edid = drm_get_edid(connector, &intel_dp->adapter);
1757 if (edid) {
1758 intel_dp->has_audio = drm_detect_monitor_audio(edid);
1759 connector->display_info.raw_edid = NULL;
1760 kfree(edid);
1761 }
1762 }
1763
1764 return connector_status_connected;
1765 }
1766
1767 static int intel_dp_get_modes(struct drm_connector *connector)
1768 {
1769 struct intel_dp *intel_dp = intel_attached_dp(connector);
1770 struct drm_device *dev = intel_dp->base.base.dev;
1771 struct drm_i915_private *dev_priv = dev->dev_private;
1772 int ret;
1773
1774 /* We should parse the EDID data and find out if it has an audio sink
1775 */
1776
1777 ret = intel_ddc_get_modes(connector, &intel_dp->adapter);
1778 if (ret) {
1779 if (is_edp(intel_dp) && !dev_priv->panel_fixed_mode) {
1780 struct drm_display_mode *newmode;
1781 list_for_each_entry(newmode, &connector->probed_modes,
1782 head) {
1783 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
1784 dev_priv->panel_fixed_mode =
1785 drm_mode_duplicate(dev, newmode);
1786 break;
1787 }
1788 }
1789 }
1790
1791 return ret;
1792 }
1793
1794 /* if eDP has no EDID, try to use fixed panel mode from VBT */
1795 if (is_edp(intel_dp)) {
1796 /* initialize panel mode from VBT if available for eDP */
1797 if (dev_priv->panel_fixed_mode == NULL && dev_priv->lfp_lvds_vbt_mode != NULL) {
1798 dev_priv->panel_fixed_mode =
1799 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
1800 if (dev_priv->panel_fixed_mode) {
1801 dev_priv->panel_fixed_mode->type |=
1802 DRM_MODE_TYPE_PREFERRED;
1803 }
1804 }
1805 if (dev_priv->panel_fixed_mode) {
1806 struct drm_display_mode *mode;
1807 mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode);
1808 drm_mode_probed_add(connector, mode);
1809 return 1;
1810 }
1811 }
1812 return 0;
1813 }
1814
1815 static bool
1816 intel_dp_detect_audio(struct drm_connector *connector)
1817 {
1818 struct intel_dp *intel_dp = intel_attached_dp(connector);
1819 struct edid *edid;
1820 bool has_audio = false;
1821
1822 edid = drm_get_edid(connector, &intel_dp->adapter);
1823 if (edid) {
1824 has_audio = drm_detect_monitor_audio(edid);
1825
1826 connector->display_info.raw_edid = NULL;
1827 kfree(edid);
1828 }
1829
1830 return has_audio;
1831 }
1832
1833 static int
1834 intel_dp_set_property(struct drm_connector *connector,
1835 struct drm_property *property,
1836 uint64_t val)
1837 {
1838 struct drm_i915_private *dev_priv = connector->dev->dev_private;
1839 struct intel_dp *intel_dp = intel_attached_dp(connector);
1840 int ret;
1841
1842 ret = drm_connector_property_set_value(connector, property, val);
1843 if (ret)
1844 return ret;
1845
1846 if (property == dev_priv->force_audio_property) {
1847 int i = val;
1848 bool has_audio;
1849
1850 if (i == intel_dp->force_audio)
1851 return 0;
1852
1853 intel_dp->force_audio = i;
1854
1855 if (i == 0)
1856 has_audio = intel_dp_detect_audio(connector);
1857 else
1858 has_audio = i > 0;
1859
1860 if (has_audio == intel_dp->has_audio)
1861 return 0;
1862
1863 intel_dp->has_audio = has_audio;
1864 goto done;
1865 }
1866
1867 if (property == dev_priv->broadcast_rgb_property) {
1868 if (val == !!intel_dp->color_range)
1869 return 0;
1870
1871 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
1872 goto done;
1873 }
1874
1875 return -EINVAL;
1876
1877 done:
1878 if (intel_dp->base.base.crtc) {
1879 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1880 drm_crtc_helper_set_mode(crtc, &crtc->mode,
1881 crtc->x, crtc->y,
1882 crtc->fb);
1883 }
1884
1885 return 0;
1886 }
1887
1888 static void
1889 intel_dp_destroy (struct drm_connector *connector)
1890 {
1891 struct drm_device *dev = connector->dev;
1892
1893 if (intel_dpd_is_edp(dev))
1894 intel_panel_destroy_backlight(dev);
1895
1896 drm_sysfs_connector_remove(connector);
1897 drm_connector_cleanup(connector);
1898 kfree(connector);
1899 }
1900
1901 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
1902 {
1903 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1904
1905 i2c_del_adapter(&intel_dp->adapter);
1906 drm_encoder_cleanup(encoder);
1907 kfree(intel_dp);
1908 }
1909
1910 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
1911 .dpms = intel_dp_dpms,
1912 .mode_fixup = intel_dp_mode_fixup,
1913 .prepare = intel_dp_prepare,
1914 .mode_set = intel_dp_mode_set,
1915 .commit = intel_dp_commit,
1916 };
1917
1918 static const struct drm_connector_funcs intel_dp_connector_funcs = {
1919 .dpms = drm_helper_connector_dpms,
1920 .detect = intel_dp_detect,
1921 .fill_modes = drm_helper_probe_single_connector_modes,
1922 .set_property = intel_dp_set_property,
1923 .destroy = intel_dp_destroy,
1924 };
1925
1926 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
1927 .get_modes = intel_dp_get_modes,
1928 .mode_valid = intel_dp_mode_valid,
1929 .best_encoder = intel_best_encoder,
1930 };
1931
1932 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
1933 .destroy = intel_dp_encoder_destroy,
1934 };
1935
1936 static void
1937 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
1938 {
1939 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
1940
1941 intel_dp_check_link_status(intel_dp);
1942 }
1943
1944 /* Return which DP Port should be selected for Transcoder DP control */
1945 int
1946 intel_trans_dp_port_sel (struct drm_crtc *crtc)
1947 {
1948 struct drm_device *dev = crtc->dev;
1949 struct drm_mode_config *mode_config = &dev->mode_config;
1950 struct drm_encoder *encoder;
1951
1952 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
1953 struct intel_dp *intel_dp;
1954
1955 if (encoder->crtc != crtc)
1956 continue;
1957
1958 intel_dp = enc_to_intel_dp(encoder);
1959 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT)
1960 return intel_dp->output_reg;
1961 }
1962
1963 return -1;
1964 }
1965
1966 /* check the VBT to see whether the eDP is on DP-D port */
1967 bool intel_dpd_is_edp(struct drm_device *dev)
1968 {
1969 struct drm_i915_private *dev_priv = dev->dev_private;
1970 struct child_device_config *p_child;
1971 int i;
1972
1973 if (!dev_priv->child_dev_num)
1974 return false;
1975
1976 for (i = 0; i < dev_priv->child_dev_num; i++) {
1977 p_child = dev_priv->child_dev + i;
1978
1979 if (p_child->dvo_port == PORT_IDPD &&
1980 p_child->device_type == DEVICE_TYPE_eDP)
1981 return true;
1982 }
1983 return false;
1984 }
1985
1986 static void
1987 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
1988 {
1989 intel_attach_force_audio_property(connector);
1990 intel_attach_broadcast_rgb_property(connector);
1991 }
1992
1993 void
1994 intel_dp_init(struct drm_device *dev, int output_reg)
1995 {
1996 struct drm_i915_private *dev_priv = dev->dev_private;
1997 struct drm_connector *connector;
1998 struct intel_dp *intel_dp;
1999 struct intel_encoder *intel_encoder;
2000 struct intel_connector *intel_connector;
2001 const char *name = NULL;
2002 int type;
2003
2004 intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
2005 if (!intel_dp)
2006 return;
2007
2008 intel_dp->output_reg = output_reg;
2009 intel_dp->dpms_mode = -1;
2010
2011 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2012 if (!intel_connector) {
2013 kfree(intel_dp);
2014 return;
2015 }
2016 intel_encoder = &intel_dp->base;
2017
2018 if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
2019 if (intel_dpd_is_edp(dev))
2020 intel_dp->is_pch_edp = true;
2021
2022 if (output_reg == DP_A || is_pch_edp(intel_dp)) {
2023 type = DRM_MODE_CONNECTOR_eDP;
2024 intel_encoder->type = INTEL_OUTPUT_EDP;
2025 } else {
2026 type = DRM_MODE_CONNECTOR_DisplayPort;
2027 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2028 }
2029
2030 connector = &intel_connector->base;
2031 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
2032 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2033
2034 connector->polled = DRM_CONNECTOR_POLL_HPD;
2035
2036 if (output_reg == DP_B || output_reg == PCH_DP_B)
2037 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
2038 else if (output_reg == DP_C || output_reg == PCH_DP_C)
2039 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
2040 else if (output_reg == DP_D || output_reg == PCH_DP_D)
2041 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
2042
2043 if (is_edp(intel_dp))
2044 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
2045
2046 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
2047 connector->interlace_allowed = true;
2048 connector->doublescan_allowed = 0;
2049
2050 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
2051 DRM_MODE_ENCODER_TMDS);
2052 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
2053
2054 intel_connector_attach_encoder(intel_connector, intel_encoder);
2055 drm_sysfs_connector_add(connector);
2056
2057 /* Set up the DDC bus. */
2058 switch (output_reg) {
2059 case DP_A:
2060 name = "DPDDC-A";
2061 break;
2062 case DP_B:
2063 case PCH_DP_B:
2064 dev_priv->hotplug_supported_mask |=
2065 HDMIB_HOTPLUG_INT_STATUS;
2066 name = "DPDDC-B";
2067 break;
2068 case DP_C:
2069 case PCH_DP_C:
2070 dev_priv->hotplug_supported_mask |=
2071 HDMIC_HOTPLUG_INT_STATUS;
2072 name = "DPDDC-C";
2073 break;
2074 case DP_D:
2075 case PCH_DP_D:
2076 dev_priv->hotplug_supported_mask |=
2077 HDMID_HOTPLUG_INT_STATUS;
2078 name = "DPDDC-D";
2079 break;
2080 }
2081
2082 /* Cache some DPCD data in the eDP case */
2083 if (is_edp(intel_dp)) {
2084 bool ret;
2085 u32 pp_on, pp_div;
2086
2087 pp_on = I915_READ(PCH_PP_ON_DELAYS);
2088 pp_div = I915_READ(PCH_PP_DIVISOR);
2089
2090 /* Get T3 & T12 values (note: VESA not bspec terminology) */
2091 dev_priv->panel_t3 = (pp_on & 0x1fff0000) >> 16;
2092 dev_priv->panel_t3 /= 10; /* t3 in 100us units */
2093 dev_priv->panel_t12 = pp_div & 0xf;
2094 dev_priv->panel_t12 *= 100; /* t12 in 100ms units */
2095
2096 ironlake_edp_panel_vdd_on(intel_dp);
2097 ret = intel_dp_get_dpcd(intel_dp);
2098 ironlake_edp_panel_vdd_off(intel_dp);
2099 if (ret) {
2100 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2101 dev_priv->no_aux_handshake =
2102 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
2103 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2104 } else {
2105 /* if this fails, presume the device is a ghost */
2106 DRM_INFO("failed to retrieve link info, disabling eDP\n");
2107 intel_dp_encoder_destroy(&intel_dp->base.base);
2108 intel_dp_destroy(&intel_connector->base);
2109 return;
2110 }
2111 }
2112
2113 intel_dp_i2c_init(intel_dp, intel_connector, name);
2114
2115 intel_encoder->hot_plug = intel_dp_hot_plug;
2116
2117 if (is_edp(intel_dp)) {
2118 dev_priv->int_edp_connector = connector;
2119 intel_panel_setup_backlight(dev);
2120 }
2121
2122 intel_dp_add_properties(intel_dp, connector);
2123
2124 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2125 * 0xd. Failure to do so will result in spurious interrupts being
2126 * generated on the port when a cable is not attached.
2127 */
2128 if (IS_G4X(dev) && !IS_GM45(dev)) {
2129 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2130 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2131 }
2132 }
Linus' kernel tree