2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
3 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
4 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
5 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
7 Based on the original rt2800pci.c and rt2800usb.c.
8 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
9 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
10 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
11 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
12 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
13 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
14 <http://rt2x00.serialmonkey.com>
16 This program is free software; you can redistribute it and/or modify
17 it under the terms of the GNU General Public License as published by
18 the Free Software Foundation; either version 2 of the License, or
19 (at your option) any later version.
21 This program is distributed in the hope that it will be useful,
22 but WITHOUT ANY WARRANTY; without even the implied warranty of
23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 GNU General Public License for more details.
26 You should have received a copy of the GNU General Public License
27 along with this program; if not, write to the
28 Free Software Foundation, Inc.,
29 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
34 Abstract: rt2800 generic device routines.
37 #include <linux/crc-ccitt.h>
38 #include <linux/kernel.h>
39 #include <linux/module.h>
40 #include <linux/slab.h>
43 #include "rt2800lib.h"
48 * All access to the CSR registers will go through the methods
49 * rt2800_register_read and rt2800_register_write.
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
58 * The _lock versions must be used if you already hold the csr_mutex
60 #define WAIT_FOR_BBP(__dev, __reg) \
61 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
62 #define WAIT_FOR_RFCSR(__dev, __reg) \
63 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
64 #define WAIT_FOR_RF(__dev, __reg) \
65 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
66 #define WAIT_FOR_MCU(__dev, __reg) \
67 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
68 H2M_MAILBOX_CSR_OWNER, (__reg))
70 static inline bool rt2800_is_305x_soc(struct rt2x00_dev
*rt2x00dev
)
72 /* check for rt2872 on SoC */
73 if (!rt2x00_is_soc(rt2x00dev
) ||
74 !rt2x00_rt(rt2x00dev
, RT2872
))
77 /* we know for sure that these rf chipsets are used on rt305x boards */
78 if (rt2x00_rf(rt2x00dev
, RF3020
) ||
79 rt2x00_rf(rt2x00dev
, RF3021
) ||
80 rt2x00_rf(rt2x00dev
, RF3022
))
83 NOTICE(rt2x00dev
, "Unknown RF chipset on rt305x\n");
87 static void rt2800_bbp_write(struct rt2x00_dev
*rt2x00dev
,
88 const unsigned int word
, const u8 value
)
92 mutex_lock(&rt2x00dev
->csr_mutex
);
95 * Wait until the BBP becomes available, afterwards we
96 * can safely write the new data into the register.
98 if (WAIT_FOR_BBP(rt2x00dev
, ®
)) {
100 rt2x00_set_field32(®
, BBP_CSR_CFG_VALUE
, value
);
101 rt2x00_set_field32(®
, BBP_CSR_CFG_REGNUM
, word
);
102 rt2x00_set_field32(®
, BBP_CSR_CFG_BUSY
, 1);
103 rt2x00_set_field32(®
, BBP_CSR_CFG_READ_CONTROL
, 0);
104 rt2x00_set_field32(®
, BBP_CSR_CFG_BBP_RW_MODE
, 1);
106 rt2800_register_write_lock(rt2x00dev
, BBP_CSR_CFG
, reg
);
109 mutex_unlock(&rt2x00dev
->csr_mutex
);
112 static void rt2800_bbp_read(struct rt2x00_dev
*rt2x00dev
,
113 const unsigned int word
, u8
*value
)
117 mutex_lock(&rt2x00dev
->csr_mutex
);
120 * Wait until the BBP becomes available, afterwards we
121 * can safely write the read request into the register.
122 * After the data has been written, we wait until hardware
123 * returns the correct value, if at any time the register
124 * doesn't become available in time, reg will be 0xffffffff
125 * which means we return 0xff to the caller.
127 if (WAIT_FOR_BBP(rt2x00dev
, ®
)) {
129 rt2x00_set_field32(®
, BBP_CSR_CFG_REGNUM
, word
);
130 rt2x00_set_field32(®
, BBP_CSR_CFG_BUSY
, 1);
131 rt2x00_set_field32(®
, BBP_CSR_CFG_READ_CONTROL
, 1);
132 rt2x00_set_field32(®
, BBP_CSR_CFG_BBP_RW_MODE
, 1);
134 rt2800_register_write_lock(rt2x00dev
, BBP_CSR_CFG
, reg
);
136 WAIT_FOR_BBP(rt2x00dev
, ®
);
139 *value
= rt2x00_get_field32(reg
, BBP_CSR_CFG_VALUE
);
141 mutex_unlock(&rt2x00dev
->csr_mutex
);
144 static void rt2800_rfcsr_write(struct rt2x00_dev
*rt2x00dev
,
145 const unsigned int word
, const u8 value
)
149 mutex_lock(&rt2x00dev
->csr_mutex
);
152 * Wait until the RFCSR becomes available, afterwards we
153 * can safely write the new data into the register.
155 if (WAIT_FOR_RFCSR(rt2x00dev
, ®
)) {
157 rt2x00_set_field32(®
, RF_CSR_CFG_DATA
, value
);
158 rt2x00_set_field32(®
, RF_CSR_CFG_REGNUM
, word
);
159 rt2x00_set_field32(®
, RF_CSR_CFG_WRITE
, 1);
160 rt2x00_set_field32(®
, RF_CSR_CFG_BUSY
, 1);
162 rt2800_register_write_lock(rt2x00dev
, RF_CSR_CFG
, reg
);
165 mutex_unlock(&rt2x00dev
->csr_mutex
);
168 static void rt2800_rfcsr_read(struct rt2x00_dev
*rt2x00dev
,
169 const unsigned int word
, u8
*value
)
173 mutex_lock(&rt2x00dev
->csr_mutex
);
176 * Wait until the RFCSR becomes available, afterwards we
177 * can safely write the read request into the register.
178 * After the data has been written, we wait until hardware
179 * returns the correct value, if at any time the register
180 * doesn't become available in time, reg will be 0xffffffff
181 * which means we return 0xff to the caller.
183 if (WAIT_FOR_RFCSR(rt2x00dev
, ®
)) {
185 rt2x00_set_field32(®
, RF_CSR_CFG_REGNUM
, word
);
186 rt2x00_set_field32(®
, RF_CSR_CFG_WRITE
, 0);
187 rt2x00_set_field32(®
, RF_CSR_CFG_BUSY
, 1);
189 rt2800_register_write_lock(rt2x00dev
, RF_CSR_CFG
, reg
);
191 WAIT_FOR_RFCSR(rt2x00dev
, ®
);
194 *value
= rt2x00_get_field32(reg
, RF_CSR_CFG_DATA
);
196 mutex_unlock(&rt2x00dev
->csr_mutex
);
199 static void rt2800_rf_write(struct rt2x00_dev
*rt2x00dev
,
200 const unsigned int word
, const u32 value
)
204 mutex_lock(&rt2x00dev
->csr_mutex
);
207 * Wait until the RF becomes available, afterwards we
208 * can safely write the new data into the register.
210 if (WAIT_FOR_RF(rt2x00dev
, ®
)) {
212 rt2x00_set_field32(®
, RF_CSR_CFG0_REG_VALUE_BW
, value
);
213 rt2x00_set_field32(®
, RF_CSR_CFG0_STANDBYMODE
, 0);
214 rt2x00_set_field32(®
, RF_CSR_CFG0_SEL
, 0);
215 rt2x00_set_field32(®
, RF_CSR_CFG0_BUSY
, 1);
217 rt2800_register_write_lock(rt2x00dev
, RF_CSR_CFG0
, reg
);
218 rt2x00_rf_write(rt2x00dev
, word
, value
);
221 mutex_unlock(&rt2x00dev
->csr_mutex
);
224 void rt2800_mcu_request(struct rt2x00_dev
*rt2x00dev
,
225 const u8 command
, const u8 token
,
226 const u8 arg0
, const u8 arg1
)
231 * SOC devices don't support MCU requests.
233 if (rt2x00_is_soc(rt2x00dev
))
236 mutex_lock(&rt2x00dev
->csr_mutex
);
239 * Wait until the MCU becomes available, afterwards we
240 * can safely write the new data into the register.
242 if (WAIT_FOR_MCU(rt2x00dev
, ®
)) {
243 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_OWNER
, 1);
244 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_CMD_TOKEN
, token
);
245 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_ARG0
, arg0
);
246 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_ARG1
, arg1
);
247 rt2800_register_write_lock(rt2x00dev
, H2M_MAILBOX_CSR
, reg
);
250 rt2x00_set_field32(®
, HOST_CMD_CSR_HOST_COMMAND
, command
);
251 rt2800_register_write_lock(rt2x00dev
, HOST_CMD_CSR
, reg
);
254 mutex_unlock(&rt2x00dev
->csr_mutex
);
256 EXPORT_SYMBOL_GPL(rt2800_mcu_request
);
258 int rt2800_wait_csr_ready(struct rt2x00_dev
*rt2x00dev
)
263 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
264 rt2800_register_read(rt2x00dev
, MAC_CSR0
, ®
);
265 if (reg
&& reg
!= ~0)
270 ERROR(rt2x00dev
, "Unstable hardware.\n");
273 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready
);
275 int rt2800_wait_wpdma_ready(struct rt2x00_dev
*rt2x00dev
)
281 * Some devices are really slow to respond here. Wait a whole second
284 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
285 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
286 if (!rt2x00_get_field32(reg
, WPDMA_GLO_CFG_TX_DMA_BUSY
) &&
287 !rt2x00_get_field32(reg
, WPDMA_GLO_CFG_RX_DMA_BUSY
))
293 ERROR(rt2x00dev
, "WPDMA TX/RX busy, aborting.\n");
296 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready
);
298 static bool rt2800_check_firmware_crc(const u8
*data
, const size_t len
)
304 * The last 2 bytes in the firmware array are the crc checksum itself,
305 * this means that we should never pass those 2 bytes to the crc
308 fw_crc
= (data
[len
- 2] << 8 | data
[len
- 1]);
311 * Use the crc ccitt algorithm.
312 * This will return the same value as the legacy driver which
313 * used bit ordering reversion on the both the firmware bytes
314 * before input input as well as on the final output.
315 * Obviously using crc ccitt directly is much more efficient.
317 crc
= crc_ccitt(~0, data
, len
- 2);
320 * There is a small difference between the crc-itu-t + bitrev and
321 * the crc-ccitt crc calculation. In the latter method the 2 bytes
322 * will be swapped, use swab16 to convert the crc to the correct
327 return fw_crc
== crc
;
330 int rt2800_check_firmware(struct rt2x00_dev
*rt2x00dev
,
331 const u8
*data
, const size_t len
)
338 * PCI(e) & SOC devices require firmware with a length
339 * of 8kb. USB devices require firmware files with a length
340 * of 4kb. Certain USB chipsets however require different firmware,
341 * which Ralink only provides attached to the original firmware
342 * file. Thus for USB devices, firmware files have a length
343 * which is a multiple of 4kb.
345 if (rt2x00_is_usb(rt2x00dev
)) {
354 * Validate the firmware length
356 if (len
!= fw_len
&& (!multiple
|| (len
% fw_len
) != 0))
357 return FW_BAD_LENGTH
;
360 * Check if the chipset requires one of the upper parts
363 if (rt2x00_is_usb(rt2x00dev
) &&
364 !rt2x00_rt(rt2x00dev
, RT2860
) &&
365 !rt2x00_rt(rt2x00dev
, RT2872
) &&
366 !rt2x00_rt(rt2x00dev
, RT3070
) &&
367 ((len
/ fw_len
) == 1))
368 return FW_BAD_VERSION
;
371 * 8kb firmware files must be checked as if it were
372 * 2 separate firmware files.
374 while (offset
< len
) {
375 if (!rt2800_check_firmware_crc(data
+ offset
, fw_len
))
383 EXPORT_SYMBOL_GPL(rt2800_check_firmware
);
385 int rt2800_load_firmware(struct rt2x00_dev
*rt2x00dev
,
386 const u8
*data
, const size_t len
)
392 * If driver doesn't wake up firmware here,
393 * rt2800_load_firmware will hang forever when interface is up again.
395 rt2800_register_write(rt2x00dev
, AUTOWAKEUP_CFG
, 0x00000000);
398 * Wait for stable hardware.
400 if (rt2800_wait_csr_ready(rt2x00dev
))
403 if (rt2x00_is_pci(rt2x00dev
)) {
404 if (rt2x00_rt(rt2x00dev
, RT3572
) ||
405 rt2x00_rt(rt2x00dev
, RT5390
)) {
406 rt2800_register_read(rt2x00dev
, AUX_CTRL
, ®
);
407 rt2x00_set_field32(®
, AUX_CTRL_FORCE_PCIE_CLK
, 1);
408 rt2x00_set_field32(®
, AUX_CTRL_WAKE_PCIE_EN
, 1);
409 rt2800_register_write(rt2x00dev
, AUX_CTRL
, reg
);
411 rt2800_register_write(rt2x00dev
, PWR_PIN_CFG
, 0x00000002);
415 * Disable DMA, will be reenabled later when enabling
418 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
419 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_TX_DMA
, 0);
420 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_DMA_BUSY
, 0);
421 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_RX_DMA
, 0);
422 rt2x00_set_field32(®
, WPDMA_GLO_CFG_RX_DMA_BUSY
, 0);
423 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_WRITEBACK_DONE
, 1);
424 rt2800_register_write(rt2x00dev
, WPDMA_GLO_CFG
, reg
);
427 * Write firmware to the device.
429 rt2800_drv_write_firmware(rt2x00dev
, data
, len
);
432 * Wait for device to stabilize.
434 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
435 rt2800_register_read(rt2x00dev
, PBF_SYS_CTRL
, ®
);
436 if (rt2x00_get_field32(reg
, PBF_SYS_CTRL_READY
))
441 if (i
== REGISTER_BUSY_COUNT
) {
442 ERROR(rt2x00dev
, "PBF system register not ready.\n");
447 * Initialize firmware.
449 rt2800_register_write(rt2x00dev
, H2M_BBP_AGENT
, 0);
450 rt2800_register_write(rt2x00dev
, H2M_MAILBOX_CSR
, 0);
455 EXPORT_SYMBOL_GPL(rt2800_load_firmware
);
457 void rt2800_write_tx_data(struct queue_entry
*entry
,
458 struct txentry_desc
*txdesc
)
460 __le32
*txwi
= rt2800_drv_get_txwi(entry
);
464 * Initialize TX Info descriptor
466 rt2x00_desc_read(txwi
, 0, &word
);
467 rt2x00_set_field32(&word
, TXWI_W0_FRAG
,
468 test_bit(ENTRY_TXD_MORE_FRAG
, &txdesc
->flags
));
469 rt2x00_set_field32(&word
, TXWI_W0_MIMO_PS
,
470 test_bit(ENTRY_TXD_HT_MIMO_PS
, &txdesc
->flags
));
471 rt2x00_set_field32(&word
, TXWI_W0_CF_ACK
, 0);
472 rt2x00_set_field32(&word
, TXWI_W0_TS
,
473 test_bit(ENTRY_TXD_REQ_TIMESTAMP
, &txdesc
->flags
));
474 rt2x00_set_field32(&word
, TXWI_W0_AMPDU
,
475 test_bit(ENTRY_TXD_HT_AMPDU
, &txdesc
->flags
));
476 rt2x00_set_field32(&word
, TXWI_W0_MPDU_DENSITY
,
477 txdesc
->u
.ht
.mpdu_density
);
478 rt2x00_set_field32(&word
, TXWI_W0_TX_OP
, txdesc
->u
.ht
.txop
);
479 rt2x00_set_field32(&word
, TXWI_W0_MCS
, txdesc
->u
.ht
.mcs
);
480 rt2x00_set_field32(&word
, TXWI_W0_BW
,
481 test_bit(ENTRY_TXD_HT_BW_40
, &txdesc
->flags
));
482 rt2x00_set_field32(&word
, TXWI_W0_SHORT_GI
,
483 test_bit(ENTRY_TXD_HT_SHORT_GI
, &txdesc
->flags
));
484 rt2x00_set_field32(&word
, TXWI_W0_STBC
, txdesc
->u
.ht
.stbc
);
485 rt2x00_set_field32(&word
, TXWI_W0_PHYMODE
, txdesc
->rate_mode
);
486 rt2x00_desc_write(txwi
, 0, word
);
488 rt2x00_desc_read(txwi
, 1, &word
);
489 rt2x00_set_field32(&word
, TXWI_W1_ACK
,
490 test_bit(ENTRY_TXD_ACK
, &txdesc
->flags
));
491 rt2x00_set_field32(&word
, TXWI_W1_NSEQ
,
492 test_bit(ENTRY_TXD_GENERATE_SEQ
, &txdesc
->flags
));
493 rt2x00_set_field32(&word
, TXWI_W1_BW_WIN_SIZE
, txdesc
->u
.ht
.ba_size
);
494 rt2x00_set_field32(&word
, TXWI_W1_WIRELESS_CLI_ID
,
495 test_bit(ENTRY_TXD_ENCRYPT
, &txdesc
->flags
) ?
496 txdesc
->key_idx
: 0xff);
497 rt2x00_set_field32(&word
, TXWI_W1_MPDU_TOTAL_BYTE_COUNT
,
499 rt2x00_set_field32(&word
, TXWI_W1_PACKETID_QUEUE
, entry
->queue
->qid
);
500 rt2x00_set_field32(&word
, TXWI_W1_PACKETID_ENTRY
, (entry
->entry_idx
% 3) + 1);
501 rt2x00_desc_write(txwi
, 1, word
);
504 * Always write 0 to IV/EIV fields, hardware will insert the IV
505 * from the IVEIV register when TXD_W3_WIV is set to 0.
506 * When TXD_W3_WIV is set to 1 it will use the IV data
507 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
508 * crypto entry in the registers should be used to encrypt the frame.
510 _rt2x00_desc_write(txwi
, 2, 0 /* skbdesc->iv[0] */);
511 _rt2x00_desc_write(txwi
, 3, 0 /* skbdesc->iv[1] */);
513 EXPORT_SYMBOL_GPL(rt2800_write_tx_data
);
515 static int rt2800_agc_to_rssi(struct rt2x00_dev
*rt2x00dev
, u32 rxwi_w2
)
517 int rssi0
= rt2x00_get_field32(rxwi_w2
, RXWI_W2_RSSI0
);
518 int rssi1
= rt2x00_get_field32(rxwi_w2
, RXWI_W2_RSSI1
);
519 int rssi2
= rt2x00_get_field32(rxwi_w2
, RXWI_W2_RSSI2
);
525 if (rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
) {
526 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_BG
, &eeprom
);
527 offset0
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_BG_OFFSET0
);
528 offset1
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_BG_OFFSET1
);
529 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_BG2
, &eeprom
);
530 offset2
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_BG2_OFFSET2
);
532 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_A
, &eeprom
);
533 offset0
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_A_OFFSET0
);
534 offset1
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_A_OFFSET1
);
535 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_A2
, &eeprom
);
536 offset2
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_A2_OFFSET2
);
540 * Convert the value from the descriptor into the RSSI value
541 * If the value in the descriptor is 0, it is considered invalid
542 * and the default (extremely low) rssi value is assumed
544 rssi0
= (rssi0
) ? (-12 - offset0
- rt2x00dev
->lna_gain
- rssi0
) : -128;
545 rssi1
= (rssi1
) ? (-12 - offset1
- rt2x00dev
->lna_gain
- rssi1
) : -128;
546 rssi2
= (rssi2
) ? (-12 - offset2
- rt2x00dev
->lna_gain
- rssi2
) : -128;
549 * mac80211 only accepts a single RSSI value. Calculating the
550 * average doesn't deliver a fair answer either since -60:-60 would
551 * be considered equally good as -50:-70 while the second is the one
552 * which gives less energy...
554 rssi0
= max(rssi0
, rssi1
);
555 return max(rssi0
, rssi2
);
558 void rt2800_process_rxwi(struct queue_entry
*entry
,
559 struct rxdone_entry_desc
*rxdesc
)
561 __le32
*rxwi
= (__le32
*) entry
->skb
->data
;
564 rt2x00_desc_read(rxwi
, 0, &word
);
566 rxdesc
->cipher
= rt2x00_get_field32(word
, RXWI_W0_UDF
);
567 rxdesc
->size
= rt2x00_get_field32(word
, RXWI_W0_MPDU_TOTAL_BYTE_COUNT
);
569 rt2x00_desc_read(rxwi
, 1, &word
);
571 if (rt2x00_get_field32(word
, RXWI_W1_SHORT_GI
))
572 rxdesc
->flags
|= RX_FLAG_SHORT_GI
;
574 if (rt2x00_get_field32(word
, RXWI_W1_BW
))
575 rxdesc
->flags
|= RX_FLAG_40MHZ
;
578 * Detect RX rate, always use MCS as signal type.
580 rxdesc
->dev_flags
|= RXDONE_SIGNAL_MCS
;
581 rxdesc
->signal
= rt2x00_get_field32(word
, RXWI_W1_MCS
);
582 rxdesc
->rate_mode
= rt2x00_get_field32(word
, RXWI_W1_PHYMODE
);
585 * Mask of 0x8 bit to remove the short preamble flag.
587 if (rxdesc
->rate_mode
== RATE_MODE_CCK
)
588 rxdesc
->signal
&= ~0x8;
590 rt2x00_desc_read(rxwi
, 2, &word
);
593 * Convert descriptor AGC value to RSSI value.
595 rxdesc
->rssi
= rt2800_agc_to_rssi(entry
->queue
->rt2x00dev
, word
);
598 * Remove RXWI descriptor from start of buffer.
600 skb_pull(entry
->skb
, RXWI_DESC_SIZE
);
602 EXPORT_SYMBOL_GPL(rt2800_process_rxwi
);
604 void rt2800_txdone_entry(struct queue_entry
*entry
, u32 status
, __le32
*txwi
)
606 struct rt2x00_dev
*rt2x00dev
= entry
->queue
->rt2x00dev
;
607 struct skb_frame_desc
*skbdesc
= get_skb_frame_desc(entry
->skb
);
608 struct txdone_entry_desc txdesc
;
614 * Obtain the status about this packet.
617 rt2x00_desc_read(txwi
, 0, &word
);
619 mcs
= rt2x00_get_field32(word
, TXWI_W0_MCS
);
620 ampdu
= rt2x00_get_field32(word
, TXWI_W0_AMPDU
);
622 real_mcs
= rt2x00_get_field32(status
, TX_STA_FIFO_MCS
);
623 aggr
= rt2x00_get_field32(status
, TX_STA_FIFO_TX_AGGRE
);
626 * If a frame was meant to be sent as a single non-aggregated MPDU
627 * but ended up in an aggregate the used tx rate doesn't correlate
628 * with the one specified in the TXWI as the whole aggregate is sent
629 * with the same rate.
631 * For example: two frames are sent to rt2x00, the first one sets
632 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
633 * and requests MCS15. If the hw aggregates both frames into one
634 * AMDPU the tx status for both frames will contain MCS7 although
635 * the frame was sent successfully.
637 * Hence, replace the requested rate with the real tx rate to not
638 * confuse the rate control algortihm by providing clearly wrong
641 if (unlikely(aggr
== 1 && ampdu
== 0 && real_mcs
!= mcs
)) {
642 skbdesc
->tx_rate_idx
= real_mcs
;
646 if (aggr
== 1 || ampdu
== 1)
647 __set_bit(TXDONE_AMPDU
, &txdesc
.flags
);
650 * Ralink has a retry mechanism using a global fallback
651 * table. We setup this fallback table to try the immediate
652 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
653 * always contains the MCS used for the last transmission, be
654 * it successful or not.
656 if (rt2x00_get_field32(status
, TX_STA_FIFO_TX_SUCCESS
)) {
658 * Transmission succeeded. The number of retries is
661 __set_bit(TXDONE_SUCCESS
, &txdesc
.flags
);
662 txdesc
.retry
= ((mcs
> real_mcs
) ? mcs
- real_mcs
: 0);
665 * Transmission failed. The number of retries is
666 * always 7 in this case (for a total number of 8
669 __set_bit(TXDONE_FAILURE
, &txdesc
.flags
);
670 txdesc
.retry
= rt2x00dev
->long_retry
;
674 * the frame was retried at least once
675 * -> hw used fallback rates
678 __set_bit(TXDONE_FALLBACK
, &txdesc
.flags
);
680 rt2x00lib_txdone(entry
, &txdesc
);
682 EXPORT_SYMBOL_GPL(rt2800_txdone_entry
);
684 void rt2800_write_beacon(struct queue_entry
*entry
, struct txentry_desc
*txdesc
)
686 struct rt2x00_dev
*rt2x00dev
= entry
->queue
->rt2x00dev
;
687 struct skb_frame_desc
*skbdesc
= get_skb_frame_desc(entry
->skb
);
688 unsigned int beacon_base
;
689 unsigned int padding_len
;
693 * Disable beaconing while we are reloading the beacon data,
694 * otherwise we might be sending out invalid data.
696 rt2800_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
698 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_GEN
, 0);
699 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
702 * Add space for the TXWI in front of the skb.
704 memset(skb_push(entry
->skb
, TXWI_DESC_SIZE
), 0, TXWI_DESC_SIZE
);
707 * Register descriptor details in skb frame descriptor.
709 skbdesc
->flags
|= SKBDESC_DESC_IN_SKB
;
710 skbdesc
->desc
= entry
->skb
->data
;
711 skbdesc
->desc_len
= TXWI_DESC_SIZE
;
714 * Add the TXWI for the beacon to the skb.
716 rt2800_write_tx_data(entry
, txdesc
);
719 * Dump beacon to userspace through debugfs.
721 rt2x00debug_dump_frame(rt2x00dev
, DUMP_FRAME_BEACON
, entry
->skb
);
724 * Write entire beacon with TXWI and padding to register.
726 padding_len
= roundup(entry
->skb
->len
, 4) - entry
->skb
->len
;
727 if (padding_len
&& skb_pad(entry
->skb
, padding_len
)) {
728 ERROR(rt2x00dev
, "Failure padding beacon, aborting\n");
729 /* skb freed by skb_pad() on failure */
731 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, orig_reg
);
735 beacon_base
= HW_BEACON_OFFSET(entry
->entry_idx
);
736 rt2800_register_multiwrite(rt2x00dev
, beacon_base
, entry
->skb
->data
,
737 entry
->skb
->len
+ padding_len
);
740 * Enable beaconing again.
742 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_GEN
, 1);
743 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
746 * Clean up beacon skb.
748 dev_kfree_skb_any(entry
->skb
);
751 EXPORT_SYMBOL_GPL(rt2800_write_beacon
);
753 static inline void rt2800_clear_beacon_register(struct rt2x00_dev
*rt2x00dev
,
754 unsigned int beacon_base
)
759 * For the Beacon base registers we only need to clear
760 * the whole TXWI which (when set to 0) will invalidate
763 for (i
= 0; i
< TXWI_DESC_SIZE
; i
+= sizeof(__le32
))
764 rt2800_register_write(rt2x00dev
, beacon_base
+ i
, 0);
767 void rt2800_clear_beacon(struct queue_entry
*entry
)
769 struct rt2x00_dev
*rt2x00dev
= entry
->queue
->rt2x00dev
;
773 * Disable beaconing while we are reloading the beacon data,
774 * otherwise we might be sending out invalid data.
776 rt2800_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
777 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_GEN
, 0);
778 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
783 rt2800_clear_beacon_register(rt2x00dev
,
784 HW_BEACON_OFFSET(entry
->entry_idx
));
787 * Enabled beaconing again.
789 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_GEN
, 1);
790 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
792 EXPORT_SYMBOL_GPL(rt2800_clear_beacon
);
794 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
795 const struct rt2x00debug rt2800_rt2x00debug
= {
796 .owner
= THIS_MODULE
,
798 .read
= rt2800_register_read
,
799 .write
= rt2800_register_write
,
800 .flags
= RT2X00DEBUGFS_OFFSET
,
801 .word_base
= CSR_REG_BASE
,
802 .word_size
= sizeof(u32
),
803 .word_count
= CSR_REG_SIZE
/ sizeof(u32
),
806 .read
= rt2x00_eeprom_read
,
807 .write
= rt2x00_eeprom_write
,
808 .word_base
= EEPROM_BASE
,
809 .word_size
= sizeof(u16
),
810 .word_count
= EEPROM_SIZE
/ sizeof(u16
),
813 .read
= rt2800_bbp_read
,
814 .write
= rt2800_bbp_write
,
815 .word_base
= BBP_BASE
,
816 .word_size
= sizeof(u8
),
817 .word_count
= BBP_SIZE
/ sizeof(u8
),
820 .read
= rt2x00_rf_read
,
821 .write
= rt2800_rf_write
,
822 .word_base
= RF_BASE
,
823 .word_size
= sizeof(u32
),
824 .word_count
= RF_SIZE
/ sizeof(u32
),
827 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug
);
828 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
830 int rt2800_rfkill_poll(struct rt2x00_dev
*rt2x00dev
)
834 rt2800_register_read(rt2x00dev
, GPIO_CTRL_CFG
, ®
);
835 return rt2x00_get_field32(reg
, GPIO_CTRL_CFG_BIT2
);
837 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll
);
839 #ifdef CONFIG_RT2X00_LIB_LEDS
840 static void rt2800_brightness_set(struct led_classdev
*led_cdev
,
841 enum led_brightness brightness
)
843 struct rt2x00_led
*led
=
844 container_of(led_cdev
, struct rt2x00_led
, led_dev
);
845 unsigned int enabled
= brightness
!= LED_OFF
;
846 unsigned int bg_mode
=
847 (enabled
&& led
->rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
);
848 unsigned int polarity
=
849 rt2x00_get_field16(led
->rt2x00dev
->led_mcu_reg
,
850 EEPROM_FREQ_LED_POLARITY
);
851 unsigned int ledmode
=
852 rt2x00_get_field16(led
->rt2x00dev
->led_mcu_reg
,
853 EEPROM_FREQ_LED_MODE
);
856 /* Check for SoC (SOC devices don't support MCU requests) */
857 if (rt2x00_is_soc(led
->rt2x00dev
)) {
858 rt2800_register_read(led
->rt2x00dev
, LED_CFG
, ®
);
860 /* Set LED Polarity */
861 rt2x00_set_field32(®
, LED_CFG_LED_POLAR
, polarity
);
864 if (led
->type
== LED_TYPE_RADIO
) {
865 rt2x00_set_field32(®
, LED_CFG_G_LED_MODE
,
867 } else if (led
->type
== LED_TYPE_ASSOC
) {
868 rt2x00_set_field32(®
, LED_CFG_Y_LED_MODE
,
870 } else if (led
->type
== LED_TYPE_QUALITY
) {
871 rt2x00_set_field32(®
, LED_CFG_R_LED_MODE
,
875 rt2800_register_write(led
->rt2x00dev
, LED_CFG
, reg
);
878 if (led
->type
== LED_TYPE_RADIO
) {
879 rt2800_mcu_request(led
->rt2x00dev
, MCU_LED
, 0xff, ledmode
,
881 } else if (led
->type
== LED_TYPE_ASSOC
) {
882 rt2800_mcu_request(led
->rt2x00dev
, MCU_LED
, 0xff, ledmode
,
883 enabled
? (bg_mode
? 0x60 : 0xa0) : 0x20);
884 } else if (led
->type
== LED_TYPE_QUALITY
) {
886 * The brightness is divided into 6 levels (0 - 5),
887 * The specs tell us the following levels:
889 * to determine the level in a simple way we can simply
890 * work with bitshifting:
893 rt2800_mcu_request(led
->rt2x00dev
, MCU_LED_STRENGTH
, 0xff,
894 (1 << brightness
/ (LED_FULL
/ 6)) - 1,
900 static void rt2800_init_led(struct rt2x00_dev
*rt2x00dev
,
901 struct rt2x00_led
*led
, enum led_type type
)
903 led
->rt2x00dev
= rt2x00dev
;
905 led
->led_dev
.brightness_set
= rt2800_brightness_set
;
906 led
->flags
= LED_INITIALIZED
;
908 #endif /* CONFIG_RT2X00_LIB_LEDS */
911 * Configuration handlers.
913 static void rt2800_config_wcid_attr(struct rt2x00_dev
*rt2x00dev
,
914 struct rt2x00lib_crypto
*crypto
,
915 struct ieee80211_key_conf
*key
)
917 struct mac_wcid_entry wcid_entry
;
918 struct mac_iveiv_entry iveiv_entry
;
922 offset
= MAC_WCID_ATTR_ENTRY(key
->hw_key_idx
);
924 if (crypto
->cmd
== SET_KEY
) {
925 rt2800_register_read(rt2x00dev
, offset
, ®
);
926 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_KEYTAB
,
927 !!(key
->flags
& IEEE80211_KEY_FLAG_PAIRWISE
));
929 * Both the cipher as the BSS Idx numbers are split in a main
930 * value of 3 bits, and a extended field for adding one additional
933 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_CIPHER
,
934 (crypto
->cipher
& 0x7));
935 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_CIPHER_EXT
,
936 (crypto
->cipher
& 0x8) >> 3);
937 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_BSS_IDX
,
938 (crypto
->bssidx
& 0x7));
939 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT
,
940 (crypto
->bssidx
& 0x8) >> 3);
941 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_RX_WIUDF
, crypto
->cipher
);
942 rt2800_register_write(rt2x00dev
, offset
, reg
);
944 rt2800_register_write(rt2x00dev
, offset
, 0);
947 offset
= MAC_IVEIV_ENTRY(key
->hw_key_idx
);
949 memset(&iveiv_entry
, 0, sizeof(iveiv_entry
));
950 if ((crypto
->cipher
== CIPHER_TKIP
) ||
951 (crypto
->cipher
== CIPHER_TKIP_NO_MIC
) ||
952 (crypto
->cipher
== CIPHER_AES
))
953 iveiv_entry
.iv
[3] |= 0x20;
954 iveiv_entry
.iv
[3] |= key
->keyidx
<< 6;
955 rt2800_register_multiwrite(rt2x00dev
, offset
,
956 &iveiv_entry
, sizeof(iveiv_entry
));
958 offset
= MAC_WCID_ENTRY(key
->hw_key_idx
);
960 memset(&wcid_entry
, 0, sizeof(wcid_entry
));
961 if (crypto
->cmd
== SET_KEY
)
962 memcpy(wcid_entry
.mac
, crypto
->address
, ETH_ALEN
);
963 rt2800_register_multiwrite(rt2x00dev
, offset
,
964 &wcid_entry
, sizeof(wcid_entry
));
967 int rt2800_config_shared_key(struct rt2x00_dev
*rt2x00dev
,
968 struct rt2x00lib_crypto
*crypto
,
969 struct ieee80211_key_conf
*key
)
971 struct hw_key_entry key_entry
;
972 struct rt2x00_field32 field
;
976 if (crypto
->cmd
== SET_KEY
) {
977 key
->hw_key_idx
= (4 * crypto
->bssidx
) + key
->keyidx
;
979 memcpy(key_entry
.key
, crypto
->key
,
980 sizeof(key_entry
.key
));
981 memcpy(key_entry
.tx_mic
, crypto
->tx_mic
,
982 sizeof(key_entry
.tx_mic
));
983 memcpy(key_entry
.rx_mic
, crypto
->rx_mic
,
984 sizeof(key_entry
.rx_mic
));
986 offset
= SHARED_KEY_ENTRY(key
->hw_key_idx
);
987 rt2800_register_multiwrite(rt2x00dev
, offset
,
988 &key_entry
, sizeof(key_entry
));
992 * The cipher types are stored over multiple registers
993 * starting with SHARED_KEY_MODE_BASE each word will have
994 * 32 bits and contains the cipher types for 2 bssidx each.
995 * Using the correct defines correctly will cause overhead,
996 * so just calculate the correct offset.
998 field
.bit_offset
= 4 * (key
->hw_key_idx
% 8);
999 field
.bit_mask
= 0x7 << field
.bit_offset
;
1001 offset
= SHARED_KEY_MODE_ENTRY(key
->hw_key_idx
/ 8);
1003 rt2800_register_read(rt2x00dev
, offset
, ®
);
1004 rt2x00_set_field32(®
, field
,
1005 (crypto
->cmd
== SET_KEY
) * crypto
->cipher
);
1006 rt2800_register_write(rt2x00dev
, offset
, reg
);
1009 * Update WCID information
1011 rt2800_config_wcid_attr(rt2x00dev
, crypto
, key
);
1015 EXPORT_SYMBOL_GPL(rt2800_config_shared_key
);
1017 static inline int rt2800_find_pairwise_keyslot(struct rt2x00_dev
*rt2x00dev
)
1023 * Search for the first free pairwise key entry and return the
1024 * corresponding index.
1026 * Make sure the WCID starts _after_ the last possible shared key
1029 * Since parts of the pairwise key table might be shared with
1030 * the beacon frame buffers 6 & 7 we should only write into the
1031 * first 222 entries.
1033 for (idx
= 33; idx
<= 222; idx
++) {
1034 offset
= MAC_WCID_ATTR_ENTRY(idx
);
1035 rt2800_register_read(rt2x00dev
, offset
, ®
);
1042 int rt2800_config_pairwise_key(struct rt2x00_dev
*rt2x00dev
,
1043 struct rt2x00lib_crypto
*crypto
,
1044 struct ieee80211_key_conf
*key
)
1046 struct hw_key_entry key_entry
;
1050 if (crypto
->cmd
== SET_KEY
) {
1051 idx
= rt2800_find_pairwise_keyslot(rt2x00dev
);
1054 key
->hw_key_idx
= idx
;
1056 memcpy(key_entry
.key
, crypto
->key
,
1057 sizeof(key_entry
.key
));
1058 memcpy(key_entry
.tx_mic
, crypto
->tx_mic
,
1059 sizeof(key_entry
.tx_mic
));
1060 memcpy(key_entry
.rx_mic
, crypto
->rx_mic
,
1061 sizeof(key_entry
.rx_mic
));
1063 offset
= PAIRWISE_KEY_ENTRY(key
->hw_key_idx
);
1064 rt2800_register_multiwrite(rt2x00dev
, offset
,
1065 &key_entry
, sizeof(key_entry
));
1069 * Update WCID information
1071 rt2800_config_wcid_attr(rt2x00dev
, crypto
, key
);
1075 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key
);
1077 void rt2800_config_filter(struct rt2x00_dev
*rt2x00dev
,
1078 const unsigned int filter_flags
)
1083 * Start configuration steps.
1084 * Note that the version error will always be dropped
1085 * and broadcast frames will always be accepted since
1086 * there is no filter for it at this time.
1088 rt2800_register_read(rt2x00dev
, RX_FILTER_CFG
, ®
);
1089 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CRC_ERROR
,
1090 !(filter_flags
& FIF_FCSFAIL
));
1091 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_PHY_ERROR
,
1092 !(filter_flags
& FIF_PLCPFAIL
));
1093 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_NOT_TO_ME
,
1094 !(filter_flags
& FIF_PROMISC_IN_BSS
));
1095 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_NOT_MY_BSSD
, 0);
1096 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_VER_ERROR
, 1);
1097 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_MULTICAST
,
1098 !(filter_flags
& FIF_ALLMULTI
));
1099 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_BROADCAST
, 0);
1100 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_DUPLICATE
, 1);
1101 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CF_END_ACK
,
1102 !(filter_flags
& FIF_CONTROL
));
1103 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CF_END
,
1104 !(filter_flags
& FIF_CONTROL
));
1105 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_ACK
,
1106 !(filter_flags
& FIF_CONTROL
));
1107 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CTS
,
1108 !(filter_flags
& FIF_CONTROL
));
1109 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_RTS
,
1110 !(filter_flags
& FIF_CONTROL
));
1111 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_PSPOLL
,
1112 !(filter_flags
& FIF_PSPOLL
));
1113 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_BA
, 1);
1114 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_BAR
, 0);
1115 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CNTL
,
1116 !(filter_flags
& FIF_CONTROL
));
1117 rt2800_register_write(rt2x00dev
, RX_FILTER_CFG
, reg
);
1119 EXPORT_SYMBOL_GPL(rt2800_config_filter
);
1121 void rt2800_config_intf(struct rt2x00_dev
*rt2x00dev
, struct rt2x00_intf
*intf
,
1122 struct rt2x00intf_conf
*conf
, const unsigned int flags
)
1125 bool update_bssid
= false;
1127 if (flags
& CONFIG_UPDATE_TYPE
) {
1129 * Enable synchronisation.
1131 rt2800_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
1132 rt2x00_set_field32(®
, BCN_TIME_CFG_TSF_SYNC
, conf
->sync
);
1133 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
1135 if (conf
->sync
== TSF_SYNC_AP_NONE
) {
1137 * Tune beacon queue transmit parameters for AP mode
1139 rt2800_register_read(rt2x00dev
, TBTT_SYNC_CFG
, ®
);
1140 rt2x00_set_field32(®
, TBTT_SYNC_CFG_BCN_CWMIN
, 0);
1141 rt2x00_set_field32(®
, TBTT_SYNC_CFG_BCN_AIFSN
, 1);
1142 rt2x00_set_field32(®
, TBTT_SYNC_CFG_BCN_EXP_WIN
, 32);
1143 rt2x00_set_field32(®
, TBTT_SYNC_CFG_TBTT_ADJUST
, 0);
1144 rt2800_register_write(rt2x00dev
, TBTT_SYNC_CFG
, reg
);
1146 rt2800_register_read(rt2x00dev
, TBTT_SYNC_CFG
, ®
);
1147 rt2x00_set_field32(®
, TBTT_SYNC_CFG_BCN_CWMIN
, 4);
1148 rt2x00_set_field32(®
, TBTT_SYNC_CFG_BCN_AIFSN
, 2);
1149 rt2x00_set_field32(®
, TBTT_SYNC_CFG_BCN_EXP_WIN
, 32);
1150 rt2x00_set_field32(®
, TBTT_SYNC_CFG_TBTT_ADJUST
, 16);
1151 rt2800_register_write(rt2x00dev
, TBTT_SYNC_CFG
, reg
);
1155 if (flags
& CONFIG_UPDATE_MAC
) {
1156 if (flags
& CONFIG_UPDATE_TYPE
&&
1157 conf
->sync
== TSF_SYNC_AP_NONE
) {
1159 * The BSSID register has to be set to our own mac
1160 * address in AP mode.
1162 memcpy(conf
->bssid
, conf
->mac
, sizeof(conf
->mac
));
1163 update_bssid
= true;
1166 if (!is_zero_ether_addr((const u8
*)conf
->mac
)) {
1167 reg
= le32_to_cpu(conf
->mac
[1]);
1168 rt2x00_set_field32(®
, MAC_ADDR_DW1_UNICAST_TO_ME_MASK
, 0xff);
1169 conf
->mac
[1] = cpu_to_le32(reg
);
1172 rt2800_register_multiwrite(rt2x00dev
, MAC_ADDR_DW0
,
1173 conf
->mac
, sizeof(conf
->mac
));
1176 if ((flags
& CONFIG_UPDATE_BSSID
) || update_bssid
) {
1177 if (!is_zero_ether_addr((const u8
*)conf
->bssid
)) {
1178 reg
= le32_to_cpu(conf
->bssid
[1]);
1179 rt2x00_set_field32(®
, MAC_BSSID_DW1_BSS_ID_MASK
, 3);
1180 rt2x00_set_field32(®
, MAC_BSSID_DW1_BSS_BCN_NUM
, 7);
1181 conf
->bssid
[1] = cpu_to_le32(reg
);
1184 rt2800_register_multiwrite(rt2x00dev
, MAC_BSSID_DW0
,
1185 conf
->bssid
, sizeof(conf
->bssid
));
1188 EXPORT_SYMBOL_GPL(rt2800_config_intf
);
1190 static void rt2800_config_ht_opmode(struct rt2x00_dev
*rt2x00dev
,
1191 struct rt2x00lib_erp
*erp
)
1193 bool any_sta_nongf
= !!(erp
->ht_opmode
&
1194 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT
);
1195 u8 protection
= erp
->ht_opmode
& IEEE80211_HT_OP_MODE_PROTECTION
;
1196 u8 mm20_mode
, mm40_mode
, gf20_mode
, gf40_mode
;
1197 u16 mm20_rate
, mm40_rate
, gf20_rate
, gf40_rate
;
1200 /* default protection rate for HT20: OFDM 24M */
1201 mm20_rate
= gf20_rate
= 0x4004;
1203 /* default protection rate for HT40: duplicate OFDM 24M */
1204 mm40_rate
= gf40_rate
= 0x4084;
1206 switch (protection
) {
1207 case IEEE80211_HT_OP_MODE_PROTECTION_NONE
:
1209 * All STAs in this BSS are HT20/40 but there might be
1210 * STAs not supporting greenfield mode.
1211 * => Disable protection for HT transmissions.
1213 mm20_mode
= mm40_mode
= gf20_mode
= gf40_mode
= 0;
1216 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ
:
1218 * All STAs in this BSS are HT20 or HT20/40 but there
1219 * might be STAs not supporting greenfield mode.
1220 * => Protect all HT40 transmissions.
1222 mm20_mode
= gf20_mode
= 0;
1223 mm40_mode
= gf40_mode
= 2;
1226 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER
:
1228 * Nonmember protection:
1229 * According to 802.11n we _should_ protect all
1230 * HT transmissions (but we don't have to).
1232 * But if cts_protection is enabled we _shall_ protect
1233 * all HT transmissions using a CCK rate.
1235 * And if any station is non GF we _shall_ protect
1238 * We decide to protect everything
1239 * -> fall through to mixed mode.
1241 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED
:
1243 * Legacy STAs are present
1244 * => Protect all HT transmissions.
1246 mm20_mode
= mm40_mode
= gf20_mode
= gf40_mode
= 2;
1249 * If erp protection is needed we have to protect HT
1250 * transmissions with CCK 11M long preamble.
1252 if (erp
->cts_protection
) {
1253 /* don't duplicate RTS/CTS in CCK mode */
1254 mm20_rate
= mm40_rate
= 0x0003;
1255 gf20_rate
= gf40_rate
= 0x0003;
1260 /* check for STAs not supporting greenfield mode */
1262 gf20_mode
= gf40_mode
= 2;
1264 /* Update HT protection config */
1265 rt2800_register_read(rt2x00dev
, MM20_PROT_CFG
, ®
);
1266 rt2x00_set_field32(®
, MM20_PROT_CFG_PROTECT_RATE
, mm20_rate
);
1267 rt2x00_set_field32(®
, MM20_PROT_CFG_PROTECT_CTRL
, mm20_mode
);
1268 rt2800_register_write(rt2x00dev
, MM20_PROT_CFG
, reg
);
1270 rt2800_register_read(rt2x00dev
, MM40_PROT_CFG
, ®
);
1271 rt2x00_set_field32(®
, MM40_PROT_CFG_PROTECT_RATE
, mm40_rate
);
1272 rt2x00_set_field32(®
, MM40_PROT_CFG_PROTECT_CTRL
, mm40_mode
);
1273 rt2800_register_write(rt2x00dev
, MM40_PROT_CFG
, reg
);
1275 rt2800_register_read(rt2x00dev
, GF20_PROT_CFG
, ®
);
1276 rt2x00_set_field32(®
, GF20_PROT_CFG_PROTECT_RATE
, gf20_rate
);
1277 rt2x00_set_field32(®
, GF20_PROT_CFG_PROTECT_CTRL
, gf20_mode
);
1278 rt2800_register_write(rt2x00dev
, GF20_PROT_CFG
, reg
);
1280 rt2800_register_read(rt2x00dev
, GF40_PROT_CFG
, ®
);
1281 rt2x00_set_field32(®
, GF40_PROT_CFG_PROTECT_RATE
, gf40_rate
);
1282 rt2x00_set_field32(®
, GF40_PROT_CFG_PROTECT_CTRL
, gf40_mode
);
1283 rt2800_register_write(rt2x00dev
, GF40_PROT_CFG
, reg
);
1286 void rt2800_config_erp(struct rt2x00_dev
*rt2x00dev
, struct rt2x00lib_erp
*erp
,
1291 if (changed
& BSS_CHANGED_ERP_PREAMBLE
) {
1292 rt2800_register_read(rt2x00dev
, AUTO_RSP_CFG
, ®
);
1293 rt2x00_set_field32(®
, AUTO_RSP_CFG_BAC_ACK_POLICY
,
1294 !!erp
->short_preamble
);
1295 rt2x00_set_field32(®
, AUTO_RSP_CFG_AR_PREAMBLE
,
1296 !!erp
->short_preamble
);
1297 rt2800_register_write(rt2x00dev
, AUTO_RSP_CFG
, reg
);
1300 if (changed
& BSS_CHANGED_ERP_CTS_PROT
) {
1301 rt2800_register_read(rt2x00dev
, OFDM_PROT_CFG
, ®
);
1302 rt2x00_set_field32(®
, OFDM_PROT_CFG_PROTECT_CTRL
,
1303 erp
->cts_protection
? 2 : 0);
1304 rt2800_register_write(rt2x00dev
, OFDM_PROT_CFG
, reg
);
1307 if (changed
& BSS_CHANGED_BASIC_RATES
) {
1308 rt2800_register_write(rt2x00dev
, LEGACY_BASIC_RATE
,
1310 rt2800_register_write(rt2x00dev
, HT_BASIC_RATE
, 0x00008003);
1313 if (changed
& BSS_CHANGED_ERP_SLOT
) {
1314 rt2800_register_read(rt2x00dev
, BKOFF_SLOT_CFG
, ®
);
1315 rt2x00_set_field32(®
, BKOFF_SLOT_CFG_SLOT_TIME
,
1317 rt2800_register_write(rt2x00dev
, BKOFF_SLOT_CFG
, reg
);
1319 rt2800_register_read(rt2x00dev
, XIFS_TIME_CFG
, ®
);
1320 rt2x00_set_field32(®
, XIFS_TIME_CFG_EIFS
, erp
->eifs
);
1321 rt2800_register_write(rt2x00dev
, XIFS_TIME_CFG
, reg
);
1324 if (changed
& BSS_CHANGED_BEACON_INT
) {
1325 rt2800_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
1326 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_INTERVAL
,
1327 erp
->beacon_int
* 16);
1328 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
1331 if (changed
& BSS_CHANGED_HT
)
1332 rt2800_config_ht_opmode(rt2x00dev
, erp
);
1334 EXPORT_SYMBOL_GPL(rt2800_config_erp
);
1336 static void rt2800_config_3572bt_ant(struct rt2x00_dev
*rt2x00dev
)
1340 u8 led_ctrl
, led_g_mode
, led_r_mode
;
1342 rt2800_register_read(rt2x00dev
, GPIO_SWITCH
, ®
);
1343 if (rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
) {
1344 rt2x00_set_field32(®
, GPIO_SWITCH_0
, 1);
1345 rt2x00_set_field32(®
, GPIO_SWITCH_1
, 1);
1347 rt2x00_set_field32(®
, GPIO_SWITCH_0
, 0);
1348 rt2x00_set_field32(®
, GPIO_SWITCH_1
, 0);
1350 rt2800_register_write(rt2x00dev
, GPIO_SWITCH
, reg
);
1352 rt2800_register_read(rt2x00dev
, LED_CFG
, ®
);
1353 led_g_mode
= rt2x00_get_field32(reg
, LED_CFG_LED_POLAR
) ? 3 : 0;
1354 led_r_mode
= rt2x00_get_field32(reg
, LED_CFG_LED_POLAR
) ? 0 : 3;
1355 if (led_g_mode
!= rt2x00_get_field32(reg
, LED_CFG_G_LED_MODE
) ||
1356 led_r_mode
!= rt2x00_get_field32(reg
, LED_CFG_R_LED_MODE
)) {
1357 rt2x00_eeprom_read(rt2x00dev
, EEPROM_FREQ
, &eeprom
);
1358 led_ctrl
= rt2x00_get_field16(eeprom
, EEPROM_FREQ_LED_MODE
);
1359 if (led_ctrl
== 0 || led_ctrl
> 0x40) {
1360 rt2x00_set_field32(®
, LED_CFG_G_LED_MODE
, led_g_mode
);
1361 rt2x00_set_field32(®
, LED_CFG_R_LED_MODE
, led_r_mode
);
1362 rt2800_register_write(rt2x00dev
, LED_CFG
, reg
);
1364 rt2800_mcu_request(rt2x00dev
, MCU_BAND_SELECT
, 0xff,
1365 (led_g_mode
<< 2) | led_r_mode
, 1);
1370 static void rt2800_set_ant_diversity(struct rt2x00_dev
*rt2x00dev
,
1374 u8 eesk_pin
= (ant
== ANTENNA_A
) ? 1 : 0;
1375 u8 gpio_bit3
= (ant
== ANTENNA_A
) ? 0 : 1;
1377 if (rt2x00_is_pci(rt2x00dev
)) {
1378 rt2800_register_read(rt2x00dev
, E2PROM_CSR
, ®
);
1379 rt2x00_set_field32(®
, E2PROM_CSR_DATA_CLOCK
, eesk_pin
);
1380 rt2800_register_write(rt2x00dev
, E2PROM_CSR
, reg
);
1381 } else if (rt2x00_is_usb(rt2x00dev
))
1382 rt2800_mcu_request(rt2x00dev
, MCU_ANT_SELECT
, 0xff,
1385 rt2800_register_read(rt2x00dev
, GPIO_CTRL_CFG
, ®
);
1386 rt2x00_set_field32(®
, GPIO_CTRL_CFG_GPIOD_BIT3
, 0);
1387 rt2x00_set_field32(®
, GPIO_CTRL_CFG_BIT3
, gpio_bit3
);
1388 rt2800_register_write(rt2x00dev
, GPIO_CTRL_CFG
, reg
);
1391 void rt2800_config_ant(struct rt2x00_dev
*rt2x00dev
, struct antenna_setup
*ant
)
1397 rt2800_bbp_read(rt2x00dev
, 1, &r1
);
1398 rt2800_bbp_read(rt2x00dev
, 3, &r3
);
1400 if (rt2x00_rt(rt2x00dev
, RT3572
) &&
1401 test_bit(CAPABILITY_BT_COEXIST
, &rt2x00dev
->cap_flags
))
1402 rt2800_config_3572bt_ant(rt2x00dev
);
1405 * Configure the TX antenna.
1407 switch (ant
->tx_chain_num
) {
1409 rt2x00_set_field8(&r1
, BBP1_TX_ANTENNA
, 0);
1412 if (rt2x00_rt(rt2x00dev
, RT3572
) &&
1413 test_bit(CAPABILITY_BT_COEXIST
, &rt2x00dev
->cap_flags
))
1414 rt2x00_set_field8(&r1
, BBP1_TX_ANTENNA
, 1);
1416 rt2x00_set_field8(&r1
, BBP1_TX_ANTENNA
, 2);
1419 rt2x00_set_field8(&r1
, BBP1_TX_ANTENNA
, 0);
1424 * Configure the RX antenna.
1426 switch (ant
->rx_chain_num
) {
1428 if (rt2x00_rt(rt2x00dev
, RT3070
) ||
1429 rt2x00_rt(rt2x00dev
, RT3090
) ||
1430 rt2x00_rt(rt2x00dev
, RT3390
)) {
1431 rt2x00_eeprom_read(rt2x00dev
,
1432 EEPROM_NIC_CONF1
, &eeprom
);
1433 if (rt2x00_get_field16(eeprom
,
1434 EEPROM_NIC_CONF1_ANT_DIVERSITY
))
1435 rt2800_set_ant_diversity(rt2x00dev
,
1436 rt2x00dev
->default_ant
.rx
);
1438 rt2x00_set_field8(&r3
, BBP3_RX_ANTENNA
, 0);
1441 if (rt2x00_rt(rt2x00dev
, RT3572
) &&
1442 test_bit(CAPABILITY_BT_COEXIST
, &rt2x00dev
->cap_flags
)) {
1443 rt2x00_set_field8(&r3
, BBP3_RX_ADC
, 1);
1444 rt2x00_set_field8(&r3
, BBP3_RX_ANTENNA
,
1445 rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
);
1446 rt2800_set_ant_diversity(rt2x00dev
, ANTENNA_B
);
1448 rt2x00_set_field8(&r3
, BBP3_RX_ANTENNA
, 1);
1452 rt2x00_set_field8(&r3
, BBP3_RX_ANTENNA
, 2);
1456 rt2800_bbp_write(rt2x00dev
, 3, r3
);
1457 rt2800_bbp_write(rt2x00dev
, 1, r1
);
1459 EXPORT_SYMBOL_GPL(rt2800_config_ant
);
1461 static void rt2800_config_lna_gain(struct rt2x00_dev
*rt2x00dev
,
1462 struct rt2x00lib_conf
*libconf
)
1467 if (libconf
->rf
.channel
<= 14) {
1468 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LNA
, &eeprom
);
1469 lna_gain
= rt2x00_get_field16(eeprom
, EEPROM_LNA_BG
);
1470 } else if (libconf
->rf
.channel
<= 64) {
1471 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LNA
, &eeprom
);
1472 lna_gain
= rt2x00_get_field16(eeprom
, EEPROM_LNA_A0
);
1473 } else if (libconf
->rf
.channel
<= 128) {
1474 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_BG2
, &eeprom
);
1475 lna_gain
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_BG2_LNA_A1
);
1477 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_A2
, &eeprom
);
1478 lna_gain
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_A2_LNA_A2
);
1481 rt2x00dev
->lna_gain
= lna_gain
;
1484 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev
*rt2x00dev
,
1485 struct ieee80211_conf
*conf
,
1486 struct rf_channel
*rf
,
1487 struct channel_info
*info
)
1489 rt2x00_set_field32(&rf
->rf4
, RF4_FREQ_OFFSET
, rt2x00dev
->freq_offset
);
1491 if (rt2x00dev
->default_ant
.tx_chain_num
== 1)
1492 rt2x00_set_field32(&rf
->rf2
, RF2_ANTENNA_TX1
, 1);
1494 if (rt2x00dev
->default_ant
.rx_chain_num
== 1) {
1495 rt2x00_set_field32(&rf
->rf2
, RF2_ANTENNA_RX1
, 1);
1496 rt2x00_set_field32(&rf
->rf2
, RF2_ANTENNA_RX2
, 1);
1497 } else if (rt2x00dev
->default_ant
.rx_chain_num
== 2)
1498 rt2x00_set_field32(&rf
->rf2
, RF2_ANTENNA_RX2
, 1);
1500 if (rf
->channel
> 14) {
1502 * When TX power is below 0, we should increase it by 7 to
1503 * make it a positive value (Minimum value is -7).
1504 * However this means that values between 0 and 7 have
1505 * double meaning, and we should set a 7DBm boost flag.
1507 rt2x00_set_field32(&rf
->rf3
, RF3_TXPOWER_A_7DBM_BOOST
,
1508 (info
->default_power1
>= 0));
1510 if (info
->default_power1
< 0)
1511 info
->default_power1
+= 7;
1513 rt2x00_set_field32(&rf
->rf3
, RF3_TXPOWER_A
, info
->default_power1
);
1515 rt2x00_set_field32(&rf
->rf4
, RF4_TXPOWER_A_7DBM_BOOST
,
1516 (info
->default_power2
>= 0));
1518 if (info
->default_power2
< 0)
1519 info
->default_power2
+= 7;
1521 rt2x00_set_field32(&rf
->rf4
, RF4_TXPOWER_A
, info
->default_power2
);
1523 rt2x00_set_field32(&rf
->rf3
, RF3_TXPOWER_G
, info
->default_power1
);
1524 rt2x00_set_field32(&rf
->rf4
, RF4_TXPOWER_G
, info
->default_power2
);
1527 rt2x00_set_field32(&rf
->rf4
, RF4_HT40
, conf_is_ht40(conf
));
1529 rt2800_rf_write(rt2x00dev
, 1, rf
->rf1
);
1530 rt2800_rf_write(rt2x00dev
, 2, rf
->rf2
);
1531 rt2800_rf_write(rt2x00dev
, 3, rf
->rf3
& ~0x00000004);
1532 rt2800_rf_write(rt2x00dev
, 4, rf
->rf4
);
1536 rt2800_rf_write(rt2x00dev
, 1, rf
->rf1
);
1537 rt2800_rf_write(rt2x00dev
, 2, rf
->rf2
);
1538 rt2800_rf_write(rt2x00dev
, 3, rf
->rf3
| 0x00000004);
1539 rt2800_rf_write(rt2x00dev
, 4, rf
->rf4
);
1543 rt2800_rf_write(rt2x00dev
, 1, rf
->rf1
);
1544 rt2800_rf_write(rt2x00dev
, 2, rf
->rf2
);
1545 rt2800_rf_write(rt2x00dev
, 3, rf
->rf3
& ~0x00000004);
1546 rt2800_rf_write(rt2x00dev
, 4, rf
->rf4
);
1549 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev
*rt2x00dev
,
1550 struct ieee80211_conf
*conf
,
1551 struct rf_channel
*rf
,
1552 struct channel_info
*info
)
1556 rt2800_rfcsr_write(rt2x00dev
, 2, rf
->rf1
);
1557 rt2800_rfcsr_write(rt2x00dev
, 3, rf
->rf3
);
1559 rt2800_rfcsr_read(rt2x00dev
, 6, &rfcsr
);
1560 rt2x00_set_field8(&rfcsr
, RFCSR6_R1
, rf
->rf2
);
1561 rt2800_rfcsr_write(rt2x00dev
, 6, rfcsr
);
1563 rt2800_rfcsr_read(rt2x00dev
, 12, &rfcsr
);
1564 rt2x00_set_field8(&rfcsr
, RFCSR12_TX_POWER
, info
->default_power1
);
1565 rt2800_rfcsr_write(rt2x00dev
, 12, rfcsr
);
1567 rt2800_rfcsr_read(rt2x00dev
, 13, &rfcsr
);
1568 rt2x00_set_field8(&rfcsr
, RFCSR13_TX_POWER
, info
->default_power2
);
1569 rt2800_rfcsr_write(rt2x00dev
, 13, rfcsr
);
1571 rt2800_rfcsr_read(rt2x00dev
, 23, &rfcsr
);
1572 rt2x00_set_field8(&rfcsr
, RFCSR23_FREQ_OFFSET
, rt2x00dev
->freq_offset
);
1573 rt2800_rfcsr_write(rt2x00dev
, 23, rfcsr
);
1575 rt2800_rfcsr_write(rt2x00dev
, 24,
1576 rt2x00dev
->calibration
[conf_is_ht40(conf
)]);
1578 rt2800_rfcsr_read(rt2x00dev
, 7, &rfcsr
);
1579 rt2x00_set_field8(&rfcsr
, RFCSR7_RF_TUNING
, 1);
1580 rt2800_rfcsr_write(rt2x00dev
, 7, rfcsr
);
1583 static void rt2800_config_channel_rf3052(struct rt2x00_dev
*rt2x00dev
,
1584 struct ieee80211_conf
*conf
,
1585 struct rf_channel
*rf
,
1586 struct channel_info
*info
)
1591 if (rf
->channel
<= 14) {
1592 rt2800_bbp_write(rt2x00dev
, 25, 0x15);
1593 rt2800_bbp_write(rt2x00dev
, 26, 0x85);
1595 rt2800_bbp_write(rt2x00dev
, 25, 0x09);
1596 rt2800_bbp_write(rt2x00dev
, 26, 0xff);
1599 rt2800_rfcsr_write(rt2x00dev
, 2, rf
->rf1
);
1600 rt2800_rfcsr_write(rt2x00dev
, 3, rf
->rf3
);
1602 rt2800_rfcsr_read(rt2x00dev
, 6, &rfcsr
);
1603 rt2x00_set_field8(&rfcsr
, RFCSR6_R1
, rf
->rf2
);
1604 if (rf
->channel
<= 14)
1605 rt2x00_set_field8(&rfcsr
, RFCSR6_TXDIV
, 2);
1607 rt2x00_set_field8(&rfcsr
, RFCSR6_TXDIV
, 1);
1608 rt2800_rfcsr_write(rt2x00dev
, 6, rfcsr
);
1610 rt2800_rfcsr_read(rt2x00dev
, 5, &rfcsr
);
1611 if (rf
->channel
<= 14)
1612 rt2x00_set_field8(&rfcsr
, RFCSR5_R1
, 1);
1614 rt2x00_set_field8(&rfcsr
, RFCSR5_R1
, 2);
1615 rt2800_rfcsr_write(rt2x00dev
, 5, rfcsr
);
1617 rt2800_rfcsr_read(rt2x00dev
, 12, &rfcsr
);
1618 if (rf
->channel
<= 14) {
1619 rt2x00_set_field8(&rfcsr
, RFCSR12_DR0
, 3);
1620 rt2x00_set_field8(&rfcsr
, RFCSR12_TX_POWER
,
1621 (info
->default_power1
& 0x3) |
1622 ((info
->default_power1
& 0xC) << 1));
1624 rt2x00_set_field8(&rfcsr
, RFCSR12_DR0
, 7);
1625 rt2x00_set_field8(&rfcsr
, RFCSR12_TX_POWER
,
1626 (info
->default_power1
& 0x3) |
1627 ((info
->default_power1
& 0xC) << 1));
1629 rt2800_rfcsr_write(rt2x00dev
, 12, rfcsr
);
1631 rt2800_rfcsr_read(rt2x00dev
, 13, &rfcsr
);
1632 if (rf
->channel
<= 14) {
1633 rt2x00_set_field8(&rfcsr
, RFCSR13_DR0
, 3);
1634 rt2x00_set_field8(&rfcsr
, RFCSR13_TX_POWER
,
1635 (info
->default_power2
& 0x3) |
1636 ((info
->default_power2
& 0xC) << 1));
1638 rt2x00_set_field8(&rfcsr
, RFCSR13_DR0
, 7);
1639 rt2x00_set_field8(&rfcsr
, RFCSR13_TX_POWER
,
1640 (info
->default_power2
& 0x3) |
1641 ((info
->default_power2
& 0xC) << 1));
1643 rt2800_rfcsr_write(rt2x00dev
, 13, rfcsr
);
1645 rt2800_rfcsr_read(rt2x00dev
, 1, &rfcsr
);
1646 rt2x00_set_field8(&rfcsr
, RFCSR1_RF_BLOCK_EN
, 1);
1647 rt2x00_set_field8(&rfcsr
, RFCSR1_RX0_PD
, 0);
1648 rt2x00_set_field8(&rfcsr
, RFCSR1_TX0_PD
, 0);
1649 rt2x00_set_field8(&rfcsr
, RFCSR1_RX1_PD
, 0);
1650 rt2x00_set_field8(&rfcsr
, RFCSR1_TX1_PD
, 0);
1651 if (test_bit(CAPABILITY_BT_COEXIST
, &rt2x00dev
->cap_flags
)) {
1652 if (rf
->channel
<= 14) {
1653 rt2x00_set_field8(&rfcsr
, RFCSR1_RX0_PD
, 1);
1654 rt2x00_set_field8(&rfcsr
, RFCSR1_TX0_PD
, 1);
1656 rt2x00_set_field8(&rfcsr
, RFCSR1_RX2_PD
, 1);
1657 rt2x00_set_field8(&rfcsr
, RFCSR1_TX2_PD
, 1);
1659 switch (rt2x00dev
->default_ant
.tx_chain_num
) {
1661 rt2x00_set_field8(&rfcsr
, RFCSR1_TX1_PD
, 1);
1663 rt2x00_set_field8(&rfcsr
, RFCSR1_TX2_PD
, 1);
1667 switch (rt2x00dev
->default_ant
.rx_chain_num
) {
1669 rt2x00_set_field8(&rfcsr
, RFCSR1_RX1_PD
, 1);
1671 rt2x00_set_field8(&rfcsr
, RFCSR1_RX2_PD
, 1);
1675 rt2800_rfcsr_write(rt2x00dev
, 1, rfcsr
);
1677 rt2800_rfcsr_read(rt2x00dev
, 23, &rfcsr
);
1678 rt2x00_set_field8(&rfcsr
, RFCSR23_FREQ_OFFSET
, rt2x00dev
->freq_offset
);
1679 rt2800_rfcsr_write(rt2x00dev
, 23, rfcsr
);
1681 rt2800_rfcsr_write(rt2x00dev
, 24,
1682 rt2x00dev
->calibration
[conf_is_ht40(conf
)]);
1683 rt2800_rfcsr_write(rt2x00dev
, 31,
1684 rt2x00dev
->calibration
[conf_is_ht40(conf
)]);
1686 if (rf
->channel
<= 14) {
1687 rt2800_rfcsr_write(rt2x00dev
, 7, 0xd8);
1688 rt2800_rfcsr_write(rt2x00dev
, 9, 0xc3);
1689 rt2800_rfcsr_write(rt2x00dev
, 10, 0xf1);
1690 rt2800_rfcsr_write(rt2x00dev
, 11, 0xb9);
1691 rt2800_rfcsr_write(rt2x00dev
, 15, 0x53);
1692 rt2800_rfcsr_write(rt2x00dev
, 16, 0x4c);
1693 rt2800_rfcsr_write(rt2x00dev
, 17, 0x23);
1694 rt2800_rfcsr_write(rt2x00dev
, 19, 0x93);
1695 rt2800_rfcsr_write(rt2x00dev
, 20, 0xb3);
1696 rt2800_rfcsr_write(rt2x00dev
, 25, 0x15);
1697 rt2800_rfcsr_write(rt2x00dev
, 26, 0x85);
1698 rt2800_rfcsr_write(rt2x00dev
, 27, 0x00);
1699 rt2800_rfcsr_write(rt2x00dev
, 29, 0x9b);
1701 rt2800_rfcsr_write(rt2x00dev
, 7, 0x14);
1702 rt2800_rfcsr_write(rt2x00dev
, 9, 0xc0);
1703 rt2800_rfcsr_write(rt2x00dev
, 10, 0xf1);
1704 rt2800_rfcsr_write(rt2x00dev
, 11, 0x00);
1705 rt2800_rfcsr_write(rt2x00dev
, 15, 0x43);
1706 rt2800_rfcsr_write(rt2x00dev
, 16, 0x7a);
1707 rt2800_rfcsr_write(rt2x00dev
, 17, 0x23);
1708 if (rf
->channel
<= 64) {
1709 rt2800_rfcsr_write(rt2x00dev
, 19, 0xb7);
1710 rt2800_rfcsr_write(rt2x00dev
, 20, 0xf6);
1711 rt2800_rfcsr_write(rt2x00dev
, 25, 0x3d);
1712 } else if (rf
->channel
<= 128) {
1713 rt2800_rfcsr_write(rt2x00dev
, 19, 0x74);
1714 rt2800_rfcsr_write(rt2x00dev
, 20, 0xf4);
1715 rt2800_rfcsr_write(rt2x00dev
, 25, 0x01);
1717 rt2800_rfcsr_write(rt2x00dev
, 19, 0x72);
1718 rt2800_rfcsr_write(rt2x00dev
, 20, 0xf3);
1719 rt2800_rfcsr_write(rt2x00dev
, 25, 0x01);
1721 rt2800_rfcsr_write(rt2x00dev
, 26, 0x87);
1722 rt2800_rfcsr_write(rt2x00dev
, 27, 0x01);
1723 rt2800_rfcsr_write(rt2x00dev
, 29, 0x9f);
1726 rt2800_register_read(rt2x00dev
, GPIO_CTRL_CFG
, ®
);
1727 rt2x00_set_field32(®
, GPIO_CTRL_CFG_GPIOD_BIT7
, 0);
1728 if (rf
->channel
<= 14)
1729 rt2x00_set_field32(®
, GPIO_CTRL_CFG_BIT7
, 1);
1731 rt2x00_set_field32(®
, GPIO_CTRL_CFG_BIT7
, 0);
1732 rt2800_register_write(rt2x00dev
, GPIO_CTRL_CFG
, reg
);
1734 rt2800_rfcsr_read(rt2x00dev
, 7, &rfcsr
);
1735 rt2x00_set_field8(&rfcsr
, RFCSR7_RF_TUNING
, 1);
1736 rt2800_rfcsr_write(rt2x00dev
, 7, rfcsr
);
1739 #define RT5390_POWER_BOUND 0x27
1740 #define RT5390_FREQ_OFFSET_BOUND 0x5f
1742 static void rt2800_config_channel_rf53xx(struct rt2x00_dev
*rt2x00dev
,
1743 struct ieee80211_conf
*conf
,
1744 struct rf_channel
*rf
,
1745 struct channel_info
*info
)
1749 rt2800_rfcsr_write(rt2x00dev
, 8, rf
->rf1
);
1750 rt2800_rfcsr_write(rt2x00dev
, 9, rf
->rf3
);
1751 rt2800_rfcsr_read(rt2x00dev
, 11, &rfcsr
);
1752 rt2x00_set_field8(&rfcsr
, RFCSR11_R
, rf
->rf2
);
1753 rt2800_rfcsr_write(rt2x00dev
, 11, rfcsr
);
1755 rt2800_rfcsr_read(rt2x00dev
, 49, &rfcsr
);
1756 if (info
->default_power1
> RT5390_POWER_BOUND
)
1757 rt2x00_set_field8(&rfcsr
, RFCSR49_TX
, RT5390_POWER_BOUND
);
1759 rt2x00_set_field8(&rfcsr
, RFCSR49_TX
, info
->default_power1
);
1760 rt2800_rfcsr_write(rt2x00dev
, 49, rfcsr
);
1762 rt2800_rfcsr_read(rt2x00dev
, 1, &rfcsr
);
1763 rt2x00_set_field8(&rfcsr
, RFCSR1_RF_BLOCK_EN
, 1);
1764 rt2x00_set_field8(&rfcsr
, RFCSR1_PLL_PD
, 1);
1765 rt2x00_set_field8(&rfcsr
, RFCSR1_RX0_PD
, 1);
1766 rt2x00_set_field8(&rfcsr
, RFCSR1_TX0_PD
, 1);
1767 rt2800_rfcsr_write(rt2x00dev
, 1, rfcsr
);
1769 rt2800_rfcsr_read(rt2x00dev
, 17, &rfcsr
);
1770 if (rt2x00dev
->freq_offset
> RT5390_FREQ_OFFSET_BOUND
)
1771 rt2x00_set_field8(&rfcsr
, RFCSR17_CODE
,
1772 RT5390_FREQ_OFFSET_BOUND
);
1774 rt2x00_set_field8(&rfcsr
, RFCSR17_CODE
, rt2x00dev
->freq_offset
);
1775 rt2800_rfcsr_write(rt2x00dev
, 17, rfcsr
);
1777 if (rf
->channel
<= 14) {
1778 int idx
= rf
->channel
-1;
1780 if (test_bit(CAPABILITY_BT_COEXIST
, &rt2x00dev
->cap_flags
)) {
1781 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
)) {
1782 /* r55/r59 value array of channel 1~14 */
1783 static const char r55_bt_rev
[] = {0x83, 0x83,
1784 0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
1785 0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
1786 static const char r59_bt_rev
[] = {0x0e, 0x0e,
1787 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
1788 0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
1790 rt2800_rfcsr_write(rt2x00dev
, 55,
1792 rt2800_rfcsr_write(rt2x00dev
, 59,
1795 static const char r59_bt
[] = {0x8b, 0x8b, 0x8b,
1796 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
1797 0x88, 0x88, 0x86, 0x85, 0x84};
1799 rt2800_rfcsr_write(rt2x00dev
, 59, r59_bt
[idx
]);
1802 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
)) {
1803 static const char r55_nonbt_rev
[] = {0x23, 0x23,
1804 0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
1805 0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
1806 static const char r59_nonbt_rev
[] = {0x07, 0x07,
1807 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
1808 0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
1810 rt2800_rfcsr_write(rt2x00dev
, 55,
1811 r55_nonbt_rev
[idx
]);
1812 rt2800_rfcsr_write(rt2x00dev
, 59,
1813 r59_nonbt_rev
[idx
]);
1814 } else if (rt2x00_rt(rt2x00dev
, RT5390
)) {
1815 static const char r59_non_bt
[] = {0x8f, 0x8f,
1816 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
1817 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
1819 rt2800_rfcsr_write(rt2x00dev
, 59,
1825 rt2800_rfcsr_read(rt2x00dev
, 30, &rfcsr
);
1826 rt2x00_set_field8(&rfcsr
, RFCSR30_TX_H20M
, 0);
1827 rt2x00_set_field8(&rfcsr
, RFCSR30_RX_H20M
, 0);
1828 rt2800_rfcsr_write(rt2x00dev
, 30, rfcsr
);
1830 rt2800_rfcsr_read(rt2x00dev
, 3, &rfcsr
);
1831 rt2x00_set_field8(&rfcsr
, RFCSR30_RF_CALIBRATION
, 1);
1832 rt2800_rfcsr_write(rt2x00dev
, 3, rfcsr
);
1835 static void rt2800_config_channel(struct rt2x00_dev
*rt2x00dev
,
1836 struct ieee80211_conf
*conf
,
1837 struct rf_channel
*rf
,
1838 struct channel_info
*info
)
1841 unsigned int tx_pin
;
1844 if (rf
->channel
<= 14) {
1845 info
->default_power1
= TXPOWER_G_TO_DEV(info
->default_power1
);
1846 info
->default_power2
= TXPOWER_G_TO_DEV(info
->default_power2
);
1848 info
->default_power1
= TXPOWER_A_TO_DEV(info
->default_power1
);
1849 info
->default_power2
= TXPOWER_A_TO_DEV(info
->default_power2
);
1852 if (rt2x00_rf(rt2x00dev
, RF2020
) ||
1853 rt2x00_rf(rt2x00dev
, RF3020
) ||
1854 rt2x00_rf(rt2x00dev
, RF3021
) ||
1855 rt2x00_rf(rt2x00dev
, RF3022
) ||
1856 rt2x00_rf(rt2x00dev
, RF3320
))
1857 rt2800_config_channel_rf3xxx(rt2x00dev
, conf
, rf
, info
);
1858 else if (rt2x00_rf(rt2x00dev
, RF3052
))
1859 rt2800_config_channel_rf3052(rt2x00dev
, conf
, rf
, info
);
1860 else if (rt2x00_rf(rt2x00dev
, RF5370
) ||
1861 rt2x00_rf(rt2x00dev
, RF5390
))
1862 rt2800_config_channel_rf53xx(rt2x00dev
, conf
, rf
, info
);
1864 rt2800_config_channel_rf2xxx(rt2x00dev
, conf
, rf
, info
);
1867 * Change BBP settings
1869 rt2800_bbp_write(rt2x00dev
, 62, 0x37 - rt2x00dev
->lna_gain
);
1870 rt2800_bbp_write(rt2x00dev
, 63, 0x37 - rt2x00dev
->lna_gain
);
1871 rt2800_bbp_write(rt2x00dev
, 64, 0x37 - rt2x00dev
->lna_gain
);
1872 rt2800_bbp_write(rt2x00dev
, 86, 0);
1874 if (rf
->channel
<= 14) {
1875 if (!rt2x00_rt(rt2x00dev
, RT5390
)) {
1876 if (test_bit(CAPABILITY_EXTERNAL_LNA_BG
,
1877 &rt2x00dev
->cap_flags
)) {
1878 rt2800_bbp_write(rt2x00dev
, 82, 0x62);
1879 rt2800_bbp_write(rt2x00dev
, 75, 0x46);
1881 rt2800_bbp_write(rt2x00dev
, 82, 0x84);
1882 rt2800_bbp_write(rt2x00dev
, 75, 0x50);
1886 if (rt2x00_rt(rt2x00dev
, RT3572
))
1887 rt2800_bbp_write(rt2x00dev
, 82, 0x94);
1889 rt2800_bbp_write(rt2x00dev
, 82, 0xf2);
1891 if (test_bit(CAPABILITY_EXTERNAL_LNA_A
, &rt2x00dev
->cap_flags
))
1892 rt2800_bbp_write(rt2x00dev
, 75, 0x46);
1894 rt2800_bbp_write(rt2x00dev
, 75, 0x50);
1897 rt2800_register_read(rt2x00dev
, TX_BAND_CFG
, ®
);
1898 rt2x00_set_field32(®
, TX_BAND_CFG_HT40_MINUS
, conf_is_ht40_minus(conf
));
1899 rt2x00_set_field32(®
, TX_BAND_CFG_A
, rf
->channel
> 14);
1900 rt2x00_set_field32(®
, TX_BAND_CFG_BG
, rf
->channel
<= 14);
1901 rt2800_register_write(rt2x00dev
, TX_BAND_CFG
, reg
);
1903 if (rt2x00_rt(rt2x00dev
, RT3572
))
1904 rt2800_rfcsr_write(rt2x00dev
, 8, 0);
1908 /* Turn on unused PA or LNA when not using 1T or 1R */
1909 if (rt2x00dev
->default_ant
.tx_chain_num
== 2) {
1910 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_A1_EN
,
1912 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_G1_EN
,
1916 /* Turn on unused PA or LNA when not using 1T or 1R */
1917 if (rt2x00dev
->default_ant
.rx_chain_num
== 2) {
1918 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_LNA_PE_A1_EN
, 1);
1919 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_LNA_PE_G1_EN
, 1);
1922 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_LNA_PE_A0_EN
, 1);
1923 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_LNA_PE_G0_EN
, 1);
1924 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_RFTR_EN
, 1);
1925 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_TRSW_EN
, 1);
1926 if (test_bit(CAPABILITY_BT_COEXIST
, &rt2x00dev
->cap_flags
))
1927 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_G0_EN
, 1);
1929 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_G0_EN
,
1931 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_A0_EN
, rf
->channel
> 14);
1933 rt2800_register_write(rt2x00dev
, TX_PIN_CFG
, tx_pin
);
1935 if (rt2x00_rt(rt2x00dev
, RT3572
))
1936 rt2800_rfcsr_write(rt2x00dev
, 8, 0x80);
1938 rt2800_bbp_read(rt2x00dev
, 4, &bbp
);
1939 rt2x00_set_field8(&bbp
, BBP4_BANDWIDTH
, 2 * conf_is_ht40(conf
));
1940 rt2800_bbp_write(rt2x00dev
, 4, bbp
);
1942 rt2800_bbp_read(rt2x00dev
, 3, &bbp
);
1943 rt2x00_set_field8(&bbp
, BBP3_HT40_MINUS
, conf_is_ht40_minus(conf
));
1944 rt2800_bbp_write(rt2x00dev
, 3, bbp
);
1946 if (rt2x00_rt_rev(rt2x00dev
, RT2860
, REV_RT2860C
)) {
1947 if (conf_is_ht40(conf
)) {
1948 rt2800_bbp_write(rt2x00dev
, 69, 0x1a);
1949 rt2800_bbp_write(rt2x00dev
, 70, 0x0a);
1950 rt2800_bbp_write(rt2x00dev
, 73, 0x16);
1952 rt2800_bbp_write(rt2x00dev
, 69, 0x16);
1953 rt2800_bbp_write(rt2x00dev
, 70, 0x08);
1954 rt2800_bbp_write(rt2x00dev
, 73, 0x11);
1961 * Clear channel statistic counters
1963 rt2800_register_read(rt2x00dev
, CH_IDLE_STA
, ®
);
1964 rt2800_register_read(rt2x00dev
, CH_BUSY_STA
, ®
);
1965 rt2800_register_read(rt2x00dev
, CH_BUSY_STA_SEC
, ®
);
1968 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev
*rt2x00dev
)
1977 * Read TSSI boundaries for temperature compensation from
1980 * Array idx 0 1 2 3 4 5 6 7 8
1981 * Matching Delta value -4 -3 -2 -1 0 +1 +2 +3 +4
1982 * Example TSSI bounds 0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
1984 if (rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
) {
1985 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_BG1
, &eeprom
);
1986 tssi_bounds
[0] = rt2x00_get_field16(eeprom
,
1987 EEPROM_TSSI_BOUND_BG1_MINUS4
);
1988 tssi_bounds
[1] = rt2x00_get_field16(eeprom
,
1989 EEPROM_TSSI_BOUND_BG1_MINUS3
);
1991 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_BG2
, &eeprom
);
1992 tssi_bounds
[2] = rt2x00_get_field16(eeprom
,
1993 EEPROM_TSSI_BOUND_BG2_MINUS2
);
1994 tssi_bounds
[3] = rt2x00_get_field16(eeprom
,
1995 EEPROM_TSSI_BOUND_BG2_MINUS1
);
1997 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_BG3
, &eeprom
);
1998 tssi_bounds
[4] = rt2x00_get_field16(eeprom
,
1999 EEPROM_TSSI_BOUND_BG3_REF
);
2000 tssi_bounds
[5] = rt2x00_get_field16(eeprom
,
2001 EEPROM_TSSI_BOUND_BG3_PLUS1
);
2003 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_BG4
, &eeprom
);
2004 tssi_bounds
[6] = rt2x00_get_field16(eeprom
,
2005 EEPROM_TSSI_BOUND_BG4_PLUS2
);
2006 tssi_bounds
[7] = rt2x00_get_field16(eeprom
,
2007 EEPROM_TSSI_BOUND_BG4_PLUS3
);
2009 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_BG5
, &eeprom
);
2010 tssi_bounds
[8] = rt2x00_get_field16(eeprom
,
2011 EEPROM_TSSI_BOUND_BG5_PLUS4
);
2013 step
= rt2x00_get_field16(eeprom
,
2014 EEPROM_TSSI_BOUND_BG5_AGC_STEP
);
2016 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_A1
, &eeprom
);
2017 tssi_bounds
[0] = rt2x00_get_field16(eeprom
,
2018 EEPROM_TSSI_BOUND_A1_MINUS4
);
2019 tssi_bounds
[1] = rt2x00_get_field16(eeprom
,
2020 EEPROM_TSSI_BOUND_A1_MINUS3
);
2022 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_A2
, &eeprom
);
2023 tssi_bounds
[2] = rt2x00_get_field16(eeprom
,
2024 EEPROM_TSSI_BOUND_A2_MINUS2
);
2025 tssi_bounds
[3] = rt2x00_get_field16(eeprom
,
2026 EEPROM_TSSI_BOUND_A2_MINUS1
);
2028 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_A3
, &eeprom
);
2029 tssi_bounds
[4] = rt2x00_get_field16(eeprom
,
2030 EEPROM_TSSI_BOUND_A3_REF
);
2031 tssi_bounds
[5] = rt2x00_get_field16(eeprom
,
2032 EEPROM_TSSI_BOUND_A3_PLUS1
);
2034 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_A4
, &eeprom
);
2035 tssi_bounds
[6] = rt2x00_get_field16(eeprom
,
2036 EEPROM_TSSI_BOUND_A4_PLUS2
);
2037 tssi_bounds
[7] = rt2x00_get_field16(eeprom
,
2038 EEPROM_TSSI_BOUND_A4_PLUS3
);
2040 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_A5
, &eeprom
);
2041 tssi_bounds
[8] = rt2x00_get_field16(eeprom
,
2042 EEPROM_TSSI_BOUND_A5_PLUS4
);
2044 step
= rt2x00_get_field16(eeprom
,
2045 EEPROM_TSSI_BOUND_A5_AGC_STEP
);
2049 * Check if temperature compensation is supported.
2051 if (tssi_bounds
[4] == 0xff)
2055 * Read current TSSI (BBP 49).
2057 rt2800_bbp_read(rt2x00dev
, 49, ¤t_tssi
);
2060 * Compare TSSI value (BBP49) with the compensation boundaries
2061 * from the EEPROM and increase or decrease tx power.
2063 for (i
= 0; i
<= 3; i
++) {
2064 if (current_tssi
> tssi_bounds
[i
])
2069 for (i
= 8; i
>= 5; i
--) {
2070 if (current_tssi
< tssi_bounds
[i
])
2075 return (i
- 4) * step
;
2078 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev
*rt2x00dev
,
2079 enum ieee80211_band band
)
2086 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TXPOWER_DELTA
, &eeprom
);
2089 * HT40 compensation not required.
2091 if (eeprom
== 0xffff ||
2092 !test_bit(CONFIG_CHANNEL_HT40
, &rt2x00dev
->flags
))
2095 if (band
== IEEE80211_BAND_2GHZ
) {
2096 comp_en
= rt2x00_get_field16(eeprom
,
2097 EEPROM_TXPOWER_DELTA_ENABLE_2G
);
2099 comp_type
= rt2x00_get_field16(eeprom
,
2100 EEPROM_TXPOWER_DELTA_TYPE_2G
);
2101 comp_value
= rt2x00_get_field16(eeprom
,
2102 EEPROM_TXPOWER_DELTA_VALUE_2G
);
2104 comp_value
= -comp_value
;
2107 comp_en
= rt2x00_get_field16(eeprom
,
2108 EEPROM_TXPOWER_DELTA_ENABLE_5G
);
2110 comp_type
= rt2x00_get_field16(eeprom
,
2111 EEPROM_TXPOWER_DELTA_TYPE_5G
);
2112 comp_value
= rt2x00_get_field16(eeprom
,
2113 EEPROM_TXPOWER_DELTA_VALUE_5G
);
2115 comp_value
= -comp_value
;
2122 static u8
rt2800_compensate_txpower(struct rt2x00_dev
*rt2x00dev
, int is_rate_b
,
2123 enum ieee80211_band band
, int power_level
,
2124 u8 txpower
, int delta
)
2130 u8 eirp_txpower_criterion
;
2133 if (!((band
== IEEE80211_BAND_5GHZ
) && is_rate_b
))
2136 if (test_bit(CAPABILITY_POWER_LIMIT
, &rt2x00dev
->cap_flags
)) {
2138 * Check if eirp txpower exceed txpower_limit.
2139 * We use OFDM 6M as criterion and its eirp txpower
2140 * is stored at EEPROM_EIRP_MAX_TX_POWER.
2141 * .11b data rate need add additional 4dbm
2142 * when calculating eirp txpower.
2144 rt2800_register_read(rt2x00dev
, TX_PWR_CFG_0
, ®
);
2145 criterion
= rt2x00_get_field32(reg
, TX_PWR_CFG_0_6MBS
);
2147 rt2x00_eeprom_read(rt2x00dev
,
2148 EEPROM_EIRP_MAX_TX_POWER
, &eeprom
);
2150 if (band
== IEEE80211_BAND_2GHZ
)
2151 eirp_txpower_criterion
= rt2x00_get_field16(eeprom
,
2152 EEPROM_EIRP_MAX_TX_POWER_2GHZ
);
2154 eirp_txpower_criterion
= rt2x00_get_field16(eeprom
,
2155 EEPROM_EIRP_MAX_TX_POWER_5GHZ
);
2157 eirp_txpower
= eirp_txpower_criterion
+ (txpower
- criterion
) +
2158 (is_rate_b
? 4 : 0) + delta
;
2160 reg_limit
= (eirp_txpower
> power_level
) ?
2161 (eirp_txpower
- power_level
) : 0;
2165 return txpower
+ delta
- reg_limit
;
2168 static void rt2800_config_txpower(struct rt2x00_dev
*rt2x00dev
,
2169 enum ieee80211_band band
,
2181 * Calculate HT40 compensation delta
2183 delta
= rt2800_get_txpower_bw_comp(rt2x00dev
, band
);
2186 * calculate temperature compensation delta
2188 delta
+= rt2800_get_gain_calibration_delta(rt2x00dev
);
2191 * set to normal bbp tx power control mode: +/- 0dBm
2193 rt2800_bbp_read(rt2x00dev
, 1, &r1
);
2194 rt2x00_set_field8(&r1
, BBP1_TX_POWER_CTRL
, 0);
2195 rt2800_bbp_write(rt2x00dev
, 1, r1
);
2196 offset
= TX_PWR_CFG_0
;
2198 for (i
= 0; i
< EEPROM_TXPOWER_BYRATE_SIZE
; i
+= 2) {
2199 /* just to be safe */
2200 if (offset
> TX_PWR_CFG_4
)
2203 rt2800_register_read(rt2x00dev
, offset
, ®
);
2205 /* read the next four txpower values */
2206 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TXPOWER_BYRATE
+ i
,
2209 is_rate_b
= i
? 0 : 1;
2211 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
2212 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
2213 * TX_PWR_CFG_4: unknown
2215 txpower
= rt2x00_get_field16(eeprom
,
2216 EEPROM_TXPOWER_BYRATE_RATE0
);
2217 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
2218 power_level
, txpower
, delta
);
2219 rt2x00_set_field32(®
, TX_PWR_CFG_RATE0
, txpower
);
2222 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
2223 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
2224 * TX_PWR_CFG_4: unknown
2226 txpower
= rt2x00_get_field16(eeprom
,
2227 EEPROM_TXPOWER_BYRATE_RATE1
);
2228 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
2229 power_level
, txpower
, delta
);
2230 rt2x00_set_field32(®
, TX_PWR_CFG_RATE1
, txpower
);
2233 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
2234 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14,
2235 * TX_PWR_CFG_4: unknown
2237 txpower
= rt2x00_get_field16(eeprom
,
2238 EEPROM_TXPOWER_BYRATE_RATE2
);
2239 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
2240 power_level
, txpower
, delta
);
2241 rt2x00_set_field32(®
, TX_PWR_CFG_RATE2
, txpower
);
2244 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
2245 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15,
2246 * TX_PWR_CFG_4: unknown
2248 txpower
= rt2x00_get_field16(eeprom
,
2249 EEPROM_TXPOWER_BYRATE_RATE3
);
2250 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
2251 power_level
, txpower
, delta
);
2252 rt2x00_set_field32(®
, TX_PWR_CFG_RATE3
, txpower
);
2254 /* read the next four txpower values */
2255 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TXPOWER_BYRATE
+ i
+ 1,
2260 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
2261 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
2262 * TX_PWR_CFG_4: unknown
2264 txpower
= rt2x00_get_field16(eeprom
,
2265 EEPROM_TXPOWER_BYRATE_RATE0
);
2266 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
2267 power_level
, txpower
, delta
);
2268 rt2x00_set_field32(®
, TX_PWR_CFG_RATE4
, txpower
);
2271 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
2272 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
2273 * TX_PWR_CFG_4: unknown
2275 txpower
= rt2x00_get_field16(eeprom
,
2276 EEPROM_TXPOWER_BYRATE_RATE1
);
2277 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
2278 power_level
, txpower
, delta
);
2279 rt2x00_set_field32(®
, TX_PWR_CFG_RATE5
, txpower
);
2282 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
2283 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
2284 * TX_PWR_CFG_4: unknown
2286 txpower
= rt2x00_get_field16(eeprom
,
2287 EEPROM_TXPOWER_BYRATE_RATE2
);
2288 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
2289 power_level
, txpower
, delta
);
2290 rt2x00_set_field32(®
, TX_PWR_CFG_RATE6
, txpower
);
2293 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
2294 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
2295 * TX_PWR_CFG_4: unknown
2297 txpower
= rt2x00_get_field16(eeprom
,
2298 EEPROM_TXPOWER_BYRATE_RATE3
);
2299 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
2300 power_level
, txpower
, delta
);
2301 rt2x00_set_field32(®
, TX_PWR_CFG_RATE7
, txpower
);
2303 rt2800_register_write(rt2x00dev
, offset
, reg
);
2305 /* next TX_PWR_CFG register */
2310 void rt2800_gain_calibration(struct rt2x00_dev
*rt2x00dev
)
2312 rt2800_config_txpower(rt2x00dev
, rt2x00dev
->curr_band
,
2313 rt2x00dev
->tx_power
);
2315 EXPORT_SYMBOL_GPL(rt2800_gain_calibration
);
2317 static void rt2800_config_retry_limit(struct rt2x00_dev
*rt2x00dev
,
2318 struct rt2x00lib_conf
*libconf
)
2322 rt2800_register_read(rt2x00dev
, TX_RTY_CFG
, ®
);
2323 rt2x00_set_field32(®
, TX_RTY_CFG_SHORT_RTY_LIMIT
,
2324 libconf
->conf
->short_frame_max_tx_count
);
2325 rt2x00_set_field32(®
, TX_RTY_CFG_LONG_RTY_LIMIT
,
2326 libconf
->conf
->long_frame_max_tx_count
);
2327 rt2800_register_write(rt2x00dev
, TX_RTY_CFG
, reg
);
2330 static void rt2800_config_ps(struct rt2x00_dev
*rt2x00dev
,
2331 struct rt2x00lib_conf
*libconf
)
2333 enum dev_state state
=
2334 (libconf
->conf
->flags
& IEEE80211_CONF_PS
) ?
2335 STATE_SLEEP
: STATE_AWAKE
;
2338 if (state
== STATE_SLEEP
) {
2339 rt2800_register_write(rt2x00dev
, AUTOWAKEUP_CFG
, 0);
2341 rt2800_register_read(rt2x00dev
, AUTOWAKEUP_CFG
, ®
);
2342 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_AUTO_LEAD_TIME
, 5);
2343 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE
,
2344 libconf
->conf
->listen_interval
- 1);
2345 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_AUTOWAKE
, 1);
2346 rt2800_register_write(rt2x00dev
, AUTOWAKEUP_CFG
, reg
);
2348 rt2x00dev
->ops
->lib
->set_device_state(rt2x00dev
, state
);
2350 rt2800_register_read(rt2x00dev
, AUTOWAKEUP_CFG
, ®
);
2351 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_AUTO_LEAD_TIME
, 0);
2352 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE
, 0);
2353 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_AUTOWAKE
, 0);
2354 rt2800_register_write(rt2x00dev
, AUTOWAKEUP_CFG
, reg
);
2356 rt2x00dev
->ops
->lib
->set_device_state(rt2x00dev
, state
);
2360 void rt2800_config(struct rt2x00_dev
*rt2x00dev
,
2361 struct rt2x00lib_conf
*libconf
,
2362 const unsigned int flags
)
2364 /* Always recalculate LNA gain before changing configuration */
2365 rt2800_config_lna_gain(rt2x00dev
, libconf
);
2367 if (flags
& IEEE80211_CONF_CHANGE_CHANNEL
) {
2368 rt2800_config_channel(rt2x00dev
, libconf
->conf
,
2369 &libconf
->rf
, &libconf
->channel
);
2370 rt2800_config_txpower(rt2x00dev
, libconf
->conf
->channel
->band
,
2371 libconf
->conf
->power_level
);
2373 if (flags
& IEEE80211_CONF_CHANGE_POWER
)
2374 rt2800_config_txpower(rt2x00dev
, libconf
->conf
->channel
->band
,
2375 libconf
->conf
->power_level
);
2376 if (flags
& IEEE80211_CONF_CHANGE_RETRY_LIMITS
)
2377 rt2800_config_retry_limit(rt2x00dev
, libconf
);
2378 if (flags
& IEEE80211_CONF_CHANGE_PS
)
2379 rt2800_config_ps(rt2x00dev
, libconf
);
2381 EXPORT_SYMBOL_GPL(rt2800_config
);
2386 void rt2800_link_stats(struct rt2x00_dev
*rt2x00dev
, struct link_qual
*qual
)
2391 * Update FCS error count from register.
2393 rt2800_register_read(rt2x00dev
, RX_STA_CNT0
, ®
);
2394 qual
->rx_failed
= rt2x00_get_field32(reg
, RX_STA_CNT0_CRC_ERR
);
2396 EXPORT_SYMBOL_GPL(rt2800_link_stats
);
2398 static u8
rt2800_get_default_vgc(struct rt2x00_dev
*rt2x00dev
)
2400 if (rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
) {
2401 if (rt2x00_rt(rt2x00dev
, RT3070
) ||
2402 rt2x00_rt(rt2x00dev
, RT3071
) ||
2403 rt2x00_rt(rt2x00dev
, RT3090
) ||
2404 rt2x00_rt(rt2x00dev
, RT3390
) ||
2405 rt2x00_rt(rt2x00dev
, RT5390
))
2406 return 0x1c + (2 * rt2x00dev
->lna_gain
);
2408 return 0x2e + rt2x00dev
->lna_gain
;
2411 if (!test_bit(CONFIG_CHANNEL_HT40
, &rt2x00dev
->flags
))
2412 return 0x32 + (rt2x00dev
->lna_gain
* 5) / 3;
2414 return 0x3a + (rt2x00dev
->lna_gain
* 5) / 3;
2417 static inline void rt2800_set_vgc(struct rt2x00_dev
*rt2x00dev
,
2418 struct link_qual
*qual
, u8 vgc_level
)
2420 if (qual
->vgc_level
!= vgc_level
) {
2421 rt2800_bbp_write(rt2x00dev
, 66, vgc_level
);
2422 qual
->vgc_level
= vgc_level
;
2423 qual
->vgc_level_reg
= vgc_level
;
2427 void rt2800_reset_tuner(struct rt2x00_dev
*rt2x00dev
, struct link_qual
*qual
)
2429 rt2800_set_vgc(rt2x00dev
, qual
, rt2800_get_default_vgc(rt2x00dev
));
2431 EXPORT_SYMBOL_GPL(rt2800_reset_tuner
);
2433 void rt2800_link_tuner(struct rt2x00_dev
*rt2x00dev
, struct link_qual
*qual
,
2436 if (rt2x00_rt_rev(rt2x00dev
, RT2860
, REV_RT2860C
))
2440 * When RSSI is better then -80 increase VGC level with 0x10
2442 rt2800_set_vgc(rt2x00dev
, qual
,
2443 rt2800_get_default_vgc(rt2x00dev
) +
2444 ((qual
->rssi
> -80) * 0x10));
2446 EXPORT_SYMBOL_GPL(rt2800_link_tuner
);
2449 * Initialization functions.
2451 static int rt2800_init_registers(struct rt2x00_dev
*rt2x00dev
)
2458 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
2459 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_TX_DMA
, 0);
2460 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_DMA_BUSY
, 0);
2461 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_RX_DMA
, 0);
2462 rt2x00_set_field32(®
, WPDMA_GLO_CFG_RX_DMA_BUSY
, 0);
2463 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_WRITEBACK_DONE
, 1);
2464 rt2800_register_write(rt2x00dev
, WPDMA_GLO_CFG
, reg
);
2466 ret
= rt2800_drv_init_registers(rt2x00dev
);
2470 rt2800_register_read(rt2x00dev
, BCN_OFFSET0
, ®
);
2471 rt2x00_set_field32(®
, BCN_OFFSET0_BCN0
, 0xe0); /* 0x3800 */
2472 rt2x00_set_field32(®
, BCN_OFFSET0_BCN1
, 0xe8); /* 0x3a00 */
2473 rt2x00_set_field32(®
, BCN_OFFSET0_BCN2
, 0xf0); /* 0x3c00 */
2474 rt2x00_set_field32(®
, BCN_OFFSET0_BCN3
, 0xf8); /* 0x3e00 */
2475 rt2800_register_write(rt2x00dev
, BCN_OFFSET0
, reg
);
2477 rt2800_register_read(rt2x00dev
, BCN_OFFSET1
, ®
);
2478 rt2x00_set_field32(®
, BCN_OFFSET1_BCN4
, 0xc8); /* 0x3200 */
2479 rt2x00_set_field32(®
, BCN_OFFSET1_BCN5
, 0xd0); /* 0x3400 */
2480 rt2x00_set_field32(®
, BCN_OFFSET1_BCN6
, 0x77); /* 0x1dc0 */
2481 rt2x00_set_field32(®
, BCN_OFFSET1_BCN7
, 0x6f); /* 0x1bc0 */
2482 rt2800_register_write(rt2x00dev
, BCN_OFFSET1
, reg
);
2484 rt2800_register_write(rt2x00dev
, LEGACY_BASIC_RATE
, 0x0000013f);
2485 rt2800_register_write(rt2x00dev
, HT_BASIC_RATE
, 0x00008003);
2487 rt2800_register_write(rt2x00dev
, MAC_SYS_CTRL
, 0x00000000);
2489 rt2800_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
2490 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_INTERVAL
, 1600);
2491 rt2x00_set_field32(®
, BCN_TIME_CFG_TSF_TICKING
, 0);
2492 rt2x00_set_field32(®
, BCN_TIME_CFG_TSF_SYNC
, 0);
2493 rt2x00_set_field32(®
, BCN_TIME_CFG_TBTT_ENABLE
, 0);
2494 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_GEN
, 0);
2495 rt2x00_set_field32(®
, BCN_TIME_CFG_TX_TIME_COMPENSATE
, 0);
2496 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
2498 rt2800_config_filter(rt2x00dev
, FIF_ALLMULTI
);
2500 rt2800_register_read(rt2x00dev
, BKOFF_SLOT_CFG
, ®
);
2501 rt2x00_set_field32(®
, BKOFF_SLOT_CFG_SLOT_TIME
, 9);
2502 rt2x00_set_field32(®
, BKOFF_SLOT_CFG_CC_DELAY_TIME
, 2);
2503 rt2800_register_write(rt2x00dev
, BKOFF_SLOT_CFG
, reg
);
2505 if (rt2x00_rt(rt2x00dev
, RT3071
) ||
2506 rt2x00_rt(rt2x00dev
, RT3090
) ||
2507 rt2x00_rt(rt2x00dev
, RT3390
)) {
2508 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000400);
2509 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00000000);
2510 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3071
, REV_RT3071E
) ||
2511 rt2x00_rt_rev_lt(rt2x00dev
, RT3090
, REV_RT3090E
) ||
2512 rt2x00_rt_rev_lt(rt2x00dev
, RT3390
, REV_RT3390E
)) {
2513 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF1
, &eeprom
);
2514 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF1_DAC_TEST
))
2515 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
,
2518 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
,
2521 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x00000000);
2523 } else if (rt2x00_rt(rt2x00dev
, RT3070
)) {
2524 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000400);
2526 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070F
)) {
2527 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00000000);
2528 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x0000002c);
2530 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00080606);
2531 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x00000000);
2533 } else if (rt2800_is_305x_soc(rt2x00dev
)) {
2534 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000400);
2535 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00000000);
2536 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x00000030);
2537 } else if (rt2x00_rt(rt2x00dev
, RT3572
)) {
2538 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000400);
2539 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00080606);
2540 } else if (rt2x00_rt(rt2x00dev
, RT5390
)) {
2541 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000404);
2542 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00080606);
2543 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x00000000);
2545 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000000);
2546 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00080606);
2549 rt2800_register_read(rt2x00dev
, TX_LINK_CFG
, ®
);
2550 rt2x00_set_field32(®
, TX_LINK_CFG_REMOTE_MFB_LIFETIME
, 32);
2551 rt2x00_set_field32(®
, TX_LINK_CFG_MFB_ENABLE
, 0);
2552 rt2x00_set_field32(®
, TX_LINK_CFG_REMOTE_UMFS_ENABLE
, 0);
2553 rt2x00_set_field32(®
, TX_LINK_CFG_TX_MRQ_EN
, 0);
2554 rt2x00_set_field32(®
, TX_LINK_CFG_TX_RDG_EN
, 0);
2555 rt2x00_set_field32(®
, TX_LINK_CFG_TX_CF_ACK_EN
, 1);
2556 rt2x00_set_field32(®
, TX_LINK_CFG_REMOTE_MFB
, 0);
2557 rt2x00_set_field32(®
, TX_LINK_CFG_REMOTE_MFS
, 0);
2558 rt2800_register_write(rt2x00dev
, TX_LINK_CFG
, reg
);
2560 rt2800_register_read(rt2x00dev
, TX_TIMEOUT_CFG
, ®
);
2561 rt2x00_set_field32(®
, TX_TIMEOUT_CFG_MPDU_LIFETIME
, 9);
2562 rt2x00_set_field32(®
, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT
, 32);
2563 rt2x00_set_field32(®
, TX_TIMEOUT_CFG_TX_OP_TIMEOUT
, 10);
2564 rt2800_register_write(rt2x00dev
, TX_TIMEOUT_CFG
, reg
);
2566 rt2800_register_read(rt2x00dev
, MAX_LEN_CFG
, ®
);
2567 rt2x00_set_field32(®
, MAX_LEN_CFG_MAX_MPDU
, AGGREGATION_SIZE
);
2568 if (rt2x00_rt_rev_gte(rt2x00dev
, RT2872
, REV_RT2872E
) ||
2569 rt2x00_rt(rt2x00dev
, RT2883
) ||
2570 rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070E
))
2571 rt2x00_set_field32(®
, MAX_LEN_CFG_MAX_PSDU
, 2);
2573 rt2x00_set_field32(®
, MAX_LEN_CFG_MAX_PSDU
, 1);
2574 rt2x00_set_field32(®
, MAX_LEN_CFG_MIN_PSDU
, 0);
2575 rt2x00_set_field32(®
, MAX_LEN_CFG_MIN_MPDU
, 0);
2576 rt2800_register_write(rt2x00dev
, MAX_LEN_CFG
, reg
);
2578 rt2800_register_read(rt2x00dev
, LED_CFG
, ®
);
2579 rt2x00_set_field32(®
, LED_CFG_ON_PERIOD
, 70);
2580 rt2x00_set_field32(®
, LED_CFG_OFF_PERIOD
, 30);
2581 rt2x00_set_field32(®
, LED_CFG_SLOW_BLINK_PERIOD
, 3);
2582 rt2x00_set_field32(®
, LED_CFG_R_LED_MODE
, 3);
2583 rt2x00_set_field32(®
, LED_CFG_G_LED_MODE
, 3);
2584 rt2x00_set_field32(®
, LED_CFG_Y_LED_MODE
, 3);
2585 rt2x00_set_field32(®
, LED_CFG_LED_POLAR
, 1);
2586 rt2800_register_write(rt2x00dev
, LED_CFG
, reg
);
2588 rt2800_register_write(rt2x00dev
, PBF_MAX_PCNT
, 0x1f3fbf9f);
2590 rt2800_register_read(rt2x00dev
, TX_RTY_CFG
, ®
);
2591 rt2x00_set_field32(®
, TX_RTY_CFG_SHORT_RTY_LIMIT
, 15);
2592 rt2x00_set_field32(®
, TX_RTY_CFG_LONG_RTY_LIMIT
, 31);
2593 rt2x00_set_field32(®
, TX_RTY_CFG_LONG_RTY_THRE
, 2000);
2594 rt2x00_set_field32(®
, TX_RTY_CFG_NON_AGG_RTY_MODE
, 0);
2595 rt2x00_set_field32(®
, TX_RTY_CFG_AGG_RTY_MODE
, 0);
2596 rt2x00_set_field32(®
, TX_RTY_CFG_TX_AUTO_FB_ENABLE
, 1);
2597 rt2800_register_write(rt2x00dev
, TX_RTY_CFG
, reg
);
2599 rt2800_register_read(rt2x00dev
, AUTO_RSP_CFG
, ®
);
2600 rt2x00_set_field32(®
, AUTO_RSP_CFG_AUTORESPONDER
, 1);
2601 rt2x00_set_field32(®
, AUTO_RSP_CFG_BAC_ACK_POLICY
, 1);
2602 rt2x00_set_field32(®
, AUTO_RSP_CFG_CTS_40_MMODE
, 0);
2603 rt2x00_set_field32(®
, AUTO_RSP_CFG_CTS_40_MREF
, 0);
2604 rt2x00_set_field32(®
, AUTO_RSP_CFG_AR_PREAMBLE
, 1);
2605 rt2x00_set_field32(®
, AUTO_RSP_CFG_DUAL_CTS_EN
, 0);
2606 rt2x00_set_field32(®
, AUTO_RSP_CFG_ACK_CTS_PSM_BIT
, 0);
2607 rt2800_register_write(rt2x00dev
, AUTO_RSP_CFG
, reg
);
2609 rt2800_register_read(rt2x00dev
, CCK_PROT_CFG
, ®
);
2610 rt2x00_set_field32(®
, CCK_PROT_CFG_PROTECT_RATE
, 3);
2611 rt2x00_set_field32(®
, CCK_PROT_CFG_PROTECT_CTRL
, 0);
2612 rt2x00_set_field32(®
, CCK_PROT_CFG_PROTECT_NAV_SHORT
, 1);
2613 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
2614 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
2615 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
2616 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_MM40
, 0);
2617 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
2618 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_GF40
, 0);
2619 rt2x00_set_field32(®
, CCK_PROT_CFG_RTS_TH_EN
, 1);
2620 rt2800_register_write(rt2x00dev
, CCK_PROT_CFG
, reg
);
2622 rt2800_register_read(rt2x00dev
, OFDM_PROT_CFG
, ®
);
2623 rt2x00_set_field32(®
, OFDM_PROT_CFG_PROTECT_RATE
, 3);
2624 rt2x00_set_field32(®
, OFDM_PROT_CFG_PROTECT_CTRL
, 0);
2625 rt2x00_set_field32(®
, OFDM_PROT_CFG_PROTECT_NAV_SHORT
, 1);
2626 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
2627 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
2628 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
2629 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_MM40
, 0);
2630 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
2631 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_GF40
, 0);
2632 rt2x00_set_field32(®
, OFDM_PROT_CFG_RTS_TH_EN
, 1);
2633 rt2800_register_write(rt2x00dev
, OFDM_PROT_CFG
, reg
);
2635 rt2800_register_read(rt2x00dev
, MM20_PROT_CFG
, ®
);
2636 rt2x00_set_field32(®
, MM20_PROT_CFG_PROTECT_RATE
, 0x4004);
2637 rt2x00_set_field32(®
, MM20_PROT_CFG_PROTECT_CTRL
, 0);
2638 rt2x00_set_field32(®
, MM20_PROT_CFG_PROTECT_NAV_SHORT
, 1);
2639 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
2640 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
2641 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
2642 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_MM40
, 0);
2643 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
2644 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_GF40
, 0);
2645 rt2x00_set_field32(®
, MM20_PROT_CFG_RTS_TH_EN
, 0);
2646 rt2800_register_write(rt2x00dev
, MM20_PROT_CFG
, reg
);
2648 rt2800_register_read(rt2x00dev
, MM40_PROT_CFG
, ®
);
2649 rt2x00_set_field32(®
, MM40_PROT_CFG_PROTECT_RATE
, 0x4084);
2650 rt2x00_set_field32(®
, MM40_PROT_CFG_PROTECT_CTRL
, 0);
2651 rt2x00_set_field32(®
, MM40_PROT_CFG_PROTECT_NAV_SHORT
, 1);
2652 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
2653 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
2654 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
2655 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_MM40
, 1);
2656 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
2657 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_GF40
, 1);
2658 rt2x00_set_field32(®
, MM40_PROT_CFG_RTS_TH_EN
, 0);
2659 rt2800_register_write(rt2x00dev
, MM40_PROT_CFG
, reg
);
2661 rt2800_register_read(rt2x00dev
, GF20_PROT_CFG
, ®
);
2662 rt2x00_set_field32(®
, GF20_PROT_CFG_PROTECT_RATE
, 0x4004);
2663 rt2x00_set_field32(®
, GF20_PROT_CFG_PROTECT_CTRL
, 0);
2664 rt2x00_set_field32(®
, GF20_PROT_CFG_PROTECT_NAV_SHORT
, 1);
2665 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
2666 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
2667 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
2668 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_MM40
, 0);
2669 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
2670 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_GF40
, 0);
2671 rt2x00_set_field32(®
, GF20_PROT_CFG_RTS_TH_EN
, 0);
2672 rt2800_register_write(rt2x00dev
, GF20_PROT_CFG
, reg
);
2674 rt2800_register_read(rt2x00dev
, GF40_PROT_CFG
, ®
);
2675 rt2x00_set_field32(®
, GF40_PROT_CFG_PROTECT_RATE
, 0x4084);
2676 rt2x00_set_field32(®
, GF40_PROT_CFG_PROTECT_CTRL
, 0);
2677 rt2x00_set_field32(®
, GF40_PROT_CFG_PROTECT_NAV_SHORT
, 1);
2678 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
2679 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
2680 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
2681 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_MM40
, 1);
2682 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
2683 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_GF40
, 1);
2684 rt2x00_set_field32(®
, GF40_PROT_CFG_RTS_TH_EN
, 0);
2685 rt2800_register_write(rt2x00dev
, GF40_PROT_CFG
, reg
);
2687 if (rt2x00_is_usb(rt2x00dev
)) {
2688 rt2800_register_write(rt2x00dev
, PBF_CFG
, 0xf40006);
2690 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
2691 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_TX_DMA
, 0);
2692 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_DMA_BUSY
, 0);
2693 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_RX_DMA
, 0);
2694 rt2x00_set_field32(®
, WPDMA_GLO_CFG_RX_DMA_BUSY
, 0);
2695 rt2x00_set_field32(®
, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE
, 3);
2696 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_WRITEBACK_DONE
, 0);
2697 rt2x00_set_field32(®
, WPDMA_GLO_CFG_BIG_ENDIAN
, 0);
2698 rt2x00_set_field32(®
, WPDMA_GLO_CFG_RX_HDR_SCATTER
, 0);
2699 rt2x00_set_field32(®
, WPDMA_GLO_CFG_HDR_SEG_LEN
, 0);
2700 rt2800_register_write(rt2x00dev
, WPDMA_GLO_CFG
, reg
);
2704 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
2705 * although it is reserved.
2707 rt2800_register_read(rt2x00dev
, TXOP_CTRL_CFG
, ®
);
2708 rt2x00_set_field32(®
, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN
, 1);
2709 rt2x00_set_field32(®
, TXOP_CTRL_CFG_AC_TRUN_EN
, 1);
2710 rt2x00_set_field32(®
, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN
, 1);
2711 rt2x00_set_field32(®
, TXOP_CTRL_CFG_USER_MODE_TRUN_EN
, 1);
2712 rt2x00_set_field32(®
, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN
, 1);
2713 rt2x00_set_field32(®
, TXOP_CTRL_CFG_RESERVED_TRUN_EN
, 1);
2714 rt2x00_set_field32(®
, TXOP_CTRL_CFG_LSIG_TXOP_EN
, 0);
2715 rt2x00_set_field32(®
, TXOP_CTRL_CFG_EXT_CCA_EN
, 0);
2716 rt2x00_set_field32(®
, TXOP_CTRL_CFG_EXT_CCA_DLY
, 88);
2717 rt2x00_set_field32(®
, TXOP_CTRL_CFG_EXT_CWMIN
, 0);
2718 rt2800_register_write(rt2x00dev
, TXOP_CTRL_CFG
, reg
);
2720 rt2800_register_write(rt2x00dev
, TXOP_HLDR_ET
, 0x00000002);
2722 rt2800_register_read(rt2x00dev
, TX_RTS_CFG
, ®
);
2723 rt2x00_set_field32(®
, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT
, 32);
2724 rt2x00_set_field32(®
, TX_RTS_CFG_RTS_THRES
,
2725 IEEE80211_MAX_RTS_THRESHOLD
);
2726 rt2x00_set_field32(®
, TX_RTS_CFG_RTS_FBK_EN
, 0);
2727 rt2800_register_write(rt2x00dev
, TX_RTS_CFG
, reg
);
2729 rt2800_register_write(rt2x00dev
, EXP_ACK_TIME
, 0x002400ca);
2732 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
2733 * time should be set to 16. However, the original Ralink driver uses
2734 * 16 for both and indeed using a value of 10 for CCK SIFS results in
2735 * connection problems with 11g + CTS protection. Hence, use the same
2736 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
2738 rt2800_register_read(rt2x00dev
, XIFS_TIME_CFG
, ®
);
2739 rt2x00_set_field32(®
, XIFS_TIME_CFG_CCKM_SIFS_TIME
, 16);
2740 rt2x00_set_field32(®
, XIFS_TIME_CFG_OFDM_SIFS_TIME
, 16);
2741 rt2x00_set_field32(®
, XIFS_TIME_CFG_OFDM_XIFS_TIME
, 4);
2742 rt2x00_set_field32(®
, XIFS_TIME_CFG_EIFS
, 314);
2743 rt2x00_set_field32(®
, XIFS_TIME_CFG_BB_RXEND_ENABLE
, 1);
2744 rt2800_register_write(rt2x00dev
, XIFS_TIME_CFG
, reg
);
2746 rt2800_register_write(rt2x00dev
, PWR_PIN_CFG
, 0x00000003);
2749 * ASIC will keep garbage value after boot, clear encryption keys.
2751 for (i
= 0; i
< 4; i
++)
2752 rt2800_register_write(rt2x00dev
,
2753 SHARED_KEY_MODE_ENTRY(i
), 0);
2755 for (i
= 0; i
< 256; i
++) {
2756 static const u32 wcid
[2] = { 0xffffffff, 0x00ffffff };
2757 rt2800_register_multiwrite(rt2x00dev
, MAC_WCID_ENTRY(i
),
2758 wcid
, sizeof(wcid
));
2760 rt2800_register_write(rt2x00dev
, MAC_WCID_ATTR_ENTRY(i
), 0);
2761 rt2800_register_write(rt2x00dev
, MAC_IVEIV_ENTRY(i
), 0);
2767 rt2800_clear_beacon_register(rt2x00dev
, HW_BEACON_BASE0
);
2768 rt2800_clear_beacon_register(rt2x00dev
, HW_BEACON_BASE1
);
2769 rt2800_clear_beacon_register(rt2x00dev
, HW_BEACON_BASE2
);
2770 rt2800_clear_beacon_register(rt2x00dev
, HW_BEACON_BASE3
);
2771 rt2800_clear_beacon_register(rt2x00dev
, HW_BEACON_BASE4
);
2772 rt2800_clear_beacon_register(rt2x00dev
, HW_BEACON_BASE5
);
2773 rt2800_clear_beacon_register(rt2x00dev
, HW_BEACON_BASE6
);
2774 rt2800_clear_beacon_register(rt2x00dev
, HW_BEACON_BASE7
);
2776 if (rt2x00_is_usb(rt2x00dev
)) {
2777 rt2800_register_read(rt2x00dev
, US_CYC_CNT
, ®
);
2778 rt2x00_set_field32(®
, US_CYC_CNT_CLOCK_CYCLE
, 30);
2779 rt2800_register_write(rt2x00dev
, US_CYC_CNT
, reg
);
2780 } else if (rt2x00_is_pcie(rt2x00dev
)) {
2781 rt2800_register_read(rt2x00dev
, US_CYC_CNT
, ®
);
2782 rt2x00_set_field32(®
, US_CYC_CNT_CLOCK_CYCLE
, 125);
2783 rt2800_register_write(rt2x00dev
, US_CYC_CNT
, reg
);
2786 rt2800_register_read(rt2x00dev
, HT_FBK_CFG0
, ®
);
2787 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS0FBK
, 0);
2788 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS1FBK
, 0);
2789 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS2FBK
, 1);
2790 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS3FBK
, 2);
2791 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS4FBK
, 3);
2792 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS5FBK
, 4);
2793 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS6FBK
, 5);
2794 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS7FBK
, 6);
2795 rt2800_register_write(rt2x00dev
, HT_FBK_CFG0
, reg
);
2797 rt2800_register_read(rt2x00dev
, HT_FBK_CFG1
, ®
);
2798 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS8FBK
, 8);
2799 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS9FBK
, 8);
2800 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS10FBK
, 9);
2801 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS11FBK
, 10);
2802 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS12FBK
, 11);
2803 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS13FBK
, 12);
2804 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS14FBK
, 13);
2805 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS15FBK
, 14);
2806 rt2800_register_write(rt2x00dev
, HT_FBK_CFG1
, reg
);
2808 rt2800_register_read(rt2x00dev
, LG_FBK_CFG0
, ®
);
2809 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS0FBK
, 8);
2810 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS1FBK
, 8);
2811 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS2FBK
, 9);
2812 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS3FBK
, 10);
2813 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS4FBK
, 11);
2814 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS5FBK
, 12);
2815 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS6FBK
, 13);
2816 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS7FBK
, 14);
2817 rt2800_register_write(rt2x00dev
, LG_FBK_CFG0
, reg
);
2819 rt2800_register_read(rt2x00dev
, LG_FBK_CFG1
, ®
);
2820 rt2x00_set_field32(®
, LG_FBK_CFG0_CCKMCS0FBK
, 0);
2821 rt2x00_set_field32(®
, LG_FBK_CFG0_CCKMCS1FBK
, 0);
2822 rt2x00_set_field32(®
, LG_FBK_CFG0_CCKMCS2FBK
, 1);
2823 rt2x00_set_field32(®
, LG_FBK_CFG0_CCKMCS3FBK
, 2);
2824 rt2800_register_write(rt2x00dev
, LG_FBK_CFG1
, reg
);
2827 * Do not force the BA window size, we use the TXWI to set it
2829 rt2800_register_read(rt2x00dev
, AMPDU_BA_WINSIZE
, ®
);
2830 rt2x00_set_field32(®
, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE
, 0);
2831 rt2x00_set_field32(®
, AMPDU_BA_WINSIZE_FORCE_WINSIZE
, 0);
2832 rt2800_register_write(rt2x00dev
, AMPDU_BA_WINSIZE
, reg
);
2835 * We must clear the error counters.
2836 * These registers are cleared on read,
2837 * so we may pass a useless variable to store the value.
2839 rt2800_register_read(rt2x00dev
, RX_STA_CNT0
, ®
);
2840 rt2800_register_read(rt2x00dev
, RX_STA_CNT1
, ®
);
2841 rt2800_register_read(rt2x00dev
, RX_STA_CNT2
, ®
);
2842 rt2800_register_read(rt2x00dev
, TX_STA_CNT0
, ®
);
2843 rt2800_register_read(rt2x00dev
, TX_STA_CNT1
, ®
);
2844 rt2800_register_read(rt2x00dev
, TX_STA_CNT2
, ®
);
2847 * Setup leadtime for pre tbtt interrupt to 6ms
2849 rt2800_register_read(rt2x00dev
, INT_TIMER_CFG
, ®
);
2850 rt2x00_set_field32(®
, INT_TIMER_CFG_PRE_TBTT_TIMER
, 6 << 4);
2851 rt2800_register_write(rt2x00dev
, INT_TIMER_CFG
, reg
);
2854 * Set up channel statistics timer
2856 rt2800_register_read(rt2x00dev
, CH_TIME_CFG
, ®
);
2857 rt2x00_set_field32(®
, CH_TIME_CFG_EIFS_BUSY
, 1);
2858 rt2x00_set_field32(®
, CH_TIME_CFG_NAV_BUSY
, 1);
2859 rt2x00_set_field32(®
, CH_TIME_CFG_RX_BUSY
, 1);
2860 rt2x00_set_field32(®
, CH_TIME_CFG_TX_BUSY
, 1);
2861 rt2x00_set_field32(®
, CH_TIME_CFG_TMR_EN
, 1);
2862 rt2800_register_write(rt2x00dev
, CH_TIME_CFG
, reg
);
2867 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev
*rt2x00dev
)
2872 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
2873 rt2800_register_read(rt2x00dev
, MAC_STATUS_CFG
, ®
);
2874 if (!rt2x00_get_field32(reg
, MAC_STATUS_CFG_BBP_RF_BUSY
))
2877 udelay(REGISTER_BUSY_DELAY
);
2880 ERROR(rt2x00dev
, "BBP/RF register access failed, aborting.\n");
2884 static int rt2800_wait_bbp_ready(struct rt2x00_dev
*rt2x00dev
)
2890 * BBP was enabled after firmware was loaded,
2891 * but we need to reactivate it now.
2893 rt2800_register_write(rt2x00dev
, H2M_BBP_AGENT
, 0);
2894 rt2800_register_write(rt2x00dev
, H2M_MAILBOX_CSR
, 0);
2897 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
2898 rt2800_bbp_read(rt2x00dev
, 0, &value
);
2899 if ((value
!= 0xff) && (value
!= 0x00))
2901 udelay(REGISTER_BUSY_DELAY
);
2904 ERROR(rt2x00dev
, "BBP register access failed, aborting.\n");
2908 static int rt2800_init_bbp(struct rt2x00_dev
*rt2x00dev
)
2915 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev
) ||
2916 rt2800_wait_bbp_ready(rt2x00dev
)))
2919 if (rt2x00_rt(rt2x00dev
, RT5390
)) {
2920 rt2800_bbp_read(rt2x00dev
, 4, &value
);
2921 rt2x00_set_field8(&value
, BBP4_MAC_IF_CTRL
, 1);
2922 rt2800_bbp_write(rt2x00dev
, 4, value
);
2925 if (rt2800_is_305x_soc(rt2x00dev
) ||
2926 rt2x00_rt(rt2x00dev
, RT3572
) ||
2927 rt2x00_rt(rt2x00dev
, RT5390
))
2928 rt2800_bbp_write(rt2x00dev
, 31, 0x08);
2930 rt2800_bbp_write(rt2x00dev
, 65, 0x2c);
2931 rt2800_bbp_write(rt2x00dev
, 66, 0x38);
2933 if (rt2x00_rt(rt2x00dev
, RT5390
))
2934 rt2800_bbp_write(rt2x00dev
, 68, 0x0b);
2936 if (rt2x00_rt_rev(rt2x00dev
, RT2860
, REV_RT2860C
)) {
2937 rt2800_bbp_write(rt2x00dev
, 69, 0x16);
2938 rt2800_bbp_write(rt2x00dev
, 73, 0x12);
2939 } else if (rt2x00_rt(rt2x00dev
, RT5390
)) {
2940 rt2800_bbp_write(rt2x00dev
, 69, 0x12);
2941 rt2800_bbp_write(rt2x00dev
, 73, 0x13);
2942 rt2800_bbp_write(rt2x00dev
, 75, 0x46);
2943 rt2800_bbp_write(rt2x00dev
, 76, 0x28);
2944 rt2800_bbp_write(rt2x00dev
, 77, 0x59);
2946 rt2800_bbp_write(rt2x00dev
, 69, 0x12);
2947 rt2800_bbp_write(rt2x00dev
, 73, 0x10);
2950 rt2800_bbp_write(rt2x00dev
, 70, 0x0a);
2952 if (rt2x00_rt(rt2x00dev
, RT3070
) ||
2953 rt2x00_rt(rt2x00dev
, RT3071
) ||
2954 rt2x00_rt(rt2x00dev
, RT3090
) ||
2955 rt2x00_rt(rt2x00dev
, RT3390
) ||
2956 rt2x00_rt(rt2x00dev
, RT3572
) ||
2957 rt2x00_rt(rt2x00dev
, RT5390
)) {
2958 rt2800_bbp_write(rt2x00dev
, 79, 0x13);
2959 rt2800_bbp_write(rt2x00dev
, 80, 0x05);
2960 rt2800_bbp_write(rt2x00dev
, 81, 0x33);
2961 } else if (rt2800_is_305x_soc(rt2x00dev
)) {
2962 rt2800_bbp_write(rt2x00dev
, 78, 0x0e);
2963 rt2800_bbp_write(rt2x00dev
, 80, 0x08);
2965 rt2800_bbp_write(rt2x00dev
, 81, 0x37);
2968 rt2800_bbp_write(rt2x00dev
, 82, 0x62);
2969 if (rt2x00_rt(rt2x00dev
, RT5390
))
2970 rt2800_bbp_write(rt2x00dev
, 83, 0x7a);
2972 rt2800_bbp_write(rt2x00dev
, 83, 0x6a);
2974 if (rt2x00_rt_rev(rt2x00dev
, RT2860
, REV_RT2860D
))
2975 rt2800_bbp_write(rt2x00dev
, 84, 0x19);
2976 else if (rt2x00_rt(rt2x00dev
, RT5390
))
2977 rt2800_bbp_write(rt2x00dev
, 84, 0x9a);
2979 rt2800_bbp_write(rt2x00dev
, 84, 0x99);
2981 if (rt2x00_rt(rt2x00dev
, RT5390
))
2982 rt2800_bbp_write(rt2x00dev
, 86, 0x38);
2984 rt2800_bbp_write(rt2x00dev
, 86, 0x00);
2986 rt2800_bbp_write(rt2x00dev
, 91, 0x04);
2988 if (rt2x00_rt(rt2x00dev
, RT5390
))
2989 rt2800_bbp_write(rt2x00dev
, 92, 0x02);
2991 rt2800_bbp_write(rt2x00dev
, 92, 0x00);
2993 if (rt2x00_rt_rev_gte(rt2x00dev
, RT3070
, REV_RT3070F
) ||
2994 rt2x00_rt_rev_gte(rt2x00dev
, RT3071
, REV_RT3071E
) ||
2995 rt2x00_rt_rev_gte(rt2x00dev
, RT3090
, REV_RT3090E
) ||
2996 rt2x00_rt_rev_gte(rt2x00dev
, RT3390
, REV_RT3390E
) ||
2997 rt2x00_rt(rt2x00dev
, RT3572
) ||
2998 rt2x00_rt(rt2x00dev
, RT5390
) ||
2999 rt2800_is_305x_soc(rt2x00dev
))
3000 rt2800_bbp_write(rt2x00dev
, 103, 0xc0);
3002 rt2800_bbp_write(rt2x00dev
, 103, 0x00);
3004 if (rt2x00_rt(rt2x00dev
, RT5390
))
3005 rt2800_bbp_write(rt2x00dev
, 104, 0x92);
3007 if (rt2800_is_305x_soc(rt2x00dev
))
3008 rt2800_bbp_write(rt2x00dev
, 105, 0x01);
3009 else if (rt2x00_rt(rt2x00dev
, RT5390
))
3010 rt2800_bbp_write(rt2x00dev
, 105, 0x3c);
3012 rt2800_bbp_write(rt2x00dev
, 105, 0x05);
3014 if (rt2x00_rt(rt2x00dev
, RT5390
))
3015 rt2800_bbp_write(rt2x00dev
, 106, 0x03);
3017 rt2800_bbp_write(rt2x00dev
, 106, 0x35);
3019 if (rt2x00_rt(rt2x00dev
, RT5390
))
3020 rt2800_bbp_write(rt2x00dev
, 128, 0x12);
3022 if (rt2x00_rt(rt2x00dev
, RT3071
) ||
3023 rt2x00_rt(rt2x00dev
, RT3090
) ||
3024 rt2x00_rt(rt2x00dev
, RT3390
) ||
3025 rt2x00_rt(rt2x00dev
, RT3572
) ||
3026 rt2x00_rt(rt2x00dev
, RT5390
)) {
3027 rt2800_bbp_read(rt2x00dev
, 138, &value
);
3029 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF0
, &eeprom
);
3030 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_TXPATH
) == 1)
3032 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_RXPATH
) == 1)
3035 rt2800_bbp_write(rt2x00dev
, 138, value
);
3038 if (rt2x00_rt(rt2x00dev
, RT5390
)) {
3041 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF1
, &eeprom
);
3042 div_mode
= rt2x00_get_field16(eeprom
,
3043 EEPROM_NIC_CONF1_ANT_DIVERSITY
);
3044 ant
= (div_mode
== 3) ? 1 : 0;
3046 /* check if this is a Bluetooth combo card */
3047 if (test_bit(CAPABILITY_BT_COEXIST
, &rt2x00dev
->cap_flags
)) {
3050 rt2800_register_read(rt2x00dev
, GPIO_CTRL_CFG
, ®
);
3051 rt2x00_set_field32(®
, GPIO_CTRL_CFG_GPIOD_BIT3
, 0);
3052 rt2x00_set_field32(®
, GPIO_CTRL_CFG_GPIOD_BIT6
, 0);
3053 rt2x00_set_field32(®
, GPIO_CTRL_CFG_BIT3
, 0);
3054 rt2x00_set_field32(®
, GPIO_CTRL_CFG_BIT6
, 0);
3056 rt2x00_set_field32(®
, GPIO_CTRL_CFG_BIT3
, 1);
3058 rt2x00_set_field32(®
, GPIO_CTRL_CFG_BIT6
, 1);
3059 rt2800_register_write(rt2x00dev
, GPIO_CTRL_CFG
, reg
);
3062 rt2800_bbp_read(rt2x00dev
, 152, &value
);
3064 rt2x00_set_field8(&value
, BBP152_RX_DEFAULT_ANT
, 1);
3066 rt2x00_set_field8(&value
, BBP152_RX_DEFAULT_ANT
, 0);
3067 rt2800_bbp_write(rt2x00dev
, 152, value
);
3069 /* Init frequency calibration */
3070 rt2800_bbp_write(rt2x00dev
, 142, 1);
3071 rt2800_bbp_write(rt2x00dev
, 143, 57);
3074 for (i
= 0; i
< EEPROM_BBP_SIZE
; i
++) {
3075 rt2x00_eeprom_read(rt2x00dev
, EEPROM_BBP_START
+ i
, &eeprom
);
3077 if (eeprom
!= 0xffff && eeprom
!= 0x0000) {
3078 reg_id
= rt2x00_get_field16(eeprom
, EEPROM_BBP_REG_ID
);
3079 value
= rt2x00_get_field16(eeprom
, EEPROM_BBP_VALUE
);
3080 rt2800_bbp_write(rt2x00dev
, reg_id
, value
);
3087 static u8
rt2800_init_rx_filter(struct rt2x00_dev
*rt2x00dev
,
3088 bool bw40
, u8 rfcsr24
, u8 filter_target
)
3097 rt2800_rfcsr_write(rt2x00dev
, 24, rfcsr24
);
3099 rt2800_bbp_read(rt2x00dev
, 4, &bbp
);
3100 rt2x00_set_field8(&bbp
, BBP4_BANDWIDTH
, 2 * bw40
);
3101 rt2800_bbp_write(rt2x00dev
, 4, bbp
);
3103 rt2800_rfcsr_read(rt2x00dev
, 31, &rfcsr
);
3104 rt2x00_set_field8(&rfcsr
, RFCSR31_RX_H20M
, bw40
);
3105 rt2800_rfcsr_write(rt2x00dev
, 31, rfcsr
);
3107 rt2800_rfcsr_read(rt2x00dev
, 22, &rfcsr
);
3108 rt2x00_set_field8(&rfcsr
, RFCSR22_BASEBAND_LOOPBACK
, 1);
3109 rt2800_rfcsr_write(rt2x00dev
, 22, rfcsr
);
3112 * Set power & frequency of passband test tone
3114 rt2800_bbp_write(rt2x00dev
, 24, 0);
3116 for (i
= 0; i
< 100; i
++) {
3117 rt2800_bbp_write(rt2x00dev
, 25, 0x90);
3120 rt2800_bbp_read(rt2x00dev
, 55, &passband
);
3126 * Set power & frequency of stopband test tone
3128 rt2800_bbp_write(rt2x00dev
, 24, 0x06);
3130 for (i
= 0; i
< 100; i
++) {
3131 rt2800_bbp_write(rt2x00dev
, 25, 0x90);
3134 rt2800_bbp_read(rt2x00dev
, 55, &stopband
);
3136 if ((passband
- stopband
) <= filter_target
) {
3138 overtuned
+= ((passband
- stopband
) == filter_target
);
3142 rt2800_rfcsr_write(rt2x00dev
, 24, rfcsr24
);
3145 rfcsr24
-= !!overtuned
;
3147 rt2800_rfcsr_write(rt2x00dev
, 24, rfcsr24
);
3151 static int rt2800_init_rfcsr(struct rt2x00_dev
*rt2x00dev
)
3158 if (!rt2x00_rt(rt2x00dev
, RT3070
) &&
3159 !rt2x00_rt(rt2x00dev
, RT3071
) &&
3160 !rt2x00_rt(rt2x00dev
, RT3090
) &&
3161 !rt2x00_rt(rt2x00dev
, RT3390
) &&
3162 !rt2x00_rt(rt2x00dev
, RT3572
) &&
3163 !rt2x00_rt(rt2x00dev
, RT5390
) &&
3164 !rt2800_is_305x_soc(rt2x00dev
))
3168 * Init RF calibration.
3170 if (rt2x00_rt(rt2x00dev
, RT5390
)) {
3171 rt2800_rfcsr_read(rt2x00dev
, 2, &rfcsr
);
3172 rt2x00_set_field8(&rfcsr
, RFCSR2_RESCAL_EN
, 1);
3173 rt2800_rfcsr_write(rt2x00dev
, 2, rfcsr
);
3175 rt2x00_set_field8(&rfcsr
, RFCSR2_RESCAL_EN
, 0);
3176 rt2800_rfcsr_write(rt2x00dev
, 2, rfcsr
);
3178 rt2800_rfcsr_read(rt2x00dev
, 30, &rfcsr
);
3179 rt2x00_set_field8(&rfcsr
, RFCSR30_RF_CALIBRATION
, 1);
3180 rt2800_rfcsr_write(rt2x00dev
, 30, rfcsr
);
3182 rt2x00_set_field8(&rfcsr
, RFCSR30_RF_CALIBRATION
, 0);
3183 rt2800_rfcsr_write(rt2x00dev
, 30, rfcsr
);
3186 if (rt2x00_rt(rt2x00dev
, RT3070
) ||
3187 rt2x00_rt(rt2x00dev
, RT3071
) ||
3188 rt2x00_rt(rt2x00dev
, RT3090
)) {
3189 rt2800_rfcsr_write(rt2x00dev
, 4, 0x40);
3190 rt2800_rfcsr_write(rt2x00dev
, 5, 0x03);
3191 rt2800_rfcsr_write(rt2x00dev
, 6, 0x02);
3192 rt2800_rfcsr_write(rt2x00dev
, 7, 0x60);
3193 rt2800_rfcsr_write(rt2x00dev
, 9, 0x0f);
3194 rt2800_rfcsr_write(rt2x00dev
, 10, 0x41);
3195 rt2800_rfcsr_write(rt2x00dev
, 11, 0x21);
3196 rt2800_rfcsr_write(rt2x00dev
, 12, 0x7b);
3197 rt2800_rfcsr_write(rt2x00dev
, 14, 0x90);
3198 rt2800_rfcsr_write(rt2x00dev
, 15, 0x58);
3199 rt2800_rfcsr_write(rt2x00dev
, 16, 0xb3);
3200 rt2800_rfcsr_write(rt2x00dev
, 17, 0x92);
3201 rt2800_rfcsr_write(rt2x00dev
, 18, 0x2c);
3202 rt2800_rfcsr_write(rt2x00dev
, 19, 0x02);
3203 rt2800_rfcsr_write(rt2x00dev
, 20, 0xba);
3204 rt2800_rfcsr_write(rt2x00dev
, 21, 0xdb);
3205 rt2800_rfcsr_write(rt2x00dev
, 24, 0x16);
3206 rt2800_rfcsr_write(rt2x00dev
, 25, 0x01);
3207 rt2800_rfcsr_write(rt2x00dev
, 29, 0x1f);
3208 } else if (rt2x00_rt(rt2x00dev
, RT3390
)) {
3209 rt2800_rfcsr_write(rt2x00dev
, 0, 0xa0);
3210 rt2800_rfcsr_write(rt2x00dev
, 1, 0xe1);
3211 rt2800_rfcsr_write(rt2x00dev
, 2, 0xf1);
3212 rt2800_rfcsr_write(rt2x00dev
, 3, 0x62);
3213 rt2800_rfcsr_write(rt2x00dev
, 4, 0x40);
3214 rt2800_rfcsr_write(rt2x00dev
, 5, 0x8b);
3215 rt2800_rfcsr_write(rt2x00dev
, 6, 0x42);
3216 rt2800_rfcsr_write(rt2x00dev
, 7, 0x34);
3217 rt2800_rfcsr_write(rt2x00dev
, 8, 0x00);
3218 rt2800_rfcsr_write(rt2x00dev
, 9, 0xc0);
3219 rt2800_rfcsr_write(rt2x00dev
, 10, 0x61);
3220 rt2800_rfcsr_write(rt2x00dev
, 11, 0x21);
3221 rt2800_rfcsr_write(rt2x00dev
, 12, 0x3b);
3222 rt2800_rfcsr_write(rt2x00dev
, 13, 0xe0);
3223 rt2800_rfcsr_write(rt2x00dev
, 14, 0x90);
3224 rt2800_rfcsr_write(rt2x00dev
, 15, 0x53);
3225 rt2800_rfcsr_write(rt2x00dev
, 16, 0xe0);
3226 rt2800_rfcsr_write(rt2x00dev
, 17, 0x94);
3227 rt2800_rfcsr_write(rt2x00dev
, 18, 0x5c);
3228 rt2800_rfcsr_write(rt2x00dev
, 19, 0x4a);
3229 rt2800_rfcsr_write(rt2x00dev
, 20, 0xb2);
3230 rt2800_rfcsr_write(rt2x00dev
, 21, 0xf6);
3231 rt2800_rfcsr_write(rt2x00dev
, 22, 0x00);
3232 rt2800_rfcsr_write(rt2x00dev
, 23, 0x14);
3233 rt2800_rfcsr_write(rt2x00dev
, 24, 0x08);
3234 rt2800_rfcsr_write(rt2x00dev
, 25, 0x3d);
3235 rt2800_rfcsr_write(rt2x00dev
, 26, 0x85);
3236 rt2800_rfcsr_write(rt2x00dev
, 27, 0x00);
3237 rt2800_rfcsr_write(rt2x00dev
, 28, 0x41);
3238 rt2800_rfcsr_write(rt2x00dev
, 29, 0x8f);
3239 rt2800_rfcsr_write(rt2x00dev
, 30, 0x20);
3240 rt2800_rfcsr_write(rt2x00dev
, 31, 0x0f);
3241 } else if (rt2x00_rt(rt2x00dev
, RT3572
)) {
3242 rt2800_rfcsr_write(rt2x00dev
, 0, 0x70);
3243 rt2800_rfcsr_write(rt2x00dev
, 1, 0x81);
3244 rt2800_rfcsr_write(rt2x00dev
, 2, 0xf1);
3245 rt2800_rfcsr_write(rt2x00dev
, 3, 0x02);
3246 rt2800_rfcsr_write(rt2x00dev
, 4, 0x4c);
3247 rt2800_rfcsr_write(rt2x00dev
, 5, 0x05);
3248 rt2800_rfcsr_write(rt2x00dev
, 6, 0x4a);
3249 rt2800_rfcsr_write(rt2x00dev
, 7, 0xd8);
3250 rt2800_rfcsr_write(rt2x00dev
, 9, 0xc3);
3251 rt2800_rfcsr_write(rt2x00dev
, 10, 0xf1);
3252 rt2800_rfcsr_write(rt2x00dev
, 11, 0xb9);
3253 rt2800_rfcsr_write(rt2x00dev
, 12, 0x70);
3254 rt2800_rfcsr_write(rt2x00dev
, 13, 0x65);
3255 rt2800_rfcsr_write(rt2x00dev
, 14, 0xa0);
3256 rt2800_rfcsr_write(rt2x00dev
, 15, 0x53);
3257 rt2800_rfcsr_write(rt2x00dev
, 16, 0x4c);
3258 rt2800_rfcsr_write(rt2x00dev
, 17, 0x23);
3259 rt2800_rfcsr_write(rt2x00dev
, 18, 0xac);
3260 rt2800_rfcsr_write(rt2x00dev
, 19, 0x93);
3261 rt2800_rfcsr_write(rt2x00dev
, 20, 0xb3);
3262 rt2800_rfcsr_write(rt2x00dev
, 21, 0xd0);
3263 rt2800_rfcsr_write(rt2x00dev
, 22, 0x00);
3264 rt2800_rfcsr_write(rt2x00dev
, 23, 0x3c);
3265 rt2800_rfcsr_write(rt2x00dev
, 24, 0x16);
3266 rt2800_rfcsr_write(rt2x00dev
, 25, 0x15);
3267 rt2800_rfcsr_write(rt2x00dev
, 26, 0x85);
3268 rt2800_rfcsr_write(rt2x00dev
, 27, 0x00);
3269 rt2800_rfcsr_write(rt2x00dev
, 28, 0x00);
3270 rt2800_rfcsr_write(rt2x00dev
, 29, 0x9b);
3271 rt2800_rfcsr_write(rt2x00dev
, 30, 0x09);
3272 rt2800_rfcsr_write(rt2x00dev
, 31, 0x10);
3273 } else if (rt2800_is_305x_soc(rt2x00dev
)) {
3274 rt2800_rfcsr_write(rt2x00dev
, 0, 0x50);
3275 rt2800_rfcsr_write(rt2x00dev
, 1, 0x01);
3276 rt2800_rfcsr_write(rt2x00dev
, 2, 0xf7);
3277 rt2800_rfcsr_write(rt2x00dev
, 3, 0x75);
3278 rt2800_rfcsr_write(rt2x00dev
, 4, 0x40);
3279 rt2800_rfcsr_write(rt2x00dev
, 5, 0x03);
3280 rt2800_rfcsr_write(rt2x00dev
, 6, 0x02);
3281 rt2800_rfcsr_write(rt2x00dev
, 7, 0x50);
3282 rt2800_rfcsr_write(rt2x00dev
, 8, 0x39);
3283 rt2800_rfcsr_write(rt2x00dev
, 9, 0x0f);
3284 rt2800_rfcsr_write(rt2x00dev
, 10, 0x60);
3285 rt2800_rfcsr_write(rt2x00dev
, 11, 0x21);
3286 rt2800_rfcsr_write(rt2x00dev
, 12, 0x75);
3287 rt2800_rfcsr_write(rt2x00dev
, 13, 0x75);
3288 rt2800_rfcsr_write(rt2x00dev
, 14, 0x90);
3289 rt2800_rfcsr_write(rt2x00dev
, 15, 0x58);
3290 rt2800_rfcsr_write(rt2x00dev
, 16, 0xb3);
3291 rt2800_rfcsr_write(rt2x00dev
, 17, 0x92);
3292 rt2800_rfcsr_write(rt2x00dev
, 18, 0x2c);
3293 rt2800_rfcsr_write(rt2x00dev
, 19, 0x02);
3294 rt2800_rfcsr_write(rt2x00dev
, 20, 0xba);
3295 rt2800_rfcsr_write(rt2x00dev
, 21, 0xdb);
3296 rt2800_rfcsr_write(rt2x00dev
, 22, 0x00);
3297 rt2800_rfcsr_write(rt2x00dev
, 23, 0x31);
3298 rt2800_rfcsr_write(rt2x00dev
, 24, 0x08);
3299 rt2800_rfcsr_write(rt2x00dev
, 25, 0x01);
3300 rt2800_rfcsr_write(rt2x00dev
, 26, 0x25);
3301 rt2800_rfcsr_write(rt2x00dev
, 27, 0x23);
3302 rt2800_rfcsr_write(rt2x00dev
, 28, 0x13);
3303 rt2800_rfcsr_write(rt2x00dev
, 29, 0x83);
3304 rt2800_rfcsr_write(rt2x00dev
, 30, 0x00);
3305 rt2800_rfcsr_write(rt2x00dev
, 31, 0x00);
3307 } else if (rt2x00_rt(rt2x00dev
, RT5390
)) {
3308 rt2800_rfcsr_write(rt2x00dev
, 1, 0x0f);
3309 rt2800_rfcsr_write(rt2x00dev
, 2, 0x80);
3310 rt2800_rfcsr_write(rt2x00dev
, 3, 0x88);
3311 rt2800_rfcsr_write(rt2x00dev
, 5, 0x10);
3312 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
))
3313 rt2800_rfcsr_write(rt2x00dev
, 6, 0xe0);
3315 rt2800_rfcsr_write(rt2x00dev
, 6, 0xa0);
3316 rt2800_rfcsr_write(rt2x00dev
, 7, 0x00);
3317 rt2800_rfcsr_write(rt2x00dev
, 10, 0x53);
3318 rt2800_rfcsr_write(rt2x00dev
, 11, 0x4a);
3319 rt2800_rfcsr_write(rt2x00dev
, 12, 0xc6);
3320 rt2800_rfcsr_write(rt2x00dev
, 13, 0x9f);
3321 rt2800_rfcsr_write(rt2x00dev
, 14, 0x00);
3322 rt2800_rfcsr_write(rt2x00dev
, 15, 0x00);
3323 rt2800_rfcsr_write(rt2x00dev
, 16, 0x00);
3324 rt2800_rfcsr_write(rt2x00dev
, 18, 0x03);
3325 rt2800_rfcsr_write(rt2x00dev
, 19, 0x00);
3327 rt2800_rfcsr_write(rt2x00dev
, 20, 0x00);
3328 rt2800_rfcsr_write(rt2x00dev
, 21, 0x00);
3329 rt2800_rfcsr_write(rt2x00dev
, 22, 0x20);
3330 rt2800_rfcsr_write(rt2x00dev
, 23, 0x00);
3331 rt2800_rfcsr_write(rt2x00dev
, 24, 0x00);
3332 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
))
3333 rt2800_rfcsr_write(rt2x00dev
, 25, 0x80);
3335 rt2800_rfcsr_write(rt2x00dev
, 25, 0xc0);
3336 rt2800_rfcsr_write(rt2x00dev
, 26, 0x00);
3337 rt2800_rfcsr_write(rt2x00dev
, 27, 0x09);
3338 rt2800_rfcsr_write(rt2x00dev
, 28, 0x00);
3339 rt2800_rfcsr_write(rt2x00dev
, 29, 0x10);
3341 rt2800_rfcsr_write(rt2x00dev
, 30, 0x00);
3342 rt2800_rfcsr_write(rt2x00dev
, 31, 0x80);
3343 rt2800_rfcsr_write(rt2x00dev
, 32, 0x80);
3344 rt2800_rfcsr_write(rt2x00dev
, 33, 0x00);
3345 rt2800_rfcsr_write(rt2x00dev
, 34, 0x07);
3346 rt2800_rfcsr_write(rt2x00dev
, 35, 0x12);
3347 rt2800_rfcsr_write(rt2x00dev
, 36, 0x00);
3348 rt2800_rfcsr_write(rt2x00dev
, 37, 0x08);
3349 rt2800_rfcsr_write(rt2x00dev
, 38, 0x85);
3350 rt2800_rfcsr_write(rt2x00dev
, 39, 0x1b);
3352 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
))
3353 rt2800_rfcsr_write(rt2x00dev
, 40, 0x0b);
3355 rt2800_rfcsr_write(rt2x00dev
, 40, 0x4b);
3356 rt2800_rfcsr_write(rt2x00dev
, 41, 0xbb);
3357 rt2800_rfcsr_write(rt2x00dev
, 42, 0xd2);
3358 rt2800_rfcsr_write(rt2x00dev
, 43, 0x9a);
3359 rt2800_rfcsr_write(rt2x00dev
, 44, 0x0e);
3360 rt2800_rfcsr_write(rt2x00dev
, 45, 0xa2);
3361 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
))
3362 rt2800_rfcsr_write(rt2x00dev
, 46, 0x73);
3364 rt2800_rfcsr_write(rt2x00dev
, 46, 0x7b);
3365 rt2800_rfcsr_write(rt2x00dev
, 47, 0x00);
3366 rt2800_rfcsr_write(rt2x00dev
, 48, 0x10);
3367 rt2800_rfcsr_write(rt2x00dev
, 49, 0x94);
3369 rt2800_rfcsr_write(rt2x00dev
, 52, 0x38);
3370 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
))
3371 rt2800_rfcsr_write(rt2x00dev
, 53, 0x00);
3373 rt2800_rfcsr_write(rt2x00dev
, 53, 0x84);
3374 rt2800_rfcsr_write(rt2x00dev
, 54, 0x78);
3375 rt2800_rfcsr_write(rt2x00dev
, 55, 0x44);
3376 rt2800_rfcsr_write(rt2x00dev
, 56, 0x22);
3377 rt2800_rfcsr_write(rt2x00dev
, 57, 0x80);
3378 rt2800_rfcsr_write(rt2x00dev
, 58, 0x7f);
3379 rt2800_rfcsr_write(rt2x00dev
, 59, 0x63);
3381 rt2800_rfcsr_write(rt2x00dev
, 60, 0x45);
3382 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
))
3383 rt2800_rfcsr_write(rt2x00dev
, 61, 0xd1);
3385 rt2800_rfcsr_write(rt2x00dev
, 61, 0xdd);
3386 rt2800_rfcsr_write(rt2x00dev
, 62, 0x00);
3387 rt2800_rfcsr_write(rt2x00dev
, 63, 0x00);
3390 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070F
)) {
3391 rt2800_register_read(rt2x00dev
, LDO_CFG0
, ®
);
3392 rt2x00_set_field32(®
, LDO_CFG0_BGSEL
, 1);
3393 rt2x00_set_field32(®
, LDO_CFG0_LDO_CORE_VLEVEL
, 3);
3394 rt2800_register_write(rt2x00dev
, LDO_CFG0
, reg
);
3395 } else if (rt2x00_rt(rt2x00dev
, RT3071
) ||
3396 rt2x00_rt(rt2x00dev
, RT3090
)) {
3397 rt2800_rfcsr_write(rt2x00dev
, 31, 0x14);
3399 rt2800_rfcsr_read(rt2x00dev
, 6, &rfcsr
);
3400 rt2x00_set_field8(&rfcsr
, RFCSR6_R2
, 1);
3401 rt2800_rfcsr_write(rt2x00dev
, 6, rfcsr
);
3403 rt2800_register_read(rt2x00dev
, LDO_CFG0
, ®
);
3404 rt2x00_set_field32(®
, LDO_CFG0_BGSEL
, 1);
3405 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3071
, REV_RT3071E
) ||
3406 rt2x00_rt_rev_lt(rt2x00dev
, RT3090
, REV_RT3090E
)) {
3407 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF1
, &eeprom
);
3408 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF1_DAC_TEST
))
3409 rt2x00_set_field32(®
, LDO_CFG0_LDO_CORE_VLEVEL
, 3);
3411 rt2x00_set_field32(®
, LDO_CFG0_LDO_CORE_VLEVEL
, 0);
3413 rt2800_register_write(rt2x00dev
, LDO_CFG0
, reg
);
3415 rt2800_register_read(rt2x00dev
, GPIO_SWITCH
, ®
);
3416 rt2x00_set_field32(®
, GPIO_SWITCH_5
, 0);
3417 rt2800_register_write(rt2x00dev
, GPIO_SWITCH
, reg
);
3418 } else if (rt2x00_rt(rt2x00dev
, RT3390
)) {
3419 rt2800_register_read(rt2x00dev
, GPIO_SWITCH
, ®
);
3420 rt2x00_set_field32(®
, GPIO_SWITCH_5
, 0);
3421 rt2800_register_write(rt2x00dev
, GPIO_SWITCH
, reg
);
3422 } else if (rt2x00_rt(rt2x00dev
, RT3572
)) {
3423 rt2800_rfcsr_read(rt2x00dev
, 6, &rfcsr
);
3424 rt2x00_set_field8(&rfcsr
, RFCSR6_R2
, 1);
3425 rt2800_rfcsr_write(rt2x00dev
, 6, rfcsr
);
3427 rt2800_register_read(rt2x00dev
, LDO_CFG0
, ®
);
3428 rt2x00_set_field32(®
, LDO_CFG0_LDO_CORE_VLEVEL
, 3);
3429 rt2x00_set_field32(®
, LDO_CFG0_BGSEL
, 1);
3430 rt2800_register_write(rt2x00dev
, LDO_CFG0
, reg
);
3432 rt2800_register_read(rt2x00dev
, LDO_CFG0
, ®
);
3433 rt2x00_set_field32(®
, LDO_CFG0_BGSEL
, 1);
3434 rt2800_register_write(rt2x00dev
, LDO_CFG0
, reg
);
3438 * Set RX Filter calibration for 20MHz and 40MHz
3440 if (rt2x00_rt(rt2x00dev
, RT3070
)) {
3441 rt2x00dev
->calibration
[0] =
3442 rt2800_init_rx_filter(rt2x00dev
, false, 0x07, 0x16);
3443 rt2x00dev
->calibration
[1] =
3444 rt2800_init_rx_filter(rt2x00dev
, true, 0x27, 0x19);
3445 } else if (rt2x00_rt(rt2x00dev
, RT3071
) ||
3446 rt2x00_rt(rt2x00dev
, RT3090
) ||
3447 rt2x00_rt(rt2x00dev
, RT3390
) ||
3448 rt2x00_rt(rt2x00dev
, RT3572
)) {
3449 rt2x00dev
->calibration
[0] =
3450 rt2800_init_rx_filter(rt2x00dev
, false, 0x07, 0x13);
3451 rt2x00dev
->calibration
[1] =
3452 rt2800_init_rx_filter(rt2x00dev
, true, 0x27, 0x15);
3455 if (!rt2x00_rt(rt2x00dev
, RT5390
)) {
3457 * Set back to initial state
3459 rt2800_bbp_write(rt2x00dev
, 24, 0);
3461 rt2800_rfcsr_read(rt2x00dev
, 22, &rfcsr
);
3462 rt2x00_set_field8(&rfcsr
, RFCSR22_BASEBAND_LOOPBACK
, 0);
3463 rt2800_rfcsr_write(rt2x00dev
, 22, rfcsr
);
3466 * Set BBP back to BW20
3468 rt2800_bbp_read(rt2x00dev
, 4, &bbp
);
3469 rt2x00_set_field8(&bbp
, BBP4_BANDWIDTH
, 0);
3470 rt2800_bbp_write(rt2x00dev
, 4, bbp
);
3473 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070F
) ||
3474 rt2x00_rt_rev_lt(rt2x00dev
, RT3071
, REV_RT3071E
) ||
3475 rt2x00_rt_rev_lt(rt2x00dev
, RT3090
, REV_RT3090E
) ||
3476 rt2x00_rt_rev_lt(rt2x00dev
, RT3390
, REV_RT3390E
))
3477 rt2800_rfcsr_write(rt2x00dev
, 27, 0x03);
3479 rt2800_register_read(rt2x00dev
, OPT_14_CSR
, ®
);
3480 rt2x00_set_field32(®
, OPT_14_CSR_BIT0
, 1);
3481 rt2800_register_write(rt2x00dev
, OPT_14_CSR
, reg
);
3483 if (!rt2x00_rt(rt2x00dev
, RT5390
)) {
3484 rt2800_rfcsr_read(rt2x00dev
, 17, &rfcsr
);
3485 rt2x00_set_field8(&rfcsr
, RFCSR17_TX_LO1_EN
, 0);
3486 if (rt2x00_rt(rt2x00dev
, RT3070
) ||
3487 rt2x00_rt_rev_lt(rt2x00dev
, RT3071
, REV_RT3071E
) ||
3488 rt2x00_rt_rev_lt(rt2x00dev
, RT3090
, REV_RT3090E
) ||
3489 rt2x00_rt_rev_lt(rt2x00dev
, RT3390
, REV_RT3390E
)) {
3490 if (!test_bit(CAPABILITY_EXTERNAL_LNA_BG
,
3491 &rt2x00dev
->cap_flags
))
3492 rt2x00_set_field8(&rfcsr
, RFCSR17_R
, 1);
3494 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TXMIXER_GAIN_BG
, &eeprom
);
3495 if (rt2x00_get_field16(eeprom
, EEPROM_TXMIXER_GAIN_BG_VAL
) >= 1)
3496 rt2x00_set_field8(&rfcsr
, RFCSR17_TXMIXER_GAIN
,
3497 rt2x00_get_field16(eeprom
,
3498 EEPROM_TXMIXER_GAIN_BG_VAL
));
3499 rt2800_rfcsr_write(rt2x00dev
, 17, rfcsr
);
3502 if (rt2x00_rt(rt2x00dev
, RT3090
)) {
3503 rt2800_bbp_read(rt2x00dev
, 138, &bbp
);
3505 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
3506 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF0
, &eeprom
);
3507 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_RXPATH
) == 1)
3508 rt2x00_set_field8(&bbp
, BBP138_RX_ADC1
, 0);
3509 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_TXPATH
) == 1)
3510 rt2x00_set_field8(&bbp
, BBP138_TX_DAC1
, 1);
3512 rt2800_bbp_write(rt2x00dev
, 138, bbp
);
3515 if (rt2x00_rt(rt2x00dev
, RT3071
) ||
3516 rt2x00_rt(rt2x00dev
, RT3090
) ||
3517 rt2x00_rt(rt2x00dev
, RT3390
)) {
3518 rt2800_rfcsr_read(rt2x00dev
, 1, &rfcsr
);
3519 rt2x00_set_field8(&rfcsr
, RFCSR1_RF_BLOCK_EN
, 1);
3520 rt2x00_set_field8(&rfcsr
, RFCSR1_RX0_PD
, 0);
3521 rt2x00_set_field8(&rfcsr
, RFCSR1_TX0_PD
, 0);
3522 rt2x00_set_field8(&rfcsr
, RFCSR1_RX1_PD
, 1);
3523 rt2x00_set_field8(&rfcsr
, RFCSR1_TX1_PD
, 1);
3524 rt2800_rfcsr_write(rt2x00dev
, 1, rfcsr
);
3526 rt2800_rfcsr_read(rt2x00dev
, 15, &rfcsr
);
3527 rt2x00_set_field8(&rfcsr
, RFCSR15_TX_LO2_EN
, 0);
3528 rt2800_rfcsr_write(rt2x00dev
, 15, rfcsr
);
3530 rt2800_rfcsr_read(rt2x00dev
, 20, &rfcsr
);
3531 rt2x00_set_field8(&rfcsr
, RFCSR20_RX_LO1_EN
, 0);
3532 rt2800_rfcsr_write(rt2x00dev
, 20, rfcsr
);
3534 rt2800_rfcsr_read(rt2x00dev
, 21, &rfcsr
);
3535 rt2x00_set_field8(&rfcsr
, RFCSR21_RX_LO2_EN
, 0);
3536 rt2800_rfcsr_write(rt2x00dev
, 21, rfcsr
);
3539 if (rt2x00_rt(rt2x00dev
, RT3070
)) {
3540 rt2800_rfcsr_read(rt2x00dev
, 27, &rfcsr
);
3541 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070F
))
3542 rt2x00_set_field8(&rfcsr
, RFCSR27_R1
, 3);
3544 rt2x00_set_field8(&rfcsr
, RFCSR27_R1
, 0);
3545 rt2x00_set_field8(&rfcsr
, RFCSR27_R2
, 0);
3546 rt2x00_set_field8(&rfcsr
, RFCSR27_R3
, 0);
3547 rt2x00_set_field8(&rfcsr
, RFCSR27_R4
, 0);
3548 rt2800_rfcsr_write(rt2x00dev
, 27, rfcsr
);
3551 if (rt2x00_rt(rt2x00dev
, RT5390
)) {
3552 rt2800_rfcsr_read(rt2x00dev
, 38, &rfcsr
);
3553 rt2x00_set_field8(&rfcsr
, RFCSR38_RX_LO1_EN
, 0);
3554 rt2800_rfcsr_write(rt2x00dev
, 38, rfcsr
);
3556 rt2800_rfcsr_read(rt2x00dev
, 39, &rfcsr
);
3557 rt2x00_set_field8(&rfcsr
, RFCSR39_RX_LO2_EN
, 0);
3558 rt2800_rfcsr_write(rt2x00dev
, 39, rfcsr
);
3560 rt2800_rfcsr_read(rt2x00dev
, 30, &rfcsr
);
3561 rt2x00_set_field8(&rfcsr
, RFCSR30_RX_VCM
, 2);
3562 rt2800_rfcsr_write(rt2x00dev
, 30, rfcsr
);
3568 int rt2800_enable_radio(struct rt2x00_dev
*rt2x00dev
)
3574 * Initialize all registers.
3576 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev
) ||
3577 rt2800_init_registers(rt2x00dev
) ||
3578 rt2800_init_bbp(rt2x00dev
) ||
3579 rt2800_init_rfcsr(rt2x00dev
)))
3583 * Send signal to firmware during boot time.
3585 rt2800_mcu_request(rt2x00dev
, MCU_BOOT_SIGNAL
, 0, 0, 0);
3587 if (rt2x00_is_usb(rt2x00dev
) &&
3588 (rt2x00_rt(rt2x00dev
, RT3070
) ||
3589 rt2x00_rt(rt2x00dev
, RT3071
) ||
3590 rt2x00_rt(rt2x00dev
, RT3572
))) {
3592 rt2800_mcu_request(rt2x00dev
, MCU_CURRENT
, 0, 0, 0);
3599 rt2800_register_read(rt2x00dev
, MAC_SYS_CTRL
, ®
);
3600 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_TX
, 1);
3601 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_RX
, 0);
3602 rt2800_register_write(rt2x00dev
, MAC_SYS_CTRL
, reg
);
3606 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
3607 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_TX_DMA
, 1);
3608 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_RX_DMA
, 1);
3609 rt2x00_set_field32(®
, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE
, 2);
3610 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_WRITEBACK_DONE
, 1);
3611 rt2800_register_write(rt2x00dev
, WPDMA_GLO_CFG
, reg
);
3613 rt2800_register_read(rt2x00dev
, MAC_SYS_CTRL
, ®
);
3614 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_TX
, 1);
3615 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_RX
, 1);
3616 rt2800_register_write(rt2x00dev
, MAC_SYS_CTRL
, reg
);
3619 * Initialize LED control
3621 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LED_AG_CONF
, &word
);
3622 rt2800_mcu_request(rt2x00dev
, MCU_LED_AG_CONF
, 0xff,
3623 word
& 0xff, (word
>> 8) & 0xff);
3625 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LED_ACT_CONF
, &word
);
3626 rt2800_mcu_request(rt2x00dev
, MCU_LED_ACT_CONF
, 0xff,
3627 word
& 0xff, (word
>> 8) & 0xff);
3629 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LED_POLARITY
, &word
);
3630 rt2800_mcu_request(rt2x00dev
, MCU_LED_LED_POLARITY
, 0xff,
3631 word
& 0xff, (word
>> 8) & 0xff);
3635 EXPORT_SYMBOL_GPL(rt2800_enable_radio
);
3637 void rt2800_disable_radio(struct rt2x00_dev
*rt2x00dev
)
3641 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
3642 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_TX_DMA
, 0);
3643 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_RX_DMA
, 0);
3644 rt2800_register_write(rt2x00dev
, WPDMA_GLO_CFG
, reg
);
3646 /* Wait for DMA, ignore error */
3647 rt2800_wait_wpdma_ready(rt2x00dev
);
3649 rt2800_register_read(rt2x00dev
, MAC_SYS_CTRL
, ®
);
3650 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_TX
, 0);
3651 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_RX
, 0);
3652 rt2800_register_write(rt2x00dev
, MAC_SYS_CTRL
, reg
);
3654 EXPORT_SYMBOL_GPL(rt2800_disable_radio
);
3656 int rt2800_efuse_detect(struct rt2x00_dev
*rt2x00dev
)
3660 rt2800_register_read(rt2x00dev
, EFUSE_CTRL
, ®
);
3662 return rt2x00_get_field32(reg
, EFUSE_CTRL_PRESENT
);
3664 EXPORT_SYMBOL_GPL(rt2800_efuse_detect
);
3666 static void rt2800_efuse_read(struct rt2x00_dev
*rt2x00dev
, unsigned int i
)
3670 mutex_lock(&rt2x00dev
->csr_mutex
);
3672 rt2800_register_read_lock(rt2x00dev
, EFUSE_CTRL
, ®
);
3673 rt2x00_set_field32(®
, EFUSE_CTRL_ADDRESS_IN
, i
);
3674 rt2x00_set_field32(®
, EFUSE_CTRL_MODE
, 0);
3675 rt2x00_set_field32(®
, EFUSE_CTRL_KICK
, 1);
3676 rt2800_register_write_lock(rt2x00dev
, EFUSE_CTRL
, reg
);
3678 /* Wait until the EEPROM has been loaded */
3679 rt2800_regbusy_read(rt2x00dev
, EFUSE_CTRL
, EFUSE_CTRL_KICK
, ®
);
3681 /* Apparently the data is read from end to start */
3682 rt2800_register_read_lock(rt2x00dev
, EFUSE_DATA3
,
3683 (u32
*)&rt2x00dev
->eeprom
[i
]);
3684 rt2800_register_read_lock(rt2x00dev
, EFUSE_DATA2
,
3685 (u32
*)&rt2x00dev
->eeprom
[i
+ 2]);
3686 rt2800_register_read_lock(rt2x00dev
, EFUSE_DATA1
,
3687 (u32
*)&rt2x00dev
->eeprom
[i
+ 4]);
3688 rt2800_register_read_lock(rt2x00dev
, EFUSE_DATA0
,
3689 (u32
*)&rt2x00dev
->eeprom
[i
+ 6]);
3691 mutex_unlock(&rt2x00dev
->csr_mutex
);
3694 void rt2800_read_eeprom_efuse(struct rt2x00_dev
*rt2x00dev
)
3698 for (i
= 0; i
< EEPROM_SIZE
/ sizeof(u16
); i
+= 8)
3699 rt2800_efuse_read(rt2x00dev
, i
);
3701 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse
);
3703 int rt2800_validate_eeprom(struct rt2x00_dev
*rt2x00dev
)
3707 u8 default_lna_gain
;
3710 * Start validation of the data that has been read.
3712 mac
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_MAC_ADDR_0
);
3713 if (!is_valid_ether_addr(mac
)) {
3714 random_ether_addr(mac
);
3715 EEPROM(rt2x00dev
, "MAC: %pM\n", mac
);
3718 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF0
, &word
);
3719 if (word
== 0xffff) {
3720 rt2x00_set_field16(&word
, EEPROM_NIC_CONF0_RXPATH
, 2);
3721 rt2x00_set_field16(&word
, EEPROM_NIC_CONF0_TXPATH
, 1);
3722 rt2x00_set_field16(&word
, EEPROM_NIC_CONF0_RF_TYPE
, RF2820
);
3723 rt2x00_eeprom_write(rt2x00dev
, EEPROM_NIC_CONF0
, word
);
3724 EEPROM(rt2x00dev
, "Antenna: 0x%04x\n", word
);
3725 } else if (rt2x00_rt(rt2x00dev
, RT2860
) ||
3726 rt2x00_rt(rt2x00dev
, RT2872
)) {
3728 * There is a max of 2 RX streams for RT28x0 series
3730 if (rt2x00_get_field16(word
, EEPROM_NIC_CONF0_RXPATH
) > 2)
3731 rt2x00_set_field16(&word
, EEPROM_NIC_CONF0_RXPATH
, 2);
3732 rt2x00_eeprom_write(rt2x00dev
, EEPROM_NIC_CONF0
, word
);
3735 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF1
, &word
);
3736 if (word
== 0xffff) {
3737 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_HW_RADIO
, 0);
3738 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC
, 0);
3739 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G
, 0);
3740 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G
, 0);
3741 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_CARDBUS_ACCEL
, 0);
3742 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_BW40M_SB_2G
, 0);
3743 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_BW40M_SB_5G
, 0);
3744 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_WPS_PBC
, 0);
3745 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_BW40M_2G
, 0);
3746 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_BW40M_5G
, 0);
3747 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA
, 0);
3748 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_ANT_DIVERSITY
, 0);
3749 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_INTERNAL_TX_ALC
, 0);
3750 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_BT_COEXIST
, 0);
3751 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_DAC_TEST
, 0);
3752 rt2x00_eeprom_write(rt2x00dev
, EEPROM_NIC_CONF1
, word
);
3753 EEPROM(rt2x00dev
, "NIC: 0x%04x\n", word
);
3756 rt2x00_eeprom_read(rt2x00dev
, EEPROM_FREQ
, &word
);
3757 if ((word
& 0x00ff) == 0x00ff) {
3758 rt2x00_set_field16(&word
, EEPROM_FREQ_OFFSET
, 0);
3759 rt2x00_eeprom_write(rt2x00dev
, EEPROM_FREQ
, word
);
3760 EEPROM(rt2x00dev
, "Freq: 0x%04x\n", word
);
3762 if ((word
& 0xff00) == 0xff00) {
3763 rt2x00_set_field16(&word
, EEPROM_FREQ_LED_MODE
,
3764 LED_MODE_TXRX_ACTIVITY
);
3765 rt2x00_set_field16(&word
, EEPROM_FREQ_LED_POLARITY
, 0);
3766 rt2x00_eeprom_write(rt2x00dev
, EEPROM_FREQ
, word
);
3767 rt2x00_eeprom_write(rt2x00dev
, EEPROM_LED_AG_CONF
, 0x5555);
3768 rt2x00_eeprom_write(rt2x00dev
, EEPROM_LED_ACT_CONF
, 0x2221);
3769 rt2x00_eeprom_write(rt2x00dev
, EEPROM_LED_POLARITY
, 0xa9f8);
3770 EEPROM(rt2x00dev
, "Led Mode: 0x%04x\n", word
);
3774 * During the LNA validation we are going to use
3775 * lna0 as correct value. Note that EEPROM_LNA
3776 * is never validated.
3778 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LNA
, &word
);
3779 default_lna_gain
= rt2x00_get_field16(word
, EEPROM_LNA_A0
);
3781 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_BG
, &word
);
3782 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_BG_OFFSET0
)) > 10)
3783 rt2x00_set_field16(&word
, EEPROM_RSSI_BG_OFFSET0
, 0);
3784 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_BG_OFFSET1
)) > 10)
3785 rt2x00_set_field16(&word
, EEPROM_RSSI_BG_OFFSET1
, 0);
3786 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_BG
, word
);
3788 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_BG2
, &word
);
3789 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_BG2_OFFSET2
)) > 10)
3790 rt2x00_set_field16(&word
, EEPROM_RSSI_BG2_OFFSET2
, 0);
3791 if (rt2x00_get_field16(word
, EEPROM_RSSI_BG2_LNA_A1
) == 0x00 ||
3792 rt2x00_get_field16(word
, EEPROM_RSSI_BG2_LNA_A1
) == 0xff)
3793 rt2x00_set_field16(&word
, EEPROM_RSSI_BG2_LNA_A1
,
3795 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_BG2
, word
);
3797 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_A
, &word
);
3798 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_A_OFFSET0
)) > 10)
3799 rt2x00_set_field16(&word
, EEPROM_RSSI_A_OFFSET0
, 0);
3800 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_A_OFFSET1
)) > 10)
3801 rt2x00_set_field16(&word
, EEPROM_RSSI_A_OFFSET1
, 0);
3802 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_A
, word
);
3804 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_A2
, &word
);
3805 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_A2_OFFSET2
)) > 10)
3806 rt2x00_set_field16(&word
, EEPROM_RSSI_A2_OFFSET2
, 0);
3807 if (rt2x00_get_field16(word
, EEPROM_RSSI_A2_LNA_A2
) == 0x00 ||
3808 rt2x00_get_field16(word
, EEPROM_RSSI_A2_LNA_A2
) == 0xff)
3809 rt2x00_set_field16(&word
, EEPROM_RSSI_A2_LNA_A2
,
3811 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_A2
, word
);
3815 EXPORT_SYMBOL_GPL(rt2800_validate_eeprom
);
3817 int rt2800_init_eeprom(struct rt2x00_dev
*rt2x00dev
)
3824 * Read EEPROM word for configuration.
3826 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF0
, &eeprom
);
3829 * Identify RF chipset by EEPROM value
3830 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
3831 * RT53xx: defined in "EEPROM_CHIP_ID" field
3833 rt2800_register_read(rt2x00dev
, MAC_CSR0
, ®
);
3834 if (rt2x00_get_field32(reg
, MAC_CSR0_CHIPSET
) == RT5390
)
3835 rt2x00_eeprom_read(rt2x00dev
, EEPROM_CHIP_ID
, &value
);
3837 value
= rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_RF_TYPE
);
3839 rt2x00_set_chip(rt2x00dev
, rt2x00_get_field32(reg
, MAC_CSR0_CHIPSET
),
3840 value
, rt2x00_get_field32(reg
, MAC_CSR0_REVISION
));
3842 if (!rt2x00_rt(rt2x00dev
, RT2860
) &&
3843 !rt2x00_rt(rt2x00dev
, RT2872
) &&
3844 !rt2x00_rt(rt2x00dev
, RT2883
) &&
3845 !rt2x00_rt(rt2x00dev
, RT3070
) &&
3846 !rt2x00_rt(rt2x00dev
, RT3071
) &&
3847 !rt2x00_rt(rt2x00dev
, RT3090
) &&
3848 !rt2x00_rt(rt2x00dev
, RT3390
) &&
3849 !rt2x00_rt(rt2x00dev
, RT3572
) &&
3850 !rt2x00_rt(rt2x00dev
, RT5390
)) {
3851 ERROR(rt2x00dev
, "Invalid RT chipset detected.\n");
3855 if (!rt2x00_rf(rt2x00dev
, RF2820
) &&
3856 !rt2x00_rf(rt2x00dev
, RF2850
) &&
3857 !rt2x00_rf(rt2x00dev
, RF2720
) &&
3858 !rt2x00_rf(rt2x00dev
, RF2750
) &&
3859 !rt2x00_rf(rt2x00dev
, RF3020
) &&
3860 !rt2x00_rf(rt2x00dev
, RF2020
) &&
3861 !rt2x00_rf(rt2x00dev
, RF3021
) &&
3862 !rt2x00_rf(rt2x00dev
, RF3022
) &&
3863 !rt2x00_rf(rt2x00dev
, RF3052
) &&
3864 !rt2x00_rf(rt2x00dev
, RF3320
) &&
3865 !rt2x00_rf(rt2x00dev
, RF5370
) &&
3866 !rt2x00_rf(rt2x00dev
, RF5390
)) {
3867 ERROR(rt2x00dev
, "Invalid RF chipset detected.\n");
3872 * Identify default antenna configuration.
3874 rt2x00dev
->default_ant
.tx_chain_num
=
3875 rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_TXPATH
);
3876 rt2x00dev
->default_ant
.rx_chain_num
=
3877 rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_RXPATH
);
3879 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF1
, &eeprom
);
3881 if (rt2x00_rt(rt2x00dev
, RT3070
) ||
3882 rt2x00_rt(rt2x00dev
, RT3090
) ||
3883 rt2x00_rt(rt2x00dev
, RT3390
)) {
3884 value
= rt2x00_get_field16(eeprom
,
3885 EEPROM_NIC_CONF1_ANT_DIVERSITY
);
3890 rt2x00dev
->default_ant
.tx
= ANTENNA_A
;
3891 rt2x00dev
->default_ant
.rx
= ANTENNA_A
;
3894 rt2x00dev
->default_ant
.tx
= ANTENNA_A
;
3895 rt2x00dev
->default_ant
.rx
= ANTENNA_B
;
3899 rt2x00dev
->default_ant
.tx
= ANTENNA_A
;
3900 rt2x00dev
->default_ant
.rx
= ANTENNA_A
;
3904 * Determine external LNA informations.
3906 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G
))
3907 __set_bit(CAPABILITY_EXTERNAL_LNA_A
, &rt2x00dev
->cap_flags
);
3908 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G
))
3909 __set_bit(CAPABILITY_EXTERNAL_LNA_BG
, &rt2x00dev
->cap_flags
);
3912 * Detect if this device has an hardware controlled radio.
3914 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF1_HW_RADIO
))
3915 __set_bit(CAPABILITY_HW_BUTTON
, &rt2x00dev
->cap_flags
);
3918 * Detect if this device has Bluetooth co-existence.
3920 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF1_BT_COEXIST
))
3921 __set_bit(CAPABILITY_BT_COEXIST
, &rt2x00dev
->cap_flags
);
3924 * Read frequency offset and RF programming sequence.
3926 rt2x00_eeprom_read(rt2x00dev
, EEPROM_FREQ
, &eeprom
);
3927 rt2x00dev
->freq_offset
= rt2x00_get_field16(eeprom
, EEPROM_FREQ_OFFSET
);
3930 * Store led settings, for correct led behaviour.
3932 #ifdef CONFIG_RT2X00_LIB_LEDS
3933 rt2800_init_led(rt2x00dev
, &rt2x00dev
->led_radio
, LED_TYPE_RADIO
);
3934 rt2800_init_led(rt2x00dev
, &rt2x00dev
->led_assoc
, LED_TYPE_ASSOC
);
3935 rt2800_init_led(rt2x00dev
, &rt2x00dev
->led_qual
, LED_TYPE_QUALITY
);
3937 rt2x00dev
->led_mcu_reg
= eeprom
;
3938 #endif /* CONFIG_RT2X00_LIB_LEDS */
3941 * Check if support EIRP tx power limit feature.
3943 rt2x00_eeprom_read(rt2x00dev
, EEPROM_EIRP_MAX_TX_POWER
, &eeprom
);
3945 if (rt2x00_get_field16(eeprom
, EEPROM_EIRP_MAX_TX_POWER_2GHZ
) <
3946 EIRP_MAX_TX_POWER_LIMIT
)
3947 __set_bit(CAPABILITY_POWER_LIMIT
, &rt2x00dev
->cap_flags
);
3951 EXPORT_SYMBOL_GPL(rt2800_init_eeprom
);
3954 * RF value list for rt28xx
3955 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
3957 static const struct rf_channel rf_vals
[] = {
3958 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
3959 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
3960 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
3961 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
3962 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
3963 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
3964 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
3965 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
3966 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
3967 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
3968 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
3969 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
3970 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
3971 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
3973 /* 802.11 UNI / HyperLan 2 */
3974 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
3975 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
3976 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
3977 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
3978 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
3979 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
3980 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
3981 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
3982 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
3983 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
3984 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
3985 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
3987 /* 802.11 HyperLan 2 */
3988 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
3989 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
3990 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
3991 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
3992 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
3993 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
3994 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
3995 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
3996 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
3997 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
3998 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
3999 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
4000 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
4001 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
4002 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
4003 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
4006 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
4007 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
4008 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
4009 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
4010 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
4011 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
4012 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
4013 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
4014 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
4015 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
4016 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
4019 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
4020 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
4021 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
4022 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
4023 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
4024 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
4025 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
4029 * RF value list for rt3xxx
4030 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
4032 static const struct rf_channel rf_vals_3x
[] = {
4048 /* 802.11 UNI / HyperLan 2 */
4062 /* 802.11 HyperLan 2 */
4094 int rt2800_probe_hw_mode(struct rt2x00_dev
*rt2x00dev
)
4096 struct hw_mode_spec
*spec
= &rt2x00dev
->spec
;
4097 struct channel_info
*info
;
4098 char *default_power1
;
4099 char *default_power2
;
4104 * Disable powersaving as default on PCI devices.
4106 if (rt2x00_is_pci(rt2x00dev
) || rt2x00_is_soc(rt2x00dev
))
4107 rt2x00dev
->hw
->wiphy
->flags
&= ~WIPHY_FLAG_PS_ON_BY_DEFAULT
;
4110 * Initialize all hw fields.
4112 rt2x00dev
->hw
->flags
=
4113 IEEE80211_HW_SIGNAL_DBM
|
4114 IEEE80211_HW_SUPPORTS_PS
|
4115 IEEE80211_HW_PS_NULLFUNC_STACK
|
4116 IEEE80211_HW_AMPDU_AGGREGATION
;
4118 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
4119 * unless we are capable of sending the buffered frames out after the
4120 * DTIM transmission using rt2x00lib_beacondone. This will send out
4121 * multicast and broadcast traffic immediately instead of buffering it
4122 * infinitly and thus dropping it after some time.
4124 if (!rt2x00_is_usb(rt2x00dev
))
4125 rt2x00dev
->hw
->flags
|=
4126 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING
;
4128 SET_IEEE80211_DEV(rt2x00dev
->hw
, rt2x00dev
->dev
);
4129 SET_IEEE80211_PERM_ADDR(rt2x00dev
->hw
,
4130 rt2x00_eeprom_addr(rt2x00dev
,
4131 EEPROM_MAC_ADDR_0
));
4134 * As rt2800 has a global fallback table we cannot specify
4135 * more then one tx rate per frame but since the hw will
4136 * try several rates (based on the fallback table) we should
4137 * initialize max_report_rates to the maximum number of rates
4138 * we are going to try. Otherwise mac80211 will truncate our
4139 * reported tx rates and the rc algortihm will end up with
4142 rt2x00dev
->hw
->max_rates
= 1;
4143 rt2x00dev
->hw
->max_report_rates
= 7;
4144 rt2x00dev
->hw
->max_rate_tries
= 1;
4146 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF0
, &eeprom
);
4149 * Initialize hw_mode information.
4151 spec
->supported_bands
= SUPPORT_BAND_2GHZ
;
4152 spec
->supported_rates
= SUPPORT_RATE_CCK
| SUPPORT_RATE_OFDM
;
4154 if (rt2x00_rf(rt2x00dev
, RF2820
) ||
4155 rt2x00_rf(rt2x00dev
, RF2720
)) {
4156 spec
->num_channels
= 14;
4157 spec
->channels
= rf_vals
;
4158 } else if (rt2x00_rf(rt2x00dev
, RF2850
) ||
4159 rt2x00_rf(rt2x00dev
, RF2750
)) {
4160 spec
->supported_bands
|= SUPPORT_BAND_5GHZ
;
4161 spec
->num_channels
= ARRAY_SIZE(rf_vals
);
4162 spec
->channels
= rf_vals
;
4163 } else if (rt2x00_rf(rt2x00dev
, RF3020
) ||
4164 rt2x00_rf(rt2x00dev
, RF2020
) ||
4165 rt2x00_rf(rt2x00dev
, RF3021
) ||
4166 rt2x00_rf(rt2x00dev
, RF3022
) ||
4167 rt2x00_rf(rt2x00dev
, RF3320
) ||
4168 rt2x00_rf(rt2x00dev
, RF5370
) ||
4169 rt2x00_rf(rt2x00dev
, RF5390
)) {
4170 spec
->num_channels
= 14;
4171 spec
->channels
= rf_vals_3x
;
4172 } else if (rt2x00_rf(rt2x00dev
, RF3052
)) {
4173 spec
->supported_bands
|= SUPPORT_BAND_5GHZ
;
4174 spec
->num_channels
= ARRAY_SIZE(rf_vals_3x
);
4175 spec
->channels
= rf_vals_3x
;
4179 * Initialize HT information.
4181 if (!rt2x00_rf(rt2x00dev
, RF2020
))
4182 spec
->ht
.ht_supported
= true;
4184 spec
->ht
.ht_supported
= false;
4187 IEEE80211_HT_CAP_SUP_WIDTH_20_40
|
4188 IEEE80211_HT_CAP_GRN_FLD
|
4189 IEEE80211_HT_CAP_SGI_20
|
4190 IEEE80211_HT_CAP_SGI_40
;
4192 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_TXPATH
) >= 2)
4193 spec
->ht
.cap
|= IEEE80211_HT_CAP_TX_STBC
;
4196 rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_RXPATH
) <<
4197 IEEE80211_HT_CAP_RX_STBC_SHIFT
;
4199 spec
->ht
.ampdu_factor
= 3;
4200 spec
->ht
.ampdu_density
= 4;
4201 spec
->ht
.mcs
.tx_params
=
4202 IEEE80211_HT_MCS_TX_DEFINED
|
4203 IEEE80211_HT_MCS_TX_RX_DIFF
|
4204 ((rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_TXPATH
) - 1) <<
4205 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT
);
4207 switch (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_RXPATH
)) {
4209 spec
->ht
.mcs
.rx_mask
[2] = 0xff;
4211 spec
->ht
.mcs
.rx_mask
[1] = 0xff;
4213 spec
->ht
.mcs
.rx_mask
[0] = 0xff;
4214 spec
->ht
.mcs
.rx_mask
[4] = 0x1; /* MCS32 */
4219 * Create channel information array
4221 info
= kcalloc(spec
->num_channels
, sizeof(*info
), GFP_KERNEL
);
4225 spec
->channels_info
= info
;
4227 default_power1
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_BG1
);
4228 default_power2
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_BG2
);
4230 for (i
= 0; i
< 14; i
++) {
4231 info
[i
].default_power1
= default_power1
[i
];
4232 info
[i
].default_power2
= default_power2
[i
];
4235 if (spec
->num_channels
> 14) {
4236 default_power1
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_A1
);
4237 default_power2
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_A2
);
4239 for (i
= 14; i
< spec
->num_channels
; i
++) {
4240 info
[i
].default_power1
= default_power1
[i
];
4241 info
[i
].default_power2
= default_power2
[i
];
4247 EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode
);
4250 * IEEE80211 stack callback functions.
4252 void rt2800_get_tkip_seq(struct ieee80211_hw
*hw
, u8 hw_key_idx
, u32
*iv32
,
4255 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
4256 struct mac_iveiv_entry iveiv_entry
;
4259 offset
= MAC_IVEIV_ENTRY(hw_key_idx
);
4260 rt2800_register_multiread(rt2x00dev
, offset
,
4261 &iveiv_entry
, sizeof(iveiv_entry
));
4263 memcpy(iv16
, &iveiv_entry
.iv
[0], sizeof(*iv16
));
4264 memcpy(iv32
, &iveiv_entry
.iv
[4], sizeof(*iv32
));
4266 EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq
);
4268 int rt2800_set_rts_threshold(struct ieee80211_hw
*hw
, u32 value
)
4270 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
4272 bool enabled
= (value
< IEEE80211_MAX_RTS_THRESHOLD
);
4274 rt2800_register_read(rt2x00dev
, TX_RTS_CFG
, ®
);
4275 rt2x00_set_field32(®
, TX_RTS_CFG_RTS_THRES
, value
);
4276 rt2800_register_write(rt2x00dev
, TX_RTS_CFG
, reg
);
4278 rt2800_register_read(rt2x00dev
, CCK_PROT_CFG
, ®
);
4279 rt2x00_set_field32(®
, CCK_PROT_CFG_RTS_TH_EN
, enabled
);
4280 rt2800_register_write(rt2x00dev
, CCK_PROT_CFG
, reg
);
4282 rt2800_register_read(rt2x00dev
, OFDM_PROT_CFG
, ®
);
4283 rt2x00_set_field32(®
, OFDM_PROT_CFG_RTS_TH_EN
, enabled
);
4284 rt2800_register_write(rt2x00dev
, OFDM_PROT_CFG
, reg
);
4286 rt2800_register_read(rt2x00dev
, MM20_PROT_CFG
, ®
);
4287 rt2x00_set_field32(®
, MM20_PROT_CFG_RTS_TH_EN
, enabled
);
4288 rt2800_register_write(rt2x00dev
, MM20_PROT_CFG
, reg
);
4290 rt2800_register_read(rt2x00dev
, MM40_PROT_CFG
, ®
);
4291 rt2x00_set_field32(®
, MM40_PROT_CFG_RTS_TH_EN
, enabled
);
4292 rt2800_register_write(rt2x00dev
, MM40_PROT_CFG
, reg
);
4294 rt2800_register_read(rt2x00dev
, GF20_PROT_CFG
, ®
);
4295 rt2x00_set_field32(®
, GF20_PROT_CFG_RTS_TH_EN
, enabled
);
4296 rt2800_register_write(rt2x00dev
, GF20_PROT_CFG
, reg
);
4298 rt2800_register_read(rt2x00dev
, GF40_PROT_CFG
, ®
);
4299 rt2x00_set_field32(®
, GF40_PROT_CFG_RTS_TH_EN
, enabled
);
4300 rt2800_register_write(rt2x00dev
, GF40_PROT_CFG
, reg
);
4304 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold
);
4306 int rt2800_conf_tx(struct ieee80211_hw
*hw
, u16 queue_idx
,
4307 const struct ieee80211_tx_queue_params
*params
)
4309 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
4310 struct data_queue
*queue
;
4311 struct rt2x00_field32 field
;
4317 * First pass the configuration through rt2x00lib, that will
4318 * update the queue settings and validate the input. After that
4319 * we are free to update the registers based on the value
4320 * in the queue parameter.
4322 retval
= rt2x00mac_conf_tx(hw
, queue_idx
, params
);
4327 * We only need to perform additional register initialization
4333 queue
= rt2x00queue_get_tx_queue(rt2x00dev
, queue_idx
);
4335 /* Update WMM TXOP register */
4336 offset
= WMM_TXOP0_CFG
+ (sizeof(u32
) * (!!(queue_idx
& 2)));
4337 field
.bit_offset
= (queue_idx
& 1) * 16;
4338 field
.bit_mask
= 0xffff << field
.bit_offset
;
4340 rt2800_register_read(rt2x00dev
, offset
, ®
);
4341 rt2x00_set_field32(®
, field
, queue
->txop
);
4342 rt2800_register_write(rt2x00dev
, offset
, reg
);
4344 /* Update WMM registers */
4345 field
.bit_offset
= queue_idx
* 4;
4346 field
.bit_mask
= 0xf << field
.bit_offset
;
4348 rt2800_register_read(rt2x00dev
, WMM_AIFSN_CFG
, ®
);
4349 rt2x00_set_field32(®
, field
, queue
->aifs
);
4350 rt2800_register_write(rt2x00dev
, WMM_AIFSN_CFG
, reg
);
4352 rt2800_register_read(rt2x00dev
, WMM_CWMIN_CFG
, ®
);
4353 rt2x00_set_field32(®
, field
, queue
->cw_min
);
4354 rt2800_register_write(rt2x00dev
, WMM_CWMIN_CFG
, reg
);
4356 rt2800_register_read(rt2x00dev
, WMM_CWMAX_CFG
, ®
);
4357 rt2x00_set_field32(®
, field
, queue
->cw_max
);
4358 rt2800_register_write(rt2x00dev
, WMM_CWMAX_CFG
, reg
);
4360 /* Update EDCA registers */
4361 offset
= EDCA_AC0_CFG
+ (sizeof(u32
) * queue_idx
);
4363 rt2800_register_read(rt2x00dev
, offset
, ®
);
4364 rt2x00_set_field32(®
, EDCA_AC0_CFG_TX_OP
, queue
->txop
);
4365 rt2x00_set_field32(®
, EDCA_AC0_CFG_AIFSN
, queue
->aifs
);
4366 rt2x00_set_field32(®
, EDCA_AC0_CFG_CWMIN
, queue
->cw_min
);
4367 rt2x00_set_field32(®
, EDCA_AC0_CFG_CWMAX
, queue
->cw_max
);
4368 rt2800_register_write(rt2x00dev
, offset
, reg
);
4372 EXPORT_SYMBOL_GPL(rt2800_conf_tx
);
4374 u64
rt2800_get_tsf(struct ieee80211_hw
*hw
)
4376 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
4380 rt2800_register_read(rt2x00dev
, TSF_TIMER_DW1
, ®
);
4381 tsf
= (u64
) rt2x00_get_field32(reg
, TSF_TIMER_DW1_HIGH_WORD
) << 32;
4382 rt2800_register_read(rt2x00dev
, TSF_TIMER_DW0
, ®
);
4383 tsf
|= rt2x00_get_field32(reg
, TSF_TIMER_DW0_LOW_WORD
);
4387 EXPORT_SYMBOL_GPL(rt2800_get_tsf
);
4389 int rt2800_ampdu_action(struct ieee80211_hw
*hw
, struct ieee80211_vif
*vif
,
4390 enum ieee80211_ampdu_mlme_action action
,
4391 struct ieee80211_sta
*sta
, u16 tid
, u16
*ssn
,
4397 case IEEE80211_AMPDU_RX_START
:
4398 case IEEE80211_AMPDU_RX_STOP
:
4400 * The hw itself takes care of setting up BlockAck mechanisms.
4401 * So, we only have to allow mac80211 to nagotiate a BlockAck
4402 * agreement. Once that is done, the hw will BlockAck incoming
4403 * AMPDUs without further setup.
4406 case IEEE80211_AMPDU_TX_START
:
4407 ieee80211_start_tx_ba_cb_irqsafe(vif
, sta
->addr
, tid
);
4409 case IEEE80211_AMPDU_TX_STOP
:
4410 ieee80211_stop_tx_ba_cb_irqsafe(vif
, sta
->addr
, tid
);
4412 case IEEE80211_AMPDU_TX_OPERATIONAL
:
4415 WARNING((struct rt2x00_dev
*)hw
->priv
, "Unknown AMPDU action\n");
4420 EXPORT_SYMBOL_GPL(rt2800_ampdu_action
);
4422 int rt2800_get_survey(struct ieee80211_hw
*hw
, int idx
,
4423 struct survey_info
*survey
)
4425 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
4426 struct ieee80211_conf
*conf
= &hw
->conf
;
4427 u32 idle
, busy
, busy_ext
;
4432 survey
->channel
= conf
->channel
;
4434 rt2800_register_read(rt2x00dev
, CH_IDLE_STA
, &idle
);
4435 rt2800_register_read(rt2x00dev
, CH_BUSY_STA
, &busy
);
4436 rt2800_register_read(rt2x00dev
, CH_BUSY_STA_SEC
, &busy_ext
);
4439 survey
->filled
= SURVEY_INFO_CHANNEL_TIME
|
4440 SURVEY_INFO_CHANNEL_TIME_BUSY
|
4441 SURVEY_INFO_CHANNEL_TIME_EXT_BUSY
;
4443 survey
->channel_time
= (idle
+ busy
) / 1000;
4444 survey
->channel_time_busy
= busy
/ 1000;
4445 survey
->channel_time_ext_busy
= busy_ext
/ 1000;
4451 EXPORT_SYMBOL_GPL(rt2800_get_survey
);
4453 MODULE_AUTHOR(DRV_PROJECT
", Bartlomiej Zolnierkiewicz");
4454 MODULE_VERSION(DRV_VERSION
);
4455 MODULE_DESCRIPTION("Ralink RT2800 library");
4456 MODULE_LICENSE("GPL");