?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
mv643xx_eth: calculate descriptor pointer only once in rxq_refill()
[linux-2.6.git] / drivers / net / mv643xx_eth.c
blobb56fdf0dc875be93e913e2400478c792d4b013a8
1 /*
2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
8 *
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
10 * written by Manish Lachwani
11 *
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
13 *
14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
15 * Dale Farnsworth <dale@farnsworth.org>
16 *
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
19 *
20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
22 *
23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
27 *
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
32 *
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
36 */
37
38 #include <linux/init.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/in.h>
41 #include <linux/ip.h>
42 #include <linux/tcp.h>
43 #include <linux/udp.h>
44 #include <linux/etherdevice.h>
45 #include <linux/delay.h>
46 #include <linux/ethtool.h>
47 #include <linux/platform_device.h>
48 #include <linux/module.h>
49 #include <linux/kernel.h>
50 #include <linux/spinlock.h>
51 #include <linux/workqueue.h>
52 #include <linux/phy.h>
53 #include <linux/mv643xx_eth.h>
54 #include <linux/io.h>
55 #include <linux/types.h>
56 #include <asm/system.h>
57
58 static char mv643xx_eth_driver_name[] = "mv643xx_eth";
59 static char mv643xx_eth_driver_version[] = "1.4";
60
61
62 /*
63 * Registers shared between all ports.
64 */
65 #define PHY_ADDR 0x0000
66 #define SMI_REG 0x0004
67 #define SMI_BUSY 0x10000000
68 #define SMI_READ_VALID 0x08000000
69 #define SMI_OPCODE_READ 0x04000000
70 #define SMI_OPCODE_WRITE 0x00000000
71 #define ERR_INT_CAUSE 0x0080
72 #define ERR_INT_SMI_DONE 0x00000010
73 #define ERR_INT_MASK 0x0084
74 #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
75 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
76 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
77 #define WINDOW_BAR_ENABLE 0x0290
78 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
79
80 /*
81 * Main per-port registers. These live at offset 0x0400 for
82 * port #0, 0x0800 for port #1, and 0x0c00 for port #2.
83 */
84 #define PORT_CONFIG 0x0000
85 #define UNICAST_PROMISCUOUS_MODE 0x00000001
86 #define PORT_CONFIG_EXT 0x0004
87 #define MAC_ADDR_LOW 0x0014
88 #define MAC_ADDR_HIGH 0x0018
89 #define SDMA_CONFIG 0x001c
90 #define PORT_SERIAL_CONTROL 0x003c
91 #define PORT_STATUS 0x0044
92 #define TX_FIFO_EMPTY 0x00000400
93 #define TX_IN_PROGRESS 0x00000080
94 #define PORT_SPEED_MASK 0x00000030
95 #define PORT_SPEED_1000 0x00000010
96 #define PORT_SPEED_100 0x00000020
97 #define PORT_SPEED_10 0x00000000
98 #define FLOW_CONTROL_ENABLED 0x00000008
99 #define FULL_DUPLEX 0x00000004
100 #define LINK_UP 0x00000002
101 #define TXQ_COMMAND 0x0048
102 #define TXQ_FIX_PRIO_CONF 0x004c
103 #define TX_BW_RATE 0x0050
104 #define TX_BW_MTU 0x0058
105 #define TX_BW_BURST 0x005c
106 #define INT_CAUSE 0x0060
107 #define INT_TX_END 0x07f80000
108 #define INT_RX 0x000003fc
109 #define INT_EXT 0x00000002
110 #define INT_CAUSE_EXT 0x0064
111 #define INT_EXT_LINK_PHY 0x00110000
112 #define INT_EXT_TX 0x000000ff
113 #define INT_MASK 0x0068
114 #define INT_MASK_EXT 0x006c
115 #define TX_FIFO_URGENT_THRESHOLD 0x0074
116 #define TXQ_FIX_PRIO_CONF_MOVED 0x00dc
117 #define TX_BW_RATE_MOVED 0x00e0
118 #define TX_BW_MTU_MOVED 0x00e8
119 #define TX_BW_BURST_MOVED 0x00ec
120 #define RXQ_CURRENT_DESC_PTR(q) (0x020c + ((q) << 4))
121 #define RXQ_COMMAND 0x0280
122 #define TXQ_CURRENT_DESC_PTR(q) (0x02c0 + ((q) << 2))
123 #define TXQ_BW_TOKENS(q) (0x0300 + ((q) << 4))
124 #define TXQ_BW_CONF(q) (0x0304 + ((q) << 4))
125 #define TXQ_BW_WRR_CONF(q) (0x0308 + ((q) << 4))
126
127 /*
128 * Misc per-port registers.
129 */
130 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
131 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
132 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
133 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
134
135
136 /*
137 * SDMA configuration register.
138 */
139 #define RX_BURST_SIZE_16_64BIT (4 << 1)
140 #define BLM_RX_NO_SWAP (1 << 4)
141 #define BLM_TX_NO_SWAP (1 << 5)
142 #define TX_BURST_SIZE_16_64BIT (4 << 22)
143
144 #if defined(__BIG_ENDIAN)
145 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
146 (RX_BURST_SIZE_16_64BIT | \
147 TX_BURST_SIZE_16_64BIT)
148 #elif defined(__LITTLE_ENDIAN)
149 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
150 (RX_BURST_SIZE_16_64BIT | \
151 BLM_RX_NO_SWAP | \
152 BLM_TX_NO_SWAP | \
153 TX_BURST_SIZE_16_64BIT)
154 #else
155 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
156 #endif
157
158
159 /*
160 * Port serial control register.
161 */
162 #define SET_MII_SPEED_TO_100 (1 << 24)
163 #define SET_GMII_SPEED_TO_1000 (1 << 23)
164 #define SET_FULL_DUPLEX_MODE (1 << 21)
165 #define MAX_RX_PACKET_9700BYTE (5 << 17)
166 #define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
167 #define DO_NOT_FORCE_LINK_FAIL (1 << 10)
168 #define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
169 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
170 #define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
171 #define FORCE_LINK_PASS (1 << 1)
172 #define SERIAL_PORT_ENABLE (1 << 0)
173
174 #define DEFAULT_RX_QUEUE_SIZE 128
175 #define DEFAULT_TX_QUEUE_SIZE 256
176
177
178 /*
179 * RX/TX descriptors.
180 */
181 #if defined(__BIG_ENDIAN)
182 struct rx_desc {
183 u16 byte_cnt; /* Descriptor buffer byte count */
184 u16 buf_size; /* Buffer size */
185 u32 cmd_sts; /* Descriptor command status */
186 u32 next_desc_ptr; /* Next descriptor pointer */
187 u32 buf_ptr; /* Descriptor buffer pointer */
188 };
189
190 struct tx_desc {
191 u16 byte_cnt; /* buffer byte count */
192 u16 l4i_chk; /* CPU provided TCP checksum */
193 u32 cmd_sts; /* Command/status field */
194 u32 next_desc_ptr; /* Pointer to next descriptor */
195 u32 buf_ptr; /* pointer to buffer for this descriptor*/
196 };
197 #elif defined(__LITTLE_ENDIAN)
198 struct rx_desc {
199 u32 cmd_sts; /* Descriptor command status */
200 u16 buf_size; /* Buffer size */
201 u16 byte_cnt; /* Descriptor buffer byte count */
202 u32 buf_ptr; /* Descriptor buffer pointer */
203 u32 next_desc_ptr; /* Next descriptor pointer */
204 };
205
206 struct tx_desc {
207 u32 cmd_sts; /* Command/status field */
208 u16 l4i_chk; /* CPU provided TCP checksum */
209 u16 byte_cnt; /* buffer byte count */
210 u32 buf_ptr; /* pointer to buffer for this descriptor*/
211 u32 next_desc_ptr; /* Pointer to next descriptor */
212 };
213 #else
214 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
215 #endif
216
217 /* RX & TX descriptor command */
218 #define BUFFER_OWNED_BY_DMA 0x80000000
219
220 /* RX & TX descriptor status */
221 #define ERROR_SUMMARY 0x00000001
222
223 /* RX descriptor status */
224 #define LAYER_4_CHECKSUM_OK 0x40000000
225 #define RX_ENABLE_INTERRUPT 0x20000000
226 #define RX_FIRST_DESC 0x08000000
227 #define RX_LAST_DESC 0x04000000
228
229 /* TX descriptor command */
230 #define TX_ENABLE_INTERRUPT 0x00800000
231 #define GEN_CRC 0x00400000
232 #define TX_FIRST_DESC 0x00200000
233 #define TX_LAST_DESC 0x00100000
234 #define ZERO_PADDING 0x00080000
235 #define GEN_IP_V4_CHECKSUM 0x00040000
236 #define GEN_TCP_UDP_CHECKSUM 0x00020000
237 #define UDP_FRAME 0x00010000
238 #define MAC_HDR_EXTRA_4_BYTES 0x00008000
239 #define MAC_HDR_EXTRA_8_BYTES 0x00000200
240
241 #define TX_IHL_SHIFT 11
242
243
244 /* global *******************************************************************/
245 struct mv643xx_eth_shared_private {
246 /*
247 * Ethernet controller base address.
248 */
249 void __iomem *base;
250
251 /*
252 * Points at the right SMI instance to use.
253 */
254 struct mv643xx_eth_shared_private *smi;
255
256 /*
257 * Provides access to local SMI interface.
258 */
259 struct mii_bus *smi_bus;
260
261 /*
262 * If we have access to the error interrupt pin (which is
263 * somewhat misnamed as it not only reflects internal errors
264 * but also reflects SMI completion), use that to wait for
265 * SMI access completion instead of polling the SMI busy bit.
266 */
267 int err_interrupt;
268 wait_queue_head_t smi_busy_wait;
269
270 /*
271 * Per-port MBUS window access register value.
272 */
273 u32 win_protect;
274
275 /*
276 * Hardware-specific parameters.
277 */
278 unsigned int t_clk;
279 int extended_rx_coal_limit;
280 int tx_bw_control;
281 };
282
283 #define TX_BW_CONTROL_ABSENT 0
284 #define TX_BW_CONTROL_OLD_LAYOUT 1
285 #define TX_BW_CONTROL_NEW_LAYOUT 2
286
287
288 /* per-port *****************************************************************/
289 struct mib_counters {
290 u64 good_octets_received;
291 u32 bad_octets_received;
292 u32 internal_mac_transmit_err;
293 u32 good_frames_received;
294 u32 bad_frames_received;
295 u32 broadcast_frames_received;
296 u32 multicast_frames_received;
297 u32 frames_64_octets;
298 u32 frames_65_to_127_octets;
299 u32 frames_128_to_255_octets;
300 u32 frames_256_to_511_octets;
301 u32 frames_512_to_1023_octets;
302 u32 frames_1024_to_max_octets;
303 u64 good_octets_sent;
304 u32 good_frames_sent;
305 u32 excessive_collision;
306 u32 multicast_frames_sent;
307 u32 broadcast_frames_sent;
308 u32 unrec_mac_control_received;
309 u32 fc_sent;
310 u32 good_fc_received;
311 u32 bad_fc_received;
312 u32 undersize_received;
313 u32 fragments_received;
314 u32 oversize_received;
315 u32 jabber_received;
316 u32 mac_receive_error;
317 u32 bad_crc_event;
318 u32 collision;
319 u32 late_collision;
320 };
321
322 struct rx_queue {
323 int index;
324
325 int rx_ring_size;
326
327 int rx_desc_count;
328 int rx_curr_desc;
329 int rx_used_desc;
330
331 struct rx_desc *rx_desc_area;
332 dma_addr_t rx_desc_dma;
333 int rx_desc_area_size;
334 struct sk_buff **rx_skb;
335 };
336
337 struct tx_queue {
338 int index;
339
340 int tx_ring_size;
341
342 int tx_desc_count;
343 int tx_curr_desc;
344 int tx_used_desc;
345
346 struct tx_desc *tx_desc_area;
347 dma_addr_t tx_desc_dma;
348 int tx_desc_area_size;
349
350 struct sk_buff_head tx_skb;
351
352 unsigned long tx_packets;
353 unsigned long tx_bytes;
354 unsigned long tx_dropped;
355 };
356
357 struct mv643xx_eth_private {
358 struct mv643xx_eth_shared_private *shared;
359 void __iomem *base;
360 int port_num;
361
362 struct net_device *dev;
363
364 struct phy_device *phy;
365
366 struct timer_list mib_counters_timer;
367 spinlock_t mib_counters_lock;
368 struct mib_counters mib_counters;
369
370 struct work_struct tx_timeout_task;
371
372 struct napi_struct napi;
373 u8 work_link;
374 u8 work_tx;
375 u8 work_tx_end;
376 u8 work_rx;
377 u8 work_rx_refill;
378 u8 work_rx_oom;
379
380 int skb_size;
381 struct sk_buff_head rx_recycle;
382
383 /*
384 * RX state.
385 */
386 int default_rx_ring_size;
387 unsigned long rx_desc_sram_addr;
388 int rx_desc_sram_size;
389 int rxq_count;
390 struct timer_list rx_oom;
391 struct rx_queue rxq[8];
392
393 /*
394 * TX state.
395 */
396 int default_tx_ring_size;
397 unsigned long tx_desc_sram_addr;
398 int tx_desc_sram_size;
399 int txq_count;
400 struct tx_queue txq[8];
401 };
402
403
404 /* port register accessors **************************************************/
405 static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
406 {
407 return readl(mp->shared->base + offset);
408 }
409
410 static inline u32 rdlp(struct mv643xx_eth_private *mp, int offset)
411 {
412 return readl(mp->base + offset);
413 }
414
415 static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
416 {
417 writel(data, mp->shared->base + offset);
418 }
419
420 static inline void wrlp(struct mv643xx_eth_private *mp, int offset, u32 data)
421 {
422 writel(data, mp->base + offset);
423 }
424
425
426 /* rxq/txq helper functions *************************************************/
427 static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
428 {
429 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
430 }
431
432 static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
433 {
434 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
435 }
436
437 static void rxq_enable(struct rx_queue *rxq)
438 {
439 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
440 wrlp(mp, RXQ_COMMAND, 1 << rxq->index);
441 }
442
443 static void rxq_disable(struct rx_queue *rxq)
444 {
445 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
446 u8 mask = 1 << rxq->index;
447
448 wrlp(mp, RXQ_COMMAND, mask << 8);
449 while (rdlp(mp, RXQ_COMMAND) & mask)
450 udelay(10);
451 }
452
453 static void txq_reset_hw_ptr(struct tx_queue *txq)
454 {
455 struct mv643xx_eth_private *mp = txq_to_mp(txq);
456 u32 addr;
457
458 addr = (u32)txq->tx_desc_dma;
459 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
460 wrlp(mp, TXQ_CURRENT_DESC_PTR(txq->index), addr);
461 }
462
463 static void txq_enable(struct tx_queue *txq)
464 {
465 struct mv643xx_eth_private *mp = txq_to_mp(txq);
466 wrlp(mp, TXQ_COMMAND, 1 << txq->index);
467 }
468
469 static void txq_disable(struct tx_queue *txq)
470 {
471 struct mv643xx_eth_private *mp = txq_to_mp(txq);
472 u8 mask = 1 << txq->index;
473
474 wrlp(mp, TXQ_COMMAND, mask << 8);
475 while (rdlp(mp, TXQ_COMMAND) & mask)
476 udelay(10);
477 }
478
479 static void txq_maybe_wake(struct tx_queue *txq)
480 {
481 struct mv643xx_eth_private *mp = txq_to_mp(txq);
482 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
483
484 if (netif_tx_queue_stopped(nq)) {
485 __netif_tx_lock(nq, smp_processor_id());
486 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_SKB_FRAGS + 1)
487 netif_tx_wake_queue(nq);
488 __netif_tx_unlock(nq);
489 }
490 }
491
492
493 /* rx napi ******************************************************************/
494 static int rxq_process(struct rx_queue *rxq, int budget)
495 {
496 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
497 struct net_device_stats *stats = &mp->dev->stats;
498 int rx;
499
500 rx = 0;
501 while (rx < budget && rxq->rx_desc_count) {
502 struct rx_desc *rx_desc;
503 unsigned int cmd_sts;
504 struct sk_buff *skb;
505 u16 byte_cnt;
506
507 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
508
509 cmd_sts = rx_desc->cmd_sts;
510 if (cmd_sts & BUFFER_OWNED_BY_DMA)
511 break;
512 rmb();
513
514 skb = rxq->rx_skb[rxq->rx_curr_desc];
515 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
516
517 rxq->rx_curr_desc++;
518 if (rxq->rx_curr_desc == rxq->rx_ring_size)
519 rxq->rx_curr_desc = 0;
520
521 dma_unmap_single(NULL, rx_desc->buf_ptr,
522 rx_desc->buf_size, DMA_FROM_DEVICE);
523 rxq->rx_desc_count--;
524 rx++;
525
526 mp->work_rx_refill |= 1 << rxq->index;
527
528 byte_cnt = rx_desc->byte_cnt;
529
530 /*
531 * Update statistics.
532 *
533 * Note that the descriptor byte count includes 2 dummy
534 * bytes automatically inserted by the hardware at the
535 * start of the packet (which we don't count), and a 4
536 * byte CRC at the end of the packet (which we do count).
537 */
538 stats->rx_packets++;
539 stats->rx_bytes += byte_cnt - 2;
540
541 /*
542 * In case we received a packet without first / last bits
543 * on, or the error summary bit is set, the packet needs
544 * to be dropped.
545 */
546 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC | ERROR_SUMMARY))
547 != (RX_FIRST_DESC | RX_LAST_DESC))
548 goto err;
549
550 /*
551 * The -4 is for the CRC in the trailer of the
552 * received packet
553 */
554 skb_put(skb, byte_cnt - 2 - 4);
555
556 if (cmd_sts & LAYER_4_CHECKSUM_OK)
557 skb->ip_summed = CHECKSUM_UNNECESSARY;
558 skb->protocol = eth_type_trans(skb, mp->dev);
559 netif_receive_skb(skb);
560
561 continue;
562
563 err:
564 stats->rx_dropped++;
565
566 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
567 (RX_FIRST_DESC | RX_LAST_DESC)) {
568 if (net_ratelimit())
569 dev_printk(KERN_ERR, &mp->dev->dev,
570 "received packet spanning "
571 "multiple descriptors\n");
572 }
573
574 if (cmd_sts & ERROR_SUMMARY)
575 stats->rx_errors++;
576
577 dev_kfree_skb(skb);
578 }
579
580 if (rx < budget)
581 mp->work_rx &= ~(1 << rxq->index);
582
583 return rx;
584 }
585
586 static int rxq_refill(struct rx_queue *rxq, int budget)
587 {
588 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
589 int refilled;
590
591 refilled = 0;
592 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
593 struct sk_buff *skb;
594 int unaligned;
595 int rx;
596 struct rx_desc *rx_desc;
597
598 skb = __skb_dequeue(&mp->rx_recycle);
599 if (skb == NULL)
600 skb = dev_alloc_skb(mp->skb_size +
601 dma_get_cache_alignment() - 1);
602
603 if (skb == NULL) {
604 mp->work_rx_oom |= 1 << rxq->index;
605 goto oom;
606 }
607
608 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
609 if (unaligned)
610 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
611
612 refilled++;
613 rxq->rx_desc_count++;
614
615 rx = rxq->rx_used_desc++;
616 if (rxq->rx_used_desc == rxq->rx_ring_size)
617 rxq->rx_used_desc = 0;
618
619 rx_desc = rxq->rx_desc_area + rx;
620
621 rx_desc->buf_ptr = dma_map_single(NULL, skb->data,
622 mp->skb_size, DMA_FROM_DEVICE);
623 rx_desc->buf_size = mp->skb_size;
624 rxq->rx_skb[rx] = skb;
625 wmb();
626 rx_desc->cmd_sts = BUFFER_OWNED_BY_DMA | RX_ENABLE_INTERRUPT;
627 wmb();
628
629 /*
630 * The hardware automatically prepends 2 bytes of
631 * dummy data to each received packet, so that the
632 * IP header ends up 16-byte aligned.
633 */
634 skb_reserve(skb, 2);
635 }
636
637 if (refilled < budget)
638 mp->work_rx_refill &= ~(1 << rxq->index);
639
640 oom:
641 return refilled;
642 }
643
644
645 /* tx ***********************************************************************/
646 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
647 {
648 int frag;
649
650 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
651 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
652 if (fragp->size <= 8 && fragp->page_offset & 7)
653 return 1;
654 }
655
656 return 0;
657 }
658
659 static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
660 {
661 int nr_frags = skb_shinfo(skb)->nr_frags;
662 int frag;
663
664 for (frag = 0; frag < nr_frags; frag++) {
665 skb_frag_t *this_frag;
666 int tx_index;
667 struct tx_desc *desc;
668
669 this_frag = &skb_shinfo(skb)->frags[frag];
670 tx_index = txq->tx_curr_desc++;
671 if (txq->tx_curr_desc == txq->tx_ring_size)
672 txq->tx_curr_desc = 0;
673 desc = &txq->tx_desc_area[tx_index];
674
675 /*
676 * The last fragment will generate an interrupt
677 * which will free the skb on TX completion.
678 */
679 if (frag == nr_frags - 1) {
680 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
681 ZERO_PADDING | TX_LAST_DESC |
682 TX_ENABLE_INTERRUPT;
683 } else {
684 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
685 }
686
687 desc->l4i_chk = 0;
688 desc->byte_cnt = this_frag->size;
689 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
690 this_frag->page_offset,
691 this_frag->size,
692 DMA_TO_DEVICE);
693 }
694 }
695
696 static inline __be16 sum16_as_be(__sum16 sum)
697 {
698 return (__force __be16)sum;
699 }
700
701 static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
702 {
703 struct mv643xx_eth_private *mp = txq_to_mp(txq);
704 int nr_frags = skb_shinfo(skb)->nr_frags;
705 int tx_index;
706 struct tx_desc *desc;
707 u32 cmd_sts;
708 u16 l4i_chk;
709 int length;
710
711 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
712 l4i_chk = 0;
713
714 if (skb->ip_summed == CHECKSUM_PARTIAL) {
715 int tag_bytes;
716
717 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
718 skb->protocol != htons(ETH_P_8021Q));
719
720 tag_bytes = (void *)ip_hdr(skb) - (void *)skb->data - ETH_HLEN;
721 if (unlikely(tag_bytes & ~12)) {
722 if (skb_checksum_help(skb) == 0)
723 goto no_csum;
724 kfree_skb(skb);
725 return 1;
726 }
727
728 if (tag_bytes & 4)
729 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
730 if (tag_bytes & 8)
731 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
732
733 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
734 GEN_IP_V4_CHECKSUM |
735 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
736
737 switch (ip_hdr(skb)->protocol) {
738 case IPPROTO_UDP:
739 cmd_sts |= UDP_FRAME;
740 l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
741 break;
742 case IPPROTO_TCP:
743 l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
744 break;
745 default:
746 BUG();
747 }
748 } else {
749 no_csum:
750 /* Errata BTS #50, IHL must be 5 if no HW checksum */
751 cmd_sts |= 5 << TX_IHL_SHIFT;
752 }
753
754 tx_index = txq->tx_curr_desc++;
755 if (txq->tx_curr_desc == txq->tx_ring_size)
756 txq->tx_curr_desc = 0;
757 desc = &txq->tx_desc_area[tx_index];
758
759 if (nr_frags) {
760 txq_submit_frag_skb(txq, skb);
761 length = skb_headlen(skb);
762 } else {
763 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
764 length = skb->len;
765 }
766
767 desc->l4i_chk = l4i_chk;
768 desc->byte_cnt = length;
769 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
770
771 __skb_queue_tail(&txq->tx_skb, skb);
772
773 /* ensure all other descriptors are written before first cmd_sts */
774 wmb();
775 desc->cmd_sts = cmd_sts;
776
777 /* clear TX_END status */
778 mp->work_tx_end &= ~(1 << txq->index);
779
780 /* ensure all descriptors are written before poking hardware */
781 wmb();
782 txq_enable(txq);
783
784 txq->tx_desc_count += nr_frags + 1;
785
786 return 0;
787 }
788
789 static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
790 {
791 struct mv643xx_eth_private *mp = netdev_priv(dev);
792 int queue;
793 struct tx_queue *txq;
794 struct netdev_queue *nq;
795
796 queue = skb_get_queue_mapping(skb);
797 txq = mp->txq + queue;
798 nq = netdev_get_tx_queue(dev, queue);
799
800 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
801 txq->tx_dropped++;
802 dev_printk(KERN_DEBUG, &dev->dev,
803 "failed to linearize skb with tiny "
804 "unaligned fragment\n");
805 return NETDEV_TX_BUSY;
806 }
807
808 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
809 if (net_ratelimit())
810 dev_printk(KERN_ERR, &dev->dev, "tx queue full?!\n");
811 kfree_skb(skb);
812 return NETDEV_TX_OK;
813 }
814
815 if (!txq_submit_skb(txq, skb)) {
816 int entries_left;
817
818 txq->tx_bytes += skb->len;
819 txq->tx_packets++;
820 dev->trans_start = jiffies;
821
822 entries_left = txq->tx_ring_size - txq->tx_desc_count;
823 if (entries_left < MAX_SKB_FRAGS + 1)
824 netif_tx_stop_queue(nq);
825 }
826
827 return NETDEV_TX_OK;
828 }
829
830
831 /* tx napi ******************************************************************/
832 static void txq_kick(struct tx_queue *txq)
833 {
834 struct mv643xx_eth_private *mp = txq_to_mp(txq);
835 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
836 u32 hw_desc_ptr;
837 u32 expected_ptr;
838
839 __netif_tx_lock(nq, smp_processor_id());
840
841 if (rdlp(mp, TXQ_COMMAND) & (1 << txq->index))
842 goto out;
843
844 hw_desc_ptr = rdlp(mp, TXQ_CURRENT_DESC_PTR(txq->index));
845 expected_ptr = (u32)txq->tx_desc_dma +
846 txq->tx_curr_desc * sizeof(struct tx_desc);
847
848 if (hw_desc_ptr != expected_ptr)
849 txq_enable(txq);
850
851 out:
852 __netif_tx_unlock(nq);
853
854 mp->work_tx_end &= ~(1 << txq->index);
855 }
856
857 static int txq_reclaim(struct tx_queue *txq, int budget, int force)
858 {
859 struct mv643xx_eth_private *mp = txq_to_mp(txq);
860 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
861 int reclaimed;
862
863 __netif_tx_lock(nq, smp_processor_id());
864
865 reclaimed = 0;
866 while (reclaimed < budget && txq->tx_desc_count > 0) {
867 int tx_index;
868 struct tx_desc *desc;
869 u32 cmd_sts;
870 struct sk_buff *skb;
871
872 tx_index = txq->tx_used_desc;
873 desc = &txq->tx_desc_area[tx_index];
874 cmd_sts = desc->cmd_sts;
875
876 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
877 if (!force)
878 break;
879 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
880 }
881
882 txq->tx_used_desc = tx_index + 1;
883 if (txq->tx_used_desc == txq->tx_ring_size)
884 txq->tx_used_desc = 0;
885
886 reclaimed++;
887 txq->tx_desc_count--;
888
889 skb = NULL;
890 if (cmd_sts & TX_LAST_DESC)
891 skb = __skb_dequeue(&txq->tx_skb);
892
893 if (cmd_sts & ERROR_SUMMARY) {
894 dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
895 mp->dev->stats.tx_errors++;
896 }
897
898 if (cmd_sts & TX_FIRST_DESC) {
899 dma_unmap_single(NULL, desc->buf_ptr,
900 desc->byte_cnt, DMA_TO_DEVICE);
901 } else {
902 dma_unmap_page(NULL, desc->buf_ptr,
903 desc->byte_cnt, DMA_TO_DEVICE);
904 }
905
906 if (skb != NULL) {
907 if (skb_queue_len(&mp->rx_recycle) <
908 mp->default_rx_ring_size &&
909 skb_recycle_check(skb, mp->skb_size))
910 __skb_queue_head(&mp->rx_recycle, skb);
911 else
912 dev_kfree_skb(skb);
913 }
914 }
915
916 __netif_tx_unlock(nq);
917
918 if (reclaimed < budget)
919 mp->work_tx &= ~(1 << txq->index);
920
921 return reclaimed;
922 }
923
924
925 /* tx rate control **********************************************************/
926 /*
927 * Set total maximum TX rate (shared by all TX queues for this port)
928 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
929 */
930 static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
931 {
932 int token_rate;
933 int mtu;
934 int bucket_size;
935
936 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
937 if (token_rate > 1023)
938 token_rate = 1023;
939
940 mtu = (mp->dev->mtu + 255) >> 8;
941 if (mtu > 63)
942 mtu = 63;
943
944 bucket_size = (burst + 255) >> 8;
945 if (bucket_size > 65535)
946 bucket_size = 65535;
947
948 switch (mp->shared->tx_bw_control) {
949 case TX_BW_CONTROL_OLD_LAYOUT:
950 wrlp(mp, TX_BW_RATE, token_rate);
951 wrlp(mp, TX_BW_MTU, mtu);
952 wrlp(mp, TX_BW_BURST, bucket_size);
953 break;
954 case TX_BW_CONTROL_NEW_LAYOUT:
955 wrlp(mp, TX_BW_RATE_MOVED, token_rate);
956 wrlp(mp, TX_BW_MTU_MOVED, mtu);
957 wrlp(mp, TX_BW_BURST_MOVED, bucket_size);
958 break;
959 }
960 }
961
962 static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
963 {
964 struct mv643xx_eth_private *mp = txq_to_mp(txq);
965 int token_rate;
966 int bucket_size;
967
968 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
969 if (token_rate > 1023)
970 token_rate = 1023;
971
972 bucket_size = (burst + 255) >> 8;
973 if (bucket_size > 65535)
974 bucket_size = 65535;
975
976 wrlp(mp, TXQ_BW_TOKENS(txq->index), token_rate << 14);
977 wrlp(mp, TXQ_BW_CONF(txq->index), (bucket_size << 10) | token_rate);
978 }
979
980 static void txq_set_fixed_prio_mode(struct tx_queue *txq)
981 {
982 struct mv643xx_eth_private *mp = txq_to_mp(txq);
983 int off;
984 u32 val;
985
986 /*
987 * Turn on fixed priority mode.
988 */
989 off = 0;
990 switch (mp->shared->tx_bw_control) {
991 case TX_BW_CONTROL_OLD_LAYOUT:
992 off = TXQ_FIX_PRIO_CONF;
993 break;
994 case TX_BW_CONTROL_NEW_LAYOUT:
995 off = TXQ_FIX_PRIO_CONF_MOVED;
996 break;
997 }
998
999 if (off) {
1000 val = rdlp(mp, off);
1001 val |= 1 << txq->index;
1002 wrlp(mp, off, val);
1003 }
1004 }
1005
1006 static void txq_set_wrr(struct tx_queue *txq, int weight)
1007 {
1008 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1009 int off;
1010 u32 val;
1011
1012 /*
1013 * Turn off fixed priority mode.
1014 */
1015 off = 0;
1016 switch (mp->shared->tx_bw_control) {
1017 case TX_BW_CONTROL_OLD_LAYOUT:
1018 off = TXQ_FIX_PRIO_CONF;
1019 break;
1020 case TX_BW_CONTROL_NEW_LAYOUT:
1021 off = TXQ_FIX_PRIO_CONF_MOVED;
1022 break;
1023 }
1024
1025 if (off) {
1026 val = rdlp(mp, off);
1027 val &= ~(1 << txq->index);
1028 wrlp(mp, off, val);
1029
1030 /*
1031 * Configure WRR weight for this queue.
1032 */
1033
1034 val = rdlp(mp, off);
1035 val = (val & ~0xff) | (weight & 0xff);
1036 wrlp(mp, TXQ_BW_WRR_CONF(txq->index), val);
1037 }
1038 }
1039
1040
1041 /* mii management interface *************************************************/
1042 static irqreturn_t mv643xx_eth_err_irq(int irq, void *dev_id)
1043 {
1044 struct mv643xx_eth_shared_private *msp = dev_id;
1045
1046 if (readl(msp->base + ERR_INT_CAUSE) & ERR_INT_SMI_DONE) {
1047 writel(~ERR_INT_SMI_DONE, msp->base + ERR_INT_CAUSE);
1048 wake_up(&msp->smi_busy_wait);
1049 return IRQ_HANDLED;
1050 }
1051
1052 return IRQ_NONE;
1053 }
1054
1055 static int smi_is_done(struct mv643xx_eth_shared_private *msp)
1056 {
1057 return !(readl(msp->base + SMI_REG) & SMI_BUSY);
1058 }
1059
1060 static int smi_wait_ready(struct mv643xx_eth_shared_private *msp)
1061 {
1062 if (msp->err_interrupt == NO_IRQ) {
1063 int i;
1064
1065 for (i = 0; !smi_is_done(msp); i++) {
1066 if (i == 10)
1067 return -ETIMEDOUT;
1068 msleep(10);
1069 }
1070
1071 return 0;
1072 }
1073
1074 if (!smi_is_done(msp)) {
1075 wait_event_timeout(msp->smi_busy_wait, smi_is_done(msp),
1076 msecs_to_jiffies(100));
1077 if (!smi_is_done(msp))
1078 return -ETIMEDOUT;
1079 }
1080
1081 return 0;
1082 }
1083
1084 static int smi_bus_read(struct mii_bus *bus, int addr, int reg)
1085 {
1086 struct mv643xx_eth_shared_private *msp = bus->priv;
1087 void __iomem *smi_reg = msp->base + SMI_REG;
1088 int ret;
1089
1090 if (smi_wait_ready(msp)) {
1091 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
1092 return -ETIMEDOUT;
1093 }
1094
1095 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
1096
1097 if (smi_wait_ready(msp)) {
1098 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
1099 return -ETIMEDOUT;
1100 }
1101
1102 ret = readl(smi_reg);
1103 if (!(ret & SMI_READ_VALID)) {
1104 printk(KERN_WARNING "mv643xx_eth: SMI bus read not valid\n");
1105 return -ENODEV;
1106 }
1107
1108 return ret & 0xffff;
1109 }
1110
1111 static int smi_bus_write(struct mii_bus *bus, int addr, int reg, u16 val)
1112 {
1113 struct mv643xx_eth_shared_private *msp = bus->priv;
1114 void __iomem *smi_reg = msp->base + SMI_REG;
1115
1116 if (smi_wait_ready(msp)) {
1117 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
1118 return -ETIMEDOUT;
1119 }
1120
1121 writel(SMI_OPCODE_WRITE | (reg << 21) |
1122 (addr << 16) | (val & 0xffff), smi_reg);
1123
1124 if (smi_wait_ready(msp)) {
1125 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
1126 return -ETIMEDOUT;
1127 }
1128
1129 return 0;
1130 }
1131
1132
1133 /* statistics ***************************************************************/
1134 static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1135 {
1136 struct mv643xx_eth_private *mp = netdev_priv(dev);
1137 struct net_device_stats *stats = &dev->stats;
1138 unsigned long tx_packets = 0;
1139 unsigned long tx_bytes = 0;
1140 unsigned long tx_dropped = 0;
1141 int i;
1142
1143 for (i = 0; i < mp->txq_count; i++) {
1144 struct tx_queue *txq = mp->txq + i;
1145
1146 tx_packets += txq->tx_packets;
1147 tx_bytes += txq->tx_bytes;
1148 tx_dropped += txq->tx_dropped;
1149 }
1150
1151 stats->tx_packets = tx_packets;
1152 stats->tx_bytes = tx_bytes;
1153 stats->tx_dropped = tx_dropped;
1154
1155 return stats;
1156 }
1157
1158 static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
1159 {
1160 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1161 }
1162
1163 static void mib_counters_clear(struct mv643xx_eth_private *mp)
1164 {
1165 int i;
1166
1167 for (i = 0; i < 0x80; i += 4)
1168 mib_read(mp, i);
1169 }
1170
1171 static void mib_counters_update(struct mv643xx_eth_private *mp)
1172 {
1173 struct mib_counters *p = &mp->mib_counters;
1174
1175 spin_lock(&mp->mib_counters_lock);
1176 p->good_octets_received += mib_read(mp, 0x00);
1177 p->good_octets_received += (u64)mib_read(mp, 0x04) << 32;
1178 p->bad_octets_received += mib_read(mp, 0x08);
1179 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1180 p->good_frames_received += mib_read(mp, 0x10);
1181 p->bad_frames_received += mib_read(mp, 0x14);
1182 p->broadcast_frames_received += mib_read(mp, 0x18);
1183 p->multicast_frames_received += mib_read(mp, 0x1c);
1184 p->frames_64_octets += mib_read(mp, 0x20);
1185 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1186 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1187 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1188 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1189 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1190 p->good_octets_sent += mib_read(mp, 0x38);
1191 p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32;
1192 p->good_frames_sent += mib_read(mp, 0x40);
1193 p->excessive_collision += mib_read(mp, 0x44);
1194 p->multicast_frames_sent += mib_read(mp, 0x48);
1195 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1196 p->unrec_mac_control_received += mib_read(mp, 0x50);
1197 p->fc_sent += mib_read(mp, 0x54);
1198 p->good_fc_received += mib_read(mp, 0x58);
1199 p->bad_fc_received += mib_read(mp, 0x5c);
1200 p->undersize_received += mib_read(mp, 0x60);
1201 p->fragments_received += mib_read(mp, 0x64);
1202 p->oversize_received += mib_read(mp, 0x68);
1203 p->jabber_received += mib_read(mp, 0x6c);
1204 p->mac_receive_error += mib_read(mp, 0x70);
1205 p->bad_crc_event += mib_read(mp, 0x74);
1206 p->collision += mib_read(mp, 0x78);
1207 p->late_collision += mib_read(mp, 0x7c);
1208 spin_unlock(&mp->mib_counters_lock);
1209
1210 mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ);
1211 }
1212
1213 static void mib_counters_timer_wrapper(unsigned long _mp)
1214 {
1215 struct mv643xx_eth_private *mp = (void *)_mp;
1216
1217 mib_counters_update(mp);
1218 }
1219
1220
1221 /* ethtool ******************************************************************/
1222 struct mv643xx_eth_stats {
1223 char stat_string[ETH_GSTRING_LEN];
1224 int sizeof_stat;
1225 int netdev_off;
1226 int mp_off;
1227 };
1228
1229 #define SSTAT(m) \
1230 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1231 offsetof(struct net_device, stats.m), -1 }
1232
1233 #define MIBSTAT(m) \
1234 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1235 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1236
1237 static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1238 SSTAT(rx_packets),
1239 SSTAT(tx_packets),
1240 SSTAT(rx_bytes),
1241 SSTAT(tx_bytes),
1242 SSTAT(rx_errors),
1243 SSTAT(tx_errors),
1244 SSTAT(rx_dropped),
1245 SSTAT(tx_dropped),
1246 MIBSTAT(good_octets_received),
1247 MIBSTAT(bad_octets_received),
1248 MIBSTAT(internal_mac_transmit_err),
1249 MIBSTAT(good_frames_received),
1250 MIBSTAT(bad_frames_received),
1251 MIBSTAT(broadcast_frames_received),
1252 MIBSTAT(multicast_frames_received),
1253 MIBSTAT(frames_64_octets),
1254 MIBSTAT(frames_65_to_127_octets),
1255 MIBSTAT(frames_128_to_255_octets),
1256 MIBSTAT(frames_256_to_511_octets),
1257 MIBSTAT(frames_512_to_1023_octets),
1258 MIBSTAT(frames_1024_to_max_octets),
1259 MIBSTAT(good_octets_sent),
1260 MIBSTAT(good_frames_sent),
1261 MIBSTAT(excessive_collision),
1262 MIBSTAT(multicast_frames_sent),
1263 MIBSTAT(broadcast_frames_sent),
1264 MIBSTAT(unrec_mac_control_received),
1265 MIBSTAT(fc_sent),
1266 MIBSTAT(good_fc_received),
1267 MIBSTAT(bad_fc_received),
1268 MIBSTAT(undersize_received),
1269 MIBSTAT(fragments_received),
1270 MIBSTAT(oversize_received),
1271 MIBSTAT(jabber_received),
1272 MIBSTAT(mac_receive_error),
1273 MIBSTAT(bad_crc_event),
1274 MIBSTAT(collision),
1275 MIBSTAT(late_collision),
1276 };
1277
1278 static int
1279 mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1280 {
1281 struct mv643xx_eth_private *mp = netdev_priv(dev);
1282 int err;
1283
1284 err = phy_read_status(mp->phy);
1285 if (err == 0)
1286 err = phy_ethtool_gset(mp->phy, cmd);
1287
1288 /*
1289 * The MAC does not support 1000baseT_Half.
1290 */
1291 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1292 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1293
1294 return err;
1295 }
1296
1297 static int
1298 mv643xx_eth_get_settings_phyless(struct net_device *dev,
1299 struct ethtool_cmd *cmd)
1300 {
1301 struct mv643xx_eth_private *mp = netdev_priv(dev);
1302 u32 port_status;
1303
1304 port_status = rdlp(mp, PORT_STATUS);
1305
1306 cmd->supported = SUPPORTED_MII;
1307 cmd->advertising = ADVERTISED_MII;
1308 switch (port_status & PORT_SPEED_MASK) {
1309 case PORT_SPEED_10:
1310 cmd->speed = SPEED_10;
1311 break;
1312 case PORT_SPEED_100:
1313 cmd->speed = SPEED_100;
1314 break;
1315 case PORT_SPEED_1000:
1316 cmd->speed = SPEED_1000;
1317 break;
1318 default:
1319 cmd->speed = -1;
1320 break;
1321 }
1322 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
1323 cmd->port = PORT_MII;
1324 cmd->phy_address = 0;
1325 cmd->transceiver = XCVR_INTERNAL;
1326 cmd->autoneg = AUTONEG_DISABLE;
1327 cmd->maxtxpkt = 1;
1328 cmd->maxrxpkt = 1;
1329
1330 return 0;
1331 }
1332
1333 static int
1334 mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1335 {
1336 struct mv643xx_eth_private *mp = netdev_priv(dev);
1337
1338 /*
1339 * The MAC does not support 1000baseT_Half.
1340 */
1341 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1342
1343 return phy_ethtool_sset(mp->phy, cmd);
1344 }
1345
1346 static int
1347 mv643xx_eth_set_settings_phyless(struct net_device *dev,
1348 struct ethtool_cmd *cmd)
1349 {
1350 return -EINVAL;
1351 }
1352
1353 static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1354 struct ethtool_drvinfo *drvinfo)
1355 {
1356 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1357 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
1358 strncpy(drvinfo->fw_version, "N/A", 32);
1359 strncpy(drvinfo->bus_info, "platform", 32);
1360 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
1361 }
1362
1363 static int mv643xx_eth_nway_reset(struct net_device *dev)
1364 {
1365 struct mv643xx_eth_private *mp = netdev_priv(dev);
1366
1367 return genphy_restart_aneg(mp->phy);
1368 }
1369
1370 static int mv643xx_eth_nway_reset_phyless(struct net_device *dev)
1371 {
1372 return -EINVAL;
1373 }
1374
1375 static u32 mv643xx_eth_get_link(struct net_device *dev)
1376 {
1377 return !!netif_carrier_ok(dev);
1378 }
1379
1380 static void mv643xx_eth_get_strings(struct net_device *dev,
1381 uint32_t stringset, uint8_t *data)
1382 {
1383 int i;
1384
1385 if (stringset == ETH_SS_STATS) {
1386 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1387 memcpy(data + i * ETH_GSTRING_LEN,
1388 mv643xx_eth_stats[i].stat_string,
1389 ETH_GSTRING_LEN);
1390 }
1391 }
1392 }
1393
1394 static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1395 struct ethtool_stats *stats,
1396 uint64_t *data)
1397 {
1398 struct mv643xx_eth_private *mp = netdev_priv(dev);
1399 int i;
1400
1401 mv643xx_eth_get_stats(dev);
1402 mib_counters_update(mp);
1403
1404 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1405 const struct mv643xx_eth_stats *stat;
1406 void *p;
1407
1408 stat = mv643xx_eth_stats + i;
1409
1410 if (stat->netdev_off >= 0)
1411 p = ((void *)mp->dev) + stat->netdev_off;
1412 else
1413 p = ((void *)mp) + stat->mp_off;
1414
1415 data[i] = (stat->sizeof_stat == 8) ?
1416 *(uint64_t *)p : *(uint32_t *)p;
1417 }
1418 }
1419
1420 static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
1421 {
1422 if (sset == ETH_SS_STATS)
1423 return ARRAY_SIZE(mv643xx_eth_stats);
1424
1425 return -EOPNOTSUPP;
1426 }
1427
1428 static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
1429 .get_settings = mv643xx_eth_get_settings,
1430 .set_settings = mv643xx_eth_set_settings,
1431 .get_drvinfo = mv643xx_eth_get_drvinfo,
1432 .nway_reset = mv643xx_eth_nway_reset,
1433 .get_link = mv643xx_eth_get_link,
1434 .set_sg = ethtool_op_set_sg,
1435 .get_strings = mv643xx_eth_get_strings,
1436 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1437 .get_sset_count = mv643xx_eth_get_sset_count,
1438 };
1439
1440 static const struct ethtool_ops mv643xx_eth_ethtool_ops_phyless = {
1441 .get_settings = mv643xx_eth_get_settings_phyless,
1442 .set_settings = mv643xx_eth_set_settings_phyless,
1443 .get_drvinfo = mv643xx_eth_get_drvinfo,
1444 .nway_reset = mv643xx_eth_nway_reset_phyless,
1445 .get_link = mv643xx_eth_get_link,
1446 .set_sg = ethtool_op_set_sg,
1447 .get_strings = mv643xx_eth_get_strings,
1448 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1449 .get_sset_count = mv643xx_eth_get_sset_count,
1450 };
1451
1452
1453 /* address handling *********************************************************/
1454 static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
1455 {
1456 unsigned int mac_h = rdlp(mp, MAC_ADDR_HIGH);
1457 unsigned int mac_l = rdlp(mp, MAC_ADDR_LOW);
1458
1459 addr[0] = (mac_h >> 24) & 0xff;
1460 addr[1] = (mac_h >> 16) & 0xff;
1461 addr[2] = (mac_h >> 8) & 0xff;
1462 addr[3] = mac_h & 0xff;
1463 addr[4] = (mac_l >> 8) & 0xff;
1464 addr[5] = mac_l & 0xff;
1465 }
1466
1467 static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1468 {
1469 wrlp(mp, MAC_ADDR_HIGH,
1470 (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]);
1471 wrlp(mp, MAC_ADDR_LOW, (addr[4] << 8) | addr[5]);
1472 }
1473
1474 static u32 uc_addr_filter_mask(struct net_device *dev)
1475 {
1476 struct dev_addr_list *uc_ptr;
1477 u32 nibbles;
1478
1479 if (dev->flags & IFF_PROMISC)
1480 return 0;
1481
1482 nibbles = 1 << (dev->dev_addr[5] & 0x0f);
1483 for (uc_ptr = dev->uc_list; uc_ptr != NULL; uc_ptr = uc_ptr->next) {
1484 if (memcmp(dev->dev_addr, uc_ptr->da_addr, 5))
1485 return 0;
1486 if ((dev->dev_addr[5] ^ uc_ptr->da_addr[5]) & 0xf0)
1487 return 0;
1488
1489 nibbles |= 1 << (uc_ptr->da_addr[5] & 0x0f);
1490 }
1491
1492 return nibbles;
1493 }
1494
1495 static void mv643xx_eth_program_unicast_filter(struct net_device *dev)
1496 {
1497 struct mv643xx_eth_private *mp = netdev_priv(dev);
1498 u32 port_config;
1499 u32 nibbles;
1500 int i;
1501
1502 uc_addr_set(mp, dev->dev_addr);
1503
1504 port_config = rdlp(mp, PORT_CONFIG);
1505 nibbles = uc_addr_filter_mask(dev);
1506 if (!nibbles) {
1507 port_config |= UNICAST_PROMISCUOUS_MODE;
1508 wrlp(mp, PORT_CONFIG, port_config);
1509 return;
1510 }
1511
1512 for (i = 0; i < 16; i += 4) {
1513 int off = UNICAST_TABLE(mp->port_num) + i;
1514 u32 v;
1515
1516 v = 0;
1517 if (nibbles & 1)
1518 v |= 0x00000001;
1519 if (nibbles & 2)
1520 v |= 0x00000100;
1521 if (nibbles & 4)
1522 v |= 0x00010000;
1523 if (nibbles & 8)
1524 v |= 0x01000000;
1525 nibbles >>= 4;
1526
1527 wrl(mp, off, v);
1528 }
1529
1530 port_config &= ~UNICAST_PROMISCUOUS_MODE;
1531 wrlp(mp, PORT_CONFIG, port_config);
1532 }
1533
1534 static int addr_crc(unsigned char *addr)
1535 {
1536 int crc = 0;
1537 int i;
1538
1539 for (i = 0; i < 6; i++) {
1540 int j;
1541
1542 crc = (crc ^ addr[i]) << 8;
1543 for (j = 7; j >= 0; j--) {
1544 if (crc & (0x100 << j))
1545 crc ^= 0x107 << j;
1546 }
1547 }
1548
1549 return crc;
1550 }
1551
1552 static void mv643xx_eth_program_multicast_filter(struct net_device *dev)
1553 {
1554 struct mv643xx_eth_private *mp = netdev_priv(dev);
1555 u32 *mc_spec;
1556 u32 *mc_other;
1557 struct dev_addr_list *addr;
1558 int i;
1559
1560 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1561 int port_num;
1562 u32 accept;
1563 int i;
1564
1565 oom:
1566 port_num = mp->port_num;
1567 accept = 0x01010101;
1568 for (i = 0; i < 0x100; i += 4) {
1569 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1570 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
1571 }
1572 return;
1573 }
1574
1575 mc_spec = kmalloc(0x200, GFP_KERNEL);
1576 if (mc_spec == NULL)
1577 goto oom;
1578 mc_other = mc_spec + (0x100 >> 2);
1579
1580 memset(mc_spec, 0, 0x100);
1581 memset(mc_other, 0, 0x100);
1582
1583 for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
1584 u8 *a = addr->da_addr;
1585 u32 *table;
1586 int entry;
1587
1588 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1589 table = mc_spec;
1590 entry = a[5];
1591 } else {
1592 table = mc_other;
1593 entry = addr_crc(a);
1594 }
1595
1596 table[entry >> 2] |= 1 << (entry & 3);
1597 }
1598
1599 for (i = 0; i < 0x100; i += 4) {
1600 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, mc_spec[i >> 2]);
1601 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, mc_other[i >> 2]);
1602 }
1603
1604 kfree(mc_spec);
1605 }
1606
1607 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1608 {
1609 mv643xx_eth_program_unicast_filter(dev);
1610 mv643xx_eth_program_multicast_filter(dev);
1611 }
1612
1613 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1614 {
1615 struct sockaddr *sa = addr;
1616
1617 memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN);
1618
1619 netif_addr_lock_bh(dev);
1620 mv643xx_eth_program_unicast_filter(dev);
1621 netif_addr_unlock_bh(dev);
1622
1623 return 0;
1624 }
1625
1626
1627 /* rx/tx queue initialisation ***********************************************/
1628 static int rxq_init(struct mv643xx_eth_private *mp, int index)
1629 {
1630 struct rx_queue *rxq = mp->rxq + index;
1631 struct rx_desc *rx_desc;
1632 int size;
1633 int i;
1634
1635 rxq->index = index;
1636
1637 rxq->rx_ring_size = mp->default_rx_ring_size;
1638
1639 rxq->rx_desc_count = 0;
1640 rxq->rx_curr_desc = 0;
1641 rxq->rx_used_desc = 0;
1642
1643 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1644
1645 if (index == 0 && size <= mp->rx_desc_sram_size) {
1646 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1647 mp->rx_desc_sram_size);
1648 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1649 } else {
1650 rxq->rx_desc_area = dma_alloc_coherent(NULL, size,
1651 &rxq->rx_desc_dma,
1652 GFP_KERNEL);
1653 }
1654
1655 if (rxq->rx_desc_area == NULL) {
1656 dev_printk(KERN_ERR, &mp->dev->dev,
1657 "can't allocate rx ring (%d bytes)\n", size);
1658 goto out;
1659 }
1660 memset(rxq->rx_desc_area, 0, size);
1661
1662 rxq->rx_desc_area_size = size;
1663 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1664 GFP_KERNEL);
1665 if (rxq->rx_skb == NULL) {
1666 dev_printk(KERN_ERR, &mp->dev->dev,
1667 "can't allocate rx skb ring\n");
1668 goto out_free;
1669 }
1670
1671 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1672 for (i = 0; i < rxq->rx_ring_size; i++) {
1673 int nexti;
1674
1675 nexti = i + 1;
1676 if (nexti == rxq->rx_ring_size)
1677 nexti = 0;
1678
1679 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1680 nexti * sizeof(struct rx_desc);
1681 }
1682
1683 return 0;
1684
1685
1686 out_free:
1687 if (index == 0 && size <= mp->rx_desc_sram_size)
1688 iounmap(rxq->rx_desc_area);
1689 else
1690 dma_free_coherent(NULL, size,
1691 rxq->rx_desc_area,
1692 rxq->rx_desc_dma);
1693
1694 out:
1695 return -ENOMEM;
1696 }
1697
1698 static void rxq_deinit(struct rx_queue *rxq)
1699 {
1700 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1701 int i;
1702
1703 rxq_disable(rxq);
1704
1705 for (i = 0; i < rxq->rx_ring_size; i++) {
1706 if (rxq->rx_skb[i]) {
1707 dev_kfree_skb(rxq->rx_skb[i]);
1708 rxq->rx_desc_count--;
1709 }
1710 }
1711
1712 if (rxq->rx_desc_count) {
1713 dev_printk(KERN_ERR, &mp->dev->dev,
1714 "error freeing rx ring -- %d skbs stuck\n",
1715 rxq->rx_desc_count);
1716 }
1717
1718 if (rxq->index == 0 &&
1719 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
1720 iounmap(rxq->rx_desc_area);
1721 else
1722 dma_free_coherent(NULL, rxq->rx_desc_area_size,
1723 rxq->rx_desc_area, rxq->rx_desc_dma);
1724
1725 kfree(rxq->rx_skb);
1726 }
1727
1728 static int txq_init(struct mv643xx_eth_private *mp, int index)
1729 {
1730 struct tx_queue *txq = mp->txq + index;
1731 struct tx_desc *tx_desc;
1732 int size;
1733 int i;
1734
1735 txq->index = index;
1736
1737 txq->tx_ring_size = mp->default_tx_ring_size;
1738
1739 txq->tx_desc_count = 0;
1740 txq->tx_curr_desc = 0;
1741 txq->tx_used_desc = 0;
1742
1743 size = txq->tx_ring_size * sizeof(struct tx_desc);
1744
1745 if (index == 0 && size <= mp->tx_desc_sram_size) {
1746 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1747 mp->tx_desc_sram_size);
1748 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1749 } else {
1750 txq->tx_desc_area = dma_alloc_coherent(NULL, size,
1751 &txq->tx_desc_dma,
1752 GFP_KERNEL);
1753 }
1754
1755 if (txq->tx_desc_area == NULL) {
1756 dev_printk(KERN_ERR, &mp->dev->dev,
1757 "can't allocate tx ring (%d bytes)\n", size);
1758 return -ENOMEM;
1759 }
1760 memset(txq->tx_desc_area, 0, size);
1761
1762 txq->tx_desc_area_size = size;
1763
1764 tx_desc = (struct tx_desc *)txq->tx_desc_area;
1765 for (i = 0; i < txq->tx_ring_size; i++) {
1766 struct tx_desc *txd = tx_desc + i;
1767 int nexti;
1768
1769 nexti = i + 1;
1770 if (nexti == txq->tx_ring_size)
1771 nexti = 0;
1772
1773 txd->cmd_sts = 0;
1774 txd->next_desc_ptr = txq->tx_desc_dma +
1775 nexti * sizeof(struct tx_desc);
1776 }
1777
1778 skb_queue_head_init(&txq->tx_skb);
1779
1780 return 0;
1781 }
1782
1783 static void txq_deinit(struct tx_queue *txq)
1784 {
1785 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1786
1787 txq_disable(txq);
1788 txq_reclaim(txq, txq->tx_ring_size, 1);
1789
1790 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1791
1792 if (txq->index == 0 &&
1793 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
1794 iounmap(txq->tx_desc_area);
1795 else
1796 dma_free_coherent(NULL, txq->tx_desc_area_size,
1797 txq->tx_desc_area, txq->tx_desc_dma);
1798 }
1799
1800
1801 /* netdev ops and related ***************************************************/
1802 static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp)
1803 {
1804 u32 int_cause;
1805 u32 int_cause_ext;
1806
1807 int_cause = rdlp(mp, INT_CAUSE) & (INT_TX_END | INT_RX | INT_EXT);
1808 if (int_cause == 0)
1809 return 0;
1810
1811 int_cause_ext = 0;
1812 if (int_cause & INT_EXT)
1813 int_cause_ext = rdlp(mp, INT_CAUSE_EXT);
1814
1815 int_cause &= INT_TX_END | INT_RX;
1816 if (int_cause) {
1817 wrlp(mp, INT_CAUSE, ~int_cause);
1818 mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) &
1819 ~(rdlp(mp, TXQ_COMMAND) & 0xff);
1820 mp->work_rx |= (int_cause & INT_RX) >> 2;
1821 }
1822
1823 int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX;
1824 if (int_cause_ext) {
1825 wrlp(mp, INT_CAUSE_EXT, ~int_cause_ext);
1826 if (int_cause_ext & INT_EXT_LINK_PHY)
1827 mp->work_link = 1;
1828 mp->work_tx |= int_cause_ext & INT_EXT_TX;
1829 }
1830
1831 return 1;
1832 }
1833
1834 static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
1835 {
1836 struct net_device *dev = (struct net_device *)dev_id;
1837 struct mv643xx_eth_private *mp = netdev_priv(dev);
1838
1839 if (unlikely(!mv643xx_eth_collect_events(mp)))
1840 return IRQ_NONE;
1841
1842 wrlp(mp, INT_MASK, 0);
1843 napi_schedule(&mp->napi);
1844
1845 return IRQ_HANDLED;
1846 }
1847
1848 static void handle_link_event(struct mv643xx_eth_private *mp)
1849 {
1850 struct net_device *dev = mp->dev;
1851 u32 port_status;
1852 int speed;
1853 int duplex;
1854 int fc;
1855
1856 port_status = rdlp(mp, PORT_STATUS);
1857 if (!(port_status & LINK_UP)) {
1858 if (netif_carrier_ok(dev)) {
1859 int i;
1860
1861 printk(KERN_INFO "%s: link down\n", dev->name);
1862
1863 netif_carrier_off(dev);
1864
1865 for (i = 0; i < mp->txq_count; i++) {
1866 struct tx_queue *txq = mp->txq + i;
1867
1868 txq_reclaim(txq, txq->tx_ring_size, 1);
1869 txq_reset_hw_ptr(txq);
1870 }
1871 }
1872 return;
1873 }
1874
1875 switch (port_status & PORT_SPEED_MASK) {
1876 case PORT_SPEED_10:
1877 speed = 10;
1878 break;
1879 case PORT_SPEED_100:
1880 speed = 100;
1881 break;
1882 case PORT_SPEED_1000:
1883 speed = 1000;
1884 break;
1885 default:
1886 speed = -1;
1887 break;
1888 }
1889 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
1890 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
1891
1892 printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
1893 "flow control %sabled\n", dev->name,
1894 speed, duplex ? "full" : "half",
1895 fc ? "en" : "dis");
1896
1897 if (!netif_carrier_ok(dev))
1898 netif_carrier_on(dev);
1899 }
1900
1901 static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
1902 {
1903 struct mv643xx_eth_private *mp;
1904 int work_done;
1905
1906 mp = container_of(napi, struct mv643xx_eth_private, napi);
1907
1908 mp->work_rx_refill |= mp->work_rx_oom;
1909 mp->work_rx_oom = 0;
1910
1911 work_done = 0;
1912 while (work_done < budget) {
1913 u8 queue_mask;
1914 int queue;
1915 int work_tbd;
1916
1917 if (mp->work_link) {
1918 mp->work_link = 0;
1919 handle_link_event(mp);
1920 continue;
1921 }
1922
1923 queue_mask = mp->work_tx | mp->work_tx_end |
1924 mp->work_rx | mp->work_rx_refill;
1925 if (!queue_mask) {
1926 if (mv643xx_eth_collect_events(mp))
1927 continue;
1928 break;
1929 }
1930
1931 queue = fls(queue_mask) - 1;
1932 queue_mask = 1 << queue;
1933
1934 work_tbd = budget - work_done;
1935 if (work_tbd > 16)
1936 work_tbd = 16;
1937
1938 if (mp->work_tx_end & queue_mask) {
1939 txq_kick(mp->txq + queue);
1940 } else if (mp->work_tx & queue_mask) {
1941 work_done += txq_reclaim(mp->txq + queue, work_tbd, 0);
1942 txq_maybe_wake(mp->txq + queue);
1943 } else if (mp->work_rx & queue_mask) {
1944 work_done += rxq_process(mp->rxq + queue, work_tbd);
1945 } else if (mp->work_rx_refill & queue_mask) {
1946 work_done += rxq_refill(mp->rxq + queue, work_tbd);
1947 } else {
1948 BUG();
1949 }
1950 }
1951
1952 if (work_done < budget) {
1953 if (mp->work_rx_oom)
1954 mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
1955 napi_complete(napi);
1956 wrlp(mp, INT_MASK, INT_TX_END | INT_RX | INT_EXT);
1957 }
1958
1959 return work_done;
1960 }
1961
1962 static inline void oom_timer_wrapper(unsigned long data)
1963 {
1964 struct mv643xx_eth_private *mp = (void *)data;
1965
1966 napi_schedule(&mp->napi);
1967 }
1968
1969 static void phy_reset(struct mv643xx_eth_private *mp)
1970 {
1971 int data;
1972
1973 data = phy_read(mp->phy, MII_BMCR);
1974 if (data < 0)
1975 return;
1976
1977 data |= BMCR_RESET;
1978 if (phy_write(mp->phy, MII_BMCR, data) < 0)
1979 return;
1980
1981 do {
1982 data = phy_read(mp->phy, MII_BMCR);
1983 } while (data >= 0 && data & BMCR_RESET);
1984 }
1985
1986 static void port_start(struct mv643xx_eth_private *mp)
1987 {
1988 u32 pscr;
1989 int i;
1990
1991 /*
1992 * Perform PHY reset, if there is a PHY.
1993 */
1994 if (mp->phy != NULL) {
1995 struct ethtool_cmd cmd;
1996
1997 mv643xx_eth_get_settings(mp->dev, &cmd);
1998 phy_reset(mp);
1999 mv643xx_eth_set_settings(mp->dev, &cmd);
2000 }
2001
2002 /*
2003 * Configure basic link parameters.
2004 */
2005 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
2006
2007 pscr |= SERIAL_PORT_ENABLE;
2008 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2009
2010 pscr |= DO_NOT_FORCE_LINK_FAIL;
2011 if (mp->phy == NULL)
2012 pscr |= FORCE_LINK_PASS;
2013 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2014
2015 wrlp(mp, SDMA_CONFIG, PORT_SDMA_CONFIG_DEFAULT_VALUE);
2016
2017 /*
2018 * Configure TX path and queues.
2019 */
2020 tx_set_rate(mp, 1000000000, 16777216);
2021 for (i = 0; i < mp->txq_count; i++) {
2022 struct tx_queue *txq = mp->txq + i;
2023
2024 txq_reset_hw_ptr(txq);
2025 txq_set_rate(txq, 1000000000, 16777216);
2026 txq_set_fixed_prio_mode(txq);
2027 }
2028
2029 /*
2030 * Add configured unicast address to address filter table.
2031 */
2032 mv643xx_eth_program_unicast_filter(mp->dev);
2033
2034 /*
2035 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
2036 * frames to RX queue #0, and include the pseudo-header when
2037 * calculating receive checksums.
2038 */
2039 wrlp(mp, PORT_CONFIG, 0x02000000);
2040
2041 /*
2042 * Treat BPDUs as normal multicasts, and disable partition mode.
2043 */
2044 wrlp(mp, PORT_CONFIG_EXT, 0x00000000);
2045
2046 /*
2047 * Enable the receive queues.
2048 */
2049 for (i = 0; i < mp->rxq_count; i++) {
2050 struct rx_queue *rxq = mp->rxq + i;
2051 u32 addr;
2052
2053 addr = (u32)rxq->rx_desc_dma;
2054 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
2055 wrlp(mp, RXQ_CURRENT_DESC_PTR(i), addr);
2056
2057 rxq_enable(rxq);
2058 }
2059 }
2060
2061 static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
2062 {
2063 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
2064 u32 val;
2065
2066 val = rdlp(mp, SDMA_CONFIG);
2067 if (mp->shared->extended_rx_coal_limit) {
2068 if (coal > 0xffff)
2069 coal = 0xffff;
2070 val &= ~0x023fff80;
2071 val |= (coal & 0x8000) << 10;
2072 val |= (coal & 0x7fff) << 7;
2073 } else {
2074 if (coal > 0x3fff)
2075 coal = 0x3fff;
2076 val &= ~0x003fff00;
2077 val |= (coal & 0x3fff) << 8;
2078 }
2079 wrlp(mp, SDMA_CONFIG, val);
2080 }
2081
2082 static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
2083 {
2084 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
2085
2086 if (coal > 0x3fff)
2087 coal = 0x3fff;
2088 wrlp(mp, TX_FIFO_URGENT_THRESHOLD, (coal & 0x3fff) << 4);
2089 }
2090
2091 static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp)
2092 {
2093 int skb_size;
2094
2095 /*
2096 * Reserve 2+14 bytes for an ethernet header (the hardware
2097 * automatically prepends 2 bytes of dummy data to each
2098 * received packet), 16 bytes for up to four VLAN tags, and
2099 * 4 bytes for the trailing FCS -- 36 bytes total.
2100 */
2101 skb_size = mp->dev->mtu + 36;
2102
2103 /*
2104 * Make sure that the skb size is a multiple of 8 bytes, as
2105 * the lower three bits of the receive descriptor's buffer
2106 * size field are ignored by the hardware.
2107 */
2108 mp->skb_size = (skb_size + 7) & ~7;
2109 }
2110
2111 static int mv643xx_eth_open(struct net_device *dev)
2112 {
2113 struct mv643xx_eth_private *mp = netdev_priv(dev);
2114 int err;
2115 int i;
2116
2117 wrlp(mp, INT_CAUSE, 0);
2118 wrlp(mp, INT_CAUSE_EXT, 0);
2119 rdlp(mp, INT_CAUSE_EXT);
2120
2121 err = request_irq(dev->irq, mv643xx_eth_irq,
2122 IRQF_SHARED, dev->name, dev);
2123 if (err) {
2124 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
2125 return -EAGAIN;
2126 }
2127
2128 mv643xx_eth_recalc_skb_size(mp);
2129
2130 napi_enable(&mp->napi);
2131
2132 skb_queue_head_init(&mp->rx_recycle);
2133
2134 for (i = 0; i < mp->rxq_count; i++) {
2135 err = rxq_init(mp, i);
2136 if (err) {
2137 while (--i >= 0)
2138 rxq_deinit(mp->rxq + i);
2139 goto out;
2140 }
2141
2142 rxq_refill(mp->rxq + i, INT_MAX);
2143 }
2144
2145 if (mp->work_rx_oom) {
2146 mp->rx_oom.expires = jiffies + (HZ / 10);
2147 add_timer(&mp->rx_oom);
2148 }
2149
2150 for (i = 0; i < mp->txq_count; i++) {
2151 err = txq_init(mp, i);
2152 if (err) {
2153 while (--i >= 0)
2154 txq_deinit(mp->txq + i);
2155 goto out_free;
2156 }
2157 }
2158
2159 netif_carrier_off(dev);
2160
2161 port_start(mp);
2162
2163 set_rx_coal(mp, 0);
2164 set_tx_coal(mp, 0);
2165
2166 wrlp(mp, INT_MASK_EXT, INT_EXT_LINK_PHY | INT_EXT_TX);
2167 wrlp(mp, INT_MASK, INT_TX_END | INT_RX | INT_EXT);
2168
2169 return 0;
2170
2171
2172 out_free:
2173 for (i = 0; i < mp->rxq_count; i++)
2174 rxq_deinit(mp->rxq + i);
2175 out:
2176 free_irq(dev->irq, dev);
2177
2178 return err;
2179 }
2180
2181 static void port_reset(struct mv643xx_eth_private *mp)
2182 {
2183 unsigned int data;
2184 int i;
2185
2186 for (i = 0; i < mp->rxq_count; i++)
2187 rxq_disable(mp->rxq + i);
2188 for (i = 0; i < mp->txq_count; i++)
2189 txq_disable(mp->txq + i);
2190
2191 while (1) {
2192 u32 ps = rdlp(mp, PORT_STATUS);
2193
2194 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2195 break;
2196 udelay(10);
2197 }
2198
2199 /* Reset the Enable bit in the Configuration Register */
2200 data = rdlp(mp, PORT_SERIAL_CONTROL);
2201 data &= ~(SERIAL_PORT_ENABLE |
2202 DO_NOT_FORCE_LINK_FAIL |
2203 FORCE_LINK_PASS);
2204 wrlp(mp, PORT_SERIAL_CONTROL, data);
2205 }
2206
2207 static int mv643xx_eth_stop(struct net_device *dev)
2208 {
2209 struct mv643xx_eth_private *mp = netdev_priv(dev);
2210 int i;
2211
2212 wrlp(mp, INT_MASK, 0x00000000);
2213 rdlp(mp, INT_MASK);
2214
2215 del_timer_sync(&mp->mib_counters_timer);
2216
2217 napi_disable(&mp->napi);
2218
2219 del_timer_sync(&mp->rx_oom);
2220
2221 netif_carrier_off(dev);
2222
2223 free_irq(dev->irq, dev);
2224
2225 port_reset(mp);
2226 mv643xx_eth_get_stats(dev);
2227 mib_counters_update(mp);
2228
2229 skb_queue_purge(&mp->rx_recycle);
2230
2231 for (i = 0; i < mp->rxq_count; i++)
2232 rxq_deinit(mp->rxq + i);
2233 for (i = 0; i < mp->txq_count; i++)
2234 txq_deinit(mp->txq + i);
2235
2236 return 0;
2237 }
2238
2239 static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2240 {
2241 struct mv643xx_eth_private *mp = netdev_priv(dev);
2242
2243 if (mp->phy != NULL)
2244 return phy_mii_ioctl(mp->phy, if_mii(ifr), cmd);
2245
2246 return -EOPNOTSUPP;
2247 }
2248
2249 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
2250 {
2251 struct mv643xx_eth_private *mp = netdev_priv(dev);
2252
2253 if (new_mtu < 64 || new_mtu > 9500)
2254 return -EINVAL;
2255
2256 dev->mtu = new_mtu;
2257 mv643xx_eth_recalc_skb_size(mp);
2258 tx_set_rate(mp, 1000000000, 16777216);
2259
2260 if (!netif_running(dev))
2261 return 0;
2262
2263 /*
2264 * Stop and then re-open the interface. This will allocate RX
2265 * skbs of the new MTU.
2266 * There is a possible danger that the open will not succeed,
2267 * due to memory being full.
2268 */
2269 mv643xx_eth_stop(dev);
2270 if (mv643xx_eth_open(dev)) {
2271 dev_printk(KERN_ERR, &dev->dev,
2272 "fatal error on re-opening device after "
2273 "MTU change\n");
2274 }
2275
2276 return 0;
2277 }
2278
2279 static void tx_timeout_task(struct work_struct *ugly)
2280 {
2281 struct mv643xx_eth_private *mp;
2282
2283 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2284 if (netif_running(mp->dev)) {
2285 netif_tx_stop_all_queues(mp->dev);
2286 port_reset(mp);
2287 port_start(mp);
2288 netif_tx_wake_all_queues(mp->dev);
2289 }
2290 }
2291
2292 static void mv643xx_eth_tx_timeout(struct net_device *dev)
2293 {
2294 struct mv643xx_eth_private *mp = netdev_priv(dev);
2295
2296 dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
2297
2298 schedule_work(&mp->tx_timeout_task);
2299 }
2300
2301 #ifdef CONFIG_NET_POLL_CONTROLLER
2302 static void mv643xx_eth_netpoll(struct net_device *dev)
2303 {
2304 struct mv643xx_eth_private *mp = netdev_priv(dev);
2305
2306 wrlp(mp, INT_MASK, 0x00000000);
2307 rdlp(mp, INT_MASK);
2308
2309 mv643xx_eth_irq(dev->irq, dev);
2310
2311 wrlp(mp, INT_MASK, INT_TX_END | INT_RX | INT_EXT);
2312 }
2313 #endif
2314
2315
2316 /* platform glue ************************************************************/
2317 static void
2318 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2319 struct mbus_dram_target_info *dram)
2320 {
2321 void __iomem *base = msp->base;
2322 u32 win_enable;
2323 u32 win_protect;
2324 int i;
2325
2326 for (i = 0; i < 6; i++) {
2327 writel(0, base + WINDOW_BASE(i));
2328 writel(0, base + WINDOW_SIZE(i));
2329 if (i < 4)
2330 writel(0, base + WINDOW_REMAP_HIGH(i));
2331 }
2332
2333 win_enable = 0x3f;
2334 win_protect = 0;
2335
2336 for (i = 0; i < dram->num_cs; i++) {
2337 struct mbus_dram_window *cs = dram->cs + i;
2338
2339 writel((cs->base & 0xffff0000) |
2340 (cs->mbus_attr << 8) |
2341 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2342 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2343
2344 win_enable &= ~(1 << i);
2345 win_protect |= 3 << (2 * i);
2346 }
2347
2348 writel(win_enable, base + WINDOW_BAR_ENABLE);
2349 msp->win_protect = win_protect;
2350 }
2351
2352 static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2353 {
2354 /*
2355 * Check whether we have a 14-bit coal limit field in bits
2356 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2357 * SDMA config register.
2358 */
2359 writel(0x02000000, msp->base + 0x0400 + SDMA_CONFIG);
2360 if (readl(msp->base + 0x0400 + SDMA_CONFIG) & 0x02000000)
2361 msp->extended_rx_coal_limit = 1;
2362 else
2363 msp->extended_rx_coal_limit = 0;
2364
2365 /*
2366 * Check whether the MAC supports TX rate control, and if
2367 * yes, whether its associated registers are in the old or
2368 * the new place.
2369 */
2370 writel(1, msp->base + 0x0400 + TX_BW_MTU_MOVED);
2371 if (readl(msp->base + 0x0400 + TX_BW_MTU_MOVED) & 1) {
2372 msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT;
2373 } else {
2374 writel(7, msp->base + 0x0400 + TX_BW_RATE);
2375 if (readl(msp->base + 0x0400 + TX_BW_RATE) & 7)
2376 msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT;
2377 else
2378 msp->tx_bw_control = TX_BW_CONTROL_ABSENT;
2379 }
2380 }
2381
2382 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2383 {
2384 static int mv643xx_eth_version_printed;
2385 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
2386 struct mv643xx_eth_shared_private *msp;
2387 struct resource *res;
2388 int ret;
2389
2390 if (!mv643xx_eth_version_printed++)
2391 printk(KERN_NOTICE "MV-643xx 10/100/1000 ethernet "
2392 "driver version %s\n", mv643xx_eth_driver_version);
2393
2394 ret = -EINVAL;
2395 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2396 if (res == NULL)
2397 goto out;
2398
2399 ret = -ENOMEM;
2400 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2401 if (msp == NULL)
2402 goto out;
2403 memset(msp, 0, sizeof(*msp));
2404
2405 msp->base = ioremap(res->start, res->end - res->start + 1);
2406 if (msp->base == NULL)
2407 goto out_free;
2408
2409 /*
2410 * Set up and register SMI bus.
2411 */
2412 if (pd == NULL || pd->shared_smi == NULL) {
2413 msp->smi_bus = mdiobus_alloc();
2414 if (msp->smi_bus == NULL)
2415 goto out_unmap;
2416
2417 msp->smi_bus->priv = msp;
2418 msp->smi_bus->name = "mv643xx_eth smi";
2419 msp->smi_bus->read = smi_bus_read;
2420 msp->smi_bus->write = smi_bus_write,
2421 snprintf(msp->smi_bus->id, MII_BUS_ID_SIZE, "%d", pdev->id);
2422 msp->smi_bus->parent = &pdev->dev;
2423 msp->smi_bus->phy_mask = 0xffffffff;
2424 if (mdiobus_register(msp->smi_bus) < 0)
2425 goto out_free_mii_bus;
2426 msp->smi = msp;
2427 } else {
2428 msp->smi = platform_get_drvdata(pd->shared_smi);
2429 }
2430
2431 msp->err_interrupt = NO_IRQ;
2432 init_waitqueue_head(&msp->smi_busy_wait);
2433
2434 /*
2435 * Check whether the error interrupt is hooked up.
2436 */
2437 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2438 if (res != NULL) {
2439 int err;
2440
2441 err = request_irq(res->start, mv643xx_eth_err_irq,
2442 IRQF_SHARED, "mv643xx_eth", msp);
2443 if (!err) {
2444 writel(ERR_INT_SMI_DONE, msp->base + ERR_INT_MASK);
2445 msp->err_interrupt = res->start;
2446 }
2447 }
2448
2449 /*
2450 * (Re-)program MBUS remapping windows if we are asked to.
2451 */
2452 if (pd != NULL && pd->dram != NULL)
2453 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2454
2455 /*
2456 * Detect hardware parameters.
2457 */
2458 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
2459 infer_hw_params(msp);
2460
2461 platform_set_drvdata(pdev, msp);
2462
2463 return 0;
2464
2465 out_free_mii_bus:
2466 mdiobus_free(msp->smi_bus);
2467 out_unmap:
2468 iounmap(msp->base);
2469 out_free:
2470 kfree(msp);
2471 out:
2472 return ret;
2473 }
2474
2475 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2476 {
2477 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
2478 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
2479
2480 if (pd == NULL || pd->shared_smi == NULL) {
2481 mdiobus_free(msp->smi_bus);
2482 mdiobus_unregister(msp->smi_bus);
2483 }
2484 if (msp->err_interrupt != NO_IRQ)
2485 free_irq(msp->err_interrupt, msp);
2486 iounmap(msp->base);
2487 kfree(msp);
2488
2489 return 0;
2490 }
2491
2492 static struct platform_driver mv643xx_eth_shared_driver = {
2493 .probe = mv643xx_eth_shared_probe,
2494 .remove = mv643xx_eth_shared_remove,
2495 .driver = {
2496 .name = MV643XX_ETH_SHARED_NAME,
2497 .owner = THIS_MODULE,
2498 },
2499 };
2500
2501 static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
2502 {
2503 int addr_shift = 5 * mp->port_num;
2504 u32 data;
2505
2506 data = rdl(mp, PHY_ADDR);
2507 data &= ~(0x1f << addr_shift);
2508 data |= (phy_addr & 0x1f) << addr_shift;
2509 wrl(mp, PHY_ADDR, data);
2510 }
2511
2512 static int phy_addr_get(struct mv643xx_eth_private *mp)
2513 {
2514 unsigned int data;
2515
2516 data = rdl(mp, PHY_ADDR);
2517
2518 return (data >> (5 * mp->port_num)) & 0x1f;
2519 }
2520
2521 static void set_params(struct mv643xx_eth_private *mp,
2522 struct mv643xx_eth_platform_data *pd)
2523 {
2524 struct net_device *dev = mp->dev;
2525
2526 if (is_valid_ether_addr(pd->mac_addr))
2527 memcpy(dev->dev_addr, pd->mac_addr, 6);
2528 else
2529 uc_addr_get(mp, dev->dev_addr);
2530
2531 mp->default_rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2532 if (pd->rx_queue_size)
2533 mp->default_rx_ring_size = pd->rx_queue_size;
2534 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2535 mp->rx_desc_sram_size = pd->rx_sram_size;
2536
2537 mp->rxq_count = pd->rx_queue_count ? : 1;
2538
2539 mp->default_tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2540 if (pd->tx_queue_size)
2541 mp->default_tx_ring_size = pd->tx_queue_size;
2542 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2543 mp->tx_desc_sram_size = pd->tx_sram_size;
2544
2545 mp->txq_count = pd->tx_queue_count ? : 1;
2546 }
2547
2548 static struct phy_device *phy_scan(struct mv643xx_eth_private *mp,
2549 int phy_addr)
2550 {
2551 struct mii_bus *bus = mp->shared->smi->smi_bus;
2552 struct phy_device *phydev;
2553 int start;
2554 int num;
2555 int i;
2556
2557 if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) {
2558 start = phy_addr_get(mp) & 0x1f;
2559 num = 32;
2560 } else {
2561 start = phy_addr & 0x1f;
2562 num = 1;
2563 }
2564
2565 phydev = NULL;
2566 for (i = 0; i < num; i++) {
2567 int addr = (start + i) & 0x1f;
2568
2569 if (bus->phy_map[addr] == NULL)
2570 mdiobus_scan(bus, addr);
2571
2572 if (phydev == NULL) {
2573 phydev = bus->phy_map[addr];
2574 if (phydev != NULL)
2575 phy_addr_set(mp, addr);
2576 }
2577 }
2578
2579 return phydev;
2580 }
2581
2582 static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex)
2583 {
2584 struct phy_device *phy = mp->phy;
2585
2586 phy_reset(mp);
2587
2588 phy_attach(mp->dev, phy->dev.bus_id, 0, PHY_INTERFACE_MODE_GMII);
2589
2590 if (speed == 0) {
2591 phy->autoneg = AUTONEG_ENABLE;
2592 phy->speed = 0;
2593 phy->duplex = 0;
2594 phy->advertising = phy->supported | ADVERTISED_Autoneg;
2595 } else {
2596 phy->autoneg = AUTONEG_DISABLE;
2597 phy->advertising = 0;
2598 phy->speed = speed;
2599 phy->duplex = duplex;
2600 }
2601 phy_start_aneg(phy);
2602 }
2603
2604 static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2605 {
2606 u32 pscr;
2607
2608 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
2609 if (pscr & SERIAL_PORT_ENABLE) {
2610 pscr &= ~SERIAL_PORT_ENABLE;
2611 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2612 }
2613
2614 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
2615 if (mp->phy == NULL) {
2616 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2617 if (speed == SPEED_1000)
2618 pscr |= SET_GMII_SPEED_TO_1000;
2619 else if (speed == SPEED_100)
2620 pscr |= SET_MII_SPEED_TO_100;
2621
2622 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2623
2624 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2625 if (duplex == DUPLEX_FULL)
2626 pscr |= SET_FULL_DUPLEX_MODE;
2627 }
2628
2629 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2630 }
2631
2632 static int mv643xx_eth_probe(struct platform_device *pdev)
2633 {
2634 struct mv643xx_eth_platform_data *pd;
2635 struct mv643xx_eth_private *mp;
2636 struct net_device *dev;
2637 struct resource *res;
2638 int err;
2639
2640 pd = pdev->dev.platform_data;
2641 if (pd == NULL) {
2642 dev_printk(KERN_ERR, &pdev->dev,
2643 "no mv643xx_eth_platform_data\n");
2644 return -ENODEV;
2645 }
2646
2647 if (pd->shared == NULL) {
2648 dev_printk(KERN_ERR, &pdev->dev,
2649 "no mv643xx_eth_platform_data->shared\n");
2650 return -ENODEV;
2651 }
2652
2653 dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8);
2654 if (!dev)
2655 return -ENOMEM;
2656
2657 mp = netdev_priv(dev);
2658 platform_set_drvdata(pdev, mp);
2659
2660 mp->shared = platform_get_drvdata(pd->shared);
2661 mp->base = mp->shared->base + 0x0400 + (pd->port_number << 10);
2662 mp->port_num = pd->port_number;
2663
2664 mp->dev = dev;
2665
2666 set_params(mp, pd);
2667 dev->real_num_tx_queues = mp->txq_count;
2668
2669 if (pd->phy_addr != MV643XX_ETH_PHY_NONE)
2670 mp->phy = phy_scan(mp, pd->phy_addr);
2671
2672 if (mp->phy != NULL) {
2673 phy_init(mp, pd->speed, pd->duplex);
2674 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2675 } else {
2676 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops_phyless);
2677 }
2678
2679 init_pscr(mp, pd->speed, pd->duplex);
2680
2681
2682 mib_counters_clear(mp);
2683
2684 init_timer(&mp->mib_counters_timer);
2685 mp->mib_counters_timer.data = (unsigned long)mp;
2686 mp->mib_counters_timer.function = mib_counters_timer_wrapper;
2687 mp->mib_counters_timer.expires = jiffies + 30 * HZ;
2688 add_timer(&mp->mib_counters_timer);
2689
2690 spin_lock_init(&mp->mib_counters_lock);
2691
2692 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2693
2694 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 128);
2695
2696 init_timer(&mp->rx_oom);
2697 mp->rx_oom.data = (unsigned long)mp;
2698 mp->rx_oom.function = oom_timer_wrapper;
2699
2700
2701 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2702 BUG_ON(!res);
2703 dev->irq = res->start;
2704
2705 dev->get_stats = mv643xx_eth_get_stats;
2706 dev->hard_start_xmit = mv643xx_eth_xmit;
2707 dev->open = mv643xx_eth_open;
2708 dev->stop = mv643xx_eth_stop;
2709 dev->set_rx_mode = mv643xx_eth_set_rx_mode;
2710 dev->set_mac_address = mv643xx_eth_set_mac_address;
2711 dev->do_ioctl = mv643xx_eth_ioctl;
2712 dev->change_mtu = mv643xx_eth_change_mtu;
2713 dev->tx_timeout = mv643xx_eth_tx_timeout;
2714 #ifdef CONFIG_NET_POLL_CONTROLLER
2715 dev->poll_controller = mv643xx_eth_netpoll;
2716 #endif
2717 dev->watchdog_timeo = 2 * HZ;
2718 dev->base_addr = 0;
2719
2720 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
2721 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM;
2722
2723 SET_NETDEV_DEV(dev, &pdev->dev);
2724
2725 if (mp->shared->win_protect)
2726 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
2727
2728 err = register_netdev(dev);
2729 if (err)
2730 goto out;
2731
2732 dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %pM\n",
2733 mp->port_num, dev->dev_addr);
2734
2735 if (mp->tx_desc_sram_size > 0)
2736 dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
2737
2738 return 0;
2739
2740 out:
2741 free_netdev(dev);
2742
2743 return err;
2744 }
2745
2746 static int mv643xx_eth_remove(struct platform_device *pdev)
2747 {
2748 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2749
2750 unregister_netdev(mp->dev);
2751 if (mp->phy != NULL)
2752 phy_detach(mp->phy);
2753 flush_scheduled_work();
2754 free_netdev(mp->dev);
2755
2756 platform_set_drvdata(pdev, NULL);
2757
2758 return 0;
2759 }
2760
2761 static void mv643xx_eth_shutdown(struct platform_device *pdev)
2762 {
2763 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2764
2765 /* Mask all interrupts on ethernet port */
2766 wrlp(mp, INT_MASK, 0);
2767 rdlp(mp, INT_MASK);
2768
2769 if (netif_running(mp->dev))
2770 port_reset(mp);
2771 }
2772
2773 static struct platform_driver mv643xx_eth_driver = {
2774 .probe = mv643xx_eth_probe,
2775 .remove = mv643xx_eth_remove,
2776 .shutdown = mv643xx_eth_shutdown,
2777 .driver = {
2778 .name = MV643XX_ETH_NAME,
2779 .owner = THIS_MODULE,
2780 },
2781 };
2782
2783 static int __init mv643xx_eth_init_module(void)
2784 {
2785 int rc;
2786
2787 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2788 if (!rc) {
2789 rc = platform_driver_register(&mv643xx_eth_driver);
2790 if (rc)
2791 platform_driver_unregister(&mv643xx_eth_shared_driver);
2792 }
2793
2794 return rc;
2795 }
2796 module_init(mv643xx_eth_init_module);
2797
2798 static void __exit mv643xx_eth_cleanup_module(void)
2799 {
2800 platform_driver_unregister(&mv643xx_eth_driver);
2801 platform_driver_unregister(&mv643xx_eth_shared_driver);
2802 }
2803 module_exit(mv643xx_eth_cleanup_module);
2804
2805 MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
2806 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
2807 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
2808 MODULE_LICENSE("GPL");
2809 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
2810 MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
Linus' kernel tree